Electronic system and method for fault detection thereof, system on chip and bus system

Abstract

An electronic system is disclosed that can include one or more processing circuitry units configured to implement a master intellectual property (IP), an inspector IP, and an error detection circuit. The master IP includes a first data path and a first control signal path. The inspector IP includes a second control signal path. The error detection circuit is configured to detect errors in data by performing error-correcting code (ECC) decoding on output data output by the master IP to the error detection circuit through the first data path, and to detect errors in control signals based on a first signal output by the master IP to the error detection circuit through the first control signal path, and a second signal output by the inspector IP to the error detection circuit through the second control signal path.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0146178, filed on November 14, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to electronic systems, methods for detecting faults thereof, systems-on-chips and bus systems, and more specifically, to electronic systems, systems-on-chips, bus systems and methods thereof for detecting faults, including errors in data and various signals. Background Technology

[0004] Semiconductor devices, including System-on-Chip (SoC), are used in various industrial sectors. When semiconductor devices are used in various industrial sectors, errors may occur in the data and / or signals that are to be processed in the semiconductor device for various reasons. Summary of the Invention

[0005] This invention provides methods and apparatus for performing reliable fault detection and reducing area and / or cost in chip or system implementations of electronic systems, methods for detecting faults, system-on-chips (SoCs), and bus systems. In some example embodiments, where such electronic systems are used in various industrial sectors, fault detection performed in association with such electronic systems, SoCs, and / or bus systems can reduce or prevent the occurrence of control errors.

[0006] According to some exemplary embodiments of the present invention, an electronic system may include: a master intellectual property (IP) including a first data path and a first control signal path; a checker IP including a second control signal path; and an error detection circuit configured to: detect errors in data by performing error correction code (ECC) decoding on output data from the master IP to the error detection circuit via the first data path, and detect errors in control signals based on: a first signal from the master IP to the error detection circuit via the first control signal path, and a second signal from the checker IP to the error detection circuit via the second control signal path.

[0007] According to some exemplary embodiments of the present invention, a method for detecting faults in an electronic system, the electronic system including a first intellectual property (IP) and a second IP, the method may include: detecting errors in input data by performing error correction code (ECC) decoding on output data output from a first data path of the first IP; and detecting errors in control signals based on a first signal output from a first control signal path of the first IP and a second signal output from a second control signal path of the second IP.

[0008] According to some exemplary embodiments of the present invention, a system-on-a-chip may include: an error correction code (ECC) encoder configured to generate encoded data by performing ECC encoding on input data; a master intellectual property (IP) configured to receive the encoded data and a first control signal, and to output output data based on the encoded data via a first data path, and to output a second control signal based on the first control signal via a first control signal path; a first delay circuit configured to generate a third control signal by delaying the first control signal by a specific clock cycle; a checker IP configured to output a fourth control signal based on the third control signal via a second control signal path; an ECC decoder configured to output a data error detection signal by performing ECC decoding on the output data; a second delay circuit configured to generate a fifth control signal by delaying the second control signal by a specific clock cycle; and a checker circuit configured to detect errors in the control signals by comparing the fourth control signal with the fifth control signal.

[0009] According to some exemplary embodiments of the present invention, a bus system may include: a first intellectual property (IP) configured to output data and a first control signal; a second IP configured to output a second control signal; an error correction code (ECC) decoder configured to output a data error detection signal by performing ECC decoding on the output data; a delay circuit configured to generate a third control signal by delaying the first control signal by a specific clock cycle; and a checker circuit configured to detect errors in the control signals by comparing the second control signal with the third control signal. Attached Figure Description

[0010] Example embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 An electronic system is shown, illustrating some example embodiments of a concept according to the present invention;

[0012] Figure 2 An electronic system is shown, illustrating some example embodiments of a concept according to the present invention;

[0013] Figure 3 The main IP is shown as some example embodiments of the concept according to the present invention;

[0014] Figure 4 ECC encoders, data, and encoded data are illustrated in some example embodiments according to the present invention.

[0015] Figure 5 The inspector IP is shown as an example embodiment of some embodiments of the concept according to the present invention;

[0016] Figure 6 Flowcharts illustrating methods of operating electronic systems according to some exemplary embodiments of the present invention;

[0017] Figure 7 Flowcharts illustrating methods for transmitting data and signals using electronic systems according to some exemplary embodiments of the present invention;

[0018] Figure 8 A flowchart illustrating a method for detecting faults in an electronic system according to some exemplary embodiments of a concept based on the present invention;

[0019] Figure 9 An electronic system is shown, illustrating some example embodiments of a concept according to the present invention;

[0020] Figure 10 This is a flowchart illustrating the design of a checker IP according to some example embodiments of the concept of the present invention;

[0021] Figure 11 An electronic system is shown, illustrating some example embodiments of a concept according to the present invention;

[0022] Figure 12 A bus system, a first IP, and a second IP, are shown, representing some example embodiments of the concept according to the present invention; and

[0023] Figure 13 Driving assistance systems according to some example embodiments of the present invention are shown. Detailed Implementation

[0024] In the following sections, some exemplary embodiments of the inventive concept will be described in detail.

[0025] Figure 1 An electronic system 10 is illustrated with some example embodiments of the concept according to the present invention. The electronic system 10 may include a main IP 100 (which may also be interchangeably referred to herein as a first IP), a checker IP 200 (which may also be interchangeably referred to herein as a second IP), an ECC encoder 300, an error detection circuit 450, and a fault collection circuit 600, and the error detection circuit 450 may include an ECC decoder 400 and a checker circuit 500. It will be understood that in some example embodiments, the electronic system 10 may not include all of the main IP 100, checker IP 200, ECC encoder 300, fault collection circuit 600, and error detection circuit 450.

[0026] The electronic system 10 can be implemented in various ways. For example, the electronic system 10 can be implemented in the form of integrated circuits or various chips.

[0027] In some example embodiments, the electronic system 10 may be implemented as a System-on-Chip (SoC) (e.g., it may be implemented by a SoC). The electronic system 10 may be applied to (e.g., it may be included in) robotic devices such as drones and advanced driver assistance systems (ADAS), smart TVs, smartphones, medical devices, mobile devices, image display devices, measuring devices, the Internet of Things (IoT), etc. Additionally, the electronic system 10 may be mounted on one of a variety of electronic devices. In some example embodiments, the electronic system 10 may include components that operate in a single clock domain. For example, all main IP 100, checker IP 200, and error detection circuitry 450 may be circuitry configured to operate in a single clock domain.

[0028] In some example embodiments, at least some of the main IP 100, checker IP 200, ECC encoder 300, ECC decoder 400, checker circuit 500, and fault collection circuit 600 can be implemented as one or more digital circuits (e.g., can be implemented by one or more digital circuits), which may include one or more instances of the processing circuitry described herein. That is, all of the main IP 100, checker IP 200, ECC encoder 300, ECC decoder 400, checker circuit 500, and fault collection circuit 600 can be implemented as digital circuits, or only a portion of the main IP 100, checker IP 200, ECC encoder 300, ECC decoder 400, checker circuit 500, and fault collection circuit 600 can be implemented as digital circuits. However, the inventive concept is not limited thereto, and all of the main IP 100, checker IP 200, ECC encoder 300, ECC decoder 400, checker circuit 500, and fault collection circuit 600 can be implemented as analog circuits.

[0029] Main IP 100 may include one of various intellectual property rights (IP). For example, main IP 100 may include a processing unit, multiple cores included in the processing unit, a multi-format codec (MFC), a video module (e.g., a camera interface, a Joint Image Experts Group (JPEG) processor, a video processor, or a mixer), a 3D graphics core, an audio system, a driver, a display driver, volatile memory, non-volatile memory, a memory controller, an input and output interface block, or a cache memory, etc. Additionally, in some example embodiments, main IP 100 may include a system bus.

[0030] In some example embodiments, the main IP 100 can transmit or process data and / or signals. For example, the main IP 100 can transmit encoded data DATA_ENC, which is to be input from the ECC encoder 300, as output data DATA_OUT, or the main IP 100 can output output data DATA_OUT by processing the encoded data DATA_ENC. Additionally, for example, the main IP 100 can transmit a first signal SIG_1 as a third signal SIG_3, or it can output the third signal SIG_3 by processing the first signal SIG_1.

[0031] In some example embodiments, the main IP 100 may include a data path for transmitting or processing data and a control signal path for transmitting or processing signals. Hereinafter, signals may include a variety of signals and may include at least one of, for example, control signals for controlling various circuit components in the electronic system 10. In other words, in some example embodiments, the main IP 100 may output output data DATA_OUT based on encoded data DATA_ENC via the data path, and may output a third signal SIG_3 based on a first signal SIG_1 via the control signal path. This will refer to... Figure 3 A more detailed description will follow. It will be further understood that, where paths are described herein as performing operations and / or configured to perform operations (e.g., outputting data or signals based on another data or signal), elements including said paths (e.g., main IP 100) will be understood as being configured to perform operations, such as via or based on said paths (e.g., main IP 100 will be understood as being configured to output a third signal SIG_3 based on a first signal SIG_1 input to main IP 100 via or based on the first control signal path 140).

[0032] The checker IP 200 can transmit or process signals. For example, the checker IP 200 can transmit the second signal SIG_2 as the fourth signal SIG_4, or it can output the fourth signal SIG_4 by processing the second signal SIG_2. In some example embodiments, the second signal SIG_2 can be the first signal SIG_1, or it can be a signal generated based on the first signal SIG_1. For example, the second signal SIG_2 can be a signal generated by delaying the first signal SIG_1 by a specific (or, alternatively, predetermined) clock cycle.

[0033] In some example embodiments, the checker IP 200 may include a data path and a control signal path. The checker IP 200 may output a fourth signal SIG_4 based on the second signal SIG_2 via the control signal path. This will refer to... Figure 5 To provide a more detailed description.

[0034] In some example embodiments, during the system (or circuit) design phase, the inspector IP 200 may be designed based on the master IP 100. For example, the inspector IP 200 may be designed based on a copy of the master IP 100. In some example embodiments, the control signal path of the inspector IP 200 may be the same as or substantially the same as the control signal path of the master IP 100. In some example embodiments, the control signal path of the inspector IP 200 may include circuit elements that are the same as or substantially the same as the circuit elements included in the control signal path of the master IP 100. It will be understood that an element may be described herein as “identical” to other elements, and it will be further understood that an element described herein as “identical” to other elements may be “identical” or “substantially” to other elements, wherein an element “substantially” to other elements will be understood as being the same as other elements within manufacturing tolerances and / or material tolerances. Circuit elements that are the same as or substantially the same as other circuit elements may be structurally the same or substantially the same, functionally the same or substantially the same, and / or compositionally the same or substantially the same. Additionally, in some example embodiments, the data path of the checker IP 200 can be designed by performing boundary optimization after copying the data path of the main IP 100 and then binding all inputs to its data path (e.g., following the data path to the copied main IP 100 and then all inputs being bound, in response to the data path of the main IP 100 being copied and then all inputs being bound, etc.). Therefore, apart from the design of the main IP 100, the system designer does not need to perform a separate design for the checker IP 200. Furthermore, the size of the data path of the checker IP 200 can be smaller than the size of the data path of the main IP 100. Therefore, the size of the checker IP 200 can be smaller than the size of the main IP 100. For example, when the electronic system 10 is implemented as a system-on-a-chip, the area occupied by the on-chip checker IP 200 can be smaller than the area occupied by the on-chip main IP 100.

[0035] ECC encoder 300 can generate encoded data DATA_ENC by performing an ECC encoding operation on the data DATA to be processed in electronic system 10 or input data DATA. ECC encoder 300 can provide the encoded data DATA_ENC to main IP 100. ECC encoder 300 can perform ECC encoding by using error correction codes (ECC). Error correction codes (ECC) can include, but are not limited to, at least one of parity check, cyclic redundancy check (CRC), checksum, and Hamming code. Therefore, encoded data DATA_ENC can include data DATA and checker data generated based on data DATA. That is, in some example embodiments, the number of bits in encoded data DATA_ENC can be greater than the number of bits in data DATA. (See reference...) Figure 4 Provide a more detailed description of the data DATA and the encoded data DATA_ENC.

[0036] Error detection circuit 450 can detect errors in data and / or signals to be transmitted or processed within electronic system 10.

[0037] Error detection circuit 450 can detect data errors based on the output data DATA_OUT to be output from main IP 100. Error detection circuit 450 can also detect data errors based on the output data DATA_OUT already output from main IP 100 via a specific data path. For example, error detection circuit 450 can detect data errors by performing ECC decoding on the output data DATA_OUT already output from main IP. Error detection circuit 450 can output the result of data error detection as a data error detection signal DED based on the output data DATA_OUT, and can provide the data error detection signal DED to fault collection circuit 600. For example, when a data error is detected, error detection circuit 450 can output a data error detection signal DED with a first logic level (e.g., "1"). Similarly, for example, when no data error is detected, error detection circuit 450 may not output a separate signal, or may output a data error detection signal DED with a second logic level (e.g., "0"). To this end, the error detection circuit 450 may include an ECC decoder 400 configured to output a data error detection signal DED by performing ECC decoding on the output data DATA_OUT. The ECC decoder 400 may perform ECC decoding using ECC methods such as parity check, cyclic redundancy check (CRC), checksum, and Hamming code. The ECC decoder 400 may detect errors in the data by using checker data included in the output data DATA_OUT. In some example embodiments, when a correctable error exists in the output data DATA_OUT, the ECC decoder 400 may perform an operation to correct the output data DATA_OUT.

[0038] As described herein, data or signals described as “to” be input or output with respect to one or more parts of the electronic system 10, bus system 1000, driver assistance system 2000, etc., can be interchangeably described as data or signals “being” or “already” input or output with respect to one or more parts of the electronic system 10, bus system 1000, driver assistance system 2000, etc. For example, an error detection circuit 450 that can detect data errors based on output data DATA_OUT to be output from main IP 100 can be interchangeably described as detecting data errors based on output data DATA_OUT that has already been output from main IP 100 (e.g., via a specific data path). It will also be understood that data or signals “output” from one or more parts of the electronic system 10, bus system 1000, driver assistance system 2000, etc., can be interchangeably referred to herein as “generated at” or “sent from” one or more parts of the electronic system 10, bus system 1000, driver assistance system 2000, etc.

[0039] Error detection circuit 450 can detect errors in the control signals based on the third signal SIG_3 to be output from main IP 100 and the fourth signal SIG_4 to be output from checker IP 200. In some example embodiments, such as Figure 2 As shown, the error detection circuit 450 can be based on the fourth signal SIG_4 and Figure 2 Errors in the control signal are detected using the fifth signal SIG_5, which is a delayed version of the third signal SIG_3. The error detection circuit 450 can output the result of detecting data errors as a control signal error detection signal SED based on the third signal SIG_3 and the fourth signal SIG_4, and can provide the control signal error detection signal SED to the fault collection circuit 600. For example, when a data error is detected, the error detection circuit 450 can output a control signal error detection signal SED with a first logic level (e.g., "1"). Similarly, for example, when no data error is detected, the error detection circuit 450 may not output a separate signal, or it may output a control signal error detection signal SED with a second logic level (e.g., "0"). For this purpose, the error detection circuit 450 may include a checker circuit 500 configured to output the control signal error detection signal SED based on the third signal SIG_3 and the fourth signal SIG_4. In some example embodiments, the checker circuit 500 can detect control signal errors based on the third signal SIG_3 and the fourth signal SIG_4 using a cyclic verification method. In other words, in some example embodiments, the checker circuit 500 may include a cyclic verification unit (CCU).

[0040] The fault collection circuit 600 can collect information about faults occurring in the electronic system 10 based on the data error detection signal DED and the control signal error detection signal SED to be received from the error detection circuit 450. The fault collection circuit 600 can selectively output a fault detection signal FD regarding the electronic system 10 based on the data error detection signal DED and the control signal error detection signal SED, thereby reducing or preventing control errors associated with the operation of the electronic system 10 and / or any system or device that uses and / or includes the electronic system 10. For example, when an error exists in the data and / or control signals, the fault collection circuit 600 can output a fault detection signal FD with a first logic level (e.g., "1"). Similarly, for example, when no error exists in the data and / or control signals, the fault collection circuit 600 can output a fault detection signal FD with a second logic level (e.g., "0"). However, the inventive concept is not limited thereto, and depending on the number of errors detected, the fault collection circuit 600 can output a fault detection signal FD with one of three or more levels.

[0041] According to some exemplary embodiments of the electronic system 10 conceived in this invention, the electronic system 10 can efficiently detect errors in data and / or control signals through the operation of the main IP 100, the checker IP 200 designed based on the replication of the main IP 100, and the error detection circuit 450. For example, the electronic system 10 can detect data errors by using output data DATA_OUT to be output through the data path of the main IP 100, and can detect errors in control signals with high reliability based on the third signal SIG_3 to be output through the control signal path of the main IP 100 and the fourth signal SIG_4 to be output through the control signal path of the checker IP 200. In addition, while maintaining the high reliability of error detection as described above, the designer can also ensure the simplicity of the design because there is no need to design additional circuitry for the checker IP 200 separately from the circuitry design of the main IP 100. Furthermore, since the size of the checker IP 200 is smaller than that of the main IP 100, the area and / or cost for system implementation can be reduced compared to comparative examples where the size of the checker IP 200 is larger than that of the main IP 100.

[0042] Figure 2 This illustrates an electronic system 10 with some exemplary embodiments according to the concept of the present invention. The electronic system 10 may include a main IP 100, a checker IP 200, an ECC encoder 300, an ECC decoder 400, a checker circuit 500, a fault collection circuit 600, a first delay circuit 720, and a second delay circuit 740. Regarding... Figure 2 , will omit and Figure 1The description of the electronic system 10 overlaps, and will focus on the electronic system 10. Figure 1 The differences are used to provide a description.

[0043] The first signal SIG_1 can be input to the main IP 100, and the second signal SIG_2 can be input to the checker IP 200.

[0044] The first delay circuit 720 can generate the second signal SIG_2 based on the first signal SIG_1. For example, the first delay circuit 720 can generate the second signal SIG_2 by delaying the first signal SIG_1 by a specific (or, alternatively, predetermined) clock cycle. As a non-limiting example, the first delay circuit 720 can generate the second signal SIG_2 by delaying the first signal SIG_1 by two clock cycles. Therefore, it will be understood that the second signal SIG_2 can be delayed by a specific clock cycle relative to the first signal SIG_1, for example, such that the second signal SIG_2 is delayed by a specific clock cycle when it is input to the checker IP 200 relative to the time when the first signal SIG_1 is input to the main IP 100.

[0045] The main IP 100 can transmit the first signal SIG_1 as the third signal SIG_3, or it can output the third signal SIG_3 by processing the first signal SIG_1. For example, the main IP 100 can output the third signal SIG_3 based on the first signal SIG_1 through the control signal path of the main IP 100.

[0046] The checker IP 200 can transmit the second signal SIG_2 as the fourth signal SIG_4, or it can output the fourth signal SIG_4 by processing the second signal SIG_2. For example, the checker IP 200 can output the fourth signal SIG_4 based on the second signal SIG_2 through the control signal path of the checker IP 200.

[0047] The second delay circuit 740 can generate the fifth signal SIG_5 based on the third signal SIG_3. For example, the second delay circuit 740 can generate the fifth signal SIG_5 by delaying the third signal SIG_3 by a specific (or, alternatively, predetermined) clock cycle. Therefore, it will be understood that the fifth signal SIG_5 can be delayed by a specific clock cycle relative to the fourth signal SIG_4, for example, such that the fifth signal SIG_5 is delayed by a specific clock cycle when input to the error detection circuit 450. The number (e.g., amount) of clock cycles to be delayed by the second delay circuit 740 can be equal to the number of clock cycles to be delayed by the first delay circuit 720, such that the second signal SIG_2 and the fifth signal SIG_5 are both delayed by the same specific clock cycle relative to the first signal SIG_1 and the fourth signal SIG_4, respectively. As a non-limiting example, the second delay circuit 740 can generate the fifth signal SIG_5 by delaying the third signal SIG_3 by two clock cycles.

[0048] The checker circuit 500 can detect errors in the control signal using the fourth signal SIG_4 and the fifth signal SIG_5. For example, the checker circuit 500 can detect errors in the control signal using the fourth signal SIG_4 and the fifth signal SIG_5 according to a cyclic verification method. For example, the checker circuit 500 can detect errors in the control signal based on comparing the fourth signal SIG_4 and the fifth signal SIG_5 according to a cyclic verification method, and can selectively output a control signal error signal SED in response to the detection.

[0049] Figure 3 The main IP 100 is shown as some example embodiments of the concept according to the present invention. (The remaining text is omitted.) Figure 1 Overlapping descriptions of the main IP address 100. (See reference) Figure 1 Describe together Figure 3 .

[0050] The main IP 100 may include (for example, may implement) a first data path 120 (also referred to herein as the first data path) and a first control signal path 140. Figure 3 The diagram shows that the primary IP 100 includes a first data path 120, but is not limited to this, and the primary IP 100 may include multiple data paths. Similarly, Figure 3 The main IP 100 is shown to include a first control signal path 140, but is not limited thereto, and the main IP 100 may include multiple control signal paths.

[0051] The main IP 100 can output output data DATA_OUT by transmitting or processing the encoded data DATA_ENC. In some example embodiments, the first data path 120 may include all circuit elements through which the encoded data DATA_ENC is input to the main IP 100 and passes to the output of the output data DATA_OUT.

[0052] Similarly, the main IP 100 can transmit the first signal SIG_1, or it can output the third signal SIG_3 by processing the first signal SIG_1. Therefore, it will be understood that the first control signal path 140 can be configured to output the third signal SIG_3 based on the first signal SIG_1 being input to the main IP 100 (e.g., input to the first control signal path 140), for example, based on processing the first signal SIG_1. In some example embodiments, the first control signal path 140 may include all circuit elements through which the first signal SIG_1 travels from being input to the main IP 100 to the output of the third signal SIG_3. Therefore, it will be understood that the main IP 100 can be configured to receive encoded data DATA_ENC and the first signal SIG_1 as a first control signal, and output (e.g., generate, transmit, etc.) output data DATA_OUT through the first data path 120 based on the encoded data DATA_ENC, and output the third signal SIG_3 as a second control signal through the first control signal path 140 based on the first signal SIG_1 as a first control signal. It should also be understood that the first data path 120 can be configured to output the output data DATA_OUT based on the encoded data DATA_ENC, and the first control signal path 140 can be configured to output the third signal SIG_3 as a control signal based on the first signal SIG_1 as another control signal.

[0053] Therefore, in some example embodiments, the first data path 120 may be a circuit independent of the first control signal path 140. However, the inventive concept is not limited thereto, and in some cases, the first data path 120 and the first control signal path 140 may share some circuit elements.

[0054] When the electronic system 10 detects a fault, the electronic system 10 can detect the error by using ECC to decode the data through the first data path 120 of the main IP 100, and can also detect the error by using the control signal through the control signal path of the checker IP 200 and the control signal through the first control signal path 140 of the main IP 100.

[0055] Therefore, the electronic system 10 including the main IP 100, according to some exemplary embodiments of the present invention, can detect errors in data and / or signals with high reliability, thereby improving the performance of the electronic system 10.

[0056] Figure 4 ECC encoder 300, data DATA (also referred to herein as input data), and encoded data DATA_ENC are shown as some example embodiments of the invention. (The terms "and" will be omitted.) Figure 1 Overlapping descriptions of the ECC encoder 300. References Figure 1 Describe together Figure 4 .

[0057] The ECC encoder 300 can generate encoded data DATA_ENC by performing ECC encoding on the data DATA. The number of bits in the data DATA can be described as N bits, where N is a natural number.

[0058] In some example embodiments, the ECC encoder 300 can generate encoded data DATA_ENC by adding checker data DATA_C, which is to be generated based on data DATA, to data DATA. That is, encoded data DATA_ENC may include data DATA and checker data DATA_C, which is to be generated based on data DATA. Figure 4 The example shows the addition of checker data DATA_C after the data DATA, but it is not limited to this. For example, checker data DATA_C can be added before the data DATA, and in some cases, checker data DATA_C can be added in the middle of the data DATA. The number of bits in checker data DATA_C can be C bits, where C is a natural number. In some example embodiments, C can have a value less than N. In some example embodiments, the N:C ratio can be 8:1, but it is not limited to this. That is, the number of bits in the encoded data DATA_ENC can be (N + C) bits, and can be greater than the number of bits in the data DATA.

[0059] Encoded data DATA_ENC can be input to the main IP 100. The main IP 100 can output output data DATA_OUT by transmitting or processing the encoded data DATA_ENC. For the purpose of illustrating some example embodiments, it can be assumed that the main IP 100 transmits the encoded data DATA_ENC as output data DATA_OUT.

[0060] In some example embodiments, the ECC decoder 400 can detect data errors by performing ECC decoding on the output data DATA_OUT, and thus output a data error detection signal DED accordingly. For example, the ECC decoder 400 can detect data errors by generating comparison checker data using data included in the output data DATA_OUT, and then comparing the generated comparison checker data with the checker data included in the output data DATA_OUT. For example, when the generated comparison checker data and the checker data included in the output data DATA_OUT do not match, the ECC decoder 400 can determine that an error has occurred in the data and can output an error detection signal DED indicating that an error has been detected. It will be understood that performing data encoding or decoding herein may be referred to interchangeably with performing encoding or decoding on data.

[0061] Figure 5 The inspector IP 200 is shown as an example embodiment of some embodiments of the invention. (The remaining text is omitted.) Figure 1 Overlapping descriptions of Inspector IP 200. (See reference) Figure 1 and Figure 3 Describe together Figure 5 .

[0062] The checker IP 200 may include (for example, may implement) a second data path 220 and a second control signal path 240. In some example embodiments, the checker IP 200 may omit the second data path 220. Figure 5 The inspector IP 200 is shown to include a second data path 220, but is not limited thereto, and the inspector IP 200 may include multiple data paths. Similarly, Figure 5 The inspector IP 200 is shown to include a second control signal path 240, but is not limited thereto; the inspector IP 200 may include multiple control signal paths.

[0063] The checker IP 200 can output a fourth signal SIG_4 by transmitting or processing the second signal SIG_2. Therefore, it will be understood that the second control signal path 240 can be configured to output the fourth signal SIG_4 based on the second signal SIG_2 being input to the checker IP 200 (e.g., input to the second control signal path 240), for example, based on processing the second signal SIG_2. Therefore, it will be understood that the checker IP 200 can be configured to output the fourth signal SIG_4 as a fourth control signal through the second control signal path 240 based on the second signal SIG_2 as a third control signal. It will be understood that the second control signal path 240 can be configured to output the fourth signal SIG_4 as a control signal based on the second signal SIG_2, which is delayed by a specific clock cycle relative to the first signal SIG_1. In some example embodiments, the second control signal path 240 may include all circuit elements through which the second signal SIG_2 travels from being input to the checker IP 200 to the output of the fourth signal SIG_4.

[0064] In some example embodiments, the inspector IP 200 can be designed based on a copy of the master IP 100. Therefore, the second control signal path 240 of the inspector IP 200 may include circuit components that are the same as or substantially the same as those circuit components of the first control signal path 140 of the master IP 100 (e.g., the same within manufacturing and / or material tolerances). It will be understood that the terms "circuit component" and "circuit element" are used interchangeably herein. The second data path 220 of the inspector IP 200 can be designed with boundary optimization after copying the first data path 120 of the master IP 100 and binding all inputs (e.g., following the copying of the first data path 120 of the master IP 100 and binding all inputs, in response to the copying of the first data path 120 of the master IP 100 and binding all inputs, etc.). Therefore, no input signals may be supplied to the second data path 220 of the inspector IP 200, and the second data path 220 of the inspector IP 200 may not output any output signals. In other words, the input of the second data path 220 of the checker IP 200 and the output of the second data path 220 of the checker IP 200 that depends on the input can be omitted in the second data path 220.

[0065] The size of the second data path 220 of the checker IP 200 can be smaller than the size of the first data path 120 of the main IP 100. Therefore, the size of the checker IP 200 can be smaller than the size of the main IP 100. In other words, when the electronic system 10 is implemented as a system-on-a-chip, the area (e.g., circuit area) occupied by the checker IP 200 on the system-on-a-chip chip can be smaller than the area (e.g., circuit area) occupied by the main IP 100 on the system-on-a-chip chip. For example, when the electronic system 10 is implemented as a system-on-a-chip, the area (e.g., circuit area) occupied by the second data path 220 on the system-on-a-chip chip can be smaller than the area (e.g., circuit area) occupied by the first data path 120 on the system-on-a-chip chip.

[0066] Figure 6 A flowchart illustrating a method for operating an electronic system according to some exemplary embodiments of the present invention is shown. (Refer to...) Figure 1 , Figure 3 and Figure 5 Describe together Figure 6 .

[0067] Data and / or control signals can be input to the main IP 100 and the checker IP 200 (S100). Refer to... Figure 7 The operation of S100 is described in more detail.

[0068] Electronic system 10 can detect errors (S200) based on data and control signals to be output from main IP 100 and checker IP 200. For example, electronic system 10 can detect data errors based on output data to be output from main IP 100, and can detect control signal errors based on a third signal SIG_3 to be output from main IP 100 and a fourth signal SIG_4 to be output from checker IP 200. (See reference...) Figure 8 The operation of S200 is described in more detail.

[0069] Figure 7 A flowchart illustrating a method for transmitting data and signals in an electronic system according to some exemplary embodiments of a concept based on the present invention is provided. Specifically, Figure 7 It can be shown that... Figure 6 The detailed flowchart corresponding to operation S100 will be provided for reference. Figure 1 , Figure 3 and Figure 5 Describe together Figure 7 .

[0070] Electronic system 10 can generate encoded data DATA_ENC by ECC encoding of data DATA (e.g., by performing ECC encoding of data DATA) (S120). For example, ECC encoder 300 can generate encoded data DATA_ENC by ECC encoding of data DATA. Encoded data DATA_ENC may include data DATA and checker data to be generated based on data DATA. Therefore, the number of bits in encoded data DATA_ENC can be greater than the number of bits in data DATA.

[0071] The main IP 100 included in the electronic system 10 can output output data DATA_OUT based on the encoded data DATA_ENC through the first data path 120 of the main IP 100 (S140). The main IP 100 can transmit the encoded data DATA_ENC as output data DATA_OUT, or it can output output data DATA_OUT by processing the encoded data DATA_ENC.

[0072] The main IP 100 included in the electronic system 10 can output a third signal SIG_3 based on the first signal SIG_1 through the first control signal path 140 of the main IP 100 (S160). The main IP 100 can transmit the first signal SIG_1 as the third signal SIG_3, or it can output the third signal SIG_3 by processing the first signal SIG_1.

[0073] The checker IP 200 included in the electronic system 10 can output a fourth signal SIG_4 based on the second signal SIG_2 via the second control signal path 240 of the checker IP 200 (S180). The checker IP 200 can transmit the second signal SIG_2 as the fourth signal SIG_4, or it can output the fourth signal SIG_4 by processing the second signal SIG_2. In some example embodiments, the second signal SIG_2 can represent a signal in which the first signal SIG_1 is delayed by a specific (or, alternatively, predetermined) clock cycle.

[0074] Figure 8 A flowchart illustrating a method for detecting faults in an electronic system according to some exemplary embodiments of the present invention is provided. Specifically, Figure 8 It can be shown that... Figure 6 The detailed flowchart corresponding to operation S200 is provided for reference. Figure 1 , Figure 3 and Figure 5 Describe together Figure 8 .

[0075] Electronic system 10 can detect data errors by performing ECC decoding on the output data DATA_OUT to be output from main IP 100 (S220). For example, error detection circuit 450 can detect data errors by performing ECC decoding on the output data DATA_OUT to be output via the first data path 120 of main IP 100. As described herein, signals described as "to be output" by one or more elements of electronic system 10 can be understood to include, for example, signals actually output by one or more elements of electronic system 10 to one or more other elements of electronic system 10 via one or more signal paths of electronic system 10. For example, at S220, error detection circuit 450 can detect data errors by performing ECC decoding on the output data DATA_OUT output from main IP 100 to error detection circuit 450 via the first data path 120 of main IP 100. For this purpose, error detection circuit 450 may include ECC decoder 400, which can be configured to perform such ECC decoding. In other words, the ECC decoder 400 can detect data errors by performing ECC decoding on the output data DATA_OUT that will be output through the first data path 120 of the main IP 100. The ECC decoder 400 can output the result of the data error detection as a data error detection signal DED, and can provide the data error detection signal DED to the fault collection circuit 600. To reiterate, the ECC decoder 400 can be configured to perform ECC decoding on the output data to detect data errors (S220), and output the data error detection signal DED in response to the detection of data errors. Therefore, it will be understood that operation S220 may include detecting errors in input data (e.g., data input to the electronic system 10) by performing ECC decoding on the output data output from the first data path 120 of the main IP 100 (e.g., the case where output data is output from the first data path 120 based on the processing of input data). It will be understood that the output signal (e.g., the ECC decoder 400 outputs a data error detection signal DED) may include generating a signal (e.g., the ECC decoder 400 generates a data error detection signal DED) and / or sending a signal to an external component (e.g., the ECC decoder 400 sends the data error detection signal DED to the fault collection circuit 600).

[0076] Electronic system 10 can detect errors in the control signal based on a third signal SIG_3 to be output from main IP 100 and a fourth signal SIG_4 to be output from checker IP 200 (S240). For example, error detection circuit 450 can detect errors in the control signal based on a third signal SIG_3 to be output through a first control signal path 140 of main IP 100 and a fourth signal SIG_4 to be output through a second control signal path 240 of checker IP 200. For example, error detection circuit 450 can detect errors in the control signal based on a signal (e.g., the third signal SIG_3, which can be referred to as the first signal) output from main IP 100 to error detection circuit 450 (e.g., output to checker circuit 500) through the first control signal path 140 of main IP 100 and another signal (e.g., the fourth signal SIG_4, which can be referred to as the second signal) output from checker IP 200 to error detection circuit (e.g., checker circuit 500) through the second control signal path 240 of checker IP 200 (e.g., the second control signal path). In some example embodiments, for instance, error detection circuit 450 may detect errors in the control signal based on a fifth signal and a fourth signal SIG_4 to be output through the second control signal path 240 of checker IP 200, wherein the fifth signal is a signal in which a third signal SIG_3 to be output through the first control signal path 140 of main IP 100 is delayed by a specific (or, alternatively, predetermined) clock cycle. For this purpose, error detection circuit 450 may include checker circuit 500. In other words, checker circuit 500 may detect errors in the control signal based on the third signal SIG_3 to be output through the first control signal path 140 of main IP 100 and the fourth signal SIG_4 to be output through the second control signal path 240 of checker IP 200. Checker circuit 500 may output the result of the control signal error detection as a control signal error detection signal SED, and may provide the control signal error detection signal SED to fault collection circuit 600. To reiterate, the checker circuit 500 can be configured to detect errors in the control signal based on the third signal SIG_3 and the fourth signal SIG_4 (S240), and output a control signal error detection signal SED in response to detecting an error in the control signal. Therefore, it will be understood that operation S240 may include detecting errors in the control signal based on the third signal SIG_3 output from the first control signal path 140 of the main IP 100 and the fourth signal SIG_4 output from the second control signal path 240 of the checker IP 200. (At least refer to...) Figure 2Detecting an error in the control signal at S240 may include generating a fifth signal SIG_5 by delaying the third signal SIG_3 for a specific clock cycle (e.g., at the second delay circuit 740) and outputting a control signal error detection signal SED based on comparing the fifth signal SIG_5 with the fourth signal SIG_4 (e.g., at the checker circuit 500, the control signal error detection signal SED is selectively output in response to the comparison result of the fourth signal SIG_4 and the fifth signal SIG_5).

[0077] Electronic system 10 can detect faults in electronic system 10 based on the results of data error detection and control signal error detection (S260). For example, fault collection circuit 600 can detect faults in data and / or signals to be processed in electronic system 10 based on the data error detection signal DED to be received from ECC decoder 400 and the control signal error detection signal SED to be received from checker circuit 500. Fault collection circuit 600 can selectively output fault detection signal FD based on (e.g., in response to) data error detection signal DED and control signal error detection signal SED. Therefore, it will be understood that fault collection circuit 600 can receive data error detection signal DED from error detection circuit 450 (e.g., ECC decoder 400), receive control signal error detection signal SED from error detection circuit 450 (e.g., checker circuit 500), and selectively output fault detection signals related to electronic system 10 in response to data error detection signal DED and control signal error detection signal SED.

[0078] Figure 9 An electronic system 10 is shown, which includes some example embodiments of the concept according to the present invention. Figure 9 The electronic system 10 illustrates some example embodiments, in which Figure 3 Main IP 100 and Figure 5 The inspector IP 200 is applied Figure 2 The electronic system 10. That is to say, omitting and Figures 1 to 8 Overlapping Figure 9 Description of the electronic system 10.

[0079] Electronic system 10 may include main IP 100, checker IP 200, ECC encoder 300, ECC decoder 400, checker circuit 500, fault collection circuit 600, first delay circuit 720 and second delay circuit 740.

[0080] The main IP 100 may include (for example, may implement) a first data path 120 and a first control signal path 140. The main IP 100 may output output data DATA_OUT based on encoded data DATA_ENC via the first data path 120. The main IP 100 may output a third signal SIG_3 based on a first signal SIG_1 via the first control signal path 140.

[0081] The first delay circuit 720 can generate a second signal SIG_2 by delaying the first signal SIG_1 by a specific (or alternatively, predetermined) clock cycle, and can provide the generated second signal SIG_2 to the checker IP200.

[0082] The checker IP 200 may include (for example, may implement) a second data path 220 and a second control signal path 240. The checker IP 200 may output a fourth signal SIG_4 through the second control signal path 240 based on the second signal SIG_2. No data may be input to the second data path 220, and the second data path 220 may not output any data.

[0083] The ECC decoder 400 can detect data errors by using the output data DATA_OUT to be output through the first data path 120.

[0084] The second delay circuit 740 can generate a fifth signal SIG_5 by delaying the third signal SIG_3 to be output through the first control signal path 140 by a specific (or, alternatively, predetermined) clock period (which may be the same as the specific clock period by which the first delay circuit 720 delays the first signal SIG_1 to generate the second signal SIG_2), and can provide the generated fifth signal SIG_5 to the checker circuit 500.

[0085] The checker circuit 500 can detect errors in the control signal based on the fifth signal SIG_5 and the fourth signal SIG_4 to be output through the second control signal path 240.

[0086] Figure 10 A flowchart illustrating a design checker IP with some example embodiments according to the present invention is provided. (Reference) Figure 1 Describe together Figure 10 .

[0087] The designer of the electronic system 10 can obtain the design source data of the main IP 100 (S320). For example, the designer can obtain the design source data of the main IP 100 implemented in a hardware description language (HDL).

[0088] Designers can bind all inputs to the data path of the master IP 100 (S340). For example, designers can configure the function to bind all inputs to the data path based on the design source data of the master IP 100.

[0089] The designer can synthesize the circuit (S360). That is, the circuit can be synthesized based on the design source data to be ultimately obtained, according to operation S340.

[0090] Designers can obtain the netlist (S380) of inspector IP 200. The netlist can represent data in a form that can be implemented in the actual chip through the placement process.

[0091] Figure 11 An electronic system 20 is shown, representing some example embodiments of a concept according to the present invention. Figure 11 Some example embodiments are shown, in which Figure 2 The ECC encoder 300, ECC decoder 400, checker circuit 500, and fault collection circuit 600 of the electronic system 10 can be implemented as a single control circuit 800. Relative to... Figure 11 , will omit and Figures 1 to 9 Overlapping descriptions.

[0092] Electronic system 20 may include main IP 100, checker IP 200, control circuit 800, first delay circuit 720 and second delay circuit 740. Control circuit 800 may include ECC encoder 300, ECC decoder 400, checker circuit 500 and fault collection circuit 600.

[0093] In some example embodiments, the control circuit 800 may be implemented as a digital circuit (e.g., one or more instances of a processing circuit) to perform all the functions of the ECC encoder 300, ECC decoder 400, checker circuit 500, and fault collection circuit 600. For example, the control circuit 800 may provide encoded data DATA_ENC to the main IP 100 by performing ECC encoding on the data DATA. For example, the control circuit 800 may detect data errors by performing ECC decoding on the output data DATA_OUT to be output from the main IP 100. For example, the control circuit 800 may detect control signal errors by using a fourth signal SIG_4 and a fifth signal SIG_5. Based on the results of data error detection and control signal error detection, the control circuit 800 may output a fault detection signal FD regarding the electronic system 20.

[0094] Figure 12 A bus system 1000, a first IP 1001, and a second IP 1002 are shown, representing some example embodiments of the concept according to the present invention. Figure 12The bus system 1000 is shown in which the reference is Figures 1 to 11 The described electronic systems 10 and 20 are applied to (e.g., included in) some example embodiments of a bus system. In other words, refer to Figures 1 to 11 The functionality of the described components can also be applied to Figure 12 .

[0095] The first IP 1001 and the second IP 1002 can exchange data or various signals with each other through the bus system 1000.

[0096] The bus system 1000 may include a bus component 1100, a replicated bus component 1200, an ECC encoder 1300, an ECC decoder 1400, a checker circuit 1500, a fault collection circuit 1600, a first delay circuit 1720, and a second delay circuit 1740.

[0097] Bus component 1100 can be used with reference Figures 1 to 11 Corresponding to the described master IP 100, bus component 110 may be referred to as the first IP or master IP in some example embodiments. Bus component 1100 may include a first data path and a first control signal path. Bus component 1100 can output output data DATA_OUT by transmitting encoded data DATA_ENC via the first data path. Bus component 1100 may output a third signal SIG_3 (e.g., as the first control signal) based on a first signal SIG_1 via the first control signal path.

[0098] The copied bus component 1200 can be compared with the reference. Figures 1 to 11 Corresponding to the described checker IP 200, bus component 110 may be referred to as a second IP or checker IP in some example embodiments. The replicated bus component 1200 may include a second data path and a second control signal path. The replicated bus component 1200 may output a fourth signal SIG_4 (e.g., as a second control signal) via the second control signal path based on the second signal SIG_2. No data may be input to the second data path, and the second data path may not output any data.

[0099] Each of the ECC decoder 1400, checker circuit 1500, fault collection circuit 1600, first delay circuit 1720, and second delay circuit 1740 can be respectively connected to a reference. Figures 1 to 11 The ECC decoder 400, checker circuit 500, fault collection circuit 600, first delay circuit 720 and second delay circuit 740 described correspond to each other.

[0100] According to some exemplary embodiments of the bus system 1000 based on the inventive concept, the bus system 1000 can detect errors in data DATA and errors in control signals to be transmitted and received between the first IP 1001 and the second IP 1002. Furthermore, since the size of the replicated bus component 1200 can be designed to be smaller than that of the bus component 1100, the on-chip area and / or cost can be reduced in the design.

[0101] Figure 13 A driving assistance system 2000 with some example embodiments according to the present invention is illustrated. The driving assistance system 2000 may be included in a vehicle 2001, which may be any known vehicle, including automobiles, including any vehicle that can be configured to achieve at least partial autonomous driving. The driving assistance system 2000 may include a processor 2100, a sensor unit 2200, a communication module 2300, a driving control unit 2400, an autonomous driving unit 2500, and a user interface 2600.

[0102] Processor 2100 can control the overall operation of a device to which the driver assistance system 2000 is applied. Processor 2100 may include one processor core (single-core) or multiple processor cores (multi-core). Processor 2100 can process or execute programs and / or data stored in the memory of the driver assistance system 2000. In some example embodiments, processor 2100 may include an NPU capable of processing computations based on various types of networks, such as convolutional neural networks (CNNs), region-based convolutional neural networks (R-CNNs), region extraction networks (RPNs), recurrent neural networks (RNNs), fully convolutional networks (FCNs), long short-term memory (LSTM) networks, and classification networks.

[0103] Sensor unit 2200 (also simply referred to herein as a “sensor”) can collect information about objects to be sensed by a device (e.g., vehicle 2201) to which the driver assistance system 2000 is applied. In some example embodiments, sensor unit 2200 may be an image sensor unit. In some example embodiments, sensor unit 2200 may include at least one image sensor. Sensor unit 2200 can sense or receive image signals from the outside of the device to which the driver assistance system 2000 is applied and convert the image signals into image data, i.e., image frames. In some example embodiments, sensor unit 2200 may be a distance sensor unit, also simply referred to herein as a “distance sensor”. In some example embodiments, sensor unit 2200 may include at least one distance sensor. Distance sensor may include at least one of various types of sensing devices, such as light detection and ranging (LIDAR) sensors, radio detection and ranging (RADAR) sensors, time-of-flight (ToF) sensors, ultrasonic sensors, and infrared sensors. Furthermore, LIDAR sensors and RADAR sensors can be classified according to their effective measurement distance. For example, LIDAR sensors can be classified as long LIDAR sensors and short LIDAR sensors, and RADAR sensors can be classified as long RADAR sensors and short RADAR sensors. Additionally, sensor unit 2200 may include, but is not limited to, at least one of a geomagnetic sensor, a position sensor (e.g., GPS), an acceleration sensor, a barometric pressure sensor, a temperature / humidity sensor, a proximity sensor, and a gyroscope sensor. Since those skilled in the art can intuitively infer the function of each sensor from its name, a detailed description thereof will be omitted.

[0104] The communication module 2300 can send and / or receive data from a device to which the driving assistance system 2000 is applied. For example, the communication module 2300 can communicate with external objects of the device. In some example embodiments, the communication module 2300 can perform communication in a vehicle-to-everything (V2X) manner. For example, the communication module 2300 can perform communication in a vehicle-to-vehicle (V2V), vehicle-to-infrastructure (V2I), vehicle-to-pedestrian (V2P), and vehicle-to-mobile device (V2N) manner. However, the inventive concept is not limited thereto, and the communication module 2300 can send and receive data through various known communication methods. For example, the communication module 2300 can perform communication through, for example, 3G, LTE, Wi-Fi, Bluetooth, Bluetooth Low Energy (BLE), Zigbee, Near Field Communication (NFC), or ultrasonic communication methods, and can include both short-range and long-range communication.

[0105] The driving control unit 2400 (also referred to herein as the "driving controller") may include any of the following: a vehicle steering device configured to control the direction of the vehicle, a throttle device configured to control acceleration and / or deceleration by controlling a tolerance motor or engine, a braking device configured to control the braking of the vehicle, and external lighting devices, etc.

[0106] The autonomous driving unit 2500 (also referred to herein as the "autonomous driving controller") may include a computing device configured to autonomously control the driving control unit 2400 (e.g., control the driving control unit 2400 to enable autonomous driving of the vehicle 2001). For example, the autonomous driving unit 2500 may include at least one component of the means in which the driving assistance system 2000 is implemented. The autonomous driving unit 2500 may include a memory for storing a plurality of program instructions and one or more processors for executing the program instructions. The autonomous driving unit 2500 may be configured to control the driving control unit 2400 based on sensing signals to be output from the sensor unit 2200.

[0107] The user interface 2600 may include various electronic and mechanical devices included in the driver's seat or passenger seat, such as a display indicating the vehicle's dashboard.

[0108] In the automotive industry, high-level safety systems, ranging from airbag deployment systems to Advanced Driver Assistance Systems (ADAS), may be required. As a representative example, electronic devices equipped with high-level safety systems can be certified according to ISO 26262, the international standard for functional safety of motor vehicles. Specifically, to obtain ISO 26262 ASIL-D certification, electronic devices must meet a single point of failure metric (SPFM) of 99% or higher. In other words, high-safety-level electronic devices are required to detect 99% or more of the single point of failure metrics.

[0109] refer to Figures 1 to 12 The described electronic systems 10 and 20 can be applied to at least one of the following: processor 2100, sensor unit 2200, communication module 2300, driving control unit 2400, autonomous driving unit 2500, and user interface 2600 included in driving assistance system 2000.

[0110] In some example embodiments, any part or all of the system according to any example embodiment may include, may be included in and / or may be implemented by one or more instances of the following (e.g., articles, parts, units, etc.): processing circuitry such as hardware containing logic circuitry; hardware / software combination such as a processor executing software; or combinations thereof, any part or all of the system including some or all of the following: electronic system 10, electronic system 20, bus system 1000, and / or drive auxiliary system 2000 according to any example embodiment (including some or all of the following: main IP 100, checker IP). 200, ECC encoder 300, fault collection circuit 600, error detection circuit 450, first delay circuit 720, second delay circuit 740, control circuit 800, bus assembly 1100, replicated bus assembly 1200, ECC encoder 1300, ECC decoder 1400, checker circuit 1500, fault collection circuit 1600, first delay circuit 1720, second delay circuit 1740, processor 2100, sensor unit 2200, communication module 2300, driving control unit 2400, autonomous driving unit 2500, and / or user interface 2600). For example, the processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), arithmetic logic unit (ALU), digital signal processor, microcomputer, field-programmable gate array (FPGA), system-on-a-chip (SoC), programmable logic unit, microprocessor, application-specific integrated circuit (ASIC), etc. In some example embodiments, the processing circuitry may include: a non-transitory computer-readable storage device or memory storing an instruction program, such as a solid-state drive (SSD); and a processor configured to execute the instruction program to implement some or all of the functions of the system according to any example embodiment. It will be understood that, as described herein, elements described as “implementation” elements (e.g., main IP 100, checker IP 200, etc.) (e.g., processing circuitry, digital circuitry, etc.) will be understood to implement the functions of the implemented elements (e.g., the functions of main IP 100, the functions of checker IP 200, etc.).

[0111] The driving assistance system 2000, which employs electronic systems 10 and 20 according to some example embodiments of the present invention, can detect 99% or more of single points of failure and can also reduce the design area.

[0112] Although the inventive concept has been specifically shown and described with reference to exemplary embodiments thereof, it should be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An electronic system comprising: The main intellectual property (IP) includes the first data path and the first control signal path; The inspector IP includes the second control signal path; as well as The error detection circuit is configured as follows: Data errors are detected by performing ECC decoding on the output data from the main IP to the error detection circuit via the first data path. Errors in control signals are detected based on the following: The first signal is output from the main IP to the error detection circuit through the first control signal path. The second signal is output by the checker IP to the error detection circuit through the second control signal path.

2. The electronic system according to claim 1, wherein, The error detection circuit includes: An ECC decoder is configured to perform ECC decoding on the output data to detect data errors, and to output a data error detection signal in response to detecting the data error; and The checker circuit is configured to detect errors in the control signal based on the first signal and the second signal, and to further output a control signal error detection signal in response to detecting an error in the control signal.

3. The electronic system according to claim 2, further comprising: The fault collection circuit is configured as follows: The data error detection signal is received from the ECC decoder. Receive the control signal error detection signal from the inspector circuit, and In response to the data error detection signal and the control signal error detection signal, a fault detection signal for the electronic system is selectively output.

4. The electronic system according to claim 1, wherein, The first control signal path is configured to output the first signal based on the third signal input to the main IP, and The second control signal path is configured to output the second signal based on a fourth signal, which is input to the checker IP and delayed by a specific clock cycle relative to the third signal. The error detection circuit is configured to detect errors in the control signal by comparing a fifth signal with a second signal, wherein the fifth signal is delayed by a specific clock cycle relative to the first signal.

5. The electronic system according to claim 4, further comprising: A first delay circuit is configured to generate the fourth signal by delaying the third signal by the specific clock cycle; as well as The second delay circuit is configured to generate the fifth signal by delaying the first signal by the specific clock cycle.

6. The electronic system according to claim 1, further comprising: The ECC encoder is configured as follows: Encoded data is generated by performing ECC encoding on the input data, and The encoded data is provided to the master IP.

7. The electronic system according to claim 6, wherein, The encoded data includes the input data and the checker data to be generated based on the input data.

8. The electronic system according to claim 1, wherein, The second control signal path includes the same circuit elements as the first control signal path.

9. The electronic system according to claim 1, wherein, The inspector IP also includes a second data path, which is generated through boundary optimization after the first data path has been copied and all inputs have been bounded.

10. The electronic system according to claim 9, wherein, In the second data path, the inputs of the second data path and the outputs of the second data path that depend on the inputs are omitted.

11. The electronic system according to claim 9, wherein, The electronic system is implemented as a system-on-a-chip, and The second data path occupies a smaller circuit area on the chip of the system-on-a-chip than the first data path occupies on the chip of the system-on-a-chip.

12. The electronic system according to claim 1, wherein, All of the main IP, the checker IP, and the error detection circuitry are configured to operate in a single clock domain.

13. A method for detecting faults in an electronic system, the electronic system comprising a first intellectual property (IP) and a second IP, the method comprising: Errors in the input data are detected by performing ECC decoding on the output data from the first data path of the first IP. as well as Errors in the control signals are detected based on a first signal output from a first control signal path of the first IP and a second signal output from a second control signal path of the second IP.

14. The method according to claim 13, wherein, Errors detected in the control signal include: A third signal is generated by delaying the first signal by a specific clock cycle; and Based on the comparison between the third signal and the second signal, an error detection signal for the control signal is output.

15. The method of claim 14, further comprising: Based on the fourth signal, the first IP outputs the first signal through the first control signal path; The fifth signal is generated by delaying the fourth signal by the specific clock cycle; as well as Based on the fifth signal, the second IP outputs the second signal through the second control signal path.

16. The method of claim 13, further comprising: Encoded data is generated by performing ECC encoding on the input data; as well as Based on the encoded data, the first IP outputs the output data through the first data path.

17. The method according to claim 13, wherein, The second IP also includes a second data path, which is generated through boundary optimization after the first data path is copied and then all inputs are bound.

18. The method according to claim 17, wherein, In the second data path, the inputs of the second data path and the outputs of the second data path that depend on the inputs are omitted.

19. A system-on-a-chip, comprising: An error correction code (ECC) encoder is configured to generate encoded data by performing ECC encoding on the input data; The main intellectual property (IP) is configured to receive the encoded data and a first control signal, and to output output data through a first data path based on the encoded data, and to output a second control signal through a first control signal path based on the first control signal. The first delay circuit is configured to generate a third control signal by delaying the first control signal by a specific clock cycle; The inspector IP is configured to output a fourth control signal based on the third control signal via the second control signal path; The ECC decoder is configured to output a data error detection signal by performing ECC decoding on the output data; The second delay circuit is configured to generate a fifth control signal by delaying the second control signal by the specific clock period; as well as The checker circuit is configured to detect errors in the control signals by comparing the fourth control signal with the fifth control signal.

20. The system-on-a-chip according to claim 19, further comprising: The fault collection circuit is configured to output a fault detection signal about the system-on-chip in response to the data error detection signal received from the ECC decoder and the control signal error detection signal received from the checker circuit.

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