memory cell

Abstract

A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor electrodes with a ferroelectric material therebetween. The capacitor has an intrinsic current leakage path from one of the capacitor electrodes through the ferroelectric material to the other capacitor electrode. There is a parallel current leakage path from the one capacitor electrode to the other capacitor electrode. The parallel current leakage path circuit is parallel to the intrinsic path and has a lower total resistance than the intrinsic path. Other aspects are disclosed.

Description

[0001] Information related to divisional application

[0002] This case is a divisional application. The parent application of this divisional application is the invention patent application filed on January 13, 2016, with application number 201680010690.6 and invention title "Memory Unit". Technical Field

[0003] The embodiments disclosed herein relate to memory cells. Background Technology

[0004] Memory is a type of integrated circuit used in computer systems to store data. Memory can be manufactured as one or more arrays of individual memory cells. Memory cells can be written to or read from using digital lines (also called bit lines, data lines, sense lines, or data / sense lines) and access lines (also called word lines). Digital lines electrically interconnect memory cells along the columns of the array, and access lines electrically interconnect memory cells along the rows of the array. Each memory cell can be uniquely addressed by a combination of digital lines and access lines.

[0005] Memory cells can be volatile or non-volatile. Non-volatile memory cells can store data for extended periods, including when the computer is off. Volatile memory dissipates data and therefore, in many instances, needs to be refreshed / rewritten multiple times per second. Regardless, memory cells are configured to hold or store memory in at least two distinct selectable states. In binary systems, the state is considered as "0" or "1". In other systems, at least some individual memory cells can be configured to store more than two levels or states of information.

[0006] A capacitor is a type of electronic component that can be used in memory cells. A capacitor has two electrical conductors separated by an electrically insulating material. Energy, as an electric field, can be stored electrostatically within this material. One type of capacitor is a ferroelectric capacitor, which has at least a portion of ferroelectric material as the insulating material. Ferroelectric materials are characterized by having two stable polarization states. The polarization state of the ferroelectric material can be changed by applying a suitable programming voltage and remains thereafter (at least for a period of time). Each polarization state has a charge storage capacitance different from the other polarization state, and can ideally be used to write (i.e., store) and read the memory state without reversing the polarization state, until it is desired to reverse the polarization state. Less desirable is that in a memory with a ferroelectric capacitor, the act of reading the memory state reverses the polarization. Therefore, after the polarization state is determined, the memory cell is rewritten to immediately put the memory cell into a pre-fetch state after its determination. In any case, memory cells incorporated with ferroelectric capacitors are ideally non-volatile due to the bistable nature of the ferroelectric material forming the capacitor portion.

[0007] One type of memory cell has a selection device electrically coupled in series with a ferroelectric capacitor. Even when the selection device is idle (i.e., when it is not in operation or "off"), current typically leaks through the selection device to the adjacent substrate material. This causes a voltage drop at the adjacent electrodes of the ferroelectric capacitor, thus creating a voltage difference between the two capacitor electrodes. This results in an electric field being applied across the ferroelectric material when the memory cell is idle. Even a small electric field can cause individual dipoles in the ferroelectric material to begin flipping until all dipoles are flipped, thereby erasing the programmed state of the memory cell. This can happen in a short time, thereby compromising or hindering the non-volatility of the memory cell. Summary of the Invention

[0008] One aspect of this application relates to a memory cell comprising: a selection device; and a capacitor coupled to the selection device, the capacitor including a first electrode and a second electrode, the capacitor having a first current leakage path through a ferroelectric material between the first electrode and the second electrode, and the capacitor having a second current leakage path through an amorphous semiconductor material between the first electrode and the second electrode, the ferroelectric material comprising materials derived from zirconium, zirconium oxide, hafnium, barium strontium titanate, and Hf. x Si y O z and Hf x Zr y O z One or more materials selected from the group consisting of, wherein the one or more materials are optionally doped with dopants, the dopants including one or more of the group consisting of silicon, aluminum, lanthanum, yttrium, erbium, calcium, magnesium, strontium and rare earth elements.

[0009] Another aspect of this application relates to a memory cell comprising: a selection device; and a capacitor coupled to the selection device, the capacitor including a first electrode and a second electrode, the capacitor having a first current leakage path through a ferroelectric material between the first electrode and the second electrode, and the capacitor having a second current leakage path through germanium between the first electrode and the second electrode, the ferroelectric material comprising materials derived from zirconium, zirconium oxide, hafnium, barium strontium titanate, and Hf. x Si y O z and Hf x Zr y O z One or more materials selected from the group consisting of; wherein the one or more materials are optionally doped with dopants, the dopants including one or more of the group consisting of silicon, aluminum, lanthanum, yttrium, erbium, calcium, magnesium, strontium and rare earth elements.

[0010] Another aspect of this application relates to a memory cell comprising: a selection device; and a capacitor coupled to the selection device, the capacitor including a first electrode and a second electrode, the capacitor having a first current leakage path through a ferroelectric material between the first electrode and the second electrode, and the capacitor having a second current leakage path through a metal dichalcogenide between the first electrode and the second electrode, the second current leakage path having a second total resistance less than the first total resistance, the ferroelectric material comprising zirconium, zirconium oxide, hafnium, barium strontium titanate, and Hf. x Si y O z and Hf x Zr y O z One or more materials selected from the group consisting of; wherein the one or more materials are optionally doped with dopants, the dopants including one or more of the group consisting of silicon, aluminum, lanthanum, yttrium, erbium, calcium, magnesium, strontium and rare earth elements.

[0011] Another aspect of this application relates to a memory cell comprising: a selection device; and a capacitor coupled to the selection device, the capacitor including a first electrode and a second electrode, the capacitor having a first current leakage path through a ferroelectric material between the first electrode and the second electrode, and the capacitor having a second current leakage path through one or more of silicon-rich silicon nitride and silicon-rich silicon oxide between the first electrode and the second electrode, the ferroelectric material comprising materials derived from zirconium, zirconium oxide, hafnium, barium strontium titanate, and Hf. x Si y O z and Hf x Zry O z One or more materials selected from the group consisting of; wherein the one or more materials are optionally doped with dopants, the dopants including one or more of the group consisting of silicon, aluminum, lanthanum, yttrium, erbium, calcium, magnesium, strontium and rare earth elements.

[0012] Another aspect of this application relates to a memory cell comprising: a selection device; and a capacitor coupled to the selection device, the capacitor including a first electrode and a second electrode, the capacitor having a first current leakage path through a ferroelectric material between the first electrode and the second electrode, and the capacitor having a second current leakage path through an intrinsic dielectric material between the first electrode and the second electrode, the intrinsic dielectric material comprising at least one of SiO2 and Si3N4 doped with one or more of Ti, Ta, Nb, Mo, Sr, Y, Cr, Hf, Zr and lanthanide ions, and the ferroelectric material comprising materials derived from zirconium, zirconium oxide, hafnium, barium strontium titanate, and Hf. x Si y O z and Hf x Zr y O z One or more materials selected from the group consisting of; wherein the one or more materials are optionally doped with dopants, the dopants including one or more of the group consisting of silicon, aluminum, lanthanum, yttrium, erbium, calcium, magnesium, strontium and rare earth elements.

[0013] Another aspect of this application relates to a memory array that includes memory cells. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of a memory cell according to an embodiment of the present invention.

[0015] Figure 2 This is a schematic cross-sectional view of a portion of a memory cell according to an embodiment of the present invention.

[0016] Figure 3 This is a schematic cross-sectional view of a portion of a memory cell according to an embodiment of the present invention.

[0017] Figure 4 This is a schematic cross-sectional view of a portion of a memory cell according to an embodiment of the present invention.

[0018] Figure 5 This is a schematic cross-sectional view of a portion of a memory cell according to an embodiment of the present invention.

[0019] Figure 6 yes Figure 5 A top view of the constructed memory cell.

[0020] Figure 7 This is a schematic cross-sectional view of a portion of a memory cell according to an embodiment of the present invention.

[0021] Figure 8 This is a schematic cross-sectional view of a portion of a memory cell according to an embodiment of the present invention.

[0022] Figure 9 This is a schematic cross-sectional view of a portion of a memory cell according to an embodiment of the present invention.

[0023] Figure 10 yes Figure 9 A top view of the constructed memory cell. Detailed Implementation

[0024] Reference illustration Figure 1 The present invention will first illustrate and describe a memory cell 10 according to an embodiment of the invention. An integrated circuit (not shown) having memory cells 10 may have thousands or millions of such memory cells fabricated relative to a memory array or subarray, and is not particularly material for the purposes of this disclosure. Such an array or subarray may have multiple access lines and select lines, with individual memory cells 10 at their intersections. An individual memory cell may be considered to include portions constituting the individual access line and the intersection of the individual select line.

[0025] Memory cell 10 includes a selection device 12 and, for example, a capacitor 14 electrically coupled in series (i.e., circuit) to the selection device 12 via a conductive (i.e., electrical) path 16, as shown. In the depicted diagram, capacitor 14 can be considered as including two conductive capacitor electrodes 18 and 20 having a ferroelectric material 19 between them. Physically, path 16 may be simply a single electrode shared by capacitor 14 and selection device 12. Capacitor 14 includes an intrinsic current (i.e., electrical) leakage path from one of capacitor electrodes 18 or 20 through the ferroelectric material 19 to the other capacitor electrode. For clarity, Figure 1 This intrinsic path is schematically shown as a dashed line in path 22 running around the ferroelectric material 19. However, in reality, path 22 intrinsically / inherently passes through the ferroelectric material 19 to each of the capacitor electrodes 18 and 20, and lies between each of the capacitor electrodes 18 and 20. Intrinsic path 22 will have a relatively high overall / total resistance (i.e., electrical), which is schematically indicated as resistor 24 when the device 14 is used as a capacitor in operation. The total resistance of resistor 24 will depend on the composition of the ferroelectric material 19, the thickness of the ferroelectric material 19, and the dipole orientation within the ferroelectric material 19. Resistor 24 may inherently be a nonlinear / variable resistor, thereby having a voltage-dependent resistance.

[0026] Memory cell 10 includes a parallel (i.e., circuitally parallel) current leakage path 26 from one capacitor electrode 18 or 20 to another capacitor electrode. In one embodiment, the parallel path 26 has a dominant bandgap of 0.4 eV to 5.0 eV, and in one embodiment, the dominant bandgap is smaller than the dominant bandgap of the ferroelectric material 19. If the length of the parallel path 26 is much shorter than that of path 24, then this dominant bandgap may be larger than the dominant bandgap of the ferroelectric material 19. In any case, in one embodiment, the parallel path 26 has a certain total resistance (e.g., shown as resistor 28) lower than the total resistance of the intrinsic path 22. By way of example only, the total resistance through the intrinsic leakage path 22 may be 1 × 10⁻⁶. 11 Ohms to 1×10 18 Ohms, and the total resistance through parallel leakage path 26 can be 1×10 9 Ohms to 1×10 17 ohm.

[0027] The selection device 12 can be any existing or developing selection device, comprising multiple devices. Examples include diodes, field-effect transistors, and bipolar transistors. In operation, when the memory cell is idle (i.e., when the integrated circuit associated with memory cell 10 is operationally "on" but no "read" or "write" operation occurs on memory cell 10), the selection device 12 will exhibit current leakage. A selection device current leakage path 30 exists and is schematically shown as a dashed line around the selection device 12, but this path will intrinsically / inherently pass through the selection device 12 or reach the underlying substrate (e.g., held at ground or other potential). The leakage path 30 is shown with a total resistance 32. In one embodiment, the parallel path 26 is configured such that the current through the memory cell 10 when idle is greater than or equal to the current leakage through path 30 when the memory cell 10 is idle. This will depend on the construction and materials of the selection device 12, capacitor 14, and parallel path 26, and on the voltage at various points within the memory cell 10 during normal operation. Ideally and in any case, this makes the voltages at electrodes 18 and 20 equal or at least very close to each other when idle (e.g., the difference is within 50 millivolts), thereby preventing or eliminating the generation of an electric field within the ferroelectric material 19 when the memory cell 10 is idle. For example and further, any voltage difference across the capacitor during idle ideally results in any electric field in the ferroelectric material 19 being at least 20 times lower than the intrinsic coercive field of the ferroelectric material 19. This eliminates unwanted dipole direction changes within the ferroelectric material 19. Alternatively, as an example, this at least reduces the time risk or increases the time before unwanted dipole direction changes occur within the ferroelectric material 19.

[0028] In one embodiment, resistor 28 in parallel path 26 is a nonlinear resistor between capacitor electrodes 18 and 20, exhibiting a higher total resistance at higher voltages (e.g., between 1 and 5 volts) than at lower voltages (e.g., less than 250 millivolts). Ideally, this nonlinear resistor is configured to tend to provide a reduction in current leakage in parallel path 26 during higher voltage "read" and "write" operations when the lower voltage is idle.

[0029] Access lines and select lines (neither shown) may be associated with memory cells 10. For example, select device 12 may be a simple two-terminal diode or other two-terminal device. A cross-point array may then be used to connect, or a portion thereof, a conductive path 11, which is part of capacitor electrode 18, to an access line or select line (not shown), and a conductive path 13, which is part of select device 12, to another access line or select line (not shown), or a portion thereof. As an alternative example, select device 12 may be a field-effect transistor. Next, as an example, conductive path 11 may be a portion of capacitor electrode 18 shared by multiple capacitors 14 (not shown) within the memory array or subarray, component 16 may be one source / drain region of the transistor, and component 13 may be another source / drain region of the transistor. The source (not shown) of the transistor can be a portion of the access line (not shown), and the source / drain assembly 13 can be connected to a portion of the sensing line (not shown), or can be a portion of the sensing line (not shown). Of course, other architectures and constructions can be used alternatively.

[0030] Figure 2 An example physical construction of a portion of a memory cell 10, including capacitor 14 and parallel current leakage path 26, is schematically shown. Where appropriate, the same element symbols from the above embodiments have been used, with different element symbols used to indicate some differences. A selection device 12 (not shown) may be electrically coupled to either capacitor electrode 18 or 20. Material will be located on both sides, inside and outside the facade of the memory cell construction 10. For example, other parts or all of the fabrication components of the integrated circuit may be provided at a location surrounding the construction 10 and are not particularly closely related to the invention disclosed herein (except for including any suitable selection device 12, such as...). Figure 1 (As shown in the diagram).

[0031] Examples of conductive materials used for capacitor electrodes 18 and 20 include one or more of elemental metals, alloys of two or more elemental metals, conductive metal compounds, and conductive doped semiconducting materials. Example ferroelectric material 19 includes a ferroelectric material having one or more of transition metal oxides, zirconium, zirconium oxide, hafnium, hafnium oxide, lead zirconium titanate, and barium strontium titanate, and may contain dopants including one or more of silicon, aluminum, lanthanum, yttrium, erbium, calcium, magnesium, strontium, and rare earth elements. Two specific examples are Hf... x Si y O z and Hf x Zr y O z Unless otherwise indicated, any of the materials and / or structures described herein may be homogeneous or heterogeneous, and in any event, may be continuously or discontinuously deposited on any material. Furthermore, unless otherwise indicated, any suitable existing or developing technique (e.g., atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation) may be used to form each material. Examples of the thickness of each of capacitor electrodes 18 and 20 are 25 to 300 angstroms, while examples of the thickness of ferroelectric material 19 are 15 to 200 angstroms. In this invention, “thickness” itself (not the preceding directional adjective) is defined as the average straight-line distance perpendicular to the nearest surface of an adjacent material or region of a different composition through a given material or region. Additionally, the various materials described herein may have substantially constant thickness or variable thickness. If variable thickness is present, then unless otherwise indicated, the thickness refers to the average thickness.

[0032] Parallel path 26 is shown to be surrounded by or located within material 34. Example material 34 comprises one or more intrinsic dielectric materials suitable for doping with conductivity-enhancing dopants (e.g., SiO2 and / or Si3N4 doped with Ti, Ta, Nb, Mo, Sr, Y, Cr, Hf, Zr, and lanthanide ions). Material 34 and thus parallel path 26 may primarily (i.e., greater than 50 atomic percent) comprise such materials. Any of these materials may be doped or undoped to provide a desired total resistance to leakage of current flowing through the memory cell 10 when it is idle. In one embodiment, material 34 is homogeneous, thereby making parallel path 26 between capacitor electrodes 18 and 20 homogeneous. In one embodiment, material 34 is heterogeneous, thereby making parallel path 26 between capacitor electrodes 18 and 20 heterogeneous. In embodiments where material 34 and parallel path 26 are heterogeneous, parallel path 26 may be attributed to having multiple band gaps due to the different composite materials within it having different band gaps. However, parallel path 26 will have a dominant (meaning controlling) band gap of 0.4 eV to 5.0 eV, depending on the respective capacity of the individual different materials within parallel path 26. Therefore, and in any case, "dominant" is used and applied herein, regardless of the homogeneity of a particular path / material. In one embodiment, the dominant band gap of ferroelectric material 19 may be lower than the dominant band gap of parallel path 26. In one embodiment, the minimum length of parallel path 26 is made longer than the minimum thickness of ferroelectric material 19. As an example, this length relationship can be used when the dominant band gaps of ferroelectric material and parallel path are approximately the same, provided that the density of states in parallel path is equal to or greater than the density of states in ferroelectric material. As another example, this length relationship can be used when the dominant band gap of ferroelectric material is smaller than the dominant band gap of parallel path, provided that the density of states in parallel path is equal to or greater than the density of states in ferroelectric material.

[0033] In one embodiment and as follows Figure 2As shown, material 34 and thereby parallel path 26 directly abut against ferroelectric material 19. In this invention, a material or structure "directly abuts" another material or structure when the stated materials or structures are in at least one physical contact with each other. In contrast, the preceding terms "above," "on," and "abut" without the prefix "directly" encompass "direct abutment" as well as configurations in which the intervention of a material or structure results in non-physical contact between the stated materials or structures. If the two stated materials are not directly abutting each other, then materials with different compositions are present in between. As used herein, for example, if such materials are heterogeneous, then "different compositions" only require that portions of the two stated materials that can directly abut each other be chemically and / or physically different. If the two stated materials are not directly abutting each other, then "different compositions" only require that: if such materials are heterogeneous, then portions of the two closest stated materials are chemically and / or physically different. Figure 3 An alternative embodiment of memory cell 10a is depicted, wherein the parallel path 26 does not directly contact the ferroelectric material 19a. Where appropriate, the same element symbols from the above embodiments have been used, wherein the suffix "a" or different element symbols are used to indicate some construction differences. Capacitor 14a is shown to include a material 21 (e.g., a dielectric material, such as silicon dioxide and / or silicon nitride) spaced between materials 34 and 19a, whereby the parallel path 26 does not directly contact the ferroelectric material 19a. Any other properties or constructions as described above may be used.

[0034] Figure 4 Another example embodiment of memory cell 10b is shown. Where appropriate, the same element symbols from the above embodiments have been used, with the suffix "b" or different element symbols used to indicate some construction differences. Material 34b (and thus parallel path 26b) in memory cell 10b is essentially shown passing through ferroelectric material 19b, thereby forming an internal portion of capacitor configuration 14b and having two lateral sides 35 (i.e., in at least one straight cross-section), each of the two lateral sides 35 directly abutting against ferroelectric material 19b. Any other properties or configurations as described above may be used.

[0035] The parallel current leakage path may have a minimum length equal to, greater than, or less than the minimum thickness of the ferroelectric material between the two capacitor electrodes. In one embodiment, the parallel path has a minimum length within 5% of the minimum thickness of the ferroelectric material between the two capacitor electrodes. Figures 2 to 4 Essentially, parallel path 26 is represented as a minimum length having a minimum thickness substantially equal to that of the ferroelectric material 19 / 19a / 19b. For example, even in... Figure 2 and Figure 3In this embodiment, the shortest path (e.g., minimum length) through material 34 is from the bottom right corner of the material of capacitor electrode 18 to the top right corner of the material of electrode 20, but for clarity, Figure 2 and 3 Parallel path 26 is schematically shown as a wide arched path passing through material 34. In some embodiments, the parallel path may have a minimum length greater than the minimum thickness of the ferroelectric material between the two capacitor electrodes, in one embodiment it is within 30% of the minimum thickness of the ferroelectric material between the two capacitor electrodes, and in another embodiment it is at least twice the minimum thickness of the ferroelectric material between the two capacitor electrodes.

[0036] Figure 5 and 6 Another example embodiment of memory cell 10c is shown. Where appropriate, the same element symbols from the above embodiments have been used, with the suffix "c" or different element symbols used to indicate some construction differences. Capacitor 14c includes a first conductive capacitor electrode 20c having a substrate 40 and laterally spaced (i.e., in at least one straight cross-section) walls 42 extending from the substrate 40. The lateral spacer walls 42 have opposing side surfaces 43. A second conductive capacitor electrode 18c is laterally located between the walls 42 of the first capacitor electrode 20c. Ferroelectric material 19c is laterally located between the walls 42 of the first capacitor electrode 20c and laterally located between the second capacitor electrode 18c and the first capacitor electrode 20c. In one embodiment, the ferroelectric material 19c includes a lateral spacer wall 45 having a side surface 44. Figure 5 The capacitor 14c includes an intrinsic current leakage path 22 from one of the first capacitor electrode 20c and the second capacitor electrode 18c through the ferroelectric material 19c to the other capacitor electrode.

[0037] A parallel current leakage path 26c lies between the second capacitor electrode 18c and the surface 41 of the substrate 40 of the first capacitor electrode 20c. The parallel path 26 circuit is parallel to the intrinsic path 22 and has a lower total resistance than the intrinsic path 22. In one embodiment, the parallel path 26c lies within and passes through a material 34c having a dominant bandgap of 0.4 eV to 5.0 eV, and in one embodiment, its bandgap is smaller than that of the ferroelectric material 19c. Figure 5The illustrated embodiment shows a minimum length of parallel path 26c that is twice the minimum thickness of ferroelectric material 19c. In one embodiment, material 34c directly abuts the surface 41 of the substrate 40 of the first capacitor electrode 42. In another embodiment, material 34c directly abuts the side surface 44 of the lateral spacer wall 45 of the ferroelectric material 19c. Selection device 12 (not shown) is electrically coupled in series with capacitor 14c, specifically, in series with one of the first capacitor electrode 20c or the second capacitor electrode 18c. In one embodiment, and as shown, material 34c does not directly abut the side surface 43 of the lateral spacer wall 42 of the first capacitor electrode 20c. In one embodiment, and as shown, the first capacitor electrode 20c includes an annulus 48, and in one embodiment, the ferroelectric material 19c includes an annulus 50. Any other properties or constructions as described above may be used.

[0038] Any suitable technology can be used for manufacturing. Figure 5 and 6 Construction. As an example, a first capacitor electrode 20c and a ferroelectric material 19c can be formed as corresponding liner layers within an opening in a dielectric material (not shown). Next, the ferroelectric material 19c can be anisotropically etched through the substrate of the first capacitor electrode 20c to produce a structure such as... Figure 5 The structure of material 19c is shown in the figure. Next, material 34c can be deposited and etched back to produce, as shown in the figure. Figure 5 The structure shown in the figure is followed by the deposition and re-splashing or re-etching of material 18c.

[0039] Figure 7 Depicting by Figure 5 and 6 An alternative embodiment of the memory cell shown is memory cell 10d. Where appropriate, the same element symbols from the above embodiments have been used, with the suffix "d" or different element symbols used to indicate some construction differences. Ferroelectric material 19d has a substrate 54 from which lateral spacer walls 45 extend. Material 34d extends through the substrate 54 of ferroelectric material 19d. In one embodiment, and as shown, material 34d does not directly abut against the lateral side surface 44 of the lateral spacer walls 45 of ferroelectric material 19d. Selection device 12 (not shown) is electrically coupled in series with capacitor 14d, specifically, electrically coupled to one of capacitor electrodes 18d or 20c. Of course, any suitable technique can be used to manufacture it. Figure 7Construction. For example, a first capacitor electrode 20c and a ferroelectric material 19d can be formed as corresponding liner within an opening in a dielectric material (not shown). Next, material 18d can be formed first as a liner within the remaining opening, having the ferroelectric material 19d as its sidewalls and leaving a void space with a lateral width equal to the lateral width of material 34d. Then, the material 18d liner can be anisotropically etched through the substrate of the ferroelectric material 19d. This etching then continues through the substrate of the ferroelectric material 19d to material 20c to produce... Figure 7 The final structure of material 19d is shown in the figure. Next, material 34d may be deposited and etched back to produce its final structure, followed by deposition and splattering or etching back of the remaining material 18d. Any other properties or structures as described above may be used.

[0040] Figure 8 Another embodiment of memory cell 10e is shown. Where appropriate, the same element symbols from the above embodiments have been used, with the suffix "e" or different element symbols used to indicate some construction differences. Regardless of whether it has a substrate 40, the first capacitor electrode 20c has a lateral spacer wall 42. A parallel current leakage path 26e within the material 34e lies between the second capacitor electrode 18c and the surface 60 of the lateral spacer wall 42 of the first capacitor electrode 20c. In one embodiment and as shown, the surface 60 includes the lateral side surfaces of the lateral spacer wall 42 of the first capacitor electrode 20c. However, in one embodiment and as shown, the material 34e directly abuts the surface 60 of the wall 42 of the first capacitor electrode 20c. In one embodiment where the first capacitor electrode 20c has a substrate 40 (from which the lateral spacer wall 42 extends), the material 34e may directly abut the surface 61 of the substrate 40 of the first capacitor electrode 20c. The selection device 12 (not shown) will be electrically coupled in series with the capacitor 14e, specifically, electrically coupled to one of the capacitor electrodes 18c or 20c. Of course, any suitable technology can be used for manufacturing. Figure 8 Construction. For example, a first capacitor electrode 20c can be formed as a liner within an opening in a dielectric material (not shown). Next, material 34e can be deposited and etched back to create its construction, as... Figure 8 As shown in the diagram. This can then be followed by depositing a ferroelectric material 19e as a liner within the remaining opening and subsequently anisotropically etching it through the substrate of material 19e. Next, material 18c can be deposited and etched back into its final, depicted configuration. Any other properties or configurations as described above can be used.

[0041] Figure 9 and 10Another embodiment of memory cell 10f is shown. Where appropriate, the same element symbols from the above embodiments have been used, with the suffix "f" or different element symbols used to indicate some construction differences. The main similarity between memory cell 10f and memory cell 10e is that the parallel current leakage path 26f lies between the surfaces of the second capacitor electrode 18f and the lateral spacer wall 42 of the first capacitor electrode 20c. However, in memory cell 10f, this surface includes the vertical outermost surface 65 of the lateral spacer wall 42 of the first capacitor electrode 20c. Furthermore, in one embodiment and as shown, material 34f directly abuts the vertical outermost surface 66 of the ferroelectric material 19f. Furthermore, in one embodiment and as shown, material 34f includes an annulus 70. Of course, any suitable technique can be used to manufacture it. Figure 9 and 10 Construction. For example, a first capacitor electrode 20c and a ferroelectric material 19f can be formed as corresponding liner within the opening in the dielectric material (not shown). Next, material 18f can be deposited to fill the remaining opening having the ferroelectric material 19f as its sidewall. Then, materials 20c, 19f, and 18f can be etched back or polished together to heights 65 and 66. Next, material 34f can be deposited as a liner within the remaining opening, and subsequently, material 34f can be anisotropically etched through its substrate to produce, as... Figure 9 and 10 The final structure shown is illustrated in the diagram. Next, the remaining material 18f can be deposited and then sapped or etched back to the final structure depicted. Any other properties or structures as described above may be used.

[0042] In one embodiment, a memory cell (e.g., 10e or 10f) has a first capacitor electrode 20c including a ring 48. A second capacitor electrode 18c / 18f is radially located within the ring 48 of the first capacitor electrode 20c. Ferroelectric material 19e / 19f is radially located within the ring 48 of the first capacitor electrode 20c. A capacitor 14e / 14f includes an intrinsic current leakage path 22 from one of the first and second capacitor electrodes through the ferroelectric material 19e / 19f to the other capacitor electrode. A parallel current leakage path 26e / 26f is located between the surfaces of the second capacitor electrode 18c / 18f and the ring 48 of the first capacitor electrode 20c. The circuitry of the parallel path 26e / 26f is parallel to the intrinsic path 22 and has a lower total resistance than the intrinsic path 22.

[0043] In one embodiment, material 34f includes an annulus 70. In one embodiment, material 34f directly abuts the upright outermost surface 65 of annulus 48. In one embodiment, ferroelectric material 19f includes an annulus 50f, and material 34f directly abuts the upright outermost surface 66 of annulus 50f. Any other properties or constructions as described above may be used.

[0044] Summarize

[0045] In some embodiments, a memory cell includes a selection device and a capacitor electrically coupled in series with the selection device. The capacitor includes two conductive capacitor electrodes having a ferroelectric material between them. The capacitor includes an intrinsic current leakage path from one of the capacitor electrodes through the ferroelectric material to the other capacitor electrode. A parallel current leakage path exists from the capacitor electrode to the other capacitor electrode. The parallel current leakage path circuit is parallel to the intrinsic path and has a lower total resistance than the intrinsic path.

[0046] In some embodiments, a memory cell includes a selection device and a capacitor electrically coupled in series with the selection device. The capacitor includes two conductive capacitor electrodes having a ferroelectric material between them. The capacitor includes an intrinsic current leakage path from one of the capacitor electrodes through the ferroelectric material to the other capacitor electrode. A parallel current leakage path exists from the capacitor electrode to the other capacitor electrode. The parallel current leakage path circuit is parallel to the intrinsic path and has a dominant bandgap of 0.4 eV to 5.0 eV.

[0047] In some embodiments, a memory cell includes a selection device and a capacitor electrically coupled in series with the selection device. The capacitor includes a first conductive capacitor electrode having a substrate and laterally spaced walls extending from the substrate. A second conductive capacitor electrode is laterally located between the walls of the first capacitor electrode. A ferroelectric material is laterally located between the walls of the first capacitor electrode and laterally located between the second capacitor electrode and the first capacitor electrode. The capacitor includes an intrinsic current leakage path from one of the first capacitor electrode and the second capacitor electrode through the ferroelectric material to the other capacitor electrode. A parallel current leakage path exists between the surfaces of the substrates of the second capacitor electrode and the first capacitor electrode. The parallel current leakage path circuit is parallel to the intrinsic path and has a lower total resistance than the intrinsic path.

[0048] In some embodiments, a memory cell includes a selection device and a capacitor electrically coupled in series with the selection device. The capacitor includes a first conductive capacitor electrode having lateral spacer walls. A second conductive capacitor electrode is laterally located between the walls of the first capacitor electrode. A ferroelectric material is laterally located between the walls of the first capacitor electrode and laterally located between the second capacitor electrode and the first capacitor electrode. The capacitor includes an intrinsic current leakage path from one of the first capacitor electrode and the second capacitor electrode through the ferroelectric material to the other capacitor electrode. A parallel current leakage path exists between the surfaces of the lateral spacer walls of the second capacitor electrode and the first capacitor electrode. The parallel current leakage path circuit is parallel to the intrinsic path and has a lower total resistance than the intrinsic path.

[0049] In some embodiments, a memory cell includes a selection device and a capacitor electrically coupled in series with the selection device. The capacitor includes a first conductive capacitor electrode comprising a ring. A second conductive capacitor electrode is radially located within the ring of the first capacitor electrode. A ferroelectric material is radially located within the ring of the first capacitor electrode between the second capacitor electrode and the first capacitor electrode. The capacitor includes an intrinsic current leakage path from one of the first and second capacitor electrodes through the ferroelectric material to the other capacitor electrode. A parallel current leakage path exists between the surfaces of the rings of the second and first capacitor electrodes. The parallel current leakage path circuit is parallel to the intrinsic path and has a lower total resistance than the intrinsic path.

[0050] While complying with regulations, the subject matter disclosed herein has been described in language more or less specific to structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the components disclosed herein include exemplary embodiments. Therefore, the claims should be given the full scope as literal and should be properly interpreted in accordance with the teachings of the equivalents.

Claims

1. A memory cell comprising: a selection device; and A capacitor coupled to the selection device, the capacitor comprising a first electrode and a second electrode, the capacitor having a first current leakage path between the first electrode and the second electrode through a ferroelectric material, the first current leakage path having a first total resistance, the capacitor having a second current leakage path between the first electrode and the second electrode through a region consisting primarily of amorphous silicon, the second current leakage path having a second total resistance less than the first total resistance, the ferroelectric material comprising one or more materials selected from the group consisting of zirconium, zirconium oxide, hafnium, barium strontium titanate, Hf x Si y O z and Hf x Zr y O z wherein the one or more materials are optionally doped with a dopant comprising one or more selected from the group consisting of silicon, aluminum, calcium, magnesium, strontium, and a rare earth element, wherein the second current leakage path has a minimum length within 5% of a minimum thickness of the ferroelectric material between the first electrode and the second electrode.

2. A memory cell comprising: a selection device; and a capacitor coupled to the selection device, the capacitor including a first electrode and a second electrode, the capacitor having a first current leakage path through a ferroelectric material between the first electrode and the second electrode, the first current leakage path having a first total electrical resistance, the capacitor having a second current leakage path through germanium between the first electrode and the second electrode, the second current leakage path having a second total electrical resistance that is less than the first total electrical resistance, the ferroelectric material including one or more materials selected from the group consisting of zirconium, zirconium oxide, hafnium, barium strontium titanate, Hf x Si y O z and Hf x Zr y O z and Hf; and wherein the one or more materials are optionally doped with a dopant including one or more selected from the group consisting of silicon, aluminum, calcium, magnesium, strontium, and rare earth elements, wherein the second current leakage path has a minimum length that is within 5% of a minimum thickness of the ferroelectric material between the first electrode and the second electrode.

3. A memory cell comprising: a selection device; and a capacitor coupled to the selection device, the capacitor comprising a first electrode and a second electrode, the capacitor having a first current leakage path through a ferroelectric material between the first electrode and the second electrode, the first current leakage path having a first total electrical resistance, the capacitor having a second current leakage path through a metal dichalcogenide between the first electrode and the second electrode, the second current leakage path having a second total electrical resistance that is less than the first total electrical resistance, the ferroelectric material comprising one or more materials selected from the group consisting of zirconium, zirconium oxide, hafnium, barium strontium titanate, Hf x Si y O z and Hf x Zr y O z and wherein the one or more materials are optionally doped with a dopant comprising one or more selected from the group consisting of silicon, aluminum, calcium, magnesium, strontium, and rare earth elements, wherein the second current leakage path has a minimum length that is within 5% of a minimum thickness of the ferroelectric material between the first electrode and the second electrode.

4. A memory cell comprising: a selection device; and a capacitor coupled to the selection device, the capacitor comprising a first electrode and a second electrode, the capacitor having a first current leakage path through a ferroelectric material between the first electrode and the second electrode, the first current leakage path having a first total electrical resistance, the capacitor having a second current leakage path through one or more of silicon-rich silicon nitride and silicon-rich silicon oxide between the first electrode and the second electrode, the second current leakage path having a second total electrical resistance that is less than the first total electrical resistance, the ferroelectric material comprising one or more materials selected from the group consisting of zirconium, zirconium oxide, hafnium, barium strontium titanate, Hf x Si y O z and Hf x Zr y O z ; and wherein the one or more materials are optionally doped with a dopant comprising one or more selected from the group consisting of silicon, aluminum, calcium, magnesium, strontium, and rare earth elements, wherein the second current leakage path has a minimum length that is within 5% of a minimum thickness of the ferroelectric material between the first electrode and the second electrode.

5. A memory cell comprising: a selection device; and A capacitor coupled to the selection device, the capacitor comprising a first electrode and a second electrode, the capacitor having a first current leakage path through a ferroelectric material between the first electrode and the second electrode, the first current leakage path having a first total electrical resistance, the capacitor having a second current leakage path through an intrinsic dielectric material between the first electrode and the second electrode, the intrinsic dielectric material comprising at least one of SiO2 and Si3N4 doped with one or more of Ti, Ta, Nb, Mo, Sr, Y, Cr, Hf, Zr, and lanthanide ions, the second current leakage path having a second total electrical resistance less than the first total electrical resistance, the ferroelectric material comprising one or more materials selected from the group consisting of zirconium, zirconium oxide, hafnium, barium strontium titanate, Hf x Si y O z and Hf x Zr y O z and Hf; and wherein the one or more materials are optionally doped with a dopant comprising one or more from the group consisting of silicon, aluminum, calcium, magnesium, strontium, and rare earth elements, wherein the second current leakage path has a minimum length within 5% of a minimum thickness of the ferroelectric material between the first electrode and the second electrode.

6. A memory array comprising the memory cell of any one of claims 1-5.

Images