A data storage method and device for an LDPC decoder

Abstract

The present invention provides a data storage method and apparatus for an LDPC decoder. The method includes: setting up a memory RAM pool composed of a number of RAMs to store the soft information data to be decoded; setting the granularity of the RAM according to the code length and code rate supported by the LDPC decoder; setting the total number of rows of the RAM obtained by dividing the code length by the common factor of the order T of the cyclic submatrix as the depth of the RAM; and scheduling the RAMs in the RAM pool based on the currently to-be-decoded code length, code rate, and according to a predetermined logic to cache the corresponding soft information data to be decoded. In the present invention, the size of the unit sub-RAM is set according to various code lengths of LDPC, with a more reasonable size and a higher utilization rate of the unit RAM; adopting a RAM pool instead of a simple ping-pong RAM group helps to dynamically allocate the combination of RAMs according to the code length, so as to meet the requirements of the RAM size under various code lengths, making the soft information storage RAM of LDPC modular, thus facilitating exhaustive verification, and the control of each RAM particle is simple and easy to implement a faster RAM.

Description

Technical Field

[0001] The present invention relates to the technical field of low-density parity check (LDPC) decoders, and in particular to a data storage method and device for an LDPC decoder. Background Art

[0002] Low-density parity check code (LDPC) is an optimal error correction code technology that can approach the Shannon limit and is widely used in modern communication systems. Considering area and efficiency, LDPC has a variety of decoding methods. The focus of the present invention is not on these different decoding methods, but on the ASIC implementation of these decoding methods. Whether it is DVB-S2, WIFI, WIMAX or 5G communication, LDPC will be used as a codec, and for the sake of flexibility in use, these LDPCs include different code lengths and code rates. Since the LDPC decoder requires memory to cache the soft information to be decoded and store the intermediate iteration results, it is obvious to design the memory capacity according to the maximum code length. And because LDPC uses iterative decoding, most designs will use two memories plus a core decoding arithmetic unit to perform ping-pong structure alternating decoding. Its system structure is as follows Figure 1 shown. Summary of the invention

[0003] In view of this, the technical problem to be solved by the present invention is to provide a new data storage method and device for an LDPC decoder, so as to flexibly and efficiently dynamically allocate RAM resources to meet the requirements of various code lengths and code rates, thereby minimizing the waste of RAM resources.

[0004] The present invention provides a data storage method for an LDPC decoder, comprising:

[0005] A memory RAM pool consisting of 2L RAMs is set to store the soft information data to be decoded, where L is a natural number;

[0006] Set the RAM granularity according to the code length and code rate supported by the LDPC decoder, specifically:

[0007] Find the factor Cj of the order Ti of the circulant submatrix corresponding to each supported code length and code rate; where i and j are natural numbers;

[0008] Find the largest and closest common factor Cmax in the factor Cj except Ti itself. When the bit width of each soft information is K bits, set the number of bits stored in each row of the RAM to Cmax*K;

[0009] The total number of RAM rows Rmaxi is obtained by dividing the code length by Cmax, and the factor Ck of each Rmaxi is calculated. The common factor is found in the factor Ck, and the one closest to 2 is selected. n The common factor of is set as the RAM depth R;

[0010] Based on the current code length and code rate to be decoded and according to a predetermined logic, the RAM in the RAM pool is scheduled to cache the corresponding soft information data to be decoded.

[0011] More preferably, the RAMs in the RAM pool are arranged in a chain-ring structure.

[0012] Also includes:

[0013] The RAMs in the RAM pool are grouped into M groups, each group having N RAMs, where M*N=the total number of RAMs in the RAM pool; N is determined according to the current code length and code rate to be decoded.

[0014] Preferably, corresponding bits are set as chip selection indications according to the number of RAMs in the RAM pool; and corresponding bits are set as addresses for read and write operations according to the number of rows of each RAM.

[0015] The present invention also provides a data storage device for an LDPC decoder, comprising:

[0016] The memory RAM pool is provided with 2L RAMs for storing the soft information data to be decoded, where L is a natural number;

[0017] Wherein, the granularity of the RAM is set according to the code length and code rate supported by the LDPC decoder;

[0018] The number of bits stored in each row of the RAM is set to Cmax*K.

[0019] Where Cmax is the largest and closest common factor other than Ti among the common factors Cj of the order Ti of the circulant submatrices corresponding to the supported code lengths and code rates; where i and j are natural numbers; K is the bit width of each soft information;

[0020] The depth of the RAM is obtained by dividing the code length by Cmax to obtain the total number of RAM rows Rmaxi, find the factors of each Rmaxi, find the common factor among these factors, and choose the one closest to 2 n The common factor of is used as the depth R and set;

[0021] The RAM in the RAM pool is used to cache corresponding soft information data to be decoded based on the current code length and code rate to be decoded and according to a predetermined logical scheduling.

[0022] Among them, the RAM in the RAM pool is arranged in a chain-ring structure.

[0023] More preferably, the RAMs in the RAM pool are grouped into M groups, each group having N RAMs, where M*N=the total number of RAMs in the RAM pool; N is determined according to the current code length and code rate to be decoded.

[0024] Preferably, corresponding bits are set as chip selection indications according to the number of RAMs in the RAM pool; and corresponding bits are set as addresses for read and write operations according to the number of rows of each RAM.

[0025] In summary, the technical solution provided by the present invention can accommodate more code blocks to be decoded at low code lengths without increasing the total size of the RAM, and the control logic of the present invention is simple, and the load of the chip select signal of each RAM is balanced, which helps to achieve a higher speed RAM, thereby making the LDPC implementation throughput higher. The reason for achieving such an effect is mainly that:

[0026] 1. The size of the basic storage unit RAM is set according to various LDPC code lengths, which is more reasonable and has a higher utilization rate of the unit RAM.

[0027] 2. Using a RAM pool instead of a simple ping-pong RAM group helps to dynamically allocate RAM combinations according to code length, thereby adapting to RAM size requirements under various code lengths.

[0028] 3. The RAM pool approach can modularize the soft information storage RAM of LDPC, thus facilitating exhaustive verification.

[0029] 4. The chip select signal and the read / write signal cooperate to select a specific RAM and a row in the RAM. The control of each small RAM particle is simple and easy to achieve a higher speed RAM.

[0030] For the above and related purposes, one or more embodiments include features that will be described in detail below and particularly pointed out in the claims. The following description and the accompanying drawings describe certain exemplary aspects in detail, and are indicative of only some of the various ways in which the principles of the various embodiments may be employed. Other benefits and novel features will become apparent as the following detailed description is considered in conjunction with the accompanying drawings, and the disclosed embodiments are intended to include all such aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a schematic diagram of the architecture of the ping-pong structure alternating decoding used in the existing LDPC decoding process;

[0032] Figure 2It is the schematic diagram of using the RAM group for storage in the LDPC decoding process of Embodiment 1 of the present invention;

[0033] Figure 3 It is the schematic diagram of RAM grouping and read / write logic control when the code length is 5376 in the LDPC decoding process of Embodiment 2 of the present invention;

[0034] Figure 4 The schematic diagram of RAM grouping and read / write logic control when the code length is 2688 in the LDPC decoding process of Embodiment 2 of the present invention;

[0035] Figure 5 The schematic diagram of RAM grouping and read / write logic control when the code length is 1344 and the code rates are 1 / 2, 5 / 8, 3 / 4 in the LDPC decoding process of Embodiment 2 of the present invention;

[0036] Figure 6 The schematic diagram of RAM grouping and read / write logic control when the code length is 1344 and the code rate is 7 / 8 in the LDPC decoding process of Embodiment 2 of the present invention;

[0037] Figure 7 The schematic diagram of RAM grouping and read / write logic control when the code length is 448 and the code rates are 1 / 2, 4 / 7 in the LDPC decoding process of Embodiment 2 of the present invention;

[0038] Figure 8 Another schematic diagram of RAM grouping and read / write logic control when the code length is 448 and the code rates are 1 / 2, 4 / 7 in the LDPC decoding process of Embodiment 2 of the present invention;

[0039] Fig. 9 The shown is the schematic diagram of RAM utilization situation by adopting the scheme of the RAM pool provided by the present invention. Detailed implementation manners

[0040] The following description and drawings fully illustrate the specific implementation manners of the present invention so that those skilled in the art can practice them. Other implementation manners may include structural, logical, electrical, process, and other changes. The embodiments only represent possible variations. Unless explicitly required, the individual components and functions are optional, and the order of operations can vary. Parts and features of some embodiments can be included in or replaced by parts and features of other embodiments. The scope of the embodiments of the present invention includes the entire scope of the claims and all available equivalents of the claims. In this document, these embodiments of the present invention can be individually or collectively referred to by the term "invention" for convenience only, and if in fact more than one invention is disclosed, it is not intended to automatically limit the scope of the application to any single invention or inventive concept.

[0041] The present invention provides a data storage method for an LDPC decoder, comprising:

[0042] A memory RAM pool consisting of 2L RAMs is set to store the soft information data to be decoded, where L is a natural number;

[0043] Set the RAM granularity according to the code length and code rate supported by the LDPC decoder, specifically:

[0044] Find the common factor Cj of the order Ti of the circulant submatrix corresponding to each supported code length and code rate; where i and j are natural numbers;

[0045] Select the largest and closest common factor Cmax except Ti, and assume that the bit width of each soft information is K bits, then set the number of bits stored in each row of the RAM to Cmax*K;

[0046] By dividing the code length by the above Cmax, we can get the total number of RAM rows Rmaxi. At this time, we also need to find the factors of each Rmaxi, find the common factors among these factors, and choose the one closest to 2. n The common factor of is selected and the depth (number of rows) of RAM is set;

[0047] Based on the current code length and code rate to be decoded and according to a predetermined logic, the RAM in the RAM pool is scheduled to cache the corresponding soft information data to be decoded.

[0048] The RAMs in the RAM pool are arranged in a chain-ring structure.

[0049] The RAMs in the RAM pool are grouped into M groups, each group having N RAMs, where M*N=the total number of RAMs in the RAM pool; N is determined according to the current code length and code rate to be decoded.

[0050] The corresponding bit is set as a chip selection indication according to the number of RAMs in the RAM pool; and the corresponding bit is set as an address for read and write operations according to the number of rows of each RAM.

[0051] In order to make the principles, characteristics and advantages of the present invention more clear, they are described below in conjunction with specific embodiments.

[0052] Embodiment 1

[0053] 802.11AC is a typical communication protocol using LDPC encoding and decoding. Solution 1 of the present invention uses the LDPC encoding in this protocol to describe the invented technical core, but the technical core is not limited to use on the 802.11AC communication protocol.

[0054] The three core parameters of LDPC of 802.11AC are as follows:

[0055] Table 1

[0056] Code length (N) Bit rate (R) Circular submatrix (T) factor 1944 1 / 2,2 / 3,3 / 4,5 / 6 81 3,9,27,81 1296 1 / 2,2 / 3,3 / 4,5 / 6 54 3,9,27,54 648 1 / 2,2 / 3,3 / 4,5 / 6 27 3,9,27

[0057] For this LDPC, according to the background technology Figure 1 According to the method shown, there will be 81 vcu units constituting the core decoding logic, and each RAM Group must have a RAM that needs to store 1944 soft bit information. Assuming that the bit width of each soft bit information is 8 bits, the width of each row of the minimum RAM is Cmax*8. Then a 1944X8 RAM is needed to store these soft bit information. Here, according to the size of the circulant submatrix T, the largest and closest common factor Cmax is 9, so the width of each row of the minimum RAM is 9*8. This 1944X8 RAM can be split like this: 9 RAMs, each RAM row stores 9 soft bit information, and each RAM has 24 rows, which becomes 9*24X9*8=9*24X72. Putting 9*24X72 RAMs in two RAM Groups to form a Ping-Pong RAM Group, we will find that when the code length is 1944, at most two code blocks can be cached; when the code length is 1296, it is still two code blocks; when the code length is 648, six code blocks can be cached; but the problem is that when the code length is 1296, this traditional RAM Group structure wastes three 24X72 RAM resources. The present invention is to solve this problem by merging two RAM Groups into one RAM Group, and this RAM Group includes 18 24X72 RAMs, which are connected into a chain, and different link lengths are selected according to the code length and code rate of LDPC. Figure 2 Shows the principle of how to use this RAM Group. Figure 2 Here S represents the number of code blocks that can be stored. When the code length is 1944, it is 2 blocks; when the code length is 1296, it is 3 blocks; and when the code length is 648, it is 6 blocks.

[0058] from Figure 2It can be seen that the use of this RAM chain structure instead of the traditional ping-pong RAM Group structure can make full use of RAM resources, thereby caching LDPC code blocks to the maximum extent. This structure is effective in OFDMA systems, because in OFDMA systems, in order to deal with multiple users, the decoder resources of each user are limited. When a user uses a high code length to transmit information at a high-order MCS, it takes a long time to collect a code block, so it is often sufficient to use a ping-pong RAM structure that can store two code block resources. However, if this user uses a medium or low code length to transmit information at a high-order MCS, the number of code blocks that need to be stored in a user window is likely to exceed 2. Although the traditional ping-pong RAM structure has surplus RAM resources, it cannot be shared or merged in two groups, so it cannot handle more than 2 code blocks well.

[0059] Embodiment 2

[0060] In the above-mentioned embodiment 1, since the design of the code length and code rate cyclic submatrix of LDPC in 802.11AC is very standardized, the implementation method of 18*24X72 RAM pool or RAM chain can be well adopted to achieve full utilization of RAM resources. However, this cannot be simply implemented in some communication protocols. Therefore, a new solution is proposed for another typical LDPC scenario. The three key parameters of LDPC in this typical LDPC scenario are as follows in Table 2:

[0061] Table 2

[0062]

[0063]

[0064] To facilitate the description of the RAM bit width, we calculate here by quantizing each soft information to 8 bits. 128 bits can store 16 soft information. The amount of soft information stored in each row is related to the number of soft information received at one time. Assume that 8 soft information can be received at one time. When splitting RAM according to code length and code rate, the most important thing is that the minimum granularity cannot be too large, otherwise there will be a lot of waste, and it cannot be too small, otherwise it will cause unnecessary trouble. Another principle is that the number of soft information stored in a row can be divided by the above-mentioned circulant submatrix T. Here we need to find the appropriate common factors when T=112, 56, 42, 32, 28. The specific steps are shown in Table 3 below:

[0065] Table 3

[0066] T factor 112 2,4,7,8，14，16,28，56，112 56 2,4,7,8,14,28，56 42 2,3,7,14,21，42 32 2,4，8,16，32 28 2,4，7,14，28

[0067] In this embodiment, the selected factor is 16, which meets the condition of the largest and closest common factor, because the common factor other than T=32 is 14, and the factor of T=32 closest to 14 is 16, so 16 is selected.

[0068] From Table 3, we can see that except for T=32, the greatest common factor that is not equal to Ti itself is 14, and when T=32, the factor 16 is the closest number and greater than 14, so 16 is selected as Cmax. Using 16 soft information in one row wastes at most 2 storage spaces per row. If 14 is used, there will be more waste in one row when T=32. In addition, the total number of RAM rows required at this time is 42 rows, which is not as large as 2. n factor, so it will make the control logic unnecessarily complicated.

[0069] Table 4 below shows the process of selecting the minimum RAM. It can be seen that the depth (number of rows) of the minimum RAM is set to 8:

[0070] Table 4

[0071]

[0072] For the convenience of design, in this embodiment, it is assumed that the RAM is aligned to the little end, so the high bit indicates the subsequent soft information, so that if 14 soft information are stored, the 2 high bit soft information positions are vacant. In this way, the final minimum granularity of the RAM is 8X128. Such a RAM depth is selected to minimize the waste of RAM. Under this granularity, 5376 code length can still cache 2 code blocks of data, 2688 code length can cache 4 code blocks of data, 1344 code length can cache 7 code blocks of data, and 448 code length can cache 21 code blocks of data. If the 48X128 format is used, then at 2688, only two codewords can be stored due to the read and write characteristics of the RAM, resulting in a waste of half of the RAM space; if the 24X128 format is used, then at 1344 7 / 8 code rate, more than half of the space will be wasted, and only two codewords can be stored; if the 16X128 format is used, there will be a large waste of space at 2688 code length and 1 / 2, 5 / 8, and 3 / 4 code rates of 1344 code length, and it is difficult to control. Therefore, the final design of the RAM pool includes 84 8X128 RAMs. The following describes in detail how to schedule the RAM in this RAM pool, and defines the following variables to facilitate a clear description.

[0073] like Figure 3 As shown in the figure, when the code length is 5376, how the RAM in the RAM pool is grouped according to the SEL and ADDR signals, where Addr[2:0] is used to select the row address of the specific RAM (this reflects that the minimum RAM depth is 2 nThe benefit of this is to use Addr[5:3] to select the RAM particles that need to be spliced ​​into a large RAM. SEL indicates which specific RAM is selected.

[0074] 1.[83:0]SEL. This signal is initially all zero. When a bit is 1, it indicates that a RAM in the RAM pool is selected.

[0075] 2.[5:0]WAddr, this is the write address signal. The lower [2:0] bits are the actual row address of the selected RAM, and the upper [5:3] bits are used to splice several smallest particles to form a larger RAM.

[0076] 3.[5:0]RAddr, this is the read address signal, and the bit allocation is similar to WAddr.

[0077] Figure 3 In the READ / WRITE address range, the range is still [41:0]. The upper three bits are used to select different RAMs, and the lower three bits are used to select the address inside the RAM. A high bit of SEL indicates which RAM is selected.

[0078] Six consecutive RAM sub-units are used to form a large RAM (48X128). Such grouping is only for the convenience of description and does not change the essential principle of the present invention.

[0079] When initializing the RAM pool, after collecting 16 soft information, the corresponding RAM particles will be written, so there will be no parallel writing. If SEL=84'h0_0000_0000_0000_0000_0001, WAddr=6'h00, it means that the 0th row of RAM0 is selected;

[0080] After another 16 soft messages, SEL=84'h0_0000_0000_0000_0000_0040, WAddr=6'h00, indicating that row 0 of RAM6 is selected;

[0081] Similarly, when the last 16 soft information arrives, SEL = 84'h0_0000_0000_0200_0000_0000, WAddr = 6'h2f, indicating that the 7th row of RAM41 is selected;

[0082] When the iteration starts, the RAM in the RAM pool will be read and written in parallel. At this time, assuming the read and write address is 0, SEL = 84'h0_0000_0000_0010_4104_1041, WAddr = 6'h00, indicating that the 0th row of RAM0, RAM6, RAM12, RAM18, RAM24, RAM30, and RAM36 are selected. Assuming the read and write address is 45, SEL = 84'h0_0000_0000_0208_2082_0820, WAddr = 6'h2d, indicating that the 5th row of RAM5, RAM11, RAM17, RAM23, RAM29, RAM35, and RAM41 are selected.

[0083] Figure 4 As shown in the figure, when the code length is 2688, how the RAM in the RAM pool is grouped according to the SEL and ADDR signals. The difference from 5376 is that Addr[4:3] is used to select the RAM particles that need to be spliced ​​into a large RAM. Addr[2:0] still indicates the row address of a specific RAM, and SEL indicates which specific RAM is selected. Use the [4:3] bits to select different RAMs, and the lower three bits select the address inside the RAM; a high bit of SEL indicates which RAM is selected. Three consecutive RAM sub-units constitute a large RAM (24X128).

[0084] For example, when initializing the RAM pool, assuming that after collecting 16 soft information, SEL = 84'h0_0000_0000_0000_0000_0001, WAddr = 6'h00, indicating that the 0th row of RAM0 is selected; after another 8 soft information, SEL = 84'h0_0000_0000_0000_0000_0008, WAddr = 6'h00, indicating that the 0th row of RAM3 is selected;

[0085] Similarly, when the last 16 soft information arrives, SEL = 84'h0_0000_0000_0000_0010_0000, WAddr = 6'h17, indicating that the 7th row of RAM20 is selected; and at the beginning of the iteration, there will be a situation where the RAM in the RAM pool is read and written in parallel. At this time, assuming the read and write address is 3, then SEL = 84'h0_0000_0000_0000_0004_9249, WAddr = 6'h17. r=6'h03, indicating that the third row of RAM0, RAM3, RAM6, RAM9, RAM12, RAM15, and RAM18 is selected. Assuming the read / write address is 21, then SEL=84'h0_0000_0000_0000_0012_4924, WAddr=6'h15, indicating that the fifth row of RAM2, RAM5, RAM8, RAM11, RAM14, RAM17, and RAM20 is selected.

[0086] Figure 5 It shows how the RAM in the RAM pool is grouped according to the SEL and ADDR signals when the code length is 1344 and the code rate is 1 / 2, 3 / 4, and 5 / 8. Like 2688, Addr[4:3] is used to select the RAM particles that need to be spliced ​​into a large RAM. Addr[2:0] still indicates the row address of a specific RAM. SEL indicates which specific RAM is selected. Use [4:3] to select different RAMs, and the lower three bits select the address inside the RAM; a certain bit of SEL is high to indicate which RAM is selected; 3 consecutive RAM sub-units constitute a large RAM (24X128, 24X112 is actually used).

[0087] For example, when initializing the RAM pool, assuming that after collecting 14 soft information, SEL = 84'h0_0000_0000_0000_0000_0001, WAddr = 6'h00, indicating that the 0th row of RAM0 is selected; after another 14 soft information, SEL = 84'h0_0000_0000_0000_0000_0008, WAddr = 6'h00, indicating that the 0th row of RAM3 is selected;

[0088] By analogy, when the last 14 soft information arrives, SEL = 84'h0_0000_0000_0000_0000_0800, WAddr = 6'h17, indicating that the 7th row of RAM11 is selected; and when the iteration starts, there will be a situation of parallel reading and writing of RAM in the RAM pool. At this time, assuming the read and write address is 13, then SEL = 84'h0_0000_0000_0000_0000_0492, WAddr = 6'h0d, indicating that the 5th row of RAM1, RAM4, RAM7, and RAM10 are selected. Assuming the read and write address is 22, then SEL = 84'h0_0000_0000_0000_0000_0924, WAddr = 6'h16, indicating that the 5th row of RAM2, RAM5, RAM8, and RAM11 are selected.

[0089] Figure 6 The figure shows how the RAM in the RAM pool is grouped according to the SEL and ADDR signals when the code length is 1344 and the code rate is 7 / 8. Addr[4:3] is still used to select the RAM particles that need to be spliced ​​into a large RAM, and Addr[2:0] still indicates the row address of the specific RAM. SEL indicates which specific RAM is selected.

[0090] Specifically, [4:3] is used to select different RAMs, and the lower three bits select the address inside the RAM; a high bit of SEL indicates which RAM is selected. 2. 4 consecutive RAM subunits form a large RAM (32X128, 32X112 is actually used).

[0091] For example, when initializing the RAM pool, assuming that after collecting 14 soft information, SEL = 84'h0_0000_0000_0000_0000_0001, WAddr = 6'h00, indicating that the 0th row of RAM0 is selected; after another 14 soft information, SEL = 84'h0_0000_0000_0000_0000_0010, WAddr = 6'h00, indicating that the 0th row of RAM4 is selected;

[0092] By analogy, when the last 14 soft information arrives, SEL = 84'h0_0000_0000_0000_0000_0800, WAddr = 6'h1f, indicating that the 7th row of RAM11 is selected; and when the iteration starts, the RAM in the RAM pool will be read and written in parallel. At this time, assuming the read and write address is 17, then SEL = 84'h0_0000_0000_0000_0000_0444, WAddr = 6'h11, indicating that the 1st row of RAM2, RAM6, and RAM10 is selected. Assuming the read and write address is 30, then SEL = 84'h0_0000_0000_0000_0000_0888, WAddr = 6'h1e, indicating that the 6th row of RAM3, RAM7, and RAM11 is selected.

[0093] Figure 7 It shows how the RAM in the RAM pool is grouped according to the SEL and ADDR signals when the code length is 448 and the code rate is 1 / 2 or 4 / 7. Addr[3] is used to select the RAM particles that need to be spliced ​​into a large RAM. Addr[2:0] still indicates the row address of the specific RAM. SEL indicates which specific RAM is selected.

[0094] The read and write address range is [15:0] at 1 / 2 bit rate and [13:0] at 4 / 7 bit rate. Use [3] to select different RAMs. The lower three bits select the address inside the RAM. A high bit of SEL indicates which RAM is selected. Two consecutive RAM subunits constitute a large RAM (16X128).

[0095] For example, when initializing the RAM pool, assuming that 14 soft information are collected at 1 / 2 code rate and 16 soft information are collected at 4 / 7 code rate, SEL=84'h0_0000_0000_0000_0000_0001, WAddr=6'h00, indicating that the 0th row of RAM0 is selected; after another 8 soft information, SEL=84'h0_0000_0000_0000_0000_0004, WAddr=6'h00, indicating that the 0th row of RAM2 is selected;

[0096] Similarly, when the last 14 or 16 soft information arrives, if the code rate is 1 / 2, SEL = 84'h0_0000_0000_0000_0000_0008, WAddr = 6'h0f, indicating that the 7th row of RAM3 is selected; if the code rate is 4 / 7, SEL = 84'h0_0000_0000_0000_0000_0008, WAddr = 6'h0d, indicating that the 5th row of RAM3 is selected; and at the beginning of the iteration, Now let's look at the situation of parallel reading and writing of the RAM in the RAM pool. At this time, assuming the read / write address is 14, then SEL = 84'h0_0000_0000_0000_0000_000a, WAddr = 6'he, indicating that the 6th row of RAM1 and RAM3 is selected. Assuming the read / write address is 6, then SEL = 84'h0_0000_0000_0000_0000_0005, WAddr = 6'h6, indicating that the 6th row of RAM0 and RAM2 is selected.

[0097] from Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 It can be seen that choosing the smallest RAM particle of 8X128 size can achieve the effect of minimum waste. Using a RAM pool instead of simply two ping-pong RAM groups can greatly improve the utilization of RAM without increasing the overall size of RAM. Introducing the SEL signal without changing the original W / RAddr calculation method can solve the problem of RAM selection and grouping. The reason why SEL uses the same number of bits as the RAM in the RAM pool is to make the load of each bit the same, so that the timing will be better during implementation. If you want to reduce the number of bits of SEL, you can use the encoding and decoding method to select the RAM in the RAM pool. This does not affect the central idea of ​​the method. The [5:3] bits of the original W / RAddr are used to control how many RAM units need to be spliced ​​to form a large block of RAM. For example, when the code length is 5374, six 8X128 blocks need to be spliced ​​into a 48X128 block. When the code length is 2688, three 8X128 blocks need to be spliced ​​into a 24X128 block. When the original address reaches 32, four 8X128 blocks need to be spliced ​​into a 32X128 block. When the original data only needs a length of 112, a 128-bit RAM is still used, but the upper 16 bits are a bit wasted. However, this does not affect the entire control logic and still saves a lot of RAM resources compared to using two ping-pong RAM groups.

[0098] The following uses the case of code length 448 and code rate 4 / 7 to illustrate how to allocate RAM and how to maximize the RAM in the RAM pool to accommodate the code blocks to be decoded. Figure 8 shown. Figure 8 In the example, each bit of sel[83:0] controls the chip select of a RAM, and each consecutive four bits control the RAM group required for a 448-code block. In this way, the RAM in the RAM pool can accommodate the information to be decoded for 21 code blocks. The code blocks are grouped in a ring, group 1, group 2...group 21, group 1, group 2.

[0099] from Figure 8 It can be seen that the RAM pool structure can easily realize the mechanism of accommodating multiple LDPC code blocks to be decoded, and this mechanism itself does not need to increase the size of RAM, and the control is simple. However, the solution of using two ping-pong RAM groups (the size of a single RAM is large) is complex to control and will waste a lot of RAM space in many cases.

[0100] An embodiment of the present invention further provides a data storage device for an LDPC decoder, comprising:

[0101] The memory RAM pool is provided with 2L RAMs for storing the soft information data to be decoded, where L is a natural number;

[0102] Among them, the granularity of RAM is set according to the code length and code rate supported by the LDPC decoder;

[0103] The number of bits stored in each row of RAM is set to Cmax*K, where Cmax is the largest and closest common factor other than Ti among the common factors Cj of the order Ti of the circulant submatrices corresponding to each supported code length and code rate; i and j are natural numbers; K is the bit width of each soft information;

[0104] The depth of RAM is obtained by dividing the code length by Cmax to get the total number of RAM rows Rmaxi, find the factors of each Rmaxi, find the common factor among these factors, and choose the one closest to 2 n The common factor of is used as the depth R and set;

[0105] The RAM in the RAM pool is used to cache corresponding soft information data to be decoded based on the current code length and code rate to be decoded and according to a predetermined logical scheduling.

[0106] Among them, the RAM in the RAM pool is arranged in a chain-ring structure.

[0107] More preferably, the RAMs in the RAM pool are grouped into M groups, each group having N RAMs, where M*N=the total number of RAMs in the RAM pool; N is determined according to the current code length and code rate to be decoded.

[0108] Preferably, corresponding bits are set as chip selection indications according to the number of RAMs in the RAM pool; and corresponding bits are set as addresses for read and write operations according to the number of rows of each RAM.

[0109] The above mainly introduces the use of SEL signals and W / RAddr signals under various code lengths and code rates and circulant sub-matrices of different sizes. The following uses a diagram to describe the RAM utilization using the RAM pool method provided by the present invention. Fig. 9 It can be seen that this design method will result in much less waste than designing RAM particles according to the maximum size when using two ping-pong RAMs, which greatly improves the utilization of RAM.

[0110] Compared with the RAM grouping method using ping-pong RAM groups and each RAM having a larger size, the present invention can accommodate more code blocks to be decoded at low code lengths without increasing the total RAM size. In addition, the present invention has simple control logic and load balance of chip select signals of each RAM, which are helpful to realize a higher-speed RAM, thereby achieving a higher throughput rate for LDPC. The main reasons for achieving such an effect are:

[0111] 1. The size of the unit sub-RAM is set according to various LDPC code lengths, so the size is more reasonable and the utilization rate of the unit RAM is higher.

[0112] 2. Using a RAM pool instead of a simple ping-pong RAM group helps to dynamically allocate RAM combinations according to code length, thereby adapting to RAM size requirements under various code lengths.

[0113] 3. The RAM pool approach can modularize the soft information storage RAM of LDPC, thus facilitating exhaustive verification.

[0114] 4. The SEL signal and the W / RAddr signal cooperate to select a specific RAM and a row in the RAM. The control of each small RAM particle is simple and easy to implement a higher-speed RAM.

[0115] The present invention adopts a RAM pool structure, and the RAM in the pool adopts a chain ring structure. The size of each RAM sub-unit is comprehensively considered according to the LDPC code length and code rate and the corresponding cyclic sub-matrix; these RAM sub-units will use the same read-write address logic as when using a large-size RAM to control, the low-order part of the read-write address is the real read-write address of a selected RAM sub-unit, and the high-order part of the read-write address determines the use of several continuous sub-units to splice into a large-size RAM to meet the needs of storing complete code blocks. The SEL signal and the read-write address cooperate to mark when which RAMs are selected and what the current read-write addresses of these RAMs are. In this way, RAM resources can be flexibly and efficiently allocated dynamically to meet the requirements of various code lengths and code rates, and the waste of RAM resources can be minimized.

[0116] It will be appreciated by those skilled in the art that the various exemplary method steps and device units described herein in conjunction with the disclosed embodiments can all be implemented in electronic hardware, software, or a combination of the two. In order to clearly illustrate the interchangeability between hardware and software, the various exemplary steps and units are generally described in the form of their functionality. Whether this functionality is implemented in hardware or software depends on the design constraints implemented by the specific application and the entire system. Those skilled in the art can implement the described functionality in a variety of ways for each specific application, but the results of this implementation should not be interpreted as departing from the scope of the present invention.

[0117] The steps of the method described in conjunction with the above disclosed embodiments may be directly embodied as hardware, a software module executed by a processor, or a combination of the two. The software module may exist in a RAM memory, a flash memory, a ROM memory, an EPROM memory, an EEPROM memory, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. A typical storage medium is coupled to a processor so that the processor can read information from the storage medium and write information to the storage medium. In an alternative embodiment, the storage medium is an integral part of the processor. The processor and the storage medium may exist in an ASIC. The ASIC may exist in a user station. In an alternative embodiment, the processor and the storage medium may exist as discrete components in a user station.

[0118] According to the disclosed embodiments, it is possible for those skilled in the art to implement or use the present invention. It is obvious to those skilled in the art that various modifications of these embodiments are possible, and the general principles defined herein can also be applied to other embodiments without departing from the scope and gist of the present invention. The embodiments described above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A data storage method for an LDPC decoder, characterized in that, it includes: setting up a memory RAM pool composed of 2L RAMs for storing soft information data to be decoded, where L is a positive integer; setting the granularity of the RAM according to the code length and code rate supported by the LDPC decoder, specifically: finding the factors Cj of the order Ti of the cyclic submatrices corresponding to each supported code length and code rate; where i and j are natural numbers; finding the largest and closest common factor Cmax other than Ti itself among the factors Cj. When the bit width of each soft information is K bits, setting the number of bits stored in each row of the RAM to Cmax * K; Divide the code length by the Cmax to obtain the total number of rows Rmaxi of the RAM, find the factor Ck of each Rmaxi, find the common factor among the factors Ck, and select the common factor closest to 2 n and set it as the depth R of the RAM; based on the current code length and code rate to be decoded and according to a predetermined logic, scheduling the RAMs in the RAM pool for caching the corresponding soft information data to be decoded.

2. The data storage method according to claim 1, characterized in that, the RAMs in the RAM pool are arranged in a chain - ring structure.

3. The data storage method according to claim 1, characterized in that, grouping the RAMs in the RAM pool into M groups, with N RAMs in each group, M * N = the total number of RAMs in the RAM pool; N is determined according to the current code length and code rate to be decoded.

4. The data storage method according to claim 1, characterized in that, setting corresponding bit positions as chip - select indicators according to the number of RAMs in the RAM pool; setting corresponding bit positions as addresses for read - write operations according to the number of rows of each RAM.

5. A data storage device for an LDPC decoder, characterized in that, it includes: a memory RAM pool with 2L RAMs set up for storing soft information data to be decoded, where L is a positive integer; wherein, the granularity of the RAM is set according to the code length and code rate supported by the LDPC decoder; the number of bits stored in each row of the RAM is set to Cmax * K, where Cmax is the largest and closest common factor other than Ti among the common factors Cj of the order Ti of the cyclic submatrices corresponding to each supported code length and code rate; where i and j are natural numbers; K is the number of bit positions of the bit width of each soft information; The depth of the RAM is obtained by dividing the code length by Cmax to get the total number of rows Rmaxi of the RAM, finding the factors of each Rmaxi, looking for the common factors among these factors, and selecting the common factor closest to 2 n as the depth R and setting it; the RAMs in the RAM pool are scheduled based on the current code length and code rate to be decoded and according to a predetermined logic for caching the corresponding soft information data to be decoded.

6. The data storage device according to claim 5, characterized in that, the RAMs in the RAM pool are arranged in a chain - ring structure.

7. The data storage device according to claim 5, characterized in that, grouping the RAMs in the RAM pool into M groups, with N RAMs in each group, M * N = the total number of RAMs in the RAM pool; N is determined according to the current code length and code rate to be decoded.

8. The data storage device according to claim 5, characterized in that, setting corresponding bit positions as chip - select indicators according to the number of RAMs in the RAM pool; setting corresponding bit positions as addresses for read - write operations according to the number of rows of each RAM.

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