A silicon carbide UMOSFET device with integrated SBD and preparation method thereof
By integrating Schottky diodes in silicon carbide UMOSFET devices and using deep P+ shielding areas and P+ injection areas, the problem of device freewheeling capability and reliability is solved, achieving higher reverse withstand voltage capability and lower Preparation costs.
Patent Information
- Application Number
- CN202110175891.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-02-07
- Publication Date
- 2025-01-21
- Estimated Expiration
- 2041-02-07
AI Technical Summary
Due to the large bandwidth of the band gap, the internal parasitic PiN diode is high and cannot provide a freewheeling effect, resulting in the need of anti-parallel Schottky diodes in full-bridge power electronics system to increase the system area; at the same time, the gate oxide layer corners The electric field at the center affects the reliability of the device.
Integrating the Schottky diode structure into the silicon carbide UMOSFET device reduces reliance on external Schottky diodes, and alleviates the electric field concentration at the corners of the gate oxide layer through the deep P+ shielding area and the P+ injection area that partially surrounds the groove corners.
The device's freewheeling capability and reverse voltage withstand capability are improved, the system area and device preparation costs are reduced, and the reliability of the device is enhanced.
Smart Images
Figure CN112820777B_ABST
Abstract
Description
[Technical field]
[0001] The invention relates to a silicon carbide UMOSFET device integrated with an SBD and a preparation method thereof. [Background technology]
[0002] In recent years, with the continuous development of power electronic systems, higher requirements have been placed on the power devices in the system. Silicon (Si)-based power electronic devices can no longer meet the requirements of system applications due to the limitations of the material itself.
[0003] As a representative of the third generation of semiconductor materials, silicon carbide (SiC) materials are far superior to silicon materials in many properties. As a commercialized device in recent years, silicon carbide MOSFET devices have great potential to replace existing IGBTs in terms of on-resistance, switching time, switching loss and heat dissipation performance.
[0004] However, due to the large bandgap width of silicon carbide materials, the turn-on voltage of the parasitic PiN diode integrated inside the silicon carbide MOSFET device is mostly around 3V, which cannot provide freewheeling for the silicon carbide MOSFET device itself. Therefore, in power electronic system applications such as full-bridge, a Schottky diode is often used in anti-parallel as a freewheeling diode, which greatly increases the area of the system. In addition, since the gate oxide layer has a groove-shaped structure, the electric field concentration generated at the corner is greater than the electric field in the drift region of the device, so that the gate oxide layer may be broken down before the body region breaks down, which greatly affects the reliability of the device. Therefore, researchers will use a variety of gate oxide reinforcement structures to weaken the electric field concentration phenomenon at the corners of the gate oxide layer of silicon carbide UMOSFET, thereby improving device performance. [Summary of the invention]
[0005] The technical problem to be solved by the present invention is to provide a silicon carbide UMOSFET device with integrated SBD and a preparation method, which integrates an additional Schottky diode to improve the device's freewheeling capability; at the same time, a deep P+ shielding area and a P+ injection area that partially surrounds the groove corners are used to effectively shield or alleviate the electric field concentration phenomenon at the left and right groove corners of the gate oxide layer, thereby improving the reverse voltage withstand capability and reliability of the device.
[0006] One of the present inventions is implemented as follows: a silicon carbide UMOSFET device with integrated SBD, comprising:
[0007] a third metal, the third metal serving as a drain electrode;
[0008] An N+ substrate, one side of the N+ substrate is connected to the third metal;
[0009] an N-epitaxial layer, the other side of the N+ substrate being connected to the N-epitaxial layer;
[0010] a first P+ implantation region, wherein the first P+ implantation region is L-shaped and connected to the N-epitaxial layer;
[0011] a second P+ implantation region, wherein the second P+ implantation region is L-shaped and connected to the N-epitaxial layer;
[0012] a first P-well region, the first P-well region being connected to the second P+ implant region and the N-epitaxial layer;
[0013] a first N+ implant region connected to the first P-well region;
[0014] a first trench, the first trench respectively connecting the N-epitaxial layer, the first P+ implantation region, the first P-well region and the first N+ implantation region;
[0015] a second trench, wherein the second trench is respectively connected to the N-epitaxial layer, the second P+ implantation region, the first P-well region and the first N+ implantation region;
[0016] a gate dielectric layer, covering the side surface of the first trench and the upper surface of the trench bottom;
[0017] a gate, covering the upper surface of the gate dielectric layer and filling the first trench;
[0018] A first metal, the first metal covers a set position on the upper surface of the first N+ implantation region, a side surface of the first N+ implantation region, a side surface of the first P-well region, and an upper surface of the second P+ implantation region to form an ohmic contact;
[0019] and a second metal, wherein the second metal covers a set position of the N-epitaxial layer to form a Schottky contact, and the second metal is connected to the first metal.
[0020] Furthermore, the first groove has a depth of 1 μm to 3 μm and a width of 0.5 μm to 2 μm, and the second groove has a depth of 1 μm to 3 μm and a width of 0.8 μm to 2.5 μm.
[0021] Furthermore, the first P-well region has a depth of 0.3 μm to 1.0 μm and a width of 0.3 μm to 1 μm, and the first N+ implantation region has a depth of 0.1 μm to 0.5 μm and a width of 0.3 μm to 1 μm.
[0022] Furthermore, the first P+ injection region has a depth of 1.5 μm to 3 μm and a width of 0.8 μm to 2 μm, and the second P+ injection region has a depth of 2 μm to 3 μm and a width of 1 μm to 2 μm.
[0023] Furthermore, the width of the second metal is between 0.2 μm and 0.5 μm.
[0024] Furthermore, the depth of the first P+ implantation region is greater than the depth of the first trench, the depth of the second P+ implantation region is greater than the depth of the second trench, and the depths of the first trench and the second trench are greater than the depth of the first P-well region.
[0025] Furthermore, a distance between the left side of the first P+ implantation region and the right side of the first trench is between 0.5 μm and 0.7 μm, and a distance between the right side of the second P+ implantation region and the left side of the first trench is between 0.1 μm and 0.3 μm.
[0026] The second aspect of the present invention is achieved as follows: a method for preparing a silicon carbide UMOSFET device integrated with an SBD comprises the following steps:
[0027] forming an N-epitaxial layer on an N+ substrate;
[0028] Performing P+ region implantation at a set position on the surface of the N-epitaxial layer to form a first P+ implantation region and a second P+ implantation region;
[0029] Performing N+ region implantation at a set position on the surface of the N- epitaxial layer to form a transitional N+ implantation region;
[0030] Performing P-region implantation on the surface of the transitional N+ implantation region to form a first P-well region;
[0031] Performing N+ region implantation on the surface of the P-region to form a first N+ implantation region;
[0032] Etching the set positions of the first N+ region, the first P-well region, the first P+ implantation region, and the second P+ implantation region to form a first trench and a second trench;
[0033] The left side wall of the first trench is provided with a first P-well region and a first N+ implantation region on the left;
[0034] The P+ injection region surrounded by the right portion of the right side wall of the first trench becomes the first P+ injection region;
[0035] The right side wall of the second trench is the first P-well region and the first N+ implantation region;
[0036] The P+ injection region to the right of the right side wall of the second trench becomes the second P+ injection region;
[0037] forming a gate dielectric layer to cover the surface of the first trench;
[0038] forming a gate on the upper surface of the gate dielectric layer;
[0039] Forming a first metal, wherein the first metal covers a portion of an upper surface of the first N+ implantation region, a side surface of the first P-well region, and an upper surface of the second P+ implantation region to form an ohmic contact;
[0040] forming a second metal, wherein the second metal covers an upper surface of the first spacer to form a Schottky contact;
[0041] A third metal is formed on the back side of the N+ substrate 11 .
[0042] Furthermore, the process of forming the ohmic contact includes: performing a rapid thermal annealing process in an argon atmosphere.
[0043] Furthermore, the formation process of the Schottky contact includes: annealing the second metal by a low-temperature rapid thermal annealing process.
[0044] The advantages of the present invention are as follows: the present invention provides a silicon carbide UMOSFET device with integrated SBD and a preparation method thereof, wherein a Schottky diode structure is integrated in the device, and when the system operates in a freewheeling mode, there is no need to connect a Schottky diode in anti-parallel, thereby reducing the system area; and the Schottky contact area will not be too large, thereby wasting the device cell area, thereby reducing the device preparation cost.
[0045] Half of the channel is sacrificed in the device, and a deep P+ injection region is introduced to partially surround the groove corner, thereby shielding the electric field concentration phenomenon at the groove corner on the right side of the gate oxide layer while ensuring that the forward current is large enough.
[0046] A second groove is formed by etching part of the first N+ injection region, the first P-well region and the second P+ injection region, and a deeper second P+ injection region is formed as a P+ shielding layer, which effectively alleviates the electric field concentration phenomenon at the groove corner on the left side of the gate oxide layer, thereby improving the voltage resistance and working reliability of the device.
Brief Description of the Drawings
[0047] The present invention will be further described below in conjunction with embodiments with reference to the accompanying drawings.
[0048] Figure 1 is a schematic diagram of a silicon carbide UMOSFET device with integrated SBD;
[0049] Figure 2 This is a schematic diagram of the corresponding structure of the silicon carbide UMOSFET device with integrated SBD Figure 1 ;
[0050] Figure 3 This is a schematic diagram of the corresponding structure of the silicon carbide UMOSFET device with integrated SBD Figure 2 ;
[0051] Figure 4This is a schematic diagram of the corresponding structure of the silicon carbide UMOSFET device with integrated SBD Figure 3 ;
[0052] Figure 5 This is a schematic diagram of the corresponding structure of the silicon carbide UMOSFET device with integrated SBD Figure 4 ;
[0053] Figure 6 This is a schematic diagram of the corresponding structure of the silicon carbide UMOSFET device with integrated SBD Figure 5 ;
[0054] Figure 7 This is a schematic diagram of the corresponding structure of the silicon carbide UMOSFET device with integrated SBD Figure 6 . [Specific implementation method]
[0055] The embodiment of the present invention provides a silicon carbide UMOSFET device with integrated SBD and a preparation method, thereby solving the shortcomings of the prior art that in order to improve the device's freewheeling capability, the Schottky contact area is too large, the device cell area is wasted, and the device preparation cost is increased; the invention also has a groove-shaped structure, and the peak electric field generated at the corner is larger than the electric field in the device drift region, so that the gate oxide layer may be broken down before the body region is broken down, and the technical problem of poor reliability is solved, thereby improving the device's freewheeling capability, and at the same time using a deep P+ shielding area and a P+ injection area that partially surrounds the groove corner to effectively shield or alleviate the electric field concentration phenomenon at the left and right groove corners of the gate oxide layer, thereby improving the reverse voltage withstand capability and the technical effect of reliability in use.
[0056] Example 1
[0057] like Figure 1 The present embodiment provides a silicon carbide UMOSFET device with integrated SBD, the device comprising: a third metal 30, an N+ substrate 11 and an N- epitaxial layer 12 from bottom to top.
[0058] The N-epitaxial layer 12 has a first P+ implantation region 23, a second P+ implantation region 20, a first spacer (not shown) and a first P-well region 21. The first P-well region 21 has a first N+ implantation region 22 (the depth of the first P-well region 21 is greater than the depth of the first N+ implantation region 22).
[0059] The device also includes: a gate dielectric layer 26, covering the bottom and side walls of the first trench 24; a gate 27, located on the gate dielectric layer 26 and filling the first trench 24; a first metal 28, the first metal 28 forms a first ohmic contact on a portion of the upper surface of the first N+ injection region 22, the side surface of the first P-well region 21 and the upper surface of the second P+ injection region 20; a second metal 29, the second metal 29 forms a first Schottky contact on the upper surface of the first spacer (not marked); and the back side of the N+ substrate 11 also has a third metal 30.
[0060] The first metal 28 is a part of the source electrode, or the source electrode includes the first metal 28 and the second metal 29. Specifically, the first metal 28 forms a first ohmic contact as a part of the source contact; the second metal 29 forms a Schottky contact, which is connected to the first ohmic contact, and they form the source electrode of the corresponding MOS device. The metal 29 forms the drain electrode of the MOS device.
[0061] In this embodiment, the N+ substrate 11 may be made of a doping concentration of 5×10 18 cm -3 The silicon carbide material may be 350 μm thick.
[0062] In this embodiment, the doping concentration of the N-epitaxial layer 12 can be 6×10 15 cm -3 , the thickness can be 10μm.
[0063] In this embodiment, the doping concentration of the first P-well region 21 is 6×10 16 cm -3 , with a width of 0.7 μm and a depth of 1 μm.
[0064] In this embodiment, the doping concentration of the first N+ implantation region 22 is 9×10 18 cm -3 , with a width of 0.7μm and a depth of 0.5μm.
[0065] In this embodiment, the first trench 24 has a width of 1.2 μm and a depth of 1.5 μm.
[0066] In this embodiment, the second trench 25 has a width of 0.7 μm and a depth of 1.8 μm.
[0067] In this embodiment, the doping concentration of the first P+ injection region 23 and the second P+ injection region 20 is 1×
[0068] 10 19 cm -3 The first P+ implantation region 23 has a width of 1.3 μm and a depth of 2 μm; the second P+ implantation region 20 has a width of 1.2 μm and a depth of 2.3 μm.
[0069] In this embodiment, the width of the first space (not shown) is 0.3 μm.
[0070] In this embodiment, the distance between the left side of the first P+ implantation region and the right side of the first trench is 0.6 μm, and the distance between the right side of the second P+ implantation region and the left side of the first trench is 0.2 μm.
[0071] This embodiment also provides a method for preparing the above-mentioned silicon carbide UMOSFET device, please refer to Figures 2 to 7 , and the final structure please refer to Figure 1 The preparation method comprises the following steps:
[0072] Please refer to Figure 2 On the N+ substrate 11, an N-epitaxial layer 12 is formed by epitaxial growth. The N+ substrate 11 on which the N-epitaxial layer 12 is grown and the N-epitaxial layer 12 are together called an epitaxial wafer.
[0073] Please refer to Figure 3 On the N-epitaxial layer 12, a first mask layer (not shown) is deposited and formed, and the thickness of the first mask is 2 μm. The first mask pattern is formed by a photolithography and etching process. Well implantation is performed on a portion of the surface of the N-epitaxial layer 12, and the implanted ions are Al ions, forming P+ implantation regions 13 and 14.
[0074] Please refer to Figure 4 , remove the first mask layer, and form a second mask layer (not shown) on the re-exposed surface of the N-epitaxial layer, and form a second mask pattern through a photolithography and etching process; then, through N ion implantation, a portion of the surface of the N-epitaxial layer 12 is well implanted to form a transitional N+ implantation region 16.
[0075] Please refer to Figure 5 By means of Al ion implantation, a portion of the surface of the N-epitaxial layer 12 is well implanted to form a P-well region 17.
[0076] Please refer to Figure 6 By N ion implantation, a portion of the surface of the N-epitaxial layer 12 is well implanted to form an N+ implantation region 19.
[0077] Please refer to Figure 7 , remove the second mask layer, and form a third mask layer (not shown) on the re-exposed N-epitaxial layer surface, and form a third mask pattern by photolithography and etching. Then, by ICP etching method, Figure 6 The portion of the P-well region 18, the N+ implant region 19, the P+ implant region 13 and the portion of the height of the N-epitaxial layer 12 are etched to form a first trench 24. Figure 6The partial P-well region 18, the N+ implantation region 19 and the partial height of the P+ implantation region 15 are shown to form a second trench 25. The first P-well region 21 and the first N+ implantation region 22 are formed on the left side wall of the first trench 24, and the first P+ implantation region 23 is formed on the right side wall of the first trench 21; the first P-well region 21 and the first N+ implantation region 22 are formed on the right side wall of the second trench 25, and the second P+ implantation region 20 is partially surrounded below the second trench 25.
[0078] Please refer back to Figure 1 A gate dielectric layer 26 is formed on the sidewall and bottom surface of the first trench 24. Polysilicon is formed to fill the first trench 24 and a gate 27 is formed on the upper surface of the gate dielectric layer 26.
[0079] Please refer back to Figure 1 , forming the first metal 28 as the source of the device, the first metal 28 covers part of the upper surface of the first N+ injection region 22, the side surface of the first P-well region 21 and the upper surface of the second P+ injection region 20 to form a first ohmic contact; forming the second metal 29 as the source of the device, the second metal 29 covers the upper surface of the first spacer (not marked) to form a first Schottky contact; when or after the first metal 28 is formed, a third metal 30 is also formed on the back side of the N+ substrate 11 as a drain electrode.
[0080] In this embodiment, a carbon film (not shown) is formed on the surface of the N-epitaxial layer 12 for protection, including using a carbon film sputtering machine to form a carbon film on the surface of the N-epitaxial layer 12. Then, the implanted ions (implanted ions) are activated by high-temperature annealing, the annealing temperature is 1650° C., the annealing time is 45 minutes, and then the carbon film is removed by an oxidation method. Then, the carbon film is removed by an oxidation method.
[0081] In this embodiment, the process of forming the gate dielectric layer 26 includes performing sacrificial oxidation on the surface of the first trench 24, removing the oxide layer, and then depositing silicon dioxide. Then, photolithography and etching are used to carve a dielectric window to form a source region. Then, a layer of silicon dioxide is grown by thermal oxidation as the gate dielectric layer 26, and annealed in a nitrogen monoxide atmosphere at a temperature of 1200° C. for 1 hour.
[0082] In this embodiment, the process of forming the gate 27 includes depositing a highly doped polysilicon layer by chemical vapor deposition, and then forming the polysilicon gate 27 by photolithography and etching.
[0083] In this embodiment, the process of depositing the first metal 28 and forming the first ohmic contact further includes: performing a rapid thermal annealing process in an argon atmosphere, with an annealing temperature of 1000° C. and an annealing time of 3 minutes. The first metal 28 is aluminum, forming an electrode pattern.
[0084] In this embodiment, the formation process of the Schottky contact includes: annealing the second metal 29 by a low temperature rapid thermal annealing process, the annealing temperature is 500° C., and the annealing time is 2 minutes. The second metal 29 is titanium.
[0085] Not shown in the figure, after forming the first metal 28, another layer of thick metal can be deposited on the back side of the epitaxial wafer and on the third metal 30. The thick metal can be titanium, nickel or silver, etc. The thick metal serves as a back electrode (the back electrode serves as part of the drain electrode).
[0086] See also Figure 1 As shown, a silicon carbide UMOSFET device with integrated SBD of the present invention comprises:
[0087] a third metal 30, wherein the third metal 30 serves as a drain electrode;
[0088] An N+ substrate 11, one side of the N+ substrate 11 is connected to the third metal 30;
[0089] An N-epitaxial layer 12, the other side of the N+ substrate 11 is connected to the N-epitaxial layer 12;
[0090] a first P+ implantation region 23, wherein the first P+ implantation region 23 is L-shaped and connected to the N-epitaxial layer 12;
[0091] a second P+ implantation region 20, wherein the second P+ implantation region 20 is L-shaped and connected to the N-epitaxial layer 12;
[0092] a first P-well region 21 , the first P-well region 21 being connected to the second P+ implantation region 20 and the N-epitaxial layer 12 ;
[0093] a first N+ implantation region 22 connected to the first P-well region 21;
[0094] a first trench 24, wherein the first trench 24 is connected to the N-epitaxial layer 12, the first P+ implantation region 23, the first P-well region 21 and the first N+ implantation region 22;
[0095] a second trench 25, wherein the second trench 25 is connected to the N-epitaxial layer 12, the second P+ implantation region 20, the first P-well region 21 and the first N+ implantation region 22;
[0096] a gate dielectric layer 26, covering the side surface and the upper surface of the bottom of the first trench 24;
[0097] a gate 27 , the gate 27 covers the upper surface of the gate dielectric layer 26 and fills the first trench 24 ;
[0098] A first metal 28, the first metal 28 covers a set position on the upper surface of the first N+ implantation region 22, a side surface of the first N+ implantation region 22, a side surface of the first P-well region 21 and an upper surface of the second P+ implantation region 20 to form an ohmic contact;
[0099] and a second metal 29 , wherein the second metal 29 covers a set position of the N-epitaxial layer 12 to form a Schottky contact, and the second metal 29 is connected to the first metal 28 .
[0100] In another embodiment, the first groove 24 has a depth of 1 μm to 3 μm and a width of 0.5 μm to 2 μm, and the second groove 25 has a depth of 1 μm to 3 μm and a width of 0.8 μm to 2.5 μm.
[0101] In another embodiment, the first P-well region 21 has a depth of 0.3 μm to 1.0 μm and a width of 0.3 μm to 1 μm, and the first N+ implantation region 22 has a depth of 0.1 μm to 0.5 μm and a width of 0.3 μm to 1 μm.
[0102] In another embodiment, the first P+ implantation region 23 has a depth of 1.5 μm to 3 μm and a width of 0.8 μm to 2 μm, and the second P+ implantation region 20 has a depth of 2 μm to 3 μm and a width of 1 μm to 2 μm.
[0103] In another embodiment, the width of the second metal 29 is between 0.2 μm and 0.5 μm.
[0104] In another embodiment, the depth of the first P+ implantation region 23 is greater than the depth of the first trench 24 , the depth of the second P+ implantation region 20 is greater than the depth of the second trench 25 , and the depths of the first trench 24 and the second trench 25 are greater than the depth of the first P-well region 21 .
[0105] In another embodiment, the distance between the left side of the first P+ implantation region 23 and the right side of the first trench 24 is 0.5 μm-0.7 μm, and the distance between the right side of the second P+ implantation region 20 and the left side of the first trench 24 is 0.1 μm-0.3 μm.
[0106] Although the specific implementation modes of the present invention are described above, those skilled in the art should understand that the specific implementation modes described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.
Claims
1. A silicon carbide UMOSFET device with integrated SBD, characterized in that: include: a third metal, the third metal serving as a drain electrode; An N+ substrate, one side of the N+ substrate is connected to the third metal; an N-epitaxial layer, the other side of the N+ substrate being connected to the N-epitaxial layer; a first P+ implantation region, wherein the first P+ implantation region is L-shaped and connected to the N-epitaxial layer; a second P+ implantation region, wherein the second P+ implantation region is L-shaped and connected to the N-epitaxial layer; a first P-well region, the first P-well region being connected to the second P+ implant region and the N-epitaxial layer; a first N+ implant region connected to the first P-well region; a first trench, the first trench respectively connecting the N-epitaxial layer, the first P+ implantation region, the first P-well region and the first N+ implantation region; a second trench, wherein the second trench is respectively connected to the N-epitaxial layer, the second P+ implantation region, the first P-well region and the first N+ implantation region; a gate dielectric layer, covering the side surface of the first trench and the upper surface of the trench bottom; a gate, covering the upper surface of the gate dielectric layer and filling the first trench; a first metal, the first metal covering a set position on the upper surface of the first N+ implantation region, a side surface of the first N+ implantation region, a side surface of the first P-well region, and an upper surface of the second P+ implantation region to form an ohmic contact; and a second metal, wherein the second metal covers a set position of the N-epitaxial layer to form a Schottky contact, and the second metal is connected to the first metal.
2. A silicon carbide UMOSFET device with integrated SBD as claimed in claim 1, characterized in that: The first groove has a depth of 1 μm to 3 μm and a width of 0.5 μm to 2 μm, and the second groove has a depth of 1 μm to 3 μm and a width of 0.8 μm to 2.5 μm.
3. The silicon carbide UMOSFET device with integrated SBD according to claim 1, characterized in that: The first P-well region has a depth of 0.3 μm to 1.0 μm and a width of 0.3 μm to 1 μm, and the first N+ implantation region has a depth of 0.1 μm to 0.5 μm and a width of 0.3 μm to 1 μm.
4. The silicon carbide UMOSFET device with integrated SBD according to claim 1, characterized in that: The first P+ injection region has a depth of 1.5 μm to 3 μm and a width of 0.8 μm to 2 μm, and the second P+ injection region has a depth of 2 μm to 3 μm and a width of 1 μm to 2 μm.
5. The silicon carbide UMOSFET device with integrated SBD according to claim 1, characterized in that: The width of the second metal is between 0.2 μm and 0.5 μm.
6. The silicon carbide UMOSFET device with integrated SBD according to claim 1, characterized in that: The depth of the first P+ implantation region is greater than the depth of the first trench, the depth of the second P+ implantation region is greater than the depth of the second trench, and the depths of the first trench and the second trench are greater than the depth of the first P-well region.
7. The silicon carbide UMOSFET device with integrated SBD according to claim 1, characterized in that: The distance between the left side of the first P+ implantation region and the right side of the first trench is 0.5 μm to 0.7 μm, and the distance between the right side of the second P+ implantation region and the left side of the first trench is 0.1 μm to 0.3 μm.
8. A method for preparing a silicon carbide UMOSFET device integrated with SBD, characterized in that: The steps include: forming an N-epitaxial layer on an N+ substrate; A P+ region is implanted at a set position on the surface of the N-epitaxial layer to form a first P+ implantation region and a second P+ implantation region arranged at intervals; In the N- epitaxial layer surface set position N + region implantation, forming a transition N + implantation region; Performing P-region implantation on the surface of the transitional N+ implantation region to form a first P-well region; Performing N+ region implantation on the surface of the first P-well region to form a first N+ implantation region; Etching the set positions of the first N+ implantation region, the first P-well region, the first P+ implantation region and the second P+ implantation region to form a first trench and a second trench; The left side wall of the first trench is, from bottom to top, an N-epitaxial layer, a first P-well region, and a first N+ implantation region, and the right side wall of the first trench is surrounded by the first P+ implantation region. The right side wall of the second trench is composed of the second P+ implantation region, the first P-well region and the first N+ implantation region from bottom to top; forming a gate dielectric layer to cover the surface of the first trench; forming a gate on the upper surface of the gate dielectric layer; Forming a first metal, wherein the first metal covers a portion of an upper surface of the first N+ implantation region, a side surface of the first P-well region, and an upper surface of the second P+ implantation region to form an ohmic contact; forming a second metal, wherein the second metal covers a set position of the N-epitaxial layer to form a Schottky contact, and the second metal is connected to the first metal; A third metal is formed on the back side of the N+ substrate.
9. The method for preparing a silicon carbide UMOSFET device integrated with SBD according to claim 8, characterized in that: The ohmic contact forming process includes: performing a rapid thermal annealing process in an argon atmosphere.
10. The method for preparing a silicon carbide UMOSFET device integrated with SBD according to claim 8, characterized in that: The formation process of the Schottky contact includes: annealing the second metal by a low-temperature rapid thermal annealing process.
Citation Information
Patent Citations
Silicon carbide UMOSFET device integrated with SBD
CN214378459U