A / D Converter

Abstract

An A / D converter comprises: a sampler (2) comprising a sampling capacitor (Cs) and sampling an input signal; a D / A converter (6) selectively outputting an analog voltage; an integrator (3) integrating an input from the sampler and an input from the D / A converter; a plurality of switches comprising a first switch (Ss3) independently connecting the sampler to the integrator, a second switch (Sd3) independently connecting the D / A converter to the integrator, a third switch (Ss2) and a fourth switch (Sd2); a quantizer (4) quantizing an output of the integrator; a control circuit (5) outputting a digital value based on the output of the quantizer; and a reference potential generating circuit (10, 20, 30) providing a second reference potential (Vcm2) to the integrator side of the sampler through the third switch and providing a first reference potential (Vcm1) to the integrator side of the D / A converter through the fourth switch.

Description

Technical Field

[0001] The present disclosure relates to an A / D converter. Background Art

[0002] In the A / D converter, as a comparative example, there is an A / D converter in which a sampler and a D / A converter (hereinafter, also referred to as DAC) are independently connected to an integrator. Such an A / D converter can perform a sample / hold operation and a DAC operation of an input signal at independent timings. Therefore, versatility is enhanced, and high-performance A / D conversion processing can be performed.

[0003] In this case, the sampler and the DAC can operate independently. Therefore, when both circuits are connected to the analog ground as a reference potential and thereafter one of these circuits is turned off, or when these circuits are turned off at the same time and a slight time difference occurs, etc., it may cause a decrease in calculation accuracy as a whole. As a result, the performance of the A / D converter may deteriorate.

[0004] Related technical literature

[0005] Patent Literature

[0006] Patent Document 1: JP 2018-133702A Summary of the invention

[0007] One example of the present disclosure provides an A / D converter capable of suppressing a decrease in calculation accuracy even when a sampler and a DAC are independent.

[0008] According to an exemplary embodiment, an A / D converter includes: a sampler, which includes a sampling capacitor and samples an input signal; a D / A converter, which selectively outputs an analog voltage according to a control signal; an integrator, which integrates an input from the sampler and an input from the D / A converter; a plurality of switches, which may include a first switch that independently connects the sampler to the integrator, a second switch, a third switch, and a fourth switch that independently connects the D / A converter to the integrator; a quantizer, which can quantize an output of the integrator; a control circuit, which can output a digital value based on the output of the quantizer; and a reference potential generating circuit, which can provide a second reference potential to the integrator side of the sampler through the third switch and provide a first reference potential to the integrator side of the D / A converter through the fourth switch.

[0009] The above configuration is adopted because the inventors found that the potential fluctuation of the reference potential (analog ground) is a factor that causes the reduction and degradation. That is, the comparative example configuration in which the sampler and the DAC (D / A converter) are independent is designed so that each of the switches connected to one reference potential is turned off at the same time on the timing diagram. However, in actual circuit operation, the switches are not turned off at the same time, and a slight delay occurs.

[0010] On the other hand, the same amplifier generates a reference potential. Therefore, in the case where such a delay occurs, when one of the switches is turned off, the other reference potential may fluctuate. Therefore, for example, in the operation of the sampler and the DAC, the operation of the case where only one of the switches is turned off is different from the operation of the case where both switches are turned off in terms of the DAC calculation amount. The performance as an A / D converter may be reduced.

[0011] According to an example of the present disclosure, even in this case, a reference potential generating circuit that independently generates a first reference potential and a second reference potential set to the same reference potential is provided, so that in these two operations, reference potential fluctuations do not occur due to interference. Therefore, fluctuations in the reference potential due to switching of the switch can be avoided, and degradation of the performance as an A / D converter can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other features and advantages of the present disclosure will become more apparent from the following detailed description with reference to the accompanying drawings. In the accompanying drawings:

[0013] Figure 1 is an electrical configuration diagram showing a first embodiment;

[0014] Figure 2 is an electrical configuration diagram of a reference potential generating circuit;

[0015] Figure 3 It is a timing diagram;

[0016] Figure 4 is an electrical configuration diagram showing a second embodiment;

[0017] Figure 5 is an electrical configuration diagram showing a third embodiment;

[0018] Figure 6 is an electrical configuration diagram showing a fourth embodiment; and

[0019] Figure 7 2 is a diagram showing the electrical configuration of the fifth embodiment. DETAILED DESCRIPTION

[0020] (First embodiment)

[0021] Below, we will refer to Figures 1 to 3 A first embodiment to which a ΔΣ modulation type A / D converter is applied is described.

[0022] exist Figure 1 In the embodiment, a ΔΣ modulation type A / D converter (hereinafter, simply referred to as “A / D converter”) 1 includes an input terminal 1a for an analog input voltage Vin and an output terminal 1b for a digital signal output Dout. The A / D converter 1 includes a sampler 2, an integration circuit 3, a quantizer 4, a control circuit 5, and a D / A converter 6.

[0023] The sampler 2 includes a sampling capacitor Cs and four switches Ss1 to Ss4. The input terminal 1a is connected in series to the integration circuit 3 through the switch Ss1, the sampling capacitor Cs, and the switch Ss3. The input side of the sampling capacitor Cs is connected to the analog ground Vcm1 as a first reference potential through the switch Ss4. The output side is connected to the analog ground Vcm2 as a second reference potential through the switch Ss2. The on-off operation of the four switches Ss1 to Ss4 is controlled by the control circuit 5. The potentials of the analog grounds Vcm1 and Vcm2 are set to be the same.

[0024] In this case, the control circuit 5 performs a sampling operation and a holding operation. In the sampling operation, the control circuit 5 turns on the switches Ss1 and Ss2, and turns off the switches Ss3 and Ss4. In the holding operation, the control circuit 5 turns off the switches Ss1 and Ss2, and turns on the switches Ss3 and Ss4.

[0025] The integration circuit 3 includes an amplifier 3a and an integration capacitor Cf. The inverting input terminal of the amplifier 3a is connected to the switch Ss3 of the sampler 2, and is connected to the output terminal through the integration capacitor Cf. The non-inverting input terminal of the amplifier 3a is connected to the analog ground Vcm1. The amplifier 3a outputs the result of the integration processing performed according to the input from the sampler 2 and the D / A converter 6 as an analog output Vamp.

[0026] The quantizer 4 includes a comparator inside. The quantizer 4 receives the analog output Vamp output from the amplifier 3a of the integration circuit 3, compares the analog output Vamp with the threshold voltage, and outputs the determination result (i.e., the quantization result Qout) to the control circuit 5. The control circuit 5 outputs a control signal corresponding to the quantization result Qout to a D / A converter 6 described later, and outputs a ΔΣ modulation result Dout according to the result of integrating the quantization result Qout.

[0027] The D / A converter 6 includes a DAC capacitor Cd and five switches Sdt, Sdm, Sdb, Sd2, and Sd3. The D / A converter 6 also has three analog potentials Vrefp, Vcm1, and Vrefm as reference potentials. The reference potential Vcm1 is set to an analog ground as a reference potential. Vrefp is set to a potential higher than Vcm1. Vrefp is set to a potential lower than Vcm1.

[0028] When the reference potential Vcm1 is 0 V, Vrefp and Vrefm are set to satisfy the equation Vrefp=-Vrefm, that is, Vrefp and Vrefm are equal in absolute value and opposite in polarity to each other. Switches Sdt, Sdm and Sdb serve as selection switches and connect Vrefp, Vcm1 and Vrefm to the input side of the DAC capacitor Cd.

[0029] The output side of the DAC capacitor Cd is connected to the analog ground Vcm1 through a switch Sd2 and to the inverting input terminal of the amplifier 3a of the integration circuit 3 through a switch Sd3. The on-off operation of the five switches Sdt, Sdm, Sdb, Sd2 and Sd3 is controlled by the control circuit 5.

[0030] In this case, the control circuit 5 performs a sampling operation and a holding operation based on a control signal corresponding to the quantization result output from the quantizer 4. In the sampling operation, the control circuit 5 turns on the switch Sd2, and turns on any one of the selection switches Sdt, Sdm, and Sdb. In the holding operation, the control circuit 5 turns off the switch Sd2, and turns on the switch Sd3, and turns on any one of the switches Sdt, Sdm, and Sdb.

[0031] The reference potential generating circuit 10 generates reference voltages Vcm1 and Vcm2 (ie, reference potentials) as analog grounds. Figure 2 As shown, specifically, in the reference potential generating circuit 10, a voltage divider circuit 11 including a series circuit of resistors 11a and 11b is connected between analog voltages Va and Vb. An output voltage Vcm is obtained from a common connection point of resistors 11a and 11b. The output voltage Vcm generates analog grounds Vcm1 and Vcm2 through two amplifiers 12 and 13. Since the analog grounds Vcm1 and Vcm2 pass through amplifiers 12 and 13, respectively, the potential fluctuation on one side does not affect the potential on the other side, that is, there is no mutual interference. In the accompanying drawings, the reference potential generating circuit 10 may also be referred to as a "REF potential generating circuit".

[0032] Next, we will refer to Figure 3The operation of the above-mentioned configuration is described, in which the sampling period and holding period of the sampling capacitor Cs do not match the sampling period and holding period of the DAC capacitor Cd, and are set independently. The sampling and holding in the sampling period and holding period are set to a period that matches the timing of the clock. Figure 3 As shown, the clock is shown from time points t0 to t4.

[0033] Figure 3 The sampling period and the holding period are shown as the operating states of the sampling capacitor Cs and the DAC capacitor Cd. In addition, Figure 3 The on-off state of each switch corresponding to the sampling period and the holding period is shown.

[0034] As a basic content of the A / D conversion process, a sampling operation is performed to bring the analog input voltage Vin input to the input terminal 1a to the sampling capacitor Cs in the sampling period S (t0 to t3), and a holding operation is performed to transfer the charge based on the input signal Vin accumulated in the sampling capacitor Cs in the holding period H (t3 to t4) to the integration capacitor Cf. In the sampler 2, the above-mentioned sampling operation and the above-mentioned holding operation are alternately performed.

[0035] At this time, in the case where the sampling operation is performed on the sampling capacitor Cs, the control circuit 5 turns on the switches Ss1 and Ss2 and turns off the switches Ss3 and Ss4 at the time point t0, as shown in FIG. Figure 3 As shown. As a result, the input side of the sampling capacitor Cs is connected to the input terminal 1a, and the output side is connected to the analog ground Vcm2. Therefore, the sampling capacitor Cs is charged by the analog input voltage Vin.

[0036] The control circuit 5 turns off the switches Ss1 and Ss2 at the time point t3, and turns on the switches Ss3 and Ss4 when performing the hold operation. Thus, the input side of the sampling capacitor Cs is connected to the analog ground Vcm1, and the output side is connected to the inverting input terminal of the amplifier 3a of the integration circuit 3. Thus, the charge accumulated in the sampling capacitor Cs is transferred to the integration capacitor Cf.

[0037] On the other hand, the control circuit 5 performs the sampling operation and the holding operation on the DAC capacitor Cd alternately for each clock, as shown in FIG. Figure 3 At this time, in the sampling operation in the sampling period S (t0 to t1), the control circuit 5 turns on the switch Sd2 at the time point t0 and keeps the switch Sd3 in the off state.

[0038] At the same time, the control circuit 5 turns on one of the selection switches Sdt, Sdm and Sdb. Thus, the input side of the DAC capacitor Cd is connected to any one of Vrefp, Vrefm and Vcm1, and the output side is connected to the analog ground Vcm1. The DAC capacitor Cd is charged by the potential of the connected voltage.

[0039] Here, for example, the selection switch Sdm is turned on, and the selection switch is maintained in an off state. Thus, the voltage Vcm1 is applied to both ends of the DAC capacitor Cd.

[0040] In the holding operation performed in the holding period (t1 to t2), the control circuit 5 turns off the switch Sd2 at the time point t1, and turns on the switch Sd3. At the same time, the control circuit 5 turns on any one of the selection switches Sdt, Sdm, and Sdb. Thus, the input side of the DAC capacitor Cd is connected to any one of Vrefp, Vrefm, and Vcm1, and the output side is connected to the inverting input terminal of the amplifier 3a of the integration circuit 3. Thus, the charge accumulated in the DAC capacitor Cd is transferred to the integration capacitor Cf.

[0041] Here, for example, the selection switch Sdt is turned on, the selection switch Sdm is turned off, and the selection switch Sdb is kept in an off state. Thus, the reference voltage Vrefp is applied to the input side of the DAC capacitor Cd, and the output side is connected to the inverting input terminal of the amplifier 3a.

[0042] At this time, by combining the three potentials Vrefp, Vrefm and Vcm1 selected by the selection switches Sdt, Sdm and Sdb in each of the sampling period and the holding period, the D / A converter 6 can transfer charges corresponding to the analog potentials of multiple levels to the integration capacitor Cf. The quantizer 4 performs quantization processing at the time points t0, t2 and t4 of the clock, and outputs the quantized data Qout to the control circuit 5.

[0043] When the operations in the sampling period and the holding period are performed as described above, at time point t1, the switch Sd2 of the D / A converter 6 is turned off and the analog ground Vcm1 is disconnected. Then, the on state of the switch Ss2 of the sampler 2 is maintained, and the output side of the sampling capacitor Cs is connected to the analog ground Vcm2.

[0044] On the other hand, at time point t3, the switch Sd2 of the D / A converter 6 is turned off, and the analog ground Vcm1 is disconnected. The switch Ss2 of the sampler 2 is also turned off, and the analog ground Vcm2 is disconnected. Then, although the switches Sd2 and Ss2 are controlled to be turned off simultaneously in sequence, in actual circuit operation, the switches are not turned off simultaneously, and a slight difference may occur.

[0045] Therefore, in the comparative example, when one of the switches is turned off, the potential of the common analog ground fluctuates. Before the other switch is turned off, the potential fluctuation effect is exerted by the switch. A state in which the calculation accuracy is reduced may occur.

[0046] In this embodiment, even when the turn-off timing of the switch differs, the analog grounds Vcm1 and Vcm2 are set to different reference potentials, and thus the influence of voltage fluctuation on one side cannot be applied to the other side. A reference potential can be provided as a stable analog ground. A decrease in overall performance can be suppressed.

[0047] According to the present embodiment as described above, the circuit 10 for applying the analog ground potential is placed. The analog grounds Vcm1 and Vcm2 for suppressing the voltage fluctuation caused by the on-off operation of the switch are independently provided. Therefore, even when the off timing of the switches Ss2 and Sd2 causes fluctuation of one reference potential, the other reference potential can be prevented from being affected.

[0048] Thus, in the sampler 2, even if the analog ground Vcm2 fluctuates when switching from sampling to holding of Vin, it does not affect the potential (Vcm1) of other analog grounds. Since the sampling capacitor Cs and the DAC capacitor Cd can push out the charge of the analog ground potential Vcm1 at the same potential during the holding period, a conversion output with high accuracy can be obtained.

[0049] In the above-described embodiment, a conversion output with higher accuracy can be obtained by feeding back the quantization result multiple times in each sampling cycle. In this case, when the quantization result is fed back multiple times, a state in which the calculation accuracy of each phase is different due to an error caused by the reference potential fluctuation during the phase in which only Sd2 is turned off and during the phase in which Ss2 and Sd2 are turned off at the same time can be suppressed. Therefore, the accuracy can be improved.

[0050] In the above embodiment, the switch Ss1 and the switch Ss2 of the sampler 2 are turned on and off in the same phase and in a synchronized manner. However, the timing of turning on and off does not have to be exactly the same, but may be slightly different. The timing of turning on and off of the switches Ss3 and Ss4 may also be slightly different.

[0051] In addition, the switch Ss1 and the switch Ss2 and the switch Ss3 and the switch Ss4 are operated to be turned on and off oppositely (i.e., in an opposite manner) to each other. However, for example, the switch Ss1 and the switch Ss4 connected to one end of the sampling capacitor Cs or the switch Ss2 and the switch Ss3 connected to the other end of the sampling capacitor Cs may be turned off simultaneously for a specific period of time at the transition between turning on and off. Similarly, although the switches Sd2 and Sd3 are operated to be turned on and off oppositely (i.e., in an opposite manner), at the time of switching, both of these switches Sd2 and Sd3 may be turned off simultaneously for a specific period of time.

[0052] (Second embodiment)

[0053] Figure 4 A second embodiment is shown. The differences from the first embodiment will be described below. This embodiment includes a reference potential generating circuit 20 instead of the reference potential generating circuit 10 of the first embodiment.

[0054] like Figure 4 As shown, in the reference potential generating circuit 20, a voltage divider circuit 21 including a series circuit of resistors 21a and 21b is connected between analog voltages Va and Vb. A first output voltage Vcm_1 is obtained from a common connection point of the resistors 21a and 21b. A voltage divider circuit 22 including a series circuit of resistors 22a and 22b is connected between analog voltages Va and Vb. A second output voltage Vcm_2 is obtained from a common connection point of the resistors 22a and 22b. The first output voltage Vcm_1 and the second output voltage Vcm_2 generate analog grounds Vcm1 and Vcm2 through amplifiers 23 and 24, respectively.

[0055] According to such a second embodiment, since the reference potential generating circuit 20 has the above-mentioned structure, it can suppress the voltage fluctuation transmitted through the parasitic capacitance between the analog grounds Vcm1 and Vcm2 as the reference potential, and can further improve the accuracy by performing operations similar to those of the first embodiment.

[0056] (Third Embodiment)

[0057] Figure 5 A third embodiment is shown. The differences from the first embodiment will be described below. This embodiment includes a reference potential generating circuit 30 instead of the reference potential generating circuit 10 of the first embodiment.

[0058] like Figure 5As shown, in the reference potential generating circuit 30, a voltage dividing circuit 31 including a series circuit of resistors 31a and 31b is connected between analog voltages Va and Vb. An output voltage Vcm is obtained from a common connection point of the resistors 31a and 31b. The output voltage Vcm is output through an amplifier 32. Then, analog grounds Vcm1 and Vcm2 are output through resistors 33 and 34, respectively.

[0059] According to such a third embodiment, since the reference potential generating circuit 30 has the above-mentioned configuration, there may be actual interference in a state where the reference potential generating circuit 30 includes a simple amplifier. An operation effect similar to that of the first embodiment can be obtained. The resistors 33 and 34 may be wiring resistors.

[0060] (Fourth embodiment)

[0061] Figure 6 A fourth embodiment is shown. The differences from the first embodiment will be described below. In the sampler 2 of the A / D converter 100 of this embodiment, the output side and the input side of the sampling capacitor Cs are connected to Vcm2 as an analog ground through switches Ss2 and Ss4, respectively.

[0062] In the above configuration, the analog grounds Vcm1 and Vcm2 are generated by the reference potential generating circuit 10. The analog grounds Vcm1 and Vcm2 may be generated by the reference potential generating circuit 20 of the second embodiment and the reference potential generating circuit 30 of the third embodiment. According to the fourth embodiment of such configuration, an operation effect similar to that of the first embodiment can be obtained.

[0063] Furthermore, according to this fourth embodiment, in addition to the above-mentioned effects, the following effects can be achieved. That is, in the above-mentioned operation, one of the switches Ss2 and Ss4 is always kept in the on state. Therefore, the analog ground Vcm2 is always connected to one terminal of the sampling capacitor Cs.

[0064] Thus, it is possible to prevent the analog ground Vcm2 from becoming unloaded and maintain a stable state. In the sample / hold operation of the sampler 2, the operation performed only by the analog ground Vcm2 can be performed. Therefore, it is not dependent on the input voltage Vin.

[0065] (Fifth Embodiment)

[0066] Figure 7 The fifth embodiment is shown. The differences from the first embodiment will be described below. The A / D converter 110 of this embodiment is shown to be applied to a device other than Figure 1 An example of a hybrid A / D converter including the sub-A / D converter 111 is included in addition to the configuration in FIG.

[0067] like Figure 7As shown, in this embodiment, the sub A / D converter 111 is placed in parallel with the quantizer 4 in the output terminal side of the amplifier 3a of the integration circuit 3. As shown in the following equation, the adder 112 adds the digital output Mout of the control circuit 5 and the digital output Lout output from the sub A / D converter 111, and the addition result is output as Dout.

[0068] Dout=Mout+Lout

[0069] The sub-A / D converter 111 performs a part of quantization in the A / D conversion process of the quantizer 4. The output of the amplifier 3a is taken and input to the adder 112 as the digital output Lout together with the digital output Mout of the control circuit 5. The adder 112 adds Mout output from the control circuit 5 and the digital output Lout output from the sub-A / D converter 111, and obtains the final digital output Dout. The quantizer 4 and the control circuit 5 generate high-order digital values. The sub-A / D converter 111 generates the remaining low-order digital values.

[0070] A generally known A / D converter can be used as the sub A / D converter 111. For example, a cyclic A / D converter can be used.

[0071] Even when the sub A / D converter is applied to the hybrid A / D converter, an operation effect similar to that of the first embodiment can be achieved.

[0072] (Other embodiments)

[0073] The present disclosure should not be limited to the above-described embodiments, and various embodiments may be further implemented without departing from the scope of the present invention. For example, the embodiments may be modified or extended as described below.

[0074] In each of the above-described embodiments, circuits 10, 20, 30, etc. are used. However, different circuit configurations can generate independent reference potentials Vcm1 and Vcm2. As reference potential generating circuits 10, 20, and 30, appropriate reference potential generating circuits can be selectively used depending on the relationship between the accuracy required for the circuit and the circuit configuration.

[0075] The first reference potential Vcm1 and the second reference potential Vcm2 are set to a ground level which is the same potential as the analog ground. However, the first reference potential Vcm1 and the second reference potential Vcm2 may be set to the same potential which is a predetermined potential other than the ground level.

[0076] In the above embodiment, the number of executed cycles in the sampling period and the holding period of the D / A converter 6 is set to two corresponding to the sampling period of the sampler 2. However, the number of executed cycles may be set to three or more.

[0077] Although the present disclosure has been described according to the embodiments, it should be understood that the present disclosure is not limited to the embodiments and structures disclosed therein. The present disclosure encompasses various modifications and variations within the scope of equivalents. In addition, various combinations and forms, and further including only one element or more or less than other combinations and forms of these elements are also within the spirit and scope of the present disclosure.

Claims

1. An A / D converter, comprising: A sampler (2), the sampler (2) comprising a sampling capacitor (Cs) and configured to sample an input signal; A D / A converter (6), the D / A converter (6) being configured to selectively output an analog voltage according to a control signal; an integrator (3), the integrator (3) being configured to integrate an input from the sampler and an input from the D / A converter; a plurality of switches, the plurality of switches comprising a first switch (Ss3) independently connecting the sampler to the integrator, a second switch (Sd3) independently connecting the D / A converter to the integrator, a third switch (Ss2) and a fourth switch (Sd2); a quantizer (4), the quantizer (4) being configured to quantize the output of the integrator; a control circuit (5) configured to output a digital value based on an output of the quantizer; as well as A reference potential generating circuit (10, 20, 30) is configured to provide a second reference potential (Vcm2) to the integrator side of the sampler through the third switch, and to provide a first reference potential (Vcm1) to the integrator side of the D / A converter through the fourth switch.

2. The A / D converter according to claim 1, wherein: The plurality of switches further includes a fifth switch (Ss4); and The reference potential generating circuit is configured to provide the first reference potential to an input side of the sampler through the fifth switch.

3. The A / D converter according to claim 1, wherein: The reference potential generating circuit (10) comprises a voltage dividing circuit (11), a first amplifier (12) for providing the first reference potential, and a second amplifier (13) for providing the second reference potential.

4. The A / D converter according to claim 1, wherein: The reference potential generating circuit (20) comprises a first voltage dividing circuit (21) for providing the first reference potential, a first amplifier (23) for providing the first reference potential, a second voltage dividing circuit (22) for providing the second reference potential, and a second amplifier (24) for providing the second reference potential.

5. The A / D converter according to claim 1, wherein: The reference potential generating circuit (30) includes a voltage dividing circuit (31), an amplifier (32), a first resistor (33) for providing the first reference potential, and a second resistor (34) for providing the second reference potential.

6. The A / D converter according to any one of claims 1 to 5, wherein: The A / D converter is a ΔΣ type A / D converter (1).

7. The A / D converter according to any one of claims 1 to 5, further comprising: a sub-A / D converter (111), the sub-A / D converter (111) being placed in parallel with the quantizer and the control circuit, in: The quantizer and the control circuit are configured to generate a high-order digital value; and The sub-A / D converter is configured to generate the remaining lower digital values.

8. The A / D converter according to claim 6, wherein: The quantization results are fed back multiple times in each sampling cycle.

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