Asymmetric silicon carbide UMOSFET device with shielding area and preparation method

Abstract

The present invention provides an asymmetric silicon carbide UMOSFET device with a shielding region and a preparation method thereof; the device comprises a second metal from bottom to top, an N+ substrate and an N-epitaxial layer; the N-epitaxial layer has a first P-well region, a first N+ injection region, a first P+ injection region, a second P+ injection region, a first groove and a second groove; and further comprises: a first metal, the first metal covers a portion of the upper surface of the first N+ injection region, a side surface of the first P-well region and an upper surface of the second P+ injection region to form an ohmic contact; a deep P+ shielding region and a P+ injection region partially surrounding the groove corner are used to effectively shield or alleviate the electric field concentration phenomenon at two groove corners of a gate oxide layer, thereby improving the reverse withstand voltage capability and the use reliability of the device.

Description

[Technical field]

[0001] The invention relates to the field of semiconductors, and in particular to an asymmetric silicon carbide UMOSFET device with a shielding region and a preparation method thereof. [Background technology]

[0002] In recent years, with the continuous development of power electronic systems, higher requirements have been placed on the power devices in the system. However, silicon (Si)-based power electronic devices can no longer meet the requirements of system applications due to the limitations of the materials themselves.

[0003] As a representative of the third generation of semiconductor materials, silicon carbide (SiC) materials are far superior to silicon materials in many characteristics. As a commercialized device in recent years, silicon carbide MOSFET devices have great potential to replace existing IGBTs in terms of on-resistance, switching time, switching loss and heat dissipation performance.

[0004] In SiC UMOSFET, due to the trench-shaped structure of the gate oxide layer, the electric field concentration generated at the corner is greater than the electric field in the device drift region, so the gate oxide layer may be broken down before the body region breaks down, which greatly affects the reliability of the device. Therefore, researchers will use a variety of gate oxide reinforcement structures to weaken the electric field concentration phenomenon at the corners of the gate oxide layer of SiC UMOSFET, thereby improving device performance. [Summary of the invention]

[0005] The technical problem to be solved by the present invention is to provide an asymmetric silicon carbide MOSFET device with a shielding area and a preparation method thereof.

[0006] One of the present inventions is achieved as follows: an asymmetric silicon carbide UMOSFET device with a shielding region, comprising

[0007] a second metal, the second metal serving as a drain electrode;

[0008] An N+ substrate, one side of the N+ substrate is connected to the second metal;

[0009] an N-epitaxial layer, the other side of the N+ substrate being connected to the N-epitaxial layer;

[0010] a first P+ implantation region, wherein the first P+ implantation region is L-shaped and connected to the N-epitaxial layer;

[0011] a second P+ implantation region, wherein the second P+ implantation region is L-shaped and connected to the N-epitaxial layer;

[0012] a first P-well region, the first P-well region being connected to the second P+ implant region and the N-epitaxial layer;

[0013] a first N+ implant region connected to the first P-well region;

[0014] a first trench, the first trench respectively connecting the N-epitaxial layer, the first P+ implantation region, the first P-well region and the first N+ implantation region;

[0015] a second trench, the second trench connecting the second P+ implantation region, the first P-well region and the first N+ implantation region respectively;

[0016] a gate dielectric layer, covering the side surface of the first trench and the upper surface of the trench bottom;

[0017] a gate, covering the upper surface of the gate dielectric layer and filling the first trench;

[0018] A first metal covers a set position on the upper surface of the first N+ implantation region, a side surface of the first N+ implantation region, a side surface of the first P-well region, and an upper surface of the second P+ implantation region to form an ohmic contact.

[0019] Furthermore, the first groove has a depth of 1 μm to 3 μm and a width of 0.5 μm to 2 μm; the second groove has a depth of 1 μm to 3 μm and a width of 0.5 μm to 2 μm.

[0020] Furthermore, the first P+ injection region has a depth of 1.5 μm to 3 μm and a width of 0.8 μm to 2 μm; the second P+ injection region has a depth of 2 μm to 3 μm and a width of 1 μm to 2 μm.

[0021] Furthermore, the first P-well region has a depth of 0.3 μm to 1.0 μm and a width of 0.3 μm to 1 μm; the first N+ implantation region has a depth of 0.1 μm to 0.5 μm and a width of 0.3 μm to 1 μm.

[0022] Further, the depth of the first P+ implantation region is greater than the depth of the first trench, and the depth of the second P+ implantation region is greater than the depth of the second trench.

[0023] Further, the depths of the first trench and the second trench are greater than the depth of the first P-well region.

[0024] Furthermore, a distance between the left side of the first P+ implantation region and the right side of the first trench is 0.5 μm to 0.7 μm.

[0025] Furthermore, a distance between the right side of the second P+ implantation region and the left side of the first trench is in the range of 0.1 μm to 0.3 μm.

[0026] The second aspect of the present invention is achieved as follows: a method for preparing an asymmetric silicon carbide UMOSFET device with a shielding region comprises the following steps:

[0027] forming an N-epitaxial layer on an N+ substrate;

[0028] Performing P+ region implantation on a portion of the surface of the N-epitaxial layer to form a first P+ implantation region and a second P+ implantation region;

[0029] Performing N+ region implantation at a set position on the surface of the N- epitaxial layer to form a transitional N+ implantation region;

[0030] Performing P-region implantation on the surface of the transitional N+ implantation region to form a first P-well region;

[0031] Performing N+ region implantation on the surface of the P-region to form a first N+ implantation region;

[0032] Etching the set positions of the first N+ region, the first P-well region, the first P+ implantation region, and the second P+ implantation region to form a first trench and a second trench;

[0033] The left side wall of the first trench is provided with a first P-well region and a first N+ implantation region on the left;

[0034] The P+ injection region to the right of the right side wall of the first trench becomes the first P+ injection region;

[0035] The right side wall of the second trench is the first P-well region and the first N+ implantation region;

[0036] The P+ injection region to the right of the right side wall of the second trench becomes the second P+ injection region;

[0037] forming a gate dielectric layer to cover the surface of the first trench;

[0038] forming a gate on the upper surface of the gate dielectric layer;

[0039] Forming a first metal, wherein the first metal covers a portion of the upper surface of the first N+ implantation region, the side surface of the first N+ implantation region, the side surface of the first P-well region, and the upper surface of the second P+ implantation region to form an ohmic contact;

[0040] A drain electrode is formed on the N+ substrate.

[0041] Furthermore, the process of forming the ohmic contact includes: performing a rapid thermal annealing process in an argon atmosphere.

[0042] The advantages of the present invention are: an asymmetric silicon carbide MOSFET device with a shielding area and a preparation method of the present invention sacrifice half of the channel in the device, introduce a deep P+ injection area that partially surrounds the groove corner, and shield the electric field concentration phenomenon at the groove corner on the right side of the gate oxide layer while ensuring that the forward current is large enough.

[0043] A second groove is formed by etching part of the first N+ injection region, the first P-well region and the second P+ injection region, and a deeper second P+ injection region is formed as a P+ shielding layer, which effectively alleviates the electric field concentration phenomenon at the groove corner on the left side of the gate oxide layer, thereby improving the voltage resistance and working reliability of the device.

Brief Description of the Drawings

[0044] The present invention will be further described below in conjunction with embodiments with reference to the accompanying drawings.

[0045] Figure 1 It is a schematic diagram of an asymmetric silicon carbide UMOSFET device with a shielding area of ​​the present invention;

[0046] Figure 2 The corresponding structure diagram of the steps for preparing an asymmetric silicon carbide UMOSFET device with a shielding area Figure 1 ;

[0047] Figure 3 The corresponding structure diagram of the steps for preparing an asymmetric silicon carbide UMOSFET device with a shielding area Figure 2 ;

[0048] Figure 4 The corresponding structure diagram of the steps for preparing an asymmetric silicon carbide UMOSFET device with a shielding area Figure 3 ;

[0049] Figure 5 The corresponding structure diagram of the steps for preparing an asymmetric silicon carbide UMOSFET device with a shielding area Figure 4 ;

[0050] Figure 6 The corresponding structure diagram of the steps for preparing an asymmetric silicon carbide UMOSFET device with a shielding area Figure 5 ;

[0051] Figure 7 The corresponding structure diagram of the steps for preparing an asymmetric silicon carbide UMOSFET device with a shielding area Figure 6 . [Specific implementation method]

[0052] The embodiment of the present invention solves the technical problems of poor voltage resistance and unreliable operation in the prior art by providing an asymmetric silicon carbide MOSFET device with a shielding area and a preparation method thereof, and achieves the technical effect of effectively alleviating the electric field concentration phenomenon at the groove corner on the left side of the gate oxide layer, thereby improving the voltage resistance and working reliability of the device.

[0053] The technical solution in the embodiment of the present invention is to solve the above problems, and the overall idea is as follows:

[0054] Example 1

[0055] like Figure 1 As shown, this embodiment provides an asymmetric silicon carbide UMOSFET device with a shielding region, and the device includes: a second metal 29 , an N+ substrate 11 and an N− epitaxial layer 12 from bottom to top.

[0056] The N-epitaxial layer 12 has a first P+ implantation region 23, a second P+ implantation region 20 and a first P-well region 21. The first P-well region 21 has a first N+ implantation region 22 (the depth of the first P-well region 21 is greater than that of the first N+ implantation region 22).

[0057] The device also includes: a gate dielectric layer 26 covering the bottom and sidewalls of the first trench 24; a gate 27 located on the gate dielectric layer 26 and filling the first trench 24; a first metal 28, the first metal 28 forms a first ohmic contact on a portion of the upper surface of the first N+ injection region 22, the side surface of the first P-well region 21 and the upper surface of the second P+ injection region 20; and a second metal 29 is also provided on the back side of the N+ substrate 11.

[0058] The first metal 28 forms a source electrode of the MOS device, and the second metal 29 forms a drain electrode of the MOS device.

[0059] In this embodiment, the N+ substrate 11 may be made of a doping concentration of 5×10 18 cm -3 The silicon carbide material may be 350 μm thick.

[0060] In this embodiment, the doping concentration of the N-epitaxial layer 12 can be 6×10 15 cm -3 , the thickness can be 10μm.

[0061] In this embodiment, the doping concentration of the first P-well region 21 is 6×10 16 cm -3 , with a width of 0.7 μm and a depth of 1 μm.

[0062] In this embodiment, the doping concentration of the first N+ implantation region 22 is 9×10 18 cm -3, with a width of 0.7μm and a depth of 0.5μm.

[0063] In this embodiment, the first trench 24 has a width of 1.2 μm and a depth of 1.5 μm.

[0064] In this embodiment, the second trench 25 has a width of 0.7 μm and a depth of 1.8 μm.

[0065] In this embodiment, the doping concentration of the first P+ injection region 23 and the second P+ injection region 20 is 1×10 19 cm -3 The first P+ implantation region 23 has a width of 1.3 μm and a depth of 2 μm; the second P+ implantation region 20 has a width of 1.2 μm and a depth of 2.3 μm.

[0066] In this embodiment, the distance between the left side of the first P+ implantation region and the right side of the first trench is 0.6 μm, and the distance between the right side of the second P+ implantation region and the left side of the first trench is 0.2 μm.

[0067] This embodiment also provides a method for preparing the above-mentioned silicon carbide UMOSFET device, please refer to Figures 2 to 7 , and the final structure please refer to Figure 1 The preparation method comprises the following steps:

[0068] Please refer to Figure 2 On the N+ substrate 11, an N-epitaxial layer 12 is formed by epitaxial growth. The N+ substrate 11 on which the N-epitaxial layer 12 is grown and the N-epitaxial layer 12 are together called an epitaxial wafer.

[0069] Please refer to Figure 3 On the N-epitaxial layer 12, a first mask layer (not shown) is deposited and formed, and the thickness of the first mask is 2 μm. The first mask pattern is formed by a photolithography and etching process. Well implantation is performed on a portion of the surface of the N-epitaxial layer 12, and the implanted ions are Al ions, forming P+ implantation regions 13 and 14.

[0070] Please refer to Figure 4 , remove the first mask layer, and form a second mask layer (not shown) on the re-exposed surface of the N-epitaxial layer, and form a second mask pattern through a photolithography and etching process; then, through N ion implantation, a portion of the surface of the N-epitaxial layer 12 is well implanted to form a transitional N+ implantation region 16.

[0071] Please refer to Figure 5 By means of Al ion implantation, a portion of the surface of the N-epitaxial layer 12 is well implanted to form a P-well region 17.

[0072] Please refer to Figure 6By N ion implantation, a portion of the surface of the N-epitaxial layer 12 is well implanted to form an N+ implantation region 19.

[0073] Please refer to Figure 7 , remove the second mask layer, and form a third mask layer (not shown) on the re-exposed N-epitaxial layer surface, and form a third mask pattern by photolithography and etching. Then, by ICP etching method, Figure 6 The portion of the P-well region 18, the N+ implant region 19, the P+ implant region 13 and the portion of the height of the N-epitaxial layer 12 are etched to form a first trench 24. Figure 6 The partial P-well region 18, the N+ implantation region 19 and the partial height of the P+ implantation region 15 are shown to form a second trench 25. The first P-well region 21 and the first N+ implantation region 22 are formed on the left side wall of the first trench 24, and the first P+ implantation region 23 is formed on the right side wall of the first trench 21; the first P-well region 21 and the first N+ implantation region 22 are formed on the right side wall of the second trench 25, and the second P+ implantation region 20 is partially surrounded below the second trench 25.

[0074] Please refer back to Figure 1 A gate dielectric layer 26 is formed on the sidewall and bottom surface of the first trench 24. Polysilicon is formed to fill the first trench 24 and a gate 27 is formed on the upper surface of the gate dielectric layer 26.

[0075] Please refer back to Figure 1 , forming the first metal 28 as the source of the device, the first metal 28 covers part of the upper surface of the first N+ injection region 22, the side surface of the first P-well region 21 and the upper surface of the second P+ injection region 20 to form a first ohmic contact. When or after forming the first metal 28, a second metal 29 is also formed on the back side of the N+ substrate 11 as a drain electrode.

[0076] In this embodiment, a carbon film (not shown) is formed on the surface of the N-epitaxial layer 12 for protection, including using a carbon film sputtering machine to form a carbon film on the surface of the N-epitaxial layer 12. Then, the implanted ions (implanted ions) are activated by high-temperature annealing, the annealing temperature is 1650° C., the annealing time is 45 minutes, and then the carbon film is removed by an oxidation method. Then, the carbon film is removed by an oxidation method.

[0077] In this embodiment, the process of forming the gate dielectric layer 26 includes performing sacrificial oxidation on the surface of the first trench 24, removing the oxide layer, and then depositing silicon dioxide. Then, photolithography and etching are used to carve a dielectric window to form a source region. Then, a layer of silicon dioxide is grown by thermal oxidation as the gate dielectric layer 26, and annealed in a nitrogen monoxide atmosphere at a temperature of 1200° C. for 1 hour.

[0078] In this embodiment, the process of forming the gate 27 includes depositing a highly doped polysilicon layer by chemical vapor deposition, and then forming the polysilicon gate 27 by photolithography and etching.

[0079] In this embodiment, the process of depositing the first metal 28 and forming the first ohmic contact further includes: performing a rapid thermal annealing process in an argon atmosphere, with an annealing temperature of 1000° C. and an annealing time of 3 minutes. The first metal 28 is aluminum, forming an electrode pattern.

[0080] Not shown in the figure, after forming the first metal 28, another layer of thick metal can be deposited on the back side of the epitaxial wafer and on the second metal 29. The thick metal can be titanium, nickel or silver, etc. The thick metal serves as a back electrode (the back electrode serves as part of the drain electrode).

[0081] See also Figure 1 As shown, an asymmetric silicon carbide UMOSFET device with a shielding region of the present invention comprises:

[0082] a second metal 29, wherein the second metal 29 serves as a drain electrode;

[0083] An N+ substrate 11, one side of the N+ substrate 11 is connected to the second metal 29;

[0084] An N-epitaxial layer 12, the other side of the N+ substrate 11 is connected to the N-epitaxial layer 12;

[0085] a first P+ implantation region 23, wherein the first P+ implantation region 23 is L-shaped and connected to the N-epitaxial layer 12;

[0086] a second P+ implantation region 20, wherein the second P+ implantation region 20 is L-shaped and connected to the N-epitaxial layer 12;

[0087] a first P-well region 21 , the first P-well region 21 being connected to the second P+ implantation region 20 and the N-epitaxial layer 12 ;

[0088] a first N+ implantation region 22 connected to the first P-well region 21;

[0089] a first trench 24, wherein the first trench 24 is connected to the N-epitaxial layer 12, the first P+ implantation region 23, the first P-well region 21 and the first N+ implantation region 22;

[0090] a second trench 25, wherein the second trench 25 is respectively connected to the second P+ implantation region 20, the first P-well region 21 and the first N+ implantation region 22;

[0091] a gate dielectric layer 26, covering the side surface and the upper surface of the bottom of the first trench 24;

[0092] a gate 27 covering the upper surface of the gate dielectric layer 26 and filling the first trench 24;

[0093] A first metal 28 covers a set position on the upper surface of the first N+ implantation region 22, a side surface of the first N+ implantation region 22, a side surface of the first P-well region 21 and an upper surface of the second P+ implantation region 20 to form an ohmic contact.

[0094] The distance between the left side of the first P+ implantation region 23 and the right side of the first trench 24 is 0.5 μm to 0.7 μm. If the distance is too small, the ability of the first P+ implantation region 23 to shield the peak electric field of the gate oxide layer will be weakened; if the distance is too large, the on-resistance of the entire device will increase, causing the device to have a large static loss.

[0095] The spacing between the right side of the second P+ implantation region 20 and the left side of the first trench 24 is 0.1 μm to 0.3 μm. If the spacing is too small, the current path of the device will be reduced, the on-resistance of the device will be increased, and the device will have a larger static loss; if the spacing is too large, the ability of the P+ shielding layer to alleviate the peak electric field of the gate oxide layer will be weakened.

[0096] Although the specific implementation modes of the present invention are described above, those skilled in the art should understand that the specific implementation modes described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. An asymmetric silicon carbide UMOSFET device with a shielding region, characterized in that: include a second metal, the second metal serving as a drain electrode; An N+ substrate, one side of the N+ substrate is connected to the second metal; an N-epitaxial layer, the other side of the N+ substrate being connected to the N-epitaxial layer; a first P+ implantation region, wherein the first P+ implantation region is L-shaped and connected to the N-epitaxial layer; a second P+ implantation region, wherein the second P+ implantation region is L-shaped and connected to the N-epitaxial layer; a first P-well region, the first P-well region being connected to the second P+ implant region and the N-epitaxial layer; a first N+ implant region connected to the first P-well region; a first trench, the first trench respectively connecting the N-epitaxial layer, the first P+ implantation region, the first P-well region and the first N+ implantation region; a second trench, the second trench respectively connecting the second P+ implantation region, the first P-well region and the first N+ implantation region; a gate dielectric layer, covering the side surface of the first trench and the upper surface of the trench bottom; a gate, covering the upper surface of the gate dielectric layer and filling the first trench; A first metal covers a set position on the upper surface of the first N+ implantation region, a side surface of the first N+ implantation region, a side surface of the first P-well region, and an upper surface of the second P+ implantation region to form an ohmic contact.

2. An asymmetric silicon carbide UMOSFET device with a shielding region as claimed in claim 1, characterized in that: The first groove has a depth of 1 μm to 3 μm and a width of 0.5 μm to 2 μm; the second groove has a depth of 1 μm to 3 μm and a width of 0.5 μm to 2 μm.

3. An asymmetric silicon carbide UMOSFET device with a shielding region according to claim 1, characterized in that: The first P+ injection region has a depth of 1.5 μm to 3 μm and a width of 0.8 μm to 2 μm; the second P+ injection region has a depth of 2 μm to 3 μm and a width of 1 μm to 2 μm.

4. An asymmetric silicon carbide UMOSFET device with a shielding region according to claim 1, characterized in that: The first P-well region has a depth of 0.3 μm to 1.0 μm and a width of 0.3 μm to 1 μm; the first N+ implantation region has a depth of 0.1 μm to 0.5 μm and a width of 0.3 μm to 1 μm.

5. An asymmetric silicon carbide UMOSFET device with a shielding region according to claim 1, characterized in that: The depth of the first P+ implantation region is greater than the depth of the first trench, and the depth of the second P+ implantation region is greater than the depth of the second trench.

6. An asymmetric silicon carbide UMOSFET device with a shielding region according to claim 1, characterized in that: The depths of the first trench and the second trench are greater than the depth of the first P-well region.

7. An asymmetric silicon carbide UMOSFET device with a shielding region according to claim 1, characterized in that: The distance between the left side of the first P+ implantation region and the right side of the first trench is 0.5 μm to 0.7 μm.

8. An asymmetric silicon carbide UMOSFET device with a shielding region according to claim 1, characterized in that: The distance between the right side of the second P+ implantation region and the left side of the first trench is 0.1 μm to 0.3 μm.

9. A method for preparing an asymmetric silicon carbide UMOSFET device with a shielding region, characterized in that: The steps include: Forming an N- epitaxial layer on the upper surface of the N+ substrate; In the surface of part of the N-epitaxial layer, a P+ region is implanted to form a first P+ implantation region and a second P+ implantation region spaced apart; In the N- epitaxial layer surface set position N + region implantation, forming a transition N + implantation region; Performing P-region implantation on the surface of the transitional N+ implantation region to form a first P-well region; Performing N+ region implantation on the surface of the first P-well region to form a first N+ implantation region; Etching the set positions of the first N+ implantation region, the first P-well region, the first P+ implantation region and the second P+ implantation region to form a first trench and a second trench; The left side wall of the first trench is, from bottom to top, an N-epitaxial layer, a first P-well region, and a first N+ implantation region, and the right side wall of the first trench is, from right to left, a first P+ implantation region; The right side wall of the second trench is composed of the second P+ implantation region, the first P-well region and the first N+ implantation region from bottom to top; forming a gate dielectric layer to cover the surface of the first trench; forming a gate on the upper surface of the gate dielectric layer; Forming a first metal, wherein the first metal covers a portion of the upper surface of the first N+ implantation region, the side surface of the first N+ implantation region, the side surface of the first P-well region, and the upper surface of the second P+ implantation region to form an ohmic contact; A drain electrode is formed on the lower surface of the N+ substrate.

10. The method for preparing an asymmetric silicon carbide UMOSFET device with a shielding region according to claim 9, characterized in that: The ohmic contact forming process includes: performing a rapid thermal annealing process in an argon atmosphere.

Images