Thin film transistor, image display panel, and method for manufacturing thin film transistor

Abstract

Disclosed are a thin film transistor, an image display panel, and a method for manufacturing a thin film transistor. A thin film transistor in one embodiment includes: a gate; a semiconductor layer formed using amorphous silicon and including a region overlapping the gate when viewed from above; a gate insulating film interposed between the gate and the semiconductor layer; and a source and a drain arranged with a predetermined interval and opposite to each other. The gate includes a first layer and a second layer, the first layer has a first work function, the second layer has a second work function and is interposed between the first layer and the gate insulating film. The semiconductor layer includes an intrinsic region and a low-concentration impurity region, the intrinsic region is composed of non-doped amorphous silicon, the low-concentration impurity region contains impurities at a specified low concentration and is formed separately from the gate insulating film, when the impurity is an n-type impurity, the second work function is smaller than the first work function, and when the impurity is a p-type impurity, the second work function is larger than the first work function.

Description

Technical Field

[0001] The present disclosure relates to a thin film transistor, an image display panel and a method for manufacturing the thin film transistor. Background Art

[0002] Thin film transistors (TFTs) are used as pixel driving elements in display panels installed in flat display devices such as liquid crystal display devices and organic EL display devices. In general, a TFT has a semiconductor layer including a gate, a gate insulating film, a source electrode and a drain electrode, and a channel portion to be a conductive path between the source electrode and the drain electrode. Among such TFTs, TFTs having a semiconductor layer composed of amorphous silicon are widely used in liquid crystal display panels in particular to effectively utilize characteristics such as low cost and low cut-off current.

[0003] In the field of flat display devices such as liquid crystal display devices, the resolution continues to be improved, and the so-called 8K, that is, 33 megapixel liquid crystal display devices are beginning to be released. In order to increase the number of pixels, it is required to miniaturize each pixel. However, if the area of ​​each pixel is simply reduced, the display performance of each pixel may be reduced along with the decrease in the aperture ratio. Therefore, in the progress of the improvement of the resolution, it is required to miniaturize the TFT that drives each pixel and / or miniaturize the bus that supplies power or various signals to each TFT. Summary of the invention

[0004] Technical Problems to be Solved by the Invention

[0005] As a countermeasure for miniaturizing TFT, shortening the channel length, which is the interval between the source and the drain, can be considered. The shortening of the channel length not only leads to the miniaturization of the TFT, but also leads to the thinning of the gate bus configured on the display panel by shortening the gate length (the width of the gate along the relative direction of the source and the drain) related to the channel length. In detail, the gate electrode is connected to the gate bus connected to the gate driver, and is formed integrally with the gate bus by a pattern including the formation of a mask caused by exposure and etching using the mask. Therefore, if only the gate bus is miniaturized, it is sometimes difficult to pattern both the gate bus and the gate with high precision in terms of setting conditions such as exposure and etching. In contrast, if the width of the gate is shortened, the gate bus can be thinned without the problem of patterning accuracy. Therefore, the shortening of the channel length is not only the miniaturization of the TFT, but also the thinning of the gate bus is achieved by shortening the gate length, which can maintain or improve the aperture ratio of each pixel.

[0006] However, the shortening of the channel length causes a decrease in the gate threshold due to the so-called short channel effect, and as a result, the desired switching characteristics may not be obtained. Therefore, in one embodiment of the present disclosure, a new thin film transistor is provided, which does not significantly reduce the performance required by the TFT, can achieve the miniaturization of the TFT, and further achieve the maintenance or improvement of the aperture ratio of the pixels of the image display panel.

[0007] Technical solutions for solving technical problems

[0008] A thin film transistor according to an embodiment of the present disclosure includes: a gate; a semiconductor layer formed using amorphous silicon and including a first region overlapping the gate when viewed from above; a gate insulating film interposed between the gate and the semiconductor layer; and a source and a drain arranged with a predetermined interval above the first region and opposite to each other, the gate including a first layer and a second layer, the first layer having a first work function, the second layer having a second work function and interposed between the first layer and the gate insulating film, the semiconductor layer including an intrinsic region and a low-concentration impurity region, the intrinsic region being composed of undoped amorphous silicon, the low-concentration impurity region containing impurities at a predetermined low concentration and being formed separately from the gate insulating film, when the impurity is an n-type impurity, the second work function is smaller than the first work function, and when the impurity is a p-type impurity, the second work function is larger than the first work function.

[0009] In another embodiment of the present disclosure, an image display panel is provided. The image display panel of another embodiment of the present disclosure includes: a plurality of thin film transistors of one embodiment of the present disclosure, which are formed in a matrix on a substrate; and a plurality of pixels, which are arranged in a matrix on the substrate and driven using the thin film transistors.

[0010] In another embodiment of the present disclosure, a method for manufacturing a thin film transistor is provided. The method for manufacturing a thin film transistor of another embodiment of the present disclosure includes: a step of forming a gate on a substrate; a step of forming a gate insulating film covering the gate; a step of forming a semiconductor layer on the gate insulating film, the semiconductor layer being a layer composed of amorphous silicon and including a first region overlapping the gate when viewed from above; forming a source and a drain having a predetermined interval and facing each other above the first region by film forming and patterning a conductor film; and adding impurities in a predetermined region separated from the gate insulating film in the semiconductor layer, and providing a low-concentration impurity region containing the impurities at a predetermined low concentration in the predetermined region, the step of forming the gate includes: a step of forming a first layer using a material having a first work function; a step of forming a second layer using a material having a second work function, wherein the second layer is between the first layer and the gate insulating film; when the impurity is an n-type impurity, the second work function is smaller than the first work function; when the impurity is a p-type impurity, the second work function is larger than the first work function.

[0011] Beneficial Effects

[0012] According to the thin film transistor and the method for manufacturing the thin film transistor of each of the above embodiments, the specific characteristics of the thin film transistor will not change, and the miniaturization of the TFT can be achieved. Furthermore, the thinning of the wiring connected to the TFT can be achieved. Then, according to the image display panel of the above embodiment, the aperture ratio of each pixel can be increased, and the number of pixels can be increased without reducing the display performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a cross-sectional view showing an example of a thin film transistor according to an embodiment of the present disclosure.

[0014] Figure 2A This is a characteristic diagram showing an example of the relationship between the channel length (L) and the gate threshold value (Vth) of a thin film transistor.

[0015] Figure 2B This is a characteristic diagram showing an example of the relationship between the channel length (L) and the drain current (Ioff) when the thin film transistor is off.

[0016] Figure 3A 3 is a characteristic diagram for explaining the effect of the present disclosure in the relationship between the gate potential (Vg) and the drain current (Id).

[0017] Figure 3B 3 is a characteristic diagram for explaining the effect of the present disclosure on the relationship between the channel length (L) and the gate threshold (Vth).

[0018] Figure 4 It is a cross-sectional view showing another example of the thin film transistor according to one embodiment of the present disclosure.

[0019] Figure 5 FIG. 1 is a schematic diagram showing an example of an image display panel including a thin film transistor according to an embodiment of the present disclosure.

[0020] Fig. 6A This is a cross-sectional view showing an example of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure.

[0021] Figure 6B This is a cross-sectional view showing an example of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure.

[0022] Figure 6C This is a cross-sectional view showing an example of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure.

[0023] Fig.6D This is a cross-sectional view showing an example of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure.

[0024] Fig. 6E This is a cross-sectional view showing an example of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure.

[0025] Fig. 6F This is a cross-sectional view showing an example of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure.

[0026] Figure 6G This is a cross-sectional view showing an example of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure.

[0027] Figure 6H This is a cross-sectional view showing an example of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0028] Hereinafter, a thin film transistor, an image display panel, and a method for manufacturing a thin film transistor according to an embodiment of the present disclosure are described with reference to the accompanying drawings. In addition, the thin film transistor, the image display panel, and the method for manufacturing a thin film transistor according to the present disclosure are not limited to the following embodiments and the description of the referenced drawings.

[0029] [Structure of thin film transistor]

[0030] Figure 1 1 is a cross-sectional view showing an example of a thin film transistor (TFT) 1 according to an embodiment of the present disclosure. Figure 1As shown, the TFT 1 includes a gate electrode 2 formed on a substrate 10, a gate insulating film 3 covering the gate electrode 2, a semiconductor layer 4, a source electrode 5s, and a drain electrode 5d. The semiconductor layer 4 includes a first region 4a overlapping the gate electrode 2 when viewed from above. The gate insulating film 3 is interposed between the gate electrode 2 and the semiconductor layer 4. The source electrode 5s and the drain electrode 5d are arranged to face each other with a predetermined interval L above the first region 4a (in the opposite direction of the gate electrode 2 relative to the semiconductor layer 4). Figure 1 In the illustrated TFT 1, an impurity-containing layer 52 made of amorphous silicon containing impurities and a contact layer 51 are formed between the source electrode 5s and the drain electrode 5d, respectively, and the semiconductor layer 4. In addition, "planar observation" means observing the TFT 1 with a line of sight parallel to the stacking direction from the gate electrode 2 to the source electrode 5s and the drain electrode 5d (a direction perpendicular to the surface of the substrate 10 on which the gate electrode 2 is formed).

[0031] The thin film transistor of the embodiment can be a field effect transistor of any carrier type, n-type or p-type. That is, the region including the impurities possessed by the semiconductor layer 4 (e.g., the low-concentration impurity region 42 described later) and the impurities added to the impurity containing layer 52 can also be any of n-type impurities and p-type impurities. As impurities added to the semiconductor layer 4 composed of amorphous silicon, pentavalent elements such as phosphorus or arsenic (n-type impurities) and trivalent elements such as boron or indium (p-type impurities) are exemplified, but the impurities added to the semiconductor layer 4 and the impurity containing layer 52 are not limited thereto. In the following description, except for the cases where it is specifically stated, the TFT of the embodiment is described by taking the case where TFT 1 is an n-type field effect transistor as an example. Therefore, the layer or region composed of a semiconductor containing impurities, such as the impurity containing layer 52, is also called "n-layer" or "n-region", or "n+ layer" or "n+ region", etc., according to the concentration of the impurity.

[0032] The source electrode 5s and the drain electrode 5d are formed of metals having appropriate conductivity such as copper or aluminum, and are spaced apart from each other and face each other. The semiconductor layer 4 includes a second region 4b sandwiched between the source electrode 5s and the drain electrode 5d when viewed from above. In the second region 4b, a channel of the TFT 1 is formed according to the potential of the gate 2. The second region 4b has a length L as the length (channel length) in the direction in which the source electrode 5s and the drain electrode 5d face each other. In addition, the gate 2 has a length LG (gate length LG) in the direction in which the source electrode 5s and the drain electrode 5d face each other.

[0033] The gate insulating film 3 is formed using silicon oxide, silicon nitride, silicon nitride oxide, or the like, and insulates the gate 2 from a non-insulating material such as the semiconductor layer 4 .

[0034] The contact layer 51 is to obtain the source electrode 5s and the drain electrode 5d respectively connected to the semiconductor layer 4 (in Figure 1The contact layer 51 is formed, for example, with a high impurity concentration (e.g., 1E+20 ( / cm 3 ) and the like) are formed by doping semiconductors such as silicon with impurities such as phosphorus or boron as mentioned above.

[0035] In addition, the n+ layer 52 can also be formed by doping a semiconductor such as silicon with impurities such as phosphorus. When the TFT 1 is a p-type field effect transistor, an impurity-containing layer (p+ layer) containing p-type impurities can also be formed between the semiconductor layer 4 and the contact layer 51. The impurity concentration of the n+ layer 52 is, for example, 1E+17 ( / cm 3 ) or above, 1E+19( / cm 3 ) or less, and has a lower impurity concentration than the contact layer 51. By providing the n+ layer 52, a depletion layer is generated between the semiconductor layer 4 and the n+ layer 52, so that the current when the TFT 1 is turned off can be reduced.

[0036] The semiconductor layer 4 is formed using amorphous silicon. In the TFT 1, the semiconductor layer 4 includes an intrinsic region 41 composed of undoped amorphous silicon and a low-concentration impurity region (n-region) 42 containing impurities at a predetermined low concentration. The "low concentration" of the low-concentration impurity region 42 means that the low-concentration impurity region 42 has an impurity concentration that indicates a sheet resistance of 20 kΩ / square or more when no voltage is applied to the gate 2. As an example of the impurity concentration of the low-concentration impurity region 42, 5E+16 ( / cm 3 ) and above 5E+18( / cm 3 ) or less. Thus, the impurity concentration of the low-concentration impurity region 42 is lower than the impurity concentration of the impurity containing layer 52.

[0037] The low-concentration impurity region 42 is separated from the gate insulating film 3, that is, is formed in the semiconductor layer 4 with a gap therebetween. Therefore, compared with the case where impurities are added in a manner that reaches the gate insulating film 3, cavitation caused by impurities is less likely to occur. In addition, a small S factor can be obtained, and good switching characteristics can be obtained.

[0038] exist Figure 1 In the TFT 1 of the example, the low-concentration impurity region 42 is formed to a predetermined depth D from the surface of the semiconductor layer 4 on the side opposite to the gate insulating film 3. The predetermined depth D is, for example, not less than 10 nm and not more than 40 nm.

[0039] exist Figure 1In the semiconductor layer 4 of the TFT 1 illustrated in FIG. 1 , a recess 43 is provided by removing the surface portion between the source electrode 5s and the drain electrode 5d. Furthermore, an n-region 42 is formed from the bottom surface of the recess 43 toward the gate insulating film 3 to a predetermined depth D. That is, the n-region 42 is included in the second region 4b sandwiched by the source electrode 5s and the drain electrode 5d in the semiconductor layer 4 when viewed from above. As described above, the channel of the TFT 1 is formed in the second region 4b. Since the n-region 42 is included in the second region 4b, the off-state current is difficult to increase.

[0040] Furthermore, in the TFT 1 of the present embodiment, the gate 2 has a stacked structure including a first layer 21 and a second layer 22 having different work functions (WF) from each other. The first layer 21 is formed using a material having a first work function, and the second layer 22 is formed using a material having a second work function. The second layer 22 is interposed between the first layer 21 and the gate insulating film 3. In addition, Figure 1 The gate electrode 2 illustrated in FIG. 1 is formed on a barrier metal 2a formed of titanium, etc. However, the barrier metal 2a does not necessarily need to be provided.

[0041] The material having the second work function used in the second layer 22 is selected according to the carrier type of the TFT 1, that is, according to the type of impurities contained in the semiconductor layer 4. In the case where the impurities contained in the low-concentration impurity region 42 of the semiconductor layer 4 are n-type impurities, the work function (second work function) of the material forming the second layer 22 is smaller than the first work function. On the other hand, in the case where the impurities contained in the low-concentration impurity region 42 are p-type impurities, the second work function is larger than the first work function. As the material used for the first layer 21, copper (WF: about 5.0 eV), aluminum (WF: about 4.2 eV), titanium (WF: about 4.3 eV), and molybdenum (WF: about 4.2 eV) can be exemplified. In the case where the TFT 1 is an n-type field effect transistor, as the material used for the second layer 22, various lanthanoid elements headed by lanthanum (WF: about 3.5 eV), magnesium (WF: about 3.4 eV), and compounds of these materials are exemplified. When the TFT 1 is a p-type field effect transistor, platinum (WF: 5.64 eV to 5.93 eV) and a compound of selenium (WF: about 5.9 eV) and a metal (e.g., zinc selenide) can be exemplified as the material used for the second layer 22. The materials exemplified as the materials of the first layer 21 or the second layer 22 can be arbitrarily combined. For example, the first layer 21 can also be formed using copper, and the second layer 22 can also contain lanthanum.

[0042] In the TFT 1 of the present embodiment, the change in characteristics accompanying the shortening of the channel length L can be suppressed or prevented, compared with the conventional TFT not having the second layer 22 and the n- region 42 of the gate electrode 2. The reason for this is described below.

[0043] [Function of TFT of Embodiment]

[0044] When the inventors of the present invention were studying the miniaturization of TFTs, they studied the effects of shortening the channel length of existing TFTs on their characteristics. Figure 2A and Figure 2B shown. Figure 2A The relationship between the channel length L and the gate threshold Vth of the TFT is shown in Figure 2B It shows the relationship between the channel length L and the drain current Ioff when it is turned off. In addition, Figure 2A The TFT used in the investigation whose results are shown in the figure has a channel width of 30 μm, and the gate potential that causes a drain current of 10 pA or more when a voltage of 10 V is applied between the drain and the source is measured as the gate threshold Vth. Figure 2B In the survey that presents the results, the Figure 2A In the investigation of the same TFT, a drain current was measured as the off-current Ioff when a voltage of 10 V was applied between the drain and the source and -5 V was applied to the gate.

[0045] like Figure 2A As shown in FIG. 1 , the gate threshold Vth decreases as the channel length L becomes shorter. In addition, as Figure 2B As shown, the off-state current Ioff increases as the channel length L becomes shorter. This is believed to be the effect of the so-called short channel effect, one of the reasons for which is the punch-through phenomenon in which the depletion layers of the source and drain are connected to each other. However, in order to achieve a so-called 8K high resolution with good display characteristics (aperture ratio of each pixel) in, for example, a liquid crystal display panel, it is believed that a gate length of less than 3um is required, and a channel length L shorter than its gate length is required. In this regard, it is speculated that if based on Figure 2A and Figure 2B Extrapolating the gate threshold Vth and the off current Ioff in a channel length L of less than 3 μm makes it difficult to obtain an ideal value of about 1 V to 2 V for the gate threshold Vth. As for the off current Ioff, it is estimated that it is difficult to obtain characteristics suitable for practical use in a channel length L of less than 3 μm.

[0046] In a TFT having such characteristics of gate threshold value Vth and off-state current Ioff (hereinafter, both characteristics are collectively referred to as switching characteristics), as described above, the TFT 1 of this embodiment includes a gate electrode 2 of a stacked structure and a low-concentration impurity region 42 in a semiconductor layer 4 (see Figure 1 ). Reference Figure 3A as well as Figure 3B , explaining the second layer 22 of the gate 2 (refer to Figure 1 ) and the role of the low-concentration impurity region (n-region) 42.

[0047] Figure 3A FIG. 4 conceptually shows the change in the relationship between the gate potential Vg and the drain current Id due to the effects of the second layer 22 and the n- region 42 of the gate 2. FIG. Figure 3A In the figure, the solid line C11 represents the Vg-Id characteristics of a TFT having a specific gate length L1 (e.g., 5 μm) and having an existing structure, that is, a TFT without the second layer 22 and the n- region 42 in the TFT 1 of the present embodiment. The TFT has Vth1 as a gate threshold (a gate potential Vg that causes a current Ith in the drain current Id). If the gate length of the TFT is made shorter than L1, the above-mentioned short channel effect causes the characteristic represented by the solid line C11 to change to the characteristic represented by the dotted line C14. That is, the gate threshold is shifted to a side lower than Vth1, and the cut-off current (the drain current Id when the gate potential Vg is lower than the gate threshold) increases.

[0048] Therefore, in the TFT 1 of the present embodiment, the second layer 22 is provided at the interface between the gate 2 mainly composed of the first layer 21 and the gate insulating film 3. In the case where the TFT 1 is an n-type field effect transistor, the second layer 22 is formed of a material having a work function (second work function) smaller than the work function (first work function) of the material constituting the first layer 21. Therefore, at the interface between the gate insulating film 3 and the semiconductor layer 4 composed of amorphous silicon, a large number of holes are induced instead of electrons as a large number of carriers. Therefore, the gate threshold can be shifted to a larger side. On the other hand, in the case where the TFT 1 is a p-type field effect transistor, the second layer 22 is formed of a material having a second work function larger than the first work function. Therefore, at the interface between the gate insulating film 3 and the semiconductor layer 4 composed of amorphous silicon, a large number of electrons are induced instead of holes as a large number of carriers. Therefore, the gate threshold can be shifted to a larger side.

[0049] In addition, the inventors have determined that by using aluminum having a work function of about 4.2 eV instead of copper having a work function of about 5.0 eV as the material of the gate, the gate threshold is increased by about 0.8 V. Therefore, when the difference between the first work function and the second work function is δ (eV), it is estimated that the gate threshold is increased by about δ (V). For example, as described above, by combining copper (first layer 21) and lanthanum (second layer 22) having a work function difference of about 1.5 eV, it is estimated that the gate threshold can be increased by about 1.5 V compared to the case where the gate is formed of only copper.

[0050] The second layer 22 is used to Figure 3AIn other words, by providing the second layer 22, the Vg-Id characteristic of the TFT of the conventional structure represented by the solid line C11 can be shifted to the increasing direction of the gate potential Vg (the direction of the arrow AL1), and the gate threshold can be increased from Vth1 to Vth2. Therefore, even if the gate length of the gate 2 is shortened and the channel length is shortened, the gate threshold can be maintained at the same level as or above the gate threshold Vth1 in the Vg-Id characteristic represented by the solid line C11.

[0051] Thus, the gate threshold is increased, and on the other hand, as the Vg-Id characteristic changes from the solid line C11 to the single-dot chain line C12, the drain current (on-current) Ion in the region where the gate potential Vg is sufficiently high (the state where the TFT is turned on) is reduced. In a liquid crystal display panel having a high resolution such as 8K, since the time for charging each pixel is shorter than that of a low resolution, it is not preferable to reduce the on-current of the pixel driving element, that is, the TFT.

[0052] Therefore, in the TFT 1 of this embodiment, a low-concentration impurity region (n-region) 42 is provided in the semiconductor layer 4 composed of amorphous silicon. By providing the n-region 42, the carrier mobility in the semiconductor layer 4 is improved. As a result, Figure 3A As shown by the double-dotted line C13, the gate threshold value is slightly reduced in the direction indicated by the arrow AL2, but the on-current Ion can be increased compared with the single-dotted line C12. Therefore, as described above, when the channel length is shortened, the gate threshold value is reduced, but according to the TFT1 of this embodiment, the gate threshold value can be maintained at the same level as Vth1 in the Vg-Id characteristic represented by the solid line C11 or above Vth1, and the reduction of the on-current Ion can be suppressed or prevented.

[0053] Furthermore, the degree of improvement of the on-current of the n- region 42 and the degree of reduction of the gate threshold can be adjusted by the impurity concentration of the n- region 42 .

[0054] Reference Figure 3B , from the previously referenced Figure 2A From the viewpoint of the relationship between the channel length L and the gate threshold Vth (L-Vth characteristics), the functions of the second layer 22 and the n- region 42 of the gate 2 will be described. Figure 3B FIG. 2 conceptually shows the change in the L-Vth characteristic caused by the second layer 22 of the gate 2 and the n-region 42. Figure 3B In the figure, the solid line C21 represents a TFT of the conventional structure, that is, Figure 3A The solid line C11 in FIG. 1 shows the L-Vth characteristics of the same TFT as the TFT whose Vg-Id characteristics are shown. Figure 2ASimilarly, as the channel length L becomes shorter, the gate threshold Vth decreases. For example, if the channel length L is shortened from L1 to L2, the gate threshold Vth decreases from Vth1 to Vth3.

[0055] In the TFT 1 of the present embodiment, since the second layer 22 is provided at the gate 2, the L-Vth characteristic represented by the solid line C21 changes to the characteristic represented by the dashed line C22. Therefore, the gate threshold in the channel length L2 can be increased to Vth2 as indicated by the arrow AL3. Moreover, in the TFT 1 of the present embodiment, since the n-region 42 is provided, the L-Vth characteristic represented by the dashed line C22 changes to the characteristic represented by the double-dashed line C23. Therefore, the gate threshold in the channel length L2 is reduced as indicated by the arrow AL4.

[0056] In the L-Vth characteristic represented by the double-dotted chain line C23, the gate threshold Vth in the channel length L2 is the gate threshold Vth1 in the channel length L1 in the existing structure TFT represented by the solid line C21. That is, although the channel length L is shortened from L1 to L2, the same gate threshold as the TFT of the existing structure is obtained. In this way, in this embodiment, the reduction of the on-current can be suppressed or prevented, and at least the reduction of the gate threshold caused by the shortening of the channel length L can be suppressed. In addition, by appropriately selecting the material used for the second layer 22 of the gate 2 and the concentration of the n-region 42 according to the shortening amount of the channel length L, it is also possible to obtain a gate threshold Vth equivalent to that of a TFT of the existing structure having a longer channel length L.

[0057] As from Figure 3B As can be understood, when the channel length L is shortened to a desired length, for example, L2, the second layer 22 can be formed using a material having a work function that increases the gate threshold Vth in L2 to Vth2, which is higher than Vth1. Thus, for example, even after forming the n-region 42, a gate threshold of Vth1 or higher can be obtained at the channel length of L2.

[0058] According to the first reference Figure 2A The survey results shown in the figure show that when the channel length is shorter than 4um, the estimated gate threshold value decreases sharply. Therefore, preferably, the gate threshold value is sufficiently increased by adding the second layer 22. However, it is also expected that the gate threshold value after the channel length is shortened does not deviate too much to the higher side than the previous gate threshold value. For example, preferably, the gate threshold value is increased by about 1.0V to 2.0V by adding the second layer 22. Therefore, in the case of forming the first layer 21 using the material used for the gate of the previous TFT, based on the relationship between the difference between the first work function and the second work function and the change in the gate threshold, the difference between the first work function and the second work function can also be greater than 1.0eV and less than 2.0eV.

[0059] In addition, even when the gate 2 is formed using only lanthanum having a lower work function than copper or the like, the gate threshold is considered to be higher than when the gate is formed using only copper. However, for example, by providing a first layer 21 composed of copper or the like and providing a second layer 22 containing a material having a second work function only near the interface with the gate insulating film 3, a gate 2 having good conductivity can be formed at low cost.

[0060] According to the present embodiment, since the channel length can be shortened while suppressing the reduction of the switching characteristics, the TFT can be miniaturized while maintaining appropriate characteristics. Further, as described later, if the image display panel has the TFT 1 of the present embodiment, the gate bus line can be thinned as the gate length is shortened as described above. Furthermore, due to the effect caused by the n-region 42 and the effect caused by the shortening of the channel length, the on-current tends to increase, so the channel width, that is, the width of the source and drain, can also be thinned. As a result, similar to the relationship between the shortening of the gate width and the thinning of the gate bus line, the thinning of the source bus line can also be achieved with the shortening of the source width. Therefore, by miniaturizing the TFT and thinning of each bus line, the aperture ratio of each pixel of the image display panel can be improved.

[0061] [Other examples of thin film transistors]

[0062] exist Figure 1 In the illustrated TFT 1, the n-region 42 is included in the second region 4b. However, the n-region 42 may be formed in the semiconductor layer 4 over the region overlapping with the source electrode 5s and the drain electrode 5d in a plan view. Figure 4 , shows another example (TFT 1a) of the present embodiment in which the n- region 42a is provided in the region other than the second region 4b.

[0063] like Figure 4 As shown, in the TFT 1a, the n-region 42a is formed not only in the second region 4b but also on the entire surface of the semiconductor layer 4 when viewed from above. That is, the n-region 42a is also formed in the region overlapping with the source electrode 5s and the portion overlapping with the drain electrode 5d in the semiconductor layer 4. However, in the TFT 1a, the n-region 42a is also separated from the gate insulating film 3.

[0064] In addition, in the TFT 1a, the semiconductor layer 4 has a three-layer structure of a first intrinsic region 411 and a second intrinsic region 412 composed of non-doped amorphous silicon, and a low-concentration impurity region (n-region) 42a. The n-region 42a is arranged on the first intrinsic region 411, and the second intrinsic region 412 is arranged on the n-region 42a. The n-region 42a is sandwiched between the first intrinsic region 411 and the second intrinsic region 412. The first intrinsic region 411 is formed on the gate insulating film 3, and an n+ layer 52 and a contact layer 51 are formed on the second intrinsic region 412, and a source 5s and a drain 5d are formed thereon, respectively. In addition, in the second region 4b sandwiched between the source 5s and the drain 5d when viewed from above in the semiconductor layer 4, the second intrinsic region 412 is removed to expose the n-region 42a.

[0065] The n-region 42a is formed to have a sheet resistance of 20 kΩ / square or more when no voltage is applied to the gate 2. Therefore, even if the n-region 42a is provided on the entire surface of the semiconductor layer 4 in a plan view, the TFT 1a can function as a switching element. Figure 4 The TFT 1a shown in the figure includes, in addition to the n-region 42a, the first intrinsic region 411 and the second intrinsic region 412, Figure 1 The same components as the TFT 1 shown in FIG. Figure 1 The same components as shown are appropriately Figure 4 Marked with Figure 1 The same reference numerals are used and their descriptions are omitted.

[0066] [Image Display Panel]

[0067] Next, refer to Figure 5 An image display panel 100 having a thin film transistor (TFT) 1 according to an embodiment of the present disclosure is described. The image display panel 100 includes TFTs 1 formed in a matrix on a substrate 6, and a plurality of pixels 7 formed in a matrix on the substrate 6 and driven by the TFTs 1. The image display panel 100 may also include Figure 4 In the illustrated embodiment, a TFT 1 a is used instead of the TFT 1 .

[0068] The image display panel 100 further includes Figure 5 in the Y direction) and along the row direction ( Figure 5The plurality of gate bus lines 8g extending in the X direction (in the X direction) and the plurality of source bus lines 8s arranged in parallel along the row direction and extending in the column direction respectively. The gate bus lines 8g are connected to the gate driver 9g, and the gate driver 9g supplies the gate signal for driving the TFT 1. The source bus lines 8s are connected to the source driver 9s, and the source driver 9s supplies the source signal applied to the pixel 7 via the TFT 1. Figure 5 In the example shown in FIG. 1 , the gate driver 9 g is formed on the image display panel 100 , and the source driver 9 s is provided outside the image display panel 100 .

[0069] exist Figure 5 In the example, the image display panel 100 is a liquid crystal display panel. In addition, the image display panel 100 is not particularly limited to a liquid crystal display panel as long as a plurality of pixels arranged in a matrix are driven by thin film transistors respectively, and may be, for example, an organic EL display panel.

[0070] The TFT 1 includes a gate electrode 2, a source electrode 5s and a drain electrode 5d. Figure 1 As shown, the TFT 1 includes a semiconductor layer 4 and a gate insulating film 3, but in Figure 5 The illustration of these electrodes is omitted. The gate electrode 2 is connected to the gate bus 8g, the source electrode 5s is connected to the source bus 8s, and the drain electrode 5d is connected to the pixel electrode 7a. The pixel electrode 7a is opposite to the counter electrode (not shown) via the liquid crystal layer. The pixel electrode 7a, the liquid crystal layer, and the counter electrode form a liquid crystal capacitor.

[0071] Since the image display panel 100 includes the TFT 1 (or TFT 1a) of one embodiment of the present disclosure, it is possible to suppress or prevent the gate threshold from decreasing, and at the same time, reduce the channel length of the TFT 1. Therefore, the image display panel 100 can include a small TFT 1 having appropriate characteristics, and accordingly, the gate bus line 8g and the source bus line 8s can be made thinner as described above. That is, the aperture ratio in each pixel 7 can be increased, and a high-resolution display device having appropriate display characteristics can be realized.

[0072] [Method for manufacturing thin film transistor]

[0073] Next, refer to Figure 6A to Figure 6H A method for manufacturing a thin film transistor (TFT) 1 according to an embodiment of the present disclosure is described below. Figure 6A to Figure 6HAs shown, the manufacturing method of TFT 1 includes: forming a gate 2 on a substrate 10 composed of a glass substrate or an insulating film, etc.; forming a gate insulating film 3 covering the gate 2; and forming a semiconductor layer 4 on the gate insulating film 3, the semiconductor layer 4 being a layer composed of amorphous silicon and including a first region 4a overlapping the gate 2 when viewed from above. The manufacturing method of TFT 1 also includes: forming a source electrode 5s and a drain electrode 5d with a predetermined interval and facing each other above the first region 4a (in the opposite direction of the gate 2 with respect to the semiconductor layer 4); and providing a low-concentration impurity region 42 containing the impurity at a predetermined low concentration by adding an impurity to a predetermined region separated from the gate insulating film 3 in the semiconductor layer 4. Here, forming the gate 2 includes: forming a first layer 21 using a material having a first work function; and forming a second layer 22 between the first layer 21 and the gate insulating film 3 using a material having a second work function. In the case of manufacturing an n-type field effect transistor as TFT 1, a material having a second work function smaller than the first work function is used in the formation of the second layer 22. On the other hand, when a p-type field effect transistor is manufactured as the TFT 1 , a material having a second work function larger than the first work function is used in forming the second layer 22 .

[0074] First, if Figure 6A to Figure 6C As shown, a gate 2 is formed on a substrate 10. Fig. 6A In the example of , barrier metal 2a is first formed on substrate 10. A first layer 21 constituting gate 2 is formed thereon. Barrier metal 2a is formed using titanium or the like. First layer 21 is formed using a material having a predetermined work function, i.e., a first work function, such as copper, aluminum, or molybdenum. For example, barrier metal (2a) and first layer (21) are formed by sputtering.

[0075] Then, if Figure 6B As shown, on the first layer 21, the second layer 22 is formed using a material having a second work function different from the first work function. The second layer 22 can also be formed by a sputtering method or the like. The material used to form the second layer 22 is selected according to the type of impurities added to the semiconductor layer 4 when forming the low-concentration impurity region 42 described later, that is, the carrier type of the TFT 1. In the case where an n-type impurity is added in the formation of the low-concentration impurity region 42, the second layer 22 is formed using a material having a second work function smaller than the first work function, such as various lanthanide elements such as lanthanum. On the other hand, in the case where a p-type impurity is added in the formation of the low-concentration impurity region 42a, the second layer 22 is formed using a material having a second work function larger than the first work function, such as platinum or a compound of a metal and selenium.

[0076] Moreover, if Figure 6CAs shown, the stacked film including the metal of the first layer 21 and the second layer 22 is patterned together with the barrier metal 2a, for example, by photolithography, to form a gate 2 having a desired shape. In addition, although not shown, a gate bus connected to the gate 2 is also formed integrally with the gate 2. In the manufacturing method of the thin film transistor of this embodiment, the gate 2 of the stacked structure is formed using two materials with different work functions, so that the gate threshold can be improved compared with the TFT manufactured by the conventional manufacturing method.

[0077] Then, if Fig.6D As shown, the gate insulating film 3 is formed by forming a silicon oxide film, a silicon nitride film, or the like using a CVD (Chemical Vapor Deposition) method, for example.

[0078] Furthermore, if Fig. 6E As shown, the semiconductor layer 4 is formed to have at least a first region 4a overlapping the gate electrode 2 in a plan view. The semiconductor layer 4 is formed by forming a semiconductor film made of amorphous silicon on the gate insulating film 3 using a CVD method, for example.

[0079] Then, if Fig. 6F As shown, an impurity containing layer 52 having a predetermined thickness is formed by doping impurities from the surface of the semiconductor layer 4, and further, a contact layer 51 is formed by doping impurities. The impurities used in forming the impurity containing layer 52 and the contact layer 51 are n-type impurities such as phosphorus or arsenic when an n-type field effect transistor is manufactured as the TFT 1, and are p-type impurities such as boron or indium when a p-type field effect transistor is manufactured as the TFT 1. Next, on the contact layer 51, a conductor film 5 to be a source and a drain is formed by, for example, sputtering using copper, molybdenum, or the like.

[0080] Then, the conductor film 5 is patterned by photolithography or the like. Figure 6G As shown in FIG. 1 , a source electrode 5s and a drain electrode 5d are formed so as to face each other while sandwiching the gate electrode 2 when viewed from above. The source electrode 5s and the drain electrode 5d are formed to be separated from each other. Figure 6G As shown, after the conductor film 5 is patterned, a portion of the semiconductor film 4 exposed between the source electrode 5 s and the drain electrode 5 d is removed by, for example, etching, to form a recessed portion 43 .

[0081] Then, if Figure 6HAs shown, by adding impurities to a predetermined region separated from the gate insulating film 3 in the semiconductor layer 4, a low-concentration impurity region 42 is formed in the predetermined region. In the case of manufacturing an n-type field effect transistor as TFT1, for example, an n-type impurity such as phosphorus or arsenic is added to form the low-concentration impurity region (n-region) 42. On the other hand, in the case of manufacturing a p-type field effect transistor as TFT1, a p-type impurity such as boron or indium is added to a predetermined region of the semiconductor layer 4. For example, 5E+16 ( / cm 3 ) or above, 5E+18( / cm 3 ) or less, and the conditions for adding impurities are adjusted in such a way that the impurities are included in the low-concentration impurity region 42. Furthermore, the conditions for adding impurities are adjusted in such a way that the low-concentration impurity region 42 is separated from the gate insulating film 3, that is, in such a way that the low-concentration impurity region 42 does not reach the gate insulating film 3.

[0082] For example, after forming the source electrode 5s and the drain electrode 5d, the n-region 42 is formed by exposing the surface of the semiconductor layer 4 exposed between the source electrode 5s and the drain electrode 5d to only an atmosphere containing a predetermined element that can become an impurity in the semiconductor layer 4. The n-region 42 can also be formed by simply storing the TFT 1 in the process of being manufactured with the exposed surface of the semiconductor layer 4 in an atmosphere containing the predetermined element.

[0083] When the impurities are added by such a method, for example, by placing the TFT 1 in an atmosphere containing phosphine at about 200°C to 350°C for about 10 seconds to 20 seconds, the n- region 42 having the concentration exemplified above can be formed. Figure 1 TFT 1 is shown in the example. In addition, in manufacturing Figure 4 In the case of TFT 1a, Fig. 6E After the steps shown, the n- region 42a is formed by adding impurities. Furthermore, after the semiconductor film made of amorphous silicon to be the second intrinsic region 412 is formed, the impurity containing layer 52 and the like are sequentially formed.

[0084] [Summarize]

[0085] (1) A thin film transistor according to an embodiment of the present disclosure includes: a gate; a semiconductor layer formed using amorphous silicon and including a first region overlapping the gate when viewed from above; a gate insulating film interposed between the gate and the semiconductor layer; and a source and a drain arranged above the first region with a predetermined interval and opposite to each other, the gate including a first layer and a second layer, the first layer having a first work function, the second layer having a second work function and interposed between the first layer and the gate insulating film, the semiconductor layer including an intrinsic region and a low-concentration impurity region, the intrinsic region being composed of undoped amorphous silicon, the low-concentration impurity region containing impurities at a predetermined low concentration and being formed separately from the gate insulating film, and when the impurity is an n-type impurity, the second work function is smaller than the first work function, and when the impurity is a p-type impurity, the second work function is larger than the first work function.

[0086] According to the configuration of (1), the TFT can be miniaturized without causing a change in specific characteristics of the thin film transistor, and further, the wiring connected to the TFT can be thinned.

[0087] (2) In the thin film transistor of the aspect (1) above, the low impurity concentration region is included in a second region sandwiched between the source and the drain in a plan view in the semiconductor layer. According to this aspect, the off current is less likely to increase.

[0088] (3) In the thin film transistor of the aspect (1) above, the low impurity concentration region is formed to a predetermined depth from the surface of the semiconductor layer on the side opposite to the gate insulating film. According to this aspect, good switching characteristics can be obtained.

[0089] (4) In the thin film transistor of the form of (1) above, the semiconductor layer has a three-layer structure, the three-layer structure including: a first intrinsic region disposed on the gate insulating film; the low-concentration impurity region disposed on the first intrinsic region; and a second intrinsic region disposed on the low-concentration impurity region, wherein in a second region of the semiconductor layer sandwiched between the source and the drain when viewed from above, the second intrinsic region is removed and the low-concentration impurity region is exposed. According to this form, the off-state current of the thin film transistor may be reduced.

[0090] (5) In the thin film transistor of any one of the above (1) to (4), the difference between the first work function and the second work function is 1.0 eV to 2.0 eV. According to this aspect, when the channel length is shortened, an appropriate gate threshold may be obtained.

[0091] (6) In the thin film transistor of any one of (1) to (5), the impurity is an n-type impurity, the first layer is formed using copper, and the second layer contains lanthanum. According to this embodiment, a gate having good conductivity can be provided in a small TFT at low cost.

[0092] (7) In a thin film transistor of any one of the forms described above (1) to (6), a contact layer in contact with the source or the drain, and an impurity containing layer composed of amorphous silicon containing impurities are further included between the source and the drain respectively and the semiconductor layer, and the impurity concentration of the low-concentration impurity region is lower than the impurity concentration of the impurity containing layer.

[0093] (8) An image display panel according to another embodiment of the present disclosure includes: a plurality of thin film transistors described in the above forms (1) to (7), which are formed in a matrix on a substrate; and a plurality of pixels, which are arranged in a matrix on the substrate and driven using the thin film transistors.

[0094] (9) Another embodiment of the present disclosure provides a method for manufacturing a thin film transistor, comprising: forming a gate on a substrate; forming a gate insulating film covering the gate; forming a semiconductor layer on the gate insulating film, the semiconductor layer being a layer composed of amorphous silicon and including a first region overlapping the gate when viewed from above; forming a source and a drain having a specified interval and facing each other above the first region by forming and patterning a conductor film; and providing a low-concentration impurity region containing the impurity at a specified low concentration in the specified region by adding an impurity to a specified region separated from the gate insulating film in the semiconductor layer, wherein the step of forming the gate comprises: forming a first layer using a material having a first work function; and forming a second layer using a material having a second work function, wherein the second layer is between the first layer and the gate insulating film; when the impurity is an n-type impurity, the second work function is smaller than the first work function; and when the impurity is a p-type impurity, the second work function is larger than the first work function.

[0095] According to the configuration of (9), it is possible to reduce the size of the TFT and further reduce the thickness of the wiring connected to the TFT without causing a change in specific characteristics of the thin film transistor.

[0096] (10) In the manufacturing method of a thin film transistor of the form of (9) above, the step of setting the low-concentration impurity region includes: after forming the source and the drain, exposing the surface of the semiconductor layer exposed between the source and the drain to an atmosphere containing a specified element, and the specified element can become an impurity in the semiconductor layer.

Claims

1. A thin film transistor, characterized in that: It includes: Gate; a semiconductor layer formed of amorphous silicon and including a first region overlapping the gate when viewed from above; a gate insulating film, which is interposed between the gate and the semiconductor layer; as well as a source electrode and a drain electrode, which are arranged above the first region with a gap therebetween and facing each other, The gate includes a first layer and a second layer, the first layer has a first work function, the second layer has a second work function and is between the first layer and the gate insulating film, The semiconductor layer includes an intrinsic region and a low-concentration impurity region, wherein the intrinsic region is composed of non-doped amorphous silicon, the low-concentration impurity region is formed separately from the gate insulating film, and the impurity concentration of the low-concentration impurity region is 5E+16 ( / cm 3 ) and above 5E+18( / cm 3 )the following, When the impurity is an n-type impurity, the second work function is smaller than the first work function, and when the impurity is a p-type impurity, the second work function is larger than the first work function.

2. The thin film transistor according to claim 1, characterized in that: The low-impurity concentration region is included in a second region sandwiched between the source and the drain in a plan view in the semiconductor layer.

3. The thin film transistor according to claim 2, characterized in that: The low-impurity concentration region is formed from a surface of the semiconductor layer on a side opposite to the gate insulating film.

4. The thin film transistor according to claim 1, characterized in that: The semiconductor layer has a three-layer structure, The three-layer structure includes: a first intrinsic region, which is arranged on the gate insulating film; The low-concentration impurity region is disposed on the first intrinsic region; and a second intrinsic region, which is arranged on the low-concentration impurity region; In a second region of the semiconductor layer that is sandwiched between the source and the drain in a plan view, the second intrinsic region is removed and the low-impurity concentration region is exposed.

5. The thin film transistor according to any one of claims 1 to 4, characterized in that: A difference between the first work function and the second work function is greater than or equal to 1.0 eV and less than or equal to 2.0 eV.

6. The thin film transistor according to any one of claims 1 to 4, characterized in that: The impurity is an n-type impurity, the first layer is formed using copper, and the second layer contains lanthanum.

7. A thin film transistor, characterized in that: It includes: Gate; a semiconductor layer formed of amorphous silicon and including a first region overlapping the gate when viewed from above; a gate insulating film, which is interposed between the gate and the semiconductor layer; as well as a source electrode and a drain electrode, which are arranged above the first region with a gap therebetween and facing each other, The gate includes a first layer and a second layer, the first layer has a first work function, the second layer has a second work function and is between the first layer and the gate insulating film, The semiconductor layer includes an intrinsic region and a low-concentration impurity region, the intrinsic region is composed of non-doped amorphous silicon, and the low-concentration impurity region is formed separately from the gate insulating film. When the impurity is an n-type impurity, the second work function is smaller than the first work function, and when the impurity is a p-type impurity, the second work function is larger than the first work function, and between the source and the drain and the semiconductor layer, a contact layer in contact with the source or the drain and an impurity containing layer composed of amorphous silicon containing impurities are further included, The impurity concentration of the low-impurity concentration region is lower than the impurity concentration of the impurity containing layer.

8. An image display panel, characterized in that: The image display panel comprises: A plurality of thin film transistors according to any one of claims 1 to 7, which are formed in a matrix on a substrate; and A plurality of pixels are arranged on the substrate in a matrix and driven by the thin film transistor.

9. A method for manufacturing a thin film transistor, characterized in that: The manufacturing method comprises: forming a gate electrode on a substrate; forming a gate insulating film covering the gate; forming a semiconductor layer on the gate insulating film, wherein the semiconductor layer is a layer composed of amorphous silicon and includes a first region overlapping the gate when viewed from above; A step of forming a source electrode and a drain electrode facing each other with a predetermined interval above the first region by forming and patterning a conductive film; and The step of adding an impurity to a predetermined region of the semiconductor layer separated from the gate insulating film, and providing a low-concentration impurity region containing the impurity at a predetermined low concentration in the predetermined region, The steps of forming the gate include: forming a first layer using a material having a first work function; a step of forming a second layer using a material having a second work function, wherein the second layer is interposed between the first layer and the gate insulating film, When the impurity is an n-type impurity, the second work function is smaller than the first work function; when the impurity is a p-type impurity, the second work function is larger than the first work function.

10. The method for manufacturing a thin film transistor according to claim 9, characterized in that: The step of providing the low-concentration impurity region includes: after forming the source and the drain, exposing the surface of the semiconductor layer exposed between the source and the drain to an atmosphere containing a predetermined element, wherein the predetermined element can become an impurity in the semiconductor layer.

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