Photovoltaic cell and manufacturing method thereof, laminated cell and photovoltaic module

Abstract

The embodiment of the invention relates to the photovoltaic field, and provides a photovoltaic cell and a manufacturing method thereof, a laminated cell and a photovoltaic module, the photovoltaic cell comprises a substrate with a front surface and a back surface opposite to each other along a first direction, and the back surface is provided with first metallized regions and first non-metallized regions which are alternately arranged; the tunneling layer and the doped polycrystalline silicon layer are located on the back face and are sequentially stacked in the first direction; the amorphous silicon layers are arranged at intervals and embedded in the part, located in the first metallization region, of the doped polycrystalline silicon layer, and the first thickness of the amorphous silicon layers is smaller than the second thickness of the part, located in the first non-metallization region, of the doped polycrystalline silicon layer in the first direction; the back electrodes are in one-to-one correspondence with the amorphous silicon layers and are at least in contact connection with the amorphous silicon layers, and the back electrodes are embedded into the amorphous silicon layers with at least partial thickness in the first direction. The embodiment of the invention is at least beneficial to improving the light absorptivity of the substrate and avoiding further permeation of the electrode so as to comprehensively improve the photoelectric conversion efficiency of the photovoltaic cell.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the photovoltaic field, and in particular to a photovoltaic cell and a manufacturing method thereof, a laminated cell, and a photovoltaic module. Background Art

[0002] As fossil energy is gradually depleted, photovoltaic cells are becoming more and more widely used as a new energy alternative. Photovoltaic cells are devices that convert sunlight into electrical energy. Photovoltaic cells use the principle of photovoltaics to generate carriers, and then use electrodes to lead the carriers out, thereby facilitating the effective use of electrical energy.

[0003] The current photovoltaic cells mainly include IBC cells (Interdigitated Back Contact), TOPCON (Tunnel Oxide Passivated Contact), PERC cells (Passivated emitter and real cell) and heterojunction cells, etc. The photoelectric conversion efficiency of photovoltaic cells is improved by reducing optical losses and reducing the recombination of photogenerated carriers on the surface and in the body of the silicon substrate through different film layer settings and functional limitations.

[0004] However, the coordination between different film layers in current photovoltaic cells and their coordination with electrodes to improve the photoelectric conversion efficiency of photovoltaic cells still needs further research. Summary of the invention

[0005] The embodiments of the present disclosure provide a photovoltaic cell and a method for manufacturing the same, a stacked cell, and a photovoltaic module, which are at least beneficial for improving the substrate's absorption rate of light while avoiding further penetration of the electrode, so as to comprehensively improve the photoelectric conversion efficiency of the photovoltaic cell.

[0006] According to some embodiments of the present disclosure, on the one hand, the embodiments of the present disclosure provide a photovoltaic cell, comprising: a substrate, the substrate having a front side and a back side opposite to each other along a first direction, the back side having a first metallization area and a first non-metallization area alternately arranged; a tunneling layer and a doped polysilicon layer located on the back side and stacked in sequence along the first direction; at least two amorphous silicon layers arranged at intervals, embedded in the portion of the doped polysilicon layer located in the first metallization area, along the first direction, the first thickness of the amorphous silicon layer is less than the second thickness of the portion of the doped polysilicon layer located in the first non-metallization area; a back electrode corresponding to the amorphous silicon layer one by one, at least in contact with the amorphous silicon layer, along the first direction, the back electrode is embedded in at least a portion of the thickness of the amorphous silicon layer.

[0007] In some embodiments, along the first direction, the back electrode is only embedded in a portion of the thickness of the amorphous silicon layer, and the back electrode is in contact with the amorphous silicon layer near the bottom surface of the substrate; or, along the first direction, the back electrode is embedded in the entire thickness of the amorphous silicon layer, and the back electrode is in contact with the doped polycrystalline silicon layer near the bottom surface of the substrate.

[0008] In some embodiments, the amorphous silicon layer has a groove, and the back electrode is located in the groove.

[0009] In some embodiments, the ratio of the first thickness to the second thickness is 1 / 12 to 1 / 2.

[0010] In some embodiments, the first thickness is 5 nm to 20 nm; and / or the second thickness is 20 nm to 60 nm.

[0011] In some embodiments, the photovoltaic cell further includes: a silicon oxide layer located between the amorphous silicon layer and the back electrode.

[0012] In some embodiments, along a direction from the doped polysilicon layer to the tunneling layer, a dangling bond density in the amorphous silicon layer gradually decreases.

[0013] In some embodiments, the front side has a second metallization area and a second non-metallization area arranged alternately; the photovoltaic cell also includes: a tunneling film and a doped polysilicon film located on the second metallization area and stacked in sequence along the first direction; at least two amorphous silicon films arranged at intervals, embedded in the doped polysilicon layer film; a front electrode corresponding one to the amorphous silicon film, at least in contact with the amorphous silicon film, and along the first direction, the front electrode is embedded in at least part of the thickness of the amorphous silicon film.

[0014] In some embodiments, the amorphous silicon layer and the doped polysilicon layer have the same type of doping elements, and a first doping concentration of the doping elements in the amorphous silicon layer is greater than a second doping concentration of the doping elements in the doped polysilicon layer.

[0015] In some embodiments, the first doping concentration is 5×10 20 atom / cm 3 ~5×10 21 atom / cm 3 ; and / or, the second doping concentration is 1×10 19 atom / cm 3 ~1×10 21 atom / cm 3 .

[0016] According to some embodiments of the present disclosure, on the other hand, the embodiments of the present disclosure further provide a method for manufacturing a photovoltaic cell, comprising: providing a substrate, the substrate having a front side and a back side opposite to each other along a first direction, the back side having a first metallization area and a first non-metallization area alternately arranged; forming a tunneling layer and an initial doped polysilicon layer stacked in sequence along the first direction on the back side; amorphizing the portion of the initial doped polysilicon layer located in the first metallization area to form an amorphous silicon layer embedded in the portion of the doped polysilicon layer located in the first metallization area, and the remaining initial doped polysilicon layer serves as a doped polysilicon layer; forming a back side electrode corresponding one-to-one to the amorphous silicon layer, the back side electrode being at least in contact with and connected to the amorphous silicon layer, and the back side electrode being embedded in at least a portion of the thickness of the amorphous silicon layer along the first direction.

[0017] In some embodiments, the step of performing the amorphization treatment on the portion of the initial doped polysilicon layer located in the first metallization area includes: performing laser treatment on the portion of the initial doped polysilicon layer located in the first metallization area to induce amorphization of a portion of the initial doped polysilicon layer to be converted into the amorphous silicon layer; wherein the process parameters of the laser treatment include: a laser wavelength of 300nm to 550nm, a laser power of 0W to 25W, and a laser spot area of ​​5000um 2 ~50000um 2 , the laser scanning speed is 300mm / s-80000mm / s.

[0018] In some embodiments, the front side has a second metallization area and a second non-metallization area arranged alternately; before the initial doped polysilicon layer is subjected to the amorphization treatment, the manufacturing method further includes: forming a tunneling film and an initial doped polysilicon film stacked in sequence along the first direction on the second metallization area; in the step of performing the amorphization treatment on a portion of the initial doped polysilicon layer located in the first metallization area, the manufacturing method further includes: performing the amorphization treatment on a portion of the initial doped polysilicon film to form an amorphous silicon film embedded in the doped polysilicon layer film, and the remaining initial doped polysilicon film serves as a doped polysilicon film.

[0019] According to some embodiments of the present disclosure, yet another aspect of the embodiments of the present disclosure further provides a stacked cell, comprising: a bottom cell, which is a photovoltaic cell as described in any one of the above items, or a photovoltaic cell formed by a manufacturing method as described in any one of the above items; and a top cell, which is located on one of the two opposite sides of the bottom cell along the first direction.

[0020] According to some embodiments of the present disclosure, on the other hand, the embodiments of the present disclosure further provide a photovoltaic module, including: a battery string, formed by connecting a plurality of photovoltaic cells as described in any one of the above items, or formed by connecting a plurality of photovoltaic cells formed by any one of the manufacturing methods as described in any one of the above items, or formed by connecting a plurality of stacked batteries as described above; a packaging film for covering the surface of the battery string; and a cover plate for covering the surface of the packaging film facing away from the battery string.

[0021] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0022] The amorphous silicon layer is designed to be embedded in the portion of the doped polysilicon layer located in the first metallization area, and the back electrode corresponds to the amorphous silicon layer one by one. Firstly, it is beneficial to effectively prevent the back electrode from penetrating into the tunneling layer by virtue of the blocking effect of the amorphous silicon layer on the conductive elements in the back electrode, so as to avoid increasing the recombination probability of carriers; secondly, compared with the doped polysilicon layer, the amorphous silicon layer has a stronger blocking effect on the conductive elements in the back electrode, so that the overall thickness of the doped polysilicon layer, i.e., the second thickness, can be reduced while designing the amorphous silicon layer, so as to realize the overall thinning design of the doped polysilicon layer, so that while improving the substrate's absorption rate of light based on the thinning design of the doped polysilicon layer, the back electrode can be prevented from further penetration based on the amorphous silicon layer, so as to comprehensively improve the photoelectric conversion efficiency of the photovoltaic cell.

[0023] In addition, while the overall thickness of the doped polysilicon layer is thinned, since the amorphous silicon layer is embedded in the doped polysilicon layer, the third thickness of the first part of the doped polysilicon layer located in the first metallization area is smaller, which is beneficial for further reducing the absorption of light by the first part while avoiding further penetration of the back electrode based on the amorphous silicon layer, thereby improving the absorption rate of light at the first metallization area. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, and these exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise specified, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0025] Figure 1 A schematic diagram of a first partial cross-sectional structure of a photovoltaic cell provided in one embodiment of the present disclosure;

[0026] Figure 2A schematic diagram of a second partial cross-sectional structure of a photovoltaic cell provided in one embodiment of the present disclosure;

[0027] Figure 3 for Figure 1 A schematic diagram of a partially enlarged cross-sectional structure of a photovoltaic cell at a square frame A shown in FIG.

[0028] Figure 4 A third partial cross-sectional structural schematic diagram of a photovoltaic cell provided in one embodiment of the present disclosure;

[0029] Figure 5 A schematic diagram of a fourth partial cross-sectional structure of a photovoltaic cell provided in one embodiment of the present disclosure;

[0030] Figure 6 to Figure 7 A schematic diagram of a partial cross-sectional structure corresponding to each step in a method for manufacturing a photovoltaic cell provided in another embodiment of the present disclosure;

[0031] Figure 8 A schematic diagram of a partial cross-sectional structure of a laminated battery provided in yet another embodiment of the present disclosure;

[0032] Fig. 9 A schematic diagram of a partial three-dimensional structure of a photovoltaic assembly provided in yet another embodiment of the present disclosure;

[0033] Fig.10 for Fig. 9 A schematic diagram of a local cross-sectional structure of a photovoltaic module along the cross-sectional direction MM1 is shown. DETAILED DESCRIPTION

[0034] As known from the background technology, the photoelectric conversion efficiency of photovoltaic cells needs to be improved.

[0035] Through analysis, it is found that in order to achieve a good passivation effect on the substrate, a tunneling layer and a doped polysilicon layer are generally designed to be stacked on the surface of the substrate, and an anti-reflection layer is further designed. In the electrode coverage area, the electrode will penetrate the anti-reflection layer and achieve electrical connection with the doped polysilicon layer, but will not penetrate the tunneling layer to maintain good interface passivation. It is worth noting that when the electrode penetrates the tunneling layer, the recombination of carriers will increase and the photoelectric conversion efficiency of the photovoltaic cell will decrease.

[0036] Currently, photovoltaic cells are limited by the wavelength range of light that can be absorbed and utilized, and the photoelectric conversion efficiency is limited. In addition, the difference in photoelectric conversion efficiency between the front and back of photovoltaic cells will also affect the overall power generation morphology of solar cells. In order to further improve the photoelectric conversion efficiency of photovoltaic cells, higher requirements are placed on the absorption rate of photovoltaic cells for light.

[0037] The doped polysilicon layer has a certain light absorption capacity, which will cause certain optical losses and affect the bifaciality of photovoltaic cells. Specifically, the doped polysilicon layer will absorb the long-wave spectrum, which is likely to cause short-circuit current loss and reduced bifaciality of photovoltaic cells. The difference in the light absorption capacity of the doped polysilicon layer is mainly affected by the absorption coefficient and the absorption optical path. Among them, the higher the absorption coefficient, the stronger the light absorption capacity, the longer the absorption optical path, and the more absorption. Thinning the thickness of the doped polysilicon layer can reduce the absorption optical path, thereby reducing the light absorption capacity of the doped polysilicon layer and improving the short-circuit current loss and bifaciality of photovoltaic cells. Therefore, thinning the thickness of the doped polysilicon layer has become a development trend.

[0038] However, as the thickness of the doped polysilicon layer becomes thinner, it is currently difficult to meet the requirement of "the electrode penetrates the anti-reflection layer and contacts the doped polysilicon layer, but does not penetrate into the tunneling layer". The adjustment of the electrode slurry composition and the electrode sintering process is relatively difficult to control, especially the regulation of the electrode slurry composition. Currently, there is no case in the market where the electrode does not penetrate into the silicon wafer in the doped polysilicon layer after the thickness is reduced.

[0039] The present disclosure provides a photovoltaic cell and a manufacturing method thereof, a stacked cell, and a photovoltaic module. In the photovoltaic cell, an amorphous silicon layer is designed to be embedded in the portion of the doped polycrystalline silicon layer located in the first metallization area, and the back electrode corresponds to the amorphous silicon layer one by one. First, it is beneficial to effectively prevent the back electrode from penetrating into the tunneling layer by means of the blocking effect of the amorphous silicon layer on the conductive elements in the back electrode, so as to avoid increasing the recombination probability of carriers; secondly, compared with the doped polycrystalline silicon layer, the amorphous silicon layer has a stronger blocking effect on the conductive elements in the back electrode, so that the thickness of the doped polycrystalline silicon layer as a whole can be reduced while designing the amorphous silicon layer, that is, the second thickness, so as to realize the overall thinning design of the doped polycrystalline silicon layer, so as to improve the substrate's absorption rate of light based on the thinning design of the doped polycrystalline silicon layer, and at the same time, it is beneficial to prevent the back electrode from further penetrating based on the amorphous silicon layer, so as to comprehensively improve the photoelectric conversion efficiency of the photovoltaic cell. In addition, while the overall thickness of the doped polysilicon layer is thinned, since the amorphous silicon layer is embedded in the doped polysilicon layer, the third thickness of the first part of the doped polysilicon layer located in the first metallization area is smaller, which is beneficial for further reducing the absorption of light by the first part while avoiding further penetration of the back electrode based on the amorphous silicon layer, thereby improving the absorption rate of light at the first metallization area.

[0040] In the description of the embodiments of the present disclosure, the technical terms "first", "second", etc. are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the indicated technical features. In the description of the embodiments of the present disclosure, the meaning of "multiple" is more than two, unless otherwise clearly and specifically defined.

[0041] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present disclosure. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0042] In the description of the embodiments of the present disclosure, the term "and / or" is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists, A and B exist at the same time, and B exists. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0043] In the description of the embodiments of the present disclosure, the term "multiple" refers to more than two (including two). Similarly, "multiple groups" refers to more than two groups (including two groups), and "multiple pieces" refers to more than two pieces (including two pieces).

[0044] In the description of the embodiments of the present disclosure, the orientations or positional relationships indicated by technical terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", and "circumferential" are based on the orientations or positional relationships shown in the accompanying drawings and are only for the convenience of describing the embodiments of the present disclosure and simplifying the description. They do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the embodiments of the present disclosure.

[0045] In the description of the embodiments of the present disclosure, unless otherwise clearly specified and limited, technical terms such as "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can be the internal connection of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present disclosure can be understood according to the specific circumstances.

[0046] In the accompanying drawings corresponding to the embodiments of the present disclosure, the thickness and area of ​​the layers are magnified for better understanding and ease of description. When describing a component (such as a layer, a film, a region or a substrate) on another component or on the surface of another component, the component may be "directly" located on the surface of the other component, or a third component may be present between the two components. On the contrary, when describing a component on the surface of another component or when another component is formed or provided on the surface of a component, it means that there is no third component between the two components. In addition, when describing a component as being "substantially" formed on another component, it means that the component is not formed on the entire surface (or front surface) of the other component, nor is it formed on a partial edge of the entire surface.

[0047] In the description of the embodiments of the present disclosure, when a component "includes" another component, unless otherwise specified, other components are not excluded, and other components may be further included. In addition, when a component such as a layer, a film, a region, or a plate is referred to as being "on / located on" another component, it may be "directly on" the other component (i.e., located on the surface of the other component with no other components between them), or another component may exist in between. In addition, when a component such as a layer, a film, a region, a plate, etc. is "directly located on" another component, or when a component such as a layer, a film, a region, a plate, etc. is located on the surface of another component, it means that no other components are located in between.

[0048] The terms used in the description of the various embodiments described herein are only used to describe specific embodiments and are not intended to be limiting. As used in the description of the various embodiments described and in the appended claims, "the components" are also intended to include plural forms unless the context clearly indicates otherwise. Among them, components include components such as layers, films, regions, or plates.

[0049] The following will describe the various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the embodiments of the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the present disclosure can be implemented.

[0050] An embodiment of the present disclosure provides a photovoltaic cell, which will be described in detail below with reference to the accompanying drawings.

[0051] refer to Figures 1 to 5The photovoltaic cell includes: a substrate 100, the substrate 100 has a front side 110 and a back side 120 opposite to each other along a first direction X, the back side 120 has a first metallized area 130 and a first non-metallized area 140 arranged alternately; a tunneling layer 101 and a doped polysilicon layer 102 located on the back side 120 and stacked in sequence along the first direction X; at least two amorphous silicon layers 103 arranged at intervals, embedded in a portion of the doped polysilicon layer 102 located in the first metallized area 130, along the first direction X, a first thickness H1 of the amorphous silicon layer 103 is less than a second thickness H2 of a portion of the doped polysilicon layer 102 located in the first non-metallized area 140; a back electrode 104 corresponding to the amorphous silicon layer 103 one by one, at least in contact with the amorphous silicon layer 103, along the first direction X, the back electrode 104 is embedded in at least a portion of the thickness of the amorphous silicon layer 103.

[0052] in, Figure 1 A schematic diagram of a first partial cross-sectional structure of a photovoltaic cell provided in one embodiment of the present disclosure; Figure 2 A schematic diagram of a second partial cross-sectional structure of a photovoltaic cell provided in one embodiment of the present disclosure.

[0053] It is worth noting that the number of the first metallized regions 130 and the number of the first non-metallized regions 140 can both be multiple, and the first metallized regions 130 and the first non-metallized regions 140 are alternately arranged along the second direction Y. In other words, the first metallized region 130 can be located in the interval between two adjacent first non-metallized regions 140, and the first non-metallized region 140 can also be located in the interval between two adjacent first metallized regions 130.

[0054] It should be noted that the embodiment of the present disclosure does not limit the number of the first metallized regions 130 and the number of the first non-metallized regions 140. Figure 1 and Figure 2 Only two first metallized regions 130 and two first non-metallized regions 140 are shown schematically.

[0055] In some embodiments, the first metallized region 130 mainly includes the region where the orthographic projection of the back electrode 104 on the substrate 100 is located, and the first non-metallized region 140 mainly includes the region other than the orthographic projection of the back electrode 104 on the substrate 100. In order to ensure that the film layer contacted by the back electrode 104 has a relatively large doping concentration or the regions contacted by the back electrode 104 are all high-concentration regions, thereby reducing the contact resistance between the back electrode 104 and the film layer contacted by it, taking the orthographic projection on the substrate 100 as an example, the orthographic projection area of ​​the first metallized region 130 is generally set to be greater than or equal to the orthographic projection area of ​​the back electrode 104. In other words, the orthographic projection area of ​​the back electrode 104 on the substrate 100 is smaller than the orthographic projection area of ​​the first metallized region 130 on the substrate 100, and the orthographic projection position of the back electrode 104 on the substrate 100 must be located within the orthographic projection of the first metallized region 130 on the substrate 100.

[0056] It is worth noting that at least two amorphous silicon layers 103 are independently embedded in the portion of the doped polysilicon layer 102 located in the first metallization area 130 , and the amorphous silicon layer 103 corresponds to the back electrode 104 one by one, and the amorphous silicon layer 103 and the first metallization area 130 can also correspond to each other one by one.

[0057] The amorphous silicon layer 103 is embedded in the portion of the doped polysilicon layer 102 located in the first metallization area 130, which can be understood as follows: the doped polysilicon layer 102 includes a first portion 112 located in the first metallization area 130 and a second portion 122 located in the first non-metallization area 140, and along the first direction X, the thickness of the second portion 122 is the second thickness H2, and the third thickness H3 of the first portion 112 is less than the thickness of the second portion 122; the amorphous silicon layer 103 is located on the side of the first portion 112 away from the tunneling layer 101, and is in contact with the side surface of the second portion 122. In other words, the first portion 112 is located between the amorphous silicon layer 103 and the tunneling layer 101, and the second portion 122 surrounds the amorphous silicon layer 103. In some examples, along the first direction X, the sum of the third thickness H3 of the first portion 112 and the first thickness H1 of the amorphous silicon layer 103 can be equal to the thickness of the second portion 122, that is, the second thickness H2.

[0058] It is worth emphasizing that the amorphous silicon layer 103 is designed to be embedded in the portion of the doped polysilicon layer 102 located in the first metallization area 130, and the back electrode 104 corresponds to the amorphous silicon layer 103. Firstly, it is beneficial to use the blocking effect of the amorphous silicon layer 103 on the conductive elements in the back electrode 104 to effectively slow down the penetration of the back electrode 104 into the amorphous silicon layer 103 and further into the doped polysilicon layer 102, and effectively prevent the back electrode 104 from penetrating into the tunneling layer 101, thereby preventing the increase in the recombination probability of carriers; secondly, compared with the doped polysilicon layer 102, the amorphous silicon layer 103 has a better blocking effect on the conductive elements in the back electrode 104, so it can be used in the design of the amorphous silicon layer 103. 3, the overall thickness of the doped polysilicon layer 102 is reduced, that is, the second thickness H2, so as to achieve a thinning design for the overall thickness of the doped polysilicon layer 102, and effectively prevent the back electrode 104 from penetrating into the tunneling layer 101 with the help of the amorphous silicon layer 103, so as to improve the light absorption rate of the back 120 based on the thinning design of the doped polysilicon layer 102, and prevent the back electrode 104 from further penetrating based on the amorphous silicon layer 103, so as to comprehensively improve the photoelectric conversion efficiency of the photovoltaic cell. In other words, on the first metallization area 130, a core film layer composed of the tunneling layer 101, the doped polysilicon layer 102 and the amorphous silicon layer 103 is designed, and the amorphous silicon layer 103 has a stronger ability to block the back electrode 104 from penetrating, so as to match the thinning design of the doped polysilicon layer 102, and prevent the back electrode 104 from penetrating into the tunneling layer 101 or further penetrating into the substrate 100 while improving the intensity of the light received by the substrate 100.

[0059] In addition, while the overall thickness of the doped polysilicon layer 102, i.e., the second thickness H2, is thinned, since the amorphous silicon layer 103 is embedded in the doped polysilicon layer 102, the third thickness H3 of the first portion 112 of the doped polysilicon layer 102 located in the first metallization area 130 is smaller, which is beneficial for further reducing the absorption of light by the first portion 112 while avoiding further penetration of the back electrode 104 based on the amorphous silicon layer 103, thereby improving the absorption rate of light at the first metallization area 130.

[0060] The photovoltaic cell provided in one embodiment of the present disclosure is described in detail below.

[0061] In some embodiments, the tunneling layer 101 and the doped polysilicon layer 102 located on the back side 120 can still constitute a first passivation contact structure, and the first passivation contact structure provides good surface passivation for the back side 120. Specifically, the tunneling layer 101 mainly serves as a tunneling layer for the majority carriers, and at the same time chemically passivates the back side 120 to reduce interface state defects. The main function of the doped polysilicon layer 102 is to serve as a field passivation layer, forming a band bending on the back side 120, realizing the selective transmission of carriers, and reducing the recombination loss of carriers. In one example, the photovoltaic cell can be a TOPCON cell.

[0062] In some embodiments, a texturing process may be performed on at least one of the front surface 110 or the back surface 120 of the substrate 100 to form a velvet surface on at least one of the front surface 110 or the back surface 120 of the substrate 100, so that the absorption utilization rate of the incident light by the front surface 110 or the back surface 120 of the substrate 100 can be enhanced. In some examples, the velvet surface may be a pyramid velvet surface, which, as a common velvet surface, not only reduces the reflectivity of the surface of the substrate 100, but also forms a light trap, thereby enhancing the absorption effect of the substrate 100 on the incident light and increasing the photoelectric conversion efficiency of the photovoltaic cell.

[0063] In some cases, the solar cell can be a single-sided cell, and a velvet surface can be formed on the light-receiving surface of the substrate 100, that is, the front surface 110, for example, a pyramid velvet surface, and the backlight surface of the substrate 100, that is, the back surface 120, can be a polished surface, that is, the backlight surface of the substrate 100 is flatter than the light-receiving surface, wherein the backlight surface can also receive incident light, but the efficiency of receiving the incident light is weaker than the efficiency of the light-receiving surface receiving the incident light. It should be noted that for single-sided cells, velvet can also be formed on both the light-receiving surface and the backlight surface of the substrate 100. In other cases, the solar cell can be a double-sided cell, that is, the first side and the second side of the solar cell are both used as light-receiving surfaces, and velvet can be formed on both the light-receiving surface and the backlight surface of the substrate 100.

[0064] In some cases, a small portion of the doping elements in the doped polysilicon layer 102 may pass through the tunneling layer 101 to form a lightly doped layer on the back surface 120 .

[0065] In some cases, the material of the amorphous silicon layer 103 may be silicon carbide.

[0066] In some cases, the material of the tunneling layer 101 may be silicon oxide.

[0067] In some cases, along the first direction X, the thickness of the tunneling layer 101 may be 1 nm to 2 nm.

[0068] In some cases, the material of the substrate 100 may be an elemental semiconductor material. Specifically, the elemental semiconductor material is composed of a single element, such as silicon or silicon. The elemental semiconductor material may be single crystal, polycrystalline, amorphous or microcrystalline (a state having both single crystal and amorphous states is called microcrystalline), for example, silicon may be at least one of single crystal silicon, polycrystalline silicon, amorphous silicon or microcrystalline silicon.

[0069] In other cases, the material of the substrate 100 may also be a compound semiconductor material. Common compound semiconductor materials include but are not limited to silicon germanium, silicon carbide, gallium arsenide, indium gallium, perovskite, cadmium telluride, copper indium selenide and other materials.

[0070] In some cases, the substrate 100 may be an N-type substrate, and the substrate 100 is doped with N-type doping elements, based on which the doped polysilicon layer 102 is an N-type doped polysilicon layer 102. In some examples, the amorphous silicon layer 103 may also be an N-type amorphous silicon layer 103.

[0071] In some examples, the N-type doping element may be any one of Group V elements such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As).

[0072] In other cases, the substrate 100 may be a P-type substrate, and the substrate 100 is doped with a P-type doping element, based on which the doped polysilicon layer 102 is a P-type doped polysilicon layer 102. In some examples, the amorphous silicon layer 103 may also be a P-type amorphous silicon layer 103.

[0073] In some examples, the P-type doping element may be any one of the Group III elements, such as boron (B), aluminum (Al), gallium (Ga), or gallium (In).

[0074] In some cases, continue to refer to Figures 1 to 5 , the amorphous silicon layer 103 and the doped polysilicon layer 102 have the same type of doping elements, and the first doping concentration of the doping elements in the amorphous silicon layer 103 is greater than the second doping concentration of the doping elements in the doped polysilicon layer 102. In this way, compared with the doped polysilicon layer 102, the first doping concentration in the amorphous silicon layer 103 is greater, which is beneficial to increase the contact resistance at the contact point between the amorphous silicon layer 103 and the back electrode 104, so as to improve the efficiency of the back electrode 104 in collecting carriers, thereby facilitating the improvement of the photoelectric conversion efficiency of the photovoltaic cell.

[0075] In some examples, the first doping concentration may be 5×10 20 atom / cm 3 ~5×10 21 atom / cm 3 For example, the first doping concentration may be 6×1020 atom / cm 3 ,7×10 20 atom / cm 3 , 8×10 20 atom / cm 3 ,9×10 20 atom / cm 3 , 1×10 21 atom / cm 3 , 2×10 21 atom / cm 3 , 3×10 21 atom / cm 3 or 4×10 21 atom / cm 3 wait.

[0076] In some examples, the second doping concentration may be 1×10 19 atom / cm 3 ~1×10 21 atom / cm 3 For example, the second doping concentration may be 2×10 19 atom / cm 3 , 3×10 19 atom / cm 3 , 4×10 19 atom / cm 3 , 5×10 19 atom / cm 3 , 6×10 19 atom / cm 3 ,7×10 19 atom / cm 3 , 8×10 19 atom / cm 3 or 9×10 19 atom / cm 3 wait.

[0077] In some embodiments, the conductive element in the back electrode 104 may be silver, and the slurry used to form the back electrode 104 may be silver slurry. The amorphous silicon layer 103 can effectively block the penetration of silver in the back electrode 104, and the core principle is as follows:

[0078] Related research shows that when sintered in an oxygen-containing gas environment, an electrochemical reaction will occur between silicon-containing materials and silver paste.

[0079] The reaction process of silver paste and silicon-containing material is as follows:

[0080] Step 1: Silver reacts with oxygen to form silver ions and oxygen ions in the glass frit of the slurry.

[0081] 4Ag (s) +O 2(g) →4Ag + (in glass) +2O 2- (in glass)

[0082] Second step: Silver ions in the glass frit of the paste react with silicon, wherein silicon donates electrons to the silver ions, forming silver particles and silicon ions in the glass frit of the paste.

[0083] Si (s) +4Ag + (in glass) →Si 4+ (in glass) +4Ag o (in glass)

[0084] It is worth emphasizing that in the second step, by designing an amorphous silicon layer 103 on the first metallization area 130, the amorphous silicon layer 103 has a weak ability to provide electrons to silver ions, thereby avoiding excessive silver ions in the back electrode 104 from reacting electrochemically with the amorphous silicon layer 103, thereby reducing the formation of silver in the second step and reducing the damage of the back electrode 104 to poly-Si. Therefore, the design of the amorphous silicon layer 103 can match the thinning design of the doped polycrystalline silicon layer 102, thereby comprehensively improving the photoelectric conversion efficiency of the photovoltaic cell.

[0085] Along the first direction X, the back electrode 104 is embedded in at least a portion of the thickness of the amorphous silicon layer 103, including at least the following two conditions:

[0086] In some cases, reference Figure 1 , along the first direction X, the back electrode 104 is only embedded in a part of the thickness of the amorphous silicon layer 103, and the back electrode 104 is in contact with the amorphous silicon layer 103 near the bottom surface of the substrate 100. In other words, the back electrode 104 does not penetrate the amorphous silicon layer 103, and the amorphous silicon layer 103 wraps the end of the back electrode 104 near the substrate 100. The amorphous silicon layer 103 can be regarded as having a groove 113, which does not penetrate the amorphous silicon layer 103, and the back electrode 104 is located in the groove 113. In this way, the side and bottom surfaces of the back electrode 104 are in contact with the amorphous silicon layer 103, and the amorphous silicon layer 103 blocks the conductive elements in the back electrode 104 from penetrating into the doped polysilicon layer 102 and the tunneling layer 101 in all directions.

[0087] In other cases, reference Figure 2, along the first direction X, the back electrode 104 is embedded in the entire thickness of the amorphous silicon layer 103, and the back electrode 104 is in contact with the doped polysilicon layer 102 near the bottom surface of the substrate 100. In other words, the back electrode 104 penetrates the amorphous silicon layer 103, and only the side surface of the back electrode 104 is in contact with the amorphous silicon layer 103. The amorphous silicon layer 103 has a groove 113, and the groove 113 penetrates the amorphous silicon layer 103, and the back electrode 104 is located in the groove 113. It is worth noting that in the step of preparing the back electrode 104, the amorphous silicon layer 103 embedded in the doped polysilicon layer 102 has been blocking the back electrode 104 from penetrating in the direction close to the back side 120 along the first direction X. Even if the back electrode 104 gradually penetrates the amorphous silicon layer 103 in this step, the amorphous silicon layer 103 can also slow down the penetration speed of the back electrode 104, effectively preventing the back electrode 104 from quickly penetrating into the doped polysilicon layer 102 and causing too much damage to the doped polysilicon layer 102. In other words, based on the pre-blocking effect of the amorphous silicon layer 103, even if the back electrode 104 penetrates the amorphous silicon layer 103, it will not penetrate deeply into the doped polysilicon layer 102. Moreover, the back electrode 104 is directly electrically connected to the doped polysilicon layer 102, which is beneficial to reducing the transmission resistance of carriers transmitted to the back electrode 104.

[0088] In some embodiments, reference Figure 1 , Figure 2 , Figure 4 or Figure 5 , the ratio of the first thickness H1 to the second thickness H2 is 1 / 12 to 1 / 2. If the ratio of the first thickness H1 to the second thickness H2 is less than 1 / 12, the first thickness H1 of the amorphous silicon layer 103 is too small compared to the overall thickness of the doped polysilicon layer 102, i.e., the second thickness H2. Even if the amorphous silicon layer 103 has a strong barrier to the back electrode 104, during the preparation of the back electrode 104, if the first thickness H1 is too small, it is easy for the conductive elements in the back electrode 104 to penetrate the amorphous silicon layer 103 in a short time, and it is not conducive to ensuring that the back electrode 104 will not penetrate the tunneling layer 101 in conjunction with the doped polysilicon layer 102 that is being thinned; if the ratio of the first thickness H1 to the second thickness H2 is greater than 1 / 2, the third thickness H3 of the doped polysilicon layer 102 including the first portion 112 located in the first metallization area 130 is small, which is not conducive to ensuring a good passivation effect of the first portion 112 on the back 120. Therefore, designing the ratio of the first thickness H1 to the second thickness H2 to be 1 / 12 to 1 / 2 is beneficial to ensuring that the amorphous silicon layer 103 and the first part 112 in the doped polycrystalline silicon layer 102 have appropriate thicknesses, so as to ensure that the amorphous silicon layer 103 can have a good blocking effect on the back electrode 104 penetrating deep into the substrate for a long time, while ensuring that the first part 112 has a good passivation effect on the back side 120.

[0089] In some examples, the ratio of the first thickness H1 to the second thickness H2 may be 1 / 11, 1 / 10, 1 / 9, 1 / 8, 1 / 7, 1 / 6, 1 / 5, 1 / 4, 1 / 3, etc.

[0090] In some examples, the first thickness H1 may be 5 nm to 20 nm. For example, the first thickness H1 may be 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, 16 nm, 17 nm, 18 nm, or 19 nm.

[0091] In some examples, the second thickness H2 may be 20 nm to 60 nm. For example, the second thickness H2 may be 22 nm, 25 nm, 30 nm, 32 nm, 35 nm, 36 nm, 40 nm, 42 nm, 45 nm, 48 nm, 50 nm, 51 nm, 52 nm, 53 nm, 54 nm, 55 nm, 56 nm, 57 nm, 58 nm or 59 nm, etc.

[0092] It is worth noting that designing the second thickness H2 to be 20nm to 60nm is conducive to making the overall thickness of the doped polysilicon layer 102 smaller, thereby achieving thinning of the doped polysilicon layer 102. In this way, not only is the thickness of the first portion 112 of the doped polysilicon layer 102 located in the first metallization area 130 thinner, but the thickness of the second portion 122 located in the first non-metallization area 140 is also thinner, thereby reducing the overall absorption of light by the doped polysilicon layer 102, so that more light can be irradiated to the first metallization area 130 and the first non-metallization area 140 in the back side 120, thereby effectively improving the light intensity received by the back side 120, thereby improving the photoelectric conversion efficiency of the photovoltaic cell.

[0093] In some embodiments, in conjunction with reference Figure 1 and Figure 3 , Figure 3 for Figure 1 The photovoltaic cell shown is a schematic diagram of a partially enlarged cross-sectional structure at the box A. The photovoltaic cell may further include: a silicon oxide layer 105, located between the amorphous silicon layer 103 and the back electrode 104. It is worth noting that the amorphous silicon layer 103 can be formed by amorphizing a portion of the doped polysilicon layer 102 located on the first non-metallized area 140. In the process of amorphizing the doped polysilicon layer 102, due to the presence of oxygen in the air, a thin silicon oxide layer 105 is formed on the surface of the formed amorphous silicon layer 103 away from the substrate 100.

[0094] It should be noted that, depending on the difference in oxygen content in actual situations, the silicon oxide layer 105 may be present in only a small area between the amorphous silicon layer 103 and the back electrode 104, or in most areas or even the entire contact interface. Figure 3 In the example, only the silicon oxide layer 105 is taken at the interface between the amorphous silicon layer 103 and the back electrode 104 along the first direction X.

[0095] In some examples, along the first direction X, the thickness of the silicon oxide layer 105 is 0.5nm-2nm. For example, the thickness of the silicon oxide layer 105 can be 0.6nm, 0.7nm, 0.8nm, 0.9nm, 1nm, 1.1nm, 1.2nm, 1.3nm, 1.4nm, 1.5nm, 1.6nm, 1.7nm, 1.8nm or 1.9nm.

[0096] In some embodiments, reference Figures 1 to 5 , along the direction from the doped polysilicon layer 102 to the tunneling layer 101, the dangling bond density in the amorphous silicon layer 103 gradually decreases. In other words, along the direction from the doped polysilicon layer 102 to the tunneling layer 101, the amorphous degree of the amorphous silicon layer 103 gradually decreases, and the crystallization rate gradually increases.

[0097] It is worth noting that the direction in which the doped polysilicon layer 102 points to the tunneling layer 101 can be regarded as the direction in which the back electrode 104 penetrates into the substrate 100. Along the penetration direction of the back electrode 104, the density of dangling bonds in the amorphous silicon layer 103 gradually decreases, and the ability of the amorphous silicon layer 103 to provide electrons to the back electrode 104 becomes worse and worse, which is more conducive to blocking the further penetration of the back electrode 104. Therefore, while the thickness of the doped polysilicon layer 102 can be thinned to improve the light absorption rate of the substrate 100, the damage of the back electrode 104 to the doped polysilicon layer 102 can be further reduced, and it is ensured that the back electrode 104 does not penetrate into the tunneling layer 101.

[0098] In some embodiments, reference Figure 4 , Figure 4 A third partial cross-sectional structural schematic diagram of a photovoltaic cell provided in an embodiment of the present disclosure, wherein the front side 110 has second metallization areas 150 and second non-metallization areas 160 arranged alternately; the photovoltaic cell may further include: a tunneling film 106 and a doped polysilicon film 107 located on the second metallization area 150 and stacked in sequence along the first direction X; at least two amorphous silicon films 108 arranged at intervals, embedded in the doped polysilicon film 107; a front electrode 109 corresponding one-to-one to the amorphous silicon film 108, at least in contact with the amorphous silicon film 108, and along the first direction X, the front side 110 electrode is embedded in at least a portion of the thickness of the amorphous silicon film 108.

[0099] It is worth noting that the second metallization area 150 mainly includes the area where the orthographic projection of the front electrode 109 on the substrate 100 is located, and the second non-metallization area 160 mainly includes the area other than the orthographic projection of the front electrode 109 on the substrate 100. In order to ensure that the film layer contacted by the front electrode 109 has a large doping concentration or the areas contacted by the front electrode 109 are all high-concentration areas, thereby reducing the contact resistance between the front electrode 109 and the film layer contacted by it, taking the orthographic projection on the substrate 100 as an example, the orthographic projection area of ​​the second metallization area 150 is generally set to be greater than or equal to the orthographic projection area of ​​the front electrode 109. In other words, the orthographic projection area of ​​the front electrode 109 on the substrate 100 is smaller than the orthographic projection area of ​​the second metallization area 150 on the substrate 100, and the orthographic projection position of the front electrode 109 on the substrate 100 must be located within the orthographic projection of the second metallization area 150 on the substrate 100.

[0100] In addition, at least two amorphous silicon films 108 are independently embedded in the portion of the doped polysilicon film 107 located in the second metallization area 150 . The amorphous silicon films 108 correspond one-to-one to the front electrodes 109 , and the amorphous silicon films 108 and the second metallization areas 150 may also correspond one-to-one.

[0101] It should be noted that the difference between the front side 110 and the back side 120 at least includes that the doped polysilicon film 107 is only located in the second metallization area 150 , which is different from the doped polysilicon layer 102 being located in the first metallization area 130 and the first non-metallization area 140 .

[0102] Based on this, the doped polysilicon film 107 and the second metallization area 150 also correspond one to one, and any doped polysilicon film 107 includes a third part 117 that is in contact with the bottom surface of the amorphous silicon film 108 and a fourth part 127 that is in contact with the side surface of the amorphous silicon film 108, wherein the third part 117 is located between the amorphous silicon film 108 and the front side 110.

[0103] In other embodiments, reference Figure 5 , Figure 5 This is a schematic diagram of the fourth partial cross-sectional structure of a photovoltaic cell provided in an embodiment of the present disclosure. In the direction from the back side 120 to the front side 110, the tunneling film 106, the doped polycrystalline silicon film 107 and the amorphous silicon film 108 can be stacked in sequence, wherein the doped polycrystalline silicon film 107 is located between the tunneling film 106 and the amorphous silicon film 108.

[0104] In the above various embodiments, a second passivation contact structure consisting of a tunneling film 106 and a doped polysilicon film 107 is formed on the second metallization region 150 of the front side 110, providing good surface passivation for the front side 110. In addition, it is beneficial to effectively prevent the front electrode 109 from penetrating into the tunneling layer 101 by means of the blocking effect of the amorphous silicon film 108 on the conductive elements in the front electrode 109, thereby preventing the increase in the recombination probability of carriers, and the thickness of the doped polysilicon film 107 can be reduced while designing the amorphous silicon film 108, so as to achieve a thinning design of the doped polysilicon film 107 as a whole, thereby helping to improve the light absorption rate of the front side 110 while preventing the front electrode 109 from further penetrating based on the amorphous silicon film 108, so as to comprehensively improve the photoelectric conversion efficiency of the photovoltaic cell.

[0105] It should be noted that the same or corresponding parts of the second metallization area 150 and the first metallization area 130, the second non-metallization area 160 and the first non-metallization area 140, the tunneling film 106 and the tunneling layer 101, the doped polysilicon film 107 and the doped polysilicon layer 102, and the amorphous silicon film 108 and the amorphous silicon layer 103 are not repeated here.

[0106] In some embodiments, a back anti-reflection layer is further designed on the surface of the doped polysilicon layer 102 and the amorphous silicon layer 103 which is away from the back surface 120 .

[0107] In some embodiments, a front anti-reflection layer is further designed on the surface formed by the second non-metallized area 160 , the doped polysilicon film 107 , and the amorphous silicon film 108 .

[0108] In some cases, the material of at least one of the back anti-reflection layer and the front anti-reflection layer may include at least one of aluminum oxide, silicon oxide, silicon nitride or silicon oxynitride, so that at least one of the back anti-reflection layer or the front anti-reflection layer serves as a hydrogen passivation layer and an optical matching layer to further improve the photoelectric conversion efficiency of the photovoltaic cell.

[0109] In summary, the amorphous silicon layer 103 is designed to be embedded in the portion of the doped polysilicon layer 102 located in the first metallization area 130, and the back electrode 104 corresponds to the amorphous silicon layer 103. Firstly, it is beneficial to effectively prevent the back electrode 104 from penetrating into the tunneling layer 101 by virtue of the blocking effect of the amorphous silicon layer 103 on the conductive elements in the back electrode 104; secondly, compared with the doped polysilicon layer 102, the amorphous silicon layer 103 has a better blocking effect on the conductive elements in the back electrode 104, so that the overall thickness of the doped polysilicon layer 102, i.e., the second thickness H2, can be reduced while designing the amorphous silicon layer 103, so as to realize the overall thinning design of the doped polysilicon layer 102, so as to help improve the substrate's absorption rate of light while avoiding further penetration of the back electrode 104, so as to comprehensively improve the photoelectric conversion efficiency of the photovoltaic cell. In addition, when the overall thickness of the doped polysilicon layer 102 is thinned, the third thickness H3 of the first portion 112 of the doped polysilicon layer 102 is smaller, which is beneficial for further reducing the absorption of light by the first portion 112 while avoiding further penetration of the back electrode 104 based on the amorphous silicon layer 103, thereby improving the absorption rate of light at the first metallization area 130.

[0110] Another embodiment of the present disclosure further provides a method for manufacturing a photovoltaic cell, which is used to manufacture the photovoltaic cell provided by the above embodiment. The method for manufacturing a photovoltaic cell provided by another embodiment of the present disclosure will be described in detail below in conjunction with the accompanying drawings. Figure 6 to Figure 7 This is a schematic diagram of the partial cross-sectional structure corresponding to each step in the photovoltaic cell manufacturing method provided in another embodiment of the present disclosure. It should be noted that the parts that are the same as or corresponding to the previous embodiments are not repeated here.

[0111] Combined with reference Figures 1 to 7 , the manufacturing method of the photovoltaic cell comprises the following steps:

[0112] S1: Reference Figure 6 A substrate 100 is provided. The substrate 100 has a front side 110 and a back side 120 opposite to each other along a first direction X. The back side 120 has first metallized areas 130 and first non-metallized areas 140 arranged alternately.

[0113] S2: Continue to refer Figure 6 , a tunneling layer 101 and an initially doped polysilicon layer 132 are sequentially stacked along a first direction X on the back side 120 .

[0114] S3: Combined with reference Figure 6 and Figure 1 , or in conjunction with reference Figure 6 and Figure 2, the portion of the initial doped polysilicon layer 132 located in the first metallization area 130 is amorphized to form an amorphous silicon layer 103 embedded in the portion of the doped polysilicon layer 102 located in the first metallization area 130, and the remaining initial doped polysilicon layer 132 serves as the doped polysilicon layer 102.

[0115] S4: Combined with reference Figure 6 and Figure 1 , or in conjunction with reference Figure 6 and Figure 2 , forming a back electrode 104 corresponding to the amorphous silicon layer 103 one by one, the back electrode 104 is at least in contact with the amorphous silicon layer 103, and along the first direction X, the back electrode 104 is embedded in at least a portion of the thickness of the amorphous silicon layer 103.

[0116] It is worth noting that in order to form an amorphous silicon layer 103 with a better blocking effect on the back electrode 104, the initial doped polycrystalline silicon layer 132 in the area where the amorphous silicon layer 103 needs to be designed can be directly amorphized. The process steps are simple, and the amorphous silicon layer 103 and the doped polycrystalline silicon layer 102 can be simultaneously formed in one step. It can be achieved by adding only one amorphization treatment process, which is simple and easy and suitable for large-scale mass production.

[0117] Moreover, relying on the better blocking effect of the amorphous silicon layer 103 on the back electrode 104, an initial doped polysilicon layer 132 with a thinner thickness along the first direction X can be prepared in step S2, so that the overall thickness of the doped polysilicon layer 102 subsequently formed based on the initial doped polysilicon layer 132, that is, the second thickness H2 is thinner, so as to achieve a thinning design for the overall thickness of the doped polysilicon layer 102. In this way, in step S4, while preventing the back electrode 104 from penetrating into the tunneling layer 101 with the help of the amorphous silicon layer 103, the absorption rate of the doped polysilicon layer 102 to light can be reduced, so that more light can be irradiated to the back side 120, so as to improve the absorption rate of the substrate 100 to light, thereby comprehensively improving the photoelectric conversion efficiency of the photovoltaic cell.

[0118] The following is a detailed description of each step of the method for manufacturing a photovoltaic cell:

[0119] In some embodiments, in step S3, the method of performing amorphization treatment on the portion of the initial doped polysilicon layer 132 located in the first metallization region 130 may include laser induced amorphization or ion implantation, so that the crystals in the portion of the initial doped polysilicon layer 132 located in the first metallization region 130 are disordered to transform into an amorphous silicon layer 103.

[0120] In some embodiments, in conjunction with reference Figure 6 and Figure 1 , or in conjunction with reference Figure 6 and Figure 2 The step of amorphizing the portion of the initial doped polysilicon layer 132 located in the first metallization area 130 may include: performing laser treatment on the portion of the initial doped polysilicon layer 132 located in the first metallization area 130 to induce amorphization of a partial thickness of the initial doped polysilicon layer 132 to convert it into an amorphous silicon layer 103.

[0121] It is worth noting that in step S3 , when the initial doped polysilicon layer 132 is subjected to amorphization treatment, no additional oxygen is provided, and the initial doped polysilicon layer 132 is mainly amorphized by the induction effect of the laser to transform it into the amorphous silicon layer 103 .

[0122] In some cases, in step S3, the process parameters of the laser treatment may include: a laser wavelength of 300nm to 550nm, a laser power of 0W to 25W, and a laser spot area of ​​5000um. 2 ~50000um 2 , the laser scanning speed is 300mm / s-80000mm / s.

[0123] In some examples, the laser wavelength can be 320nm, 330nm, 350nm, 360nm, 380nm, 400nm, 420nm, 450nm, 460nm, 480nm, 500nm, 520nm or 540nm, etc.; the laser power can be 5W, 8W, 10W, 12W, 15W, 16W, 18W, 20W, 22W or 24W, etc.; the laser spot area can be 10000um 2 、15000um 2 、20000um 2 、25000um 2 、30000um 2 、35000um 2 、40000um 2 or 45000um 2 etc.; the laser scanning speed can be 500mm / s, 1000mm / s, 5000mm / s, 10000mm / s, 20000mm / s, 30000mm / s, 40000mm / s, 50000mm / s, 60000mm / s or 70000mm / s, etc.

[0124] In some cases, in step S3, the process parameters of the laser processing may also include: a laser pulse width of 5ps-100ns, and a laser pulse frequency of 50kHz-1250kHz.

[0125] In some examples, the laser pulse width can be 10ps, 15ps, 20ps, 25ps, 30ps, 35ps, 40ps, 45ps, 50ps, 55ps, 60ps, 65ps, 70ps, 75ps, 80ps, 85ps, 90ps or 95ns, etc.; the laser pulse frequency can be 100kHz, 200kHz, 300kHz, 400kHz, 500kHz, 600kHz, 700kHz, 800kHz, 900kHz, 1000kHz, 1100kHz or 1200kHz, etc.

[0126] In some embodiments, reference Figure 6 , the front side 110 has second metallization areas 150 and second non-metallization areas 160 arranged alternately; before the initial doped polysilicon layer 132 is amorphized, that is, before step S3, refer to Figure 7 The manufacturing method may further include the following steps: forming a tunneling film 106 and an initial doped polysilicon film 137 stacked in sequence along the first direction X on the second metallization region 150; performing an amorphization treatment on the portion of the initial doped polysilicon layer 132 located in the first metallization region 130, that is, step S3, in combination with reference Figure 7 and Figure 4 , or in conjunction with reference Figure 7 and Figure 5 The manufacturing method may further include: performing an amorphization treatment on a portion of the initial doped polysilicon film 137 to form an amorphous silicon film 108 embedded in the doped polysilicon film 107 , and the remaining initial doped polysilicon film 137 serves as the doped polysilicon film 107 .

[0127] In some cases, before forming the tunneling film 106 and the initially doped polysilicon film 137 on the second metallization area 150, in step S2: forming a tunneling layer 101 and an initially doped polysilicon layer 132 stacked in sequence along the first direction X on the back side 120, a tunneling film and an initially doped polysilicon film covering the second metal area and the second non-metallic area can be simultaneously formed on the front side, and then the tunneling film and the initially doped polysilicon film located on the entire front side are removed to remove the tunneling film and the initially doped polysilicon film located on the second non-metallization area, leaving only the tunneling film 106 and the initially doped polysilicon film 137 located on the second metallization area 150.

[0128] In other cases, step S2 of forming a tunneling layer 101 and an initially doped polysilicon layer 132 stacked in sequence along the first direction X on the back side 120 and the step of forming a tunneling film 106 and an initially doped polysilicon film 137 on the second metallization area 150 can be performed separately to ensure that the tunneling film 106 and the initially doped polysilicon film 137 are not formed on the second non-metallization area 160.

[0129] It should be noted that another embodiment of the present disclosure does not limit the process method for forming the tunneling film 106 and the initial doped polysilicon film 137 on the second metallization region 150 .

[0130] It is worth noting that on the basis of forming the tunneling film 106 and the initial doped polysilicon film 137 stacked in sequence along the first direction X on the second metallization area 150, the step of amorphizing the portion of the initial doped polysilicon layer 132 located in the first metallization area 130, that is, in step S3, a portion of the initial doped polysilicon film 137 can also be amorphized.

[0131] In some cases, the step of amorphizing a portion of the initially doped polysilicon layer 132 located on the back side 120 and the step of amorphizing a portion of the initially doped polysilicon film 137 located on the front side 110 can be performed simultaneously, so that the amorphous silicon layer 103 and the amorphous silicon film 108 can be prepared almost at the same time, and in the step of simultaneously forming the amorphous silicon layer 103 and the amorphous silicon film 108, the doped polysilicon layer 102 and the doped polysilicon film 107 can also be formed simultaneously, which effectively simplifies the process steps for preparing photovoltaic cells and is suitable for large-scale mass production.

[0132] In some examples, a laser may be provided on the front side 110 and the back side 120, respectively, so that the step of amorphizing a portion of the initial doped polysilicon layer 132 and the step of amorphizing a portion of the initial doped polysilicon film 137 can be performed simultaneously. Further, in order to prevent the laser acting on the front side 110 and the laser acting on the back side 120 from simultaneously processing the same portion of the photovoltaic cell, and to prevent the photovoltaic cell from being locally overheated and being damaged, such as being broken, the orthographic projections of the first metallization area and the second metallization area on the substrate may be designed to not overlap or only partially overlap, so as to ensure that the orthographic projections of the region on the initial doped polysilicon layer that needs to be amorphized and the region on the initial doped polysilicon film that needs to be amorphized on the substrate do not overlap or only partially overlap.

[0133] It should be noted that, in actual applications, the orthographic projection area of ​​the first metallized region on the substrate and the orthographic projection area of ​​the second metallized region on the substrate may be different, and may not overlap with the orthographic projection area of ​​the first metallized region on the substrate and the orthographic projection area of ​​the second metallized region on the substrate and exist in the same photovoltaic cell at the same time; or, the orthographic projection area of ​​the first metallized region on the substrate and the orthographic projection area of ​​the second metallized region on the substrate may be different, and may only partially overlap with the orthographic projection area of ​​the first metallized region on the substrate and the orthographic projection area of ​​the second metallized region on the substrate and exist in the same photovoltaic cell at the same time.

[0134] Another embodiment of the present disclosure further provides a laminated battery, which includes the photovoltaic cell provided by the above embodiment, or the photovoltaic cell formed by the manufacturing method provided by the above embodiment. The laminated battery provided by another embodiment of the present disclosure will be described in detail below in conjunction with the accompanying drawings. It should be noted that the parts that are the same or corresponding to the above embodiment will not be repeated here.

[0135] Combined with reference Figure 1 and Figure 8 , Figure 8 A schematic diagram of a partial cross-sectional structure of a stacked battery provided in yet another embodiment of the present disclosure, the stacked battery comprises: a bottom battery 119, the bottom battery 119 is the photovoltaic cell provided in the aforementioned embodiment, or is a photovoltaic cell formed by the manufacturing method provided in the aforementioned embodiment; and a top battery 129, the top battery 129 is located on one of the two opposite sides of the bottom battery 119 along the first direction X.

[0136] In some embodiments, in conjunction with reference Figure 1 and Figure 8 The substrate 100 has a front side 110 and a back side 120 opposite to each other along a first direction X, and the top battery 129 is located on a side of the back side 120 away from the front side 110. In other embodiments, the top battery may also be located on a side of the front side away from the back side.

[0137] In some embodiments, the top cell 129 may include: a stacked first transmission layer, a perovskite substrate, a second transmission layer, a transparent conductive layer, and an anti-reflection layer. The first transmission layer is directly opposite to the bottom cell 119. In one example, the back surface 120 of the photovoltaic cell as the bottom cell, on which the doped polysilicon layer 102 is disposed, is closer to the first transmission layer in the top cell 129. In other words, the top cell 129 is located on the back surface 120 of the photovoltaic cell as the bottom cell.

[0138] In some embodiments, the first transport layer may be one of an electron transport layer and a hole transport layer, and the second transport layer may be the other of the electron transport layer and the hole transport layer.

[0139] Another embodiment of the present disclosure further provides a photovoltaic assembly, which includes a plurality of photovoltaic cells provided by the aforementioned embodiments, or a plurality of photovoltaic cells formed by the manufacturing method provided by the aforementioned embodiments, and a plurality of laminated cells provided by the aforementioned embodiments, and the photovoltaic assembly is used to convert received light energy into electrical energy. It should be noted that the parts that are the same or corresponding to the aforementioned embodiments can refer to the corresponding description of the aforementioned embodiments, and will not be repeated below.

[0140] Combined with reference Fig. 9 and Fig.10The photovoltaic module includes: a battery string, which is formed by connecting multiple photovoltaic cells 40 provided by the above embodiments, or by connecting multiple photovoltaic cells 40 formed by the manufacturing method provided by the above embodiments, or by connecting multiple laminated batteries provided by the above embodiments; a packaging film 41, which is used to cover the surface of the battery string; a cover plate 42, which is used to cover the surface of the packaging film 41 away from the battery string. The photovoltaic cells 40 are electrically connected in the form of a whole piece or multiple pieces to form multiple battery strings, and the multiple battery strings are electrically connected in series and / or parallel.

[0141] in, Fig. 9 A schematic diagram of a partial three-dimensional structure of a photovoltaic assembly provided in yet another embodiment of the present disclosure; Fig.10 for Fig. 9 A schematic diagram of a local cross-sectional structure of a photovoltaic module along the cross-sectional direction MM1 is shown.

[0142] In some embodiments, the photovoltaic cell 40 includes, but is not limited to, one or any combination of PERC cells (Passivated Emitter Rear Cell), IBC cells (Interdigitated Back Contact), TOPCon cells (Tunnel Oxide Passivated Contact), HIT / HJT cells (Heterojunction Technology heterojunction cells), solar thin-film cells, and stacked cells. Among them, solar thin-film cells include, but are not limited to, perovskite solar thin-film cells, copper indium selenide solar thin-film cells, gallium arsenide solar thin-film cells, and cadmium sulfide solar thin-film cells. Stacked cells include, but are not limited to, perovskite cells superimposed on crystalline silicon cells, perovskite cells superimposed on perovskite cells, and perovskite cells superimposed on thin-film cells.

[0143] In some embodiments, the photovoltaic cell 40 may be a monocrystalline silicon photovoltaic cell, a polycrystalline silicon photovoltaic cell, an amorphous silicon photovoltaic cell or a multi-compound photovoltaic cell, and the multi-compound photovoltaic cell may specifically be a cadmium sulfide photovoltaic cell, a gallium arsenide photovoltaic cell, a copper indium selenide photovoltaic cell or a perovskite photovoltaic cell. In addition, the photovoltaic cell 40 may be a whole cell or a sliced ​​cell, and a sliced ​​cell refers to a cell formed by a complete whole cell through a cutting process. The photovoltaic cell 40 is electrically connected in the form of a whole cell or multiple slices to form a plurality of cell strings, and the plurality of cell strings are electrically connected in series and / or in parallel.

[0144] In some embodiments, reference Fig. 9 , multiple battery strings can be electrically connected through the conductive tape 402. Fig. 9Only one positional relationship between photovoltaic cells is illustrated, that is, the arrangement direction of the electrodes with the same polarity of the cells is the same, or the electrodes with positive polarity of each cell are arranged toward the same side, so that the conductive tape connects different sides of two adjacent cells. In some embodiments, the cells can also be arranged in the order of electrodes with different polarities facing the same side, that is, the electrodes of multiple adjacent cells are arranged in the order of the first polarity, the second polarity, and the first polarity, and the conductive tape connects two adjacent cells on the same side.

[0145] In some embodiments, no intervals are set between the battery cells, that is, the battery cells overlap each other.

[0146] In some embodiments, the encapsulation film 41 includes a first encapsulation layer and a second encapsulation layer, the first encapsulation layer covers one of the front or back sides of the photovoltaic cell 40, and the second encapsulation layer covers the other of the front or back sides of the photovoltaic cell 40. Specifically, at least one of the first encapsulation layer or the second encapsulation layer can be an organic encapsulation film such as polyvinyl butyral (PVB) film, ethylene-vinyl acetate copolymer (EVA) film, polyethylene octene co-elastic (POE) film or polyethylene terephthalate (PET) film, or at least one of the first encapsulation layer or the second encapsulation layer can also be an EP film, EPE film or PVP film. Among them, EP film refers to a co-extruded film composed of stacked EVA film and POE film, EPE film refers to a co-extruded film formed by stacked EVA film + POE film + EVA film, and PVP film refers to a co-extruded film formed by stacked POE film + EVA film + POE film. Co-extruded films can be manufactured by sequentially extruding one or more raw materials onto another already manufactured film during the film processing process, or by bonding different types of already manufactured films together.

[0147] In some cases, there is a boundary between the first encapsulation layer and the second encapsulation layer before lamination. After the lamination process, the photovoltaic module is formed and there is no longer the concept of the first encapsulation layer and the second encapsulation layer, that is, the first encapsulation layer and the second encapsulation layer have formed an integral encapsulation film 41.

[0148] In some embodiments, the cover plate 42 may be a glass cover plate, a plastic cover plate or the like with a light-transmitting function. Specifically, the surface of the cover plate 42 facing the encapsulation film 41 may be a concave-convex surface or a velvet surface including a plurality of convex structures, thereby increasing the utilization rate of the incident light. The cover plate 42 includes a first cover plate and a second cover plate, the first cover plate is opposite to the first encapsulation layer, and the second cover plate is opposite to the second encapsulation layer.

[0149] In some embodiments, the photovoltaic cell 40 may be a busbar cell or a busbar-less cell.

[0150] In some cases, when the photovoltaic cell 40 is a main grid cell, the surface of the photovoltaic cell 40 has a plurality of main grids arranged at intervals along the third direction Z and a plurality of sub-grids arranged at intervals along the second direction Y, and the main grid includes a main grid connection line and a pad located on the main grid connection line. In the process of constructing a battery string using the photovoltaic cell 40, the conductive tape 402 is electrically connected to at least one main grid on each of the two adjacent photovoltaic cells 40. The conductive tape 402 can be electrically connected to the main grid by welding, or the conductive tape 402 can be fixed on the main grid by glue points in advance, and the conductive tape 402 can be electrically connected to the main grid by using the fusion of the glue points and the deformation of the conductive tape 402 during the lamination process.

[0151] In other cases, when the photovoltaic cell 40 is a main grid-free cell, the surface of the photovoltaic cell 40 has a plurality of sub-grids arranged at intervals along the second direction Y. In the process of constructing a cell string using the photovoltaic cell 40, the conductive tape 402 is electrically connected to the plurality of sub-grids on each of the two adjacent photovoltaic cells 40. The conductive tape 402 can be fixed at a specific position above the photovoltaic cell 40 by glue dots, and then the electrical connection between the conductive tape 402 and the sub-grids is achieved by utilizing the fusion of the glue dots and the deformation of the conductive tape 402 during the lamination process.

[0152] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for implementing the present disclosure, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure, so the protection scope of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A photovoltaic cell, characterized in that: include: A substrate, the substrate having a front side and a back side opposite to each other along a first direction, the back side having first metallized areas and first non-metallized areas arranged alternately; A tunneling layer and a doped polysilicon layer located on the back side and stacked in sequence along the first direction; at least two amorphous silicon layers arranged at intervals, embedded in the portion of the doped polysilicon layer located in the first metallization area, wherein along the first direction, a first thickness of the amorphous silicon layer is less than a second thickness of the portion of the doped polysilicon layer located in the first non-metallization area; The back electrodes corresponding to the amorphous silicon layers one by one are at least in contact with and connected to the amorphous silicon layer. Along the first direction, the back electrodes are embedded in at least a portion of the thickness of the amorphous silicon layer.

2. The photovoltaic cell according to claim 1, characterized in that: Along the first direction, the back electrode is only embedded in a part of the thickness of the amorphous silicon layer, and the back electrode is in contact with and connected to the amorphous silicon layer near the bottom surface of the substrate; or, Along the first direction, the back electrode is embedded in the entire thickness of the amorphous silicon layer, and the back electrode is in contact with and connected to the doped polysilicon layer near the bottom surface of the substrate.

3. The photovoltaic cell according to claim 2, characterized in that: The amorphous silicon layer has a groove, and the back electrode is located in the groove.

4. The photovoltaic cell according to claim 1, characterized in that: The ratio of the first thickness to the second thickness is 1 / 12 to 1 / 2.

5. The photovoltaic cell according to claim 4, characterized in that: The first thickness is 5 nm to 20 nm; and / or the second thickness is 20 nm to 60 nm.

6. The photovoltaic cell according to any one of claims 1 to 5, characterized in that: Also includes: The silicon oxide layer is located between the amorphous silicon layer and the back electrode.

7. The photovoltaic cell according to any one of claims 1 to 5, characterized in that: Along the direction from the doped polysilicon layer to the tunneling layer, the dangling bond density in the amorphous silicon layer gradually decreases.

8. The photovoltaic cell according to any one of claims 1 to 5, characterized in that: The front side has a second metallized area and a second non-metallized area arranged alternately; the photovoltaic cell further comprises: a tunneling film and a doped polysilicon film located on the second metallization region and sequentially stacked along the first direction; At least two amorphous silicon films arranged at intervals and embedded in the doped polysilicon layer film; The front electrodes corresponding to the amorphous silicon films one by one are at least in contact with and connected to the amorphous silicon films. Along the first direction, the front electrodes are embedded in at least a portion of the thickness of the amorphous silicon films.

9. The photovoltaic cell according to any one of claims 1 to 5, characterized in that: The amorphous silicon layer and the doped polysilicon layer have the same type of doping elements, and a first doping concentration of the doping elements in the amorphous silicon layer is greater than a second doping concentration of the doping elements in the doped polysilicon layer.

10. The photovoltaic cell according to claim 9, characterized in that: The first doping concentration is 5×10 20 atom / cm 3 ~5×10 21 atom / cm 3 ; and / or, the second doping concentration is 1×10 19 atom / cm 3 ~1×10 21 atom / cm 3 .

11. A method for manufacturing a photovoltaic cell, characterized in that: include: Providing a substrate, wherein the substrate has a front side and a back side opposite to each other along a first direction, wherein the back side has first metallized areas and first non-metallized areas arranged alternately; forming a tunneling layer and an initially doped polysilicon layer stacked in sequence along the first direction on the back side; amorphizing the portion of the initial doped polysilicon layer located in the first metallization region to form an amorphous silicon layer embedded in the portion of the doped polysilicon layer located in the first metallization region, and the remaining initial doped polysilicon layer serves as a doped polysilicon layer; A back electrode is formed corresponding to the amorphous silicon layer one by one, the back electrode is at least in contact with and connected to the amorphous silicon layer, and along the first direction, the back electrode is embedded in at least a portion of the thickness of the amorphous silicon layer.

12. The manufacturing method according to claim 11, characterized in that: The step of performing the amorphization treatment on the portion of the initial doped polysilicon layer located in the first metallization region comprises: Performing laser treatment on a portion of the initial doped polysilicon layer located in the first metallization region to induce amorphization of a portion of the initial doped polysilicon layer to transform the layer into the amorphous silicon layer; The process parameters of the laser treatment include: laser wavelength of 300nm to 550nm, laser power of 0W to 25W, laser spot area of ​​5000um 2 ~50000um 2 , the laser scanning speed is 300mm / s-80000mm / s.

13. The manufacturing method according to claim 11, characterized in that: The front side has second metallization areas and second non-metallization areas arranged alternately; before the initial doped polysilicon layer is subjected to the amorphization treatment, the manufacturing method further comprises: In the step of forming a tunneling film and an initial doped polysilicon film stacked in sequence along the first direction on the second metallization area; and performing the amorphization treatment on a portion of the initial doped polysilicon layer located in the first metallization area, the manufacturing method further comprises: The amorphization process is performed on a portion of the initial doped polysilicon film to form an amorphous silicon film embedded in the doped polysilicon layer film, and the remaining initial doped polysilicon film serves as a doped polysilicon film.

14. A laminated battery, characterized in that: include: A bottom cell, wherein the bottom cell is a photovoltaic cell according to any one of claims 1 to 10, or a photovoltaic cell formed by the manufacturing method according to any one of claims 11 to 13; A top cell is located on one of two opposite sides of the bottom cell along the first direction.

15. A photovoltaic module, characterized in that: include: A battery string, formed by connecting a plurality of photovoltaic cells according to any one of claims 1 to 10, or by connecting a plurality of photovoltaic cells formed by the manufacturing method according to any one of claims 11 to 13, or by connecting a plurality of laminated batteries according to claim 14; A packaging film, used to cover the surface of the battery string; The cover plate is used to cover the surface of the packaging film away from the battery string.

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