Voltage regulated replica transistor, comparator, ramp signal and latch circuit

Abstract

Embodiments of this application relate to voltage regulation circuits. A voltage regulation circuit (700) includes a switch output terminal (701B), a high-side output transistor (702), a low-side output transistor (704), a high-side replica transistor (722), a low-side replica transistor (724), and a comparator circuit (710). The high-side output transistor (702) is configured to drive the switch output terminal (701B). The low-side output transistor (704) is configured to drive the switch output terminal (701B). The high-side replica transistor (722) is coupled to the high-side output transistor (702). The low-side replica transistor (724) is coupled to both the high-side replica transistor (722) and the low-side output transistor (704). The comparator circuit (710) is coupled to the high-side replica transistor (722) and the low-side replica transistor (724) and is configured to compare a signal received from both the high-side replica transistor (722) and the low-side replica transistor (724) with a ramp signal.

Description

Technical Field

[0001] The embodiments of this application relate to power supply technology, specifically to voltage regulation circuits. Background Technology

[0002] A switching-mode power supply is an electronic circuit that converts an input direct current (DC) power supply voltage into one or more DC output voltages, the magnitude of which may be higher or lower than the input DC power supply voltage. A switching power supply that generates an output voltage lower than the input voltage is called a buck (or step-down) converter. A switching power supply that generates an output voltage higher than the input voltage is called a boost (or step-up) converter.

[0003] Switching power supplies include a feedback loop to control the regulation of the output voltage. The feedback loop can control the regulation based on the power supply output voltage, inductor current, and / or other power supply parameters. Voltage-mode control compares the output voltage with a reference voltage and determines an error voltage. The error voltage is then compared with a triangular wave to set the pulse width of the control power supply output transistor. Summary of the Invention

[0004] This document discloses a switch-mode power supply with applied voltage-mode control. The voltage-mode control circuit provides discontinuous mode operation, a wide compensation range, and rapid stabilization. In one example, a voltage regulation circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a switch output terminal, a comparator circuit, and a compensation circuit. The switch output terminal is coupled to a first terminal of the first transistor and a first terminal of the second transistor. The comparator circuit includes an output terminal coupled to a second terminal of the first transistor and a second terminal of the second transistor. The third transistor includes a first terminal coupled to the second terminal of the first transistor. The fourth transistor includes: a first terminal coupled to the second terminal of the second transistor; and a second terminal coupled to the second terminal of the third transistor, a first input terminal of the comparator circuit, and a second input terminal of the comparator circuit. The compensation circuit is configured to provide an error signal to the third and fourth input terminals of the comparator circuit.

[0005] In another example, a voltage regulation circuit includes a switch output terminal, a high-side output transistor, a low-side output transistor, a high-side replica transistor, a low-side replica transistor, and a comparator circuit. The high-side output transistor is configured to drive the switch output terminal. The low-side output transistor is configured to drive the switch output terminal. The high-side replica transistor is coupled to the high-side output transistor. The low-side replica transistor is coupled to both the high-side replica transistor and the low-side replica transistor. The comparator circuit is coupled to the high-side replica transistor and the low-side replica transistor and is configured to compare a signal received from both the high-side replica transistor and the low-side replica transistor with a ramp signal.

[0006] In another example, a switch-mode power supply includes a switch output terminal, a first transistor, a second transistor, a third transistor, a fourth transistor, a comparator circuit, and a compensation circuit. The first transistor includes a first terminal coupled to the switch output terminal. The second transistor includes a first terminal coupled to the switch output terminal. The comparator circuit includes an output terminal coupled to a second terminal of the first transistor and a second terminal of the second transistor. The third transistor includes a first terminal coupled to the second terminal of the first transistor. The fourth transistor includes: a first terminal coupled to the second terminal of the second transistor; and a second terminal coupled to the second terminal of the third transistor, a first input terminal of the comparator circuit, and a second input terminal of the comparator circuit. The compensation circuit includes: a first input terminal coupled to the output of a voltage divider circuit; a second input terminal coupled to a reference voltage source; a first output terminal coupled to the third input terminal of the comparator circuit; and a second output terminal coupled to the fourth input terminal of the comparator circuit. Attached Figure Description

[0007] For a detailed description of the various examples, please refer to the accompanying drawings, in which:

[0008] Figure 1 shows a schematic diagram of an exemplary fixed-frequency voltage-mode regulation circuit;

[0009] Figure 2 shows the loop gain and phase in the fixed-frequency voltage-mode regulation circuit of Figure 1;

[0010] Figure 3 shows the output voltage response in the fixed-frequency voltage mode regulation circuit of Figure 1;

[0011] Figures 4 to 6 show examples of discontinuous mode operation suitable for use with the fixed-frequency voltage-mode regulation circuit of Figure 1;

[0012] Figure 7A and 7B A schematic diagram of an exemplary fixed-frequency enhanced voltage mode regulation circuit is shown.

[0013] Figure 8 It shows Figure 7A and 7B The output voltage response in a fixed-frequency enhanced voltage-mode regulation circuit; and

[0014] Figure 9 This demonstrates operation for discontinuous modes. Figure 7A and 7B The signal in the fixed-frequency enhanced voltage mode conditioning circuit;

[0015] Figure 10 It shows Figure 7A and 7B The loop gain and phase in a fixed-frequency boost voltage-mode conditioning circuit; and

[0016] Figure 11 A block diagram of a server system is shown, which includes a fixed-frequency boost voltage mode regulation circuit as described herein. Detailed Implementation

[0017] Compared to current-mode control, voltage-mode control-based voltage regulation circuits (such as switch-mode power supplies) can be relatively simple, applying voltage only in the feedback loop and providing fixed-frequency and high-bandwidth operation. However, such circuits can be difficult to stabilize if not using excessive current, and the implementation of discontinuous-mode operation can be complex. Figure 1 shows a schematic diagram of an exemplary fixed-frequency voltage-mode regulation circuit 100. The fixed-frequency voltage-mode regulation circuit 100 is a buck converter. The fixed-frequency voltage-mode regulation circuit 100 includes a high-side output transistor 102, a low-side output transistor 104, an inductor 106, a voltage divider 108, a comparator circuit 110, a ramp generation circuit 112, a compensation circuit 114, and a low-pass filter circuit 116.

[0018] High-side output transistor 102 and low-side output transistor 104 are coupled to inductor 106. Current flows through high-side output transistor 102 to charge inductor 106, while low-side output transistor 104 grounds inductor 106 to discharge it. High-side output transistor 102 and low-side output transistor 104 are coupled to comparator circuit 110 and are complementaryly turned on and off by an output signal generated by comparator circuit 110. Comparator circuit 110 is a summation comparator that generates an output based on the sum of differential inputs (e.g., generating a logic "high" output based on the sum of "+" inputs being greater than the sum of "-" inputs).

[0019] The input of comparator circuit 110 is coupled to inductor 106 via low-pass filter circuit 116 to receive a feedback voltage from inductor 106. The voltage output of low-pass filter circuit 116 is proportional to the voltage output (Vout) of inductor 106. Ramp generation circuit 112 is coupled to another input of comparator circuit 110. Ramp generation circuit 112 generates a ramp signal to be compared with the feedback voltage received via low-pass filter circuit 116 through comparator circuit 110. The voltage of the ramp signal is proportional to the voltage (Vin) on the power rail coupled to high-side output transistor 102.

[0020] Voltage divider 108 is coupled to inductor 106 to divide the voltage at the output of inductor 106 as determined by the resistors of voltage divider 108. Voltage divider 108 is coupled to compensation circuit 114. Compensation circuit 114 boosts the phase and compensates the loop formed by comparator circuit 110, high-side output transistor 102, low-side output transistor 104, inductor 106, voltage divider 108, and compensation circuit 114. The gain boost associated with the phase boost helps achieve a fast transient response. Figure 2 shows the loop gain and phase in fixed-frequency voltage mode regulation circuit 100. The uncompensated gain in fixed-frequency voltage mode regulation circuit 100 is shown as 202, while the compensated gain via compensation circuit 114 is shown as 204. The phase in fixed-frequency voltage mode regulation circuit 100 is shown as 206, while the compensated phase via compensation circuit 114 is shown as 208. While the compensation circuit 114 provides an improvement in the phase performance of the fixed-frequency voltage-mode regulation circuit 100, achieving a greater phase boost in the compensation circuit 114 requires a higher quiescent current, which is undesirable. Since the phase boost provided by the compensation circuit 114 is limited, it undesirably restricts the range of inductor and capacitor values ​​suitable for use in the inductor 106 and output capacitor 118. For example, smaller inductor and capacitor values ​​are desirable to reduce power supply size and cost.

[0021] The DC resistance of inductor 106 generates a load-dependent voltage drop at the output of the fixed-frequency voltage-mode regulation circuit 100. This voltage drop can be expressed as:

[0022]

[0023] The load-dependent voltage drop is readjusted by a low-pass filter circuit 116 with an associated recovery time. A wide range of output inductance and capacitance values ​​exacerbates the voltage drop regulation. Figure 3 shows the output voltage response in the fixed-frequency voltage-mode regulation circuit 100. Figure 3 shows an output voltage drop of approximately 7 millivolts at a 2-amp load current. In this example, the DC resistance of inductor 106 is 50 milliohms, the gain from the ramp signal is 10, and the gain from comparator circuit 110 is 1.5.

[0024]

[0025] The fixed-frequency voltage-mode regulation circuit 100 shown in Figure 1 does not support discontinuous mode operation. Figures 4 through 6 illustrate examples of discontinuous mode operation suitable for use with various implementations of the fixed-frequency voltage-mode regulation circuit 100. Figure 4 shows the inductor current 406 and the power supply output voltage 402 for operating the pulse train discontinuous mode. A reverse inductor current is detected, and the low-side output transistor is turned off. When the power supply output voltage 402 drops below a lower threshold 404, the controller generates a pulse train until the inductor current returns to zero. Disadvantages of this mode include: generating multiple pulses, indeterminate output voltage ripple, and indeterminate hysteresis between discontinuous and continuous modes.

[0026] Figure 5 illustrates the inductor current 506 and the power supply output voltage 502 for peak efficiency pulse train mode operation. When the power supply output voltage 502 drops below the lower threshold 504, the controller generates a pulse train, thereby generating an average current in the inductor corresponding to the maximum efficiency current 512. The output voltage rises, and the pulse train continues until the output voltage reaches the upper threshold 510. Disadvantages of this mode include: generating multiple pulses, unpredictable output voltage ripple, circuit complexity, and short-time pulse wave interference at the boundary conduction point.

[0027] Figure 6 illustrates the inductor current 606 and the power supply output voltage 602 for single-pulse train mode operation. This discontinuous mode operation is typically associated with a 'constant on-time' controller. The controller generates a single pulse when the power supply output voltage 602 drops below a lower threshold 604. The pulse width can be controlled by a monostable multivibrator. The output voltage rises, and the sequence terminates when the inductor current returns to zero. A disadvantage of this mode is the generation of multiple pulses to achieve a high power supply output capacitance.

[0028] Figure 7A and 7BA schematic diagram of an exemplary fixed-frequency enhanced voltage mode regulation circuit 700 is shown. The fixed-frequency enhanced voltage mode regulation circuit 700 is a buck converter. The fixed-frequency enhanced voltage mode regulation circuit 700 includes an enhanced voltage mode regulation control circuit 701, an inductor 706, and a voltage divider 708. The enhanced voltage mode regulation control circuit 701 includes a feedback terminal 701A, a switch output terminal 701B, a high-side output transistor 702, a low-side output transistor 704, a high-side replica transistor 722, a low-side replica transistor 724, a comparator circuit 710, a ramp generation circuit 712, a low-pass filter circuit 716, a latch circuit 720, switches 726, 727, 728, and 730.

[0029] High-side output transistor 702 and low-side output transistor 704 are coupled to and drive switch output terminal 701B and inductor 706. Current flows through high-side output transistor 702 to charge inductor 706, while low-side output transistor 704 grounds inductor 706 to discharge it. High-side output transistor 702 and low-side output transistor 704 are coupled to comparator circuit 710 and are complementaryly turned on and off by signal 717 generated by comparator circuit 710. Comparator circuit 710 is a summation comparator that generates an output based on the sum of differential inputs (e.g., generating a logic "high" output based on the sum of "+" inputs being greater than the sum of "-" inputs).

[0030] The high-side output transistor 702 includes a drain terminal 702D coupled to the power rail, a source terminal 702S coupled to the inductor 706, and a gate terminal 702G coupled to the output terminal 710E of the comparator circuit 710. The low-side output transistor 704 includes the source terminal 702S coupled to the high-side output transistor 702 and the drain terminal 704D coupled to the inductor 706, a source terminal 704S coupled to ground, and a gate terminal 704G coupled to the output terminal 710E of the comparator circuit 710 via an inverter 756.

[0031] High-side replication transistor 722 and low-side replication transistor 724 are coupled in parallel with high-side output transistor 702 and low-side output transistor 704 to the output terminal 710E of comparator circuit 710. High-side replication transistor 722 includes a drain terminal 722D coupled to the drain terminal 702D of high-side output transistor 702, a source terminal 722S coupled to the drain terminal 724D of low-side replication transistor 724, and a gate terminal 722G coupled to the gate terminal 702G of high-side output transistor 702 for common control. Low-side replication transistor 724 includes a drain terminal 724D coupled to the source terminal 722S of high-side replication transistor 722 (to provide a push-pull output of replication switch output terminal 701B), a source terminal 724S coupled to ground, and a gate terminal 724G coupled to the gate terminal 704G of low-side output transistor 704 for common control.

[0032] The input terminal 710C of comparator circuit 710 is coupled to the source terminal 722S of high-side replica transistor 722 and the drain terminal 724D of low-side replica transistor 724 via switch 727 and low-pass filter circuit 716 to receive feedback voltage from high-side replica transistor 722 and low-side replica transistor 724. Similarly, the input terminal 710C of comparator circuit 710 is coupled to the source terminal 702S of high-side output transistor 702 and the drain terminal 704D of low-side output transistor 704 via switch 726 and low-pass filter circuit 716 to receive feedback voltage from high-side output transistor 702 and low-side output transistor 704. The voltage output of the low-pass filter circuit 716 is proportional to Vout + Iout * Rou, where Vout is the voltage output of the fixed-frequency boost voltage mode regulation circuit 700, Iout is the current flowing to the load circuit, and Rou is the output resistance of the fixed-frequency boost voltage mode regulation circuit 700 (e.g., the DC resistance of inductor 706). Therefore, the high-side replica transistor 722 and the low-side replica transistor 724 generate a voltage at the input terminal 710C of the comparator circuit 710, which includes the voltage drop across the output of the fixed-frequency boost voltage mode regulation circuit 700. This allows the fixed-frequency boost voltage mode regulation circuit 700 to compensate for the output voltage drop. Figure 8 A comparison is shown between the output voltage response of the fixed-frequency boost voltage mode regulation circuit 700 and the response of the fixed-frequency voltage mode regulation circuit 100. At a 2-amp load current 806, the output voltage 723 of the fixed-frequency boost voltage mode regulation circuit 700 does not exhibit the 7 millivolt voltage drop found in the output voltage 804 generated by the fixed-frequency voltage mode regulation circuit 100.

[0033] The input terminal 710C of comparator circuit 710 is coupled to the input terminal 710D of comparator circuit 710 via switch 728. Switch 728 includes a terminal 728A coupled to the input terminal 710C of comparator circuit 710, a terminal 728B coupled to the input terminal 710D of comparator circuit 710, and a terminal 728C coupled to the output terminal 720C of latch circuit 720. Latch circuit 720 includes an input terminal 720A coupled to the output terminal 710E of comparator circuit 710 and an input terminal 720B coupled to the source terminal 704S of low-side output transistor 704. When inductor 706 discharges and the current direction in low-side output transistor 704 changes, signal 718 output by latch circuit 720 is activated to indicate that fixed-frequency boost voltage mode regulation circuit 700 is driving a high-impedance load, and fixed-frequency boost voltage mode regulation circuit 700 can operate in discontinuous mode. When signal 718 is valid, switch 728 is closed.

[0034] The drain terminal 704D of the low-side output transistor 704 is coupled to the low-pass filter circuit 716 via switch 726. Switch 726 includes a terminal 726A coupled to the low-pass filter circuit 716, a terminal 726B coupled to the source terminal 702S of the high-side output transistor 702, and a terminal 726C coupled to the output terminal 720C of the latch circuit 720 via an inverter. When the regulating circuit 700 is not driving a high-impedance load, switch 726 closes when signal 718 is invalid to provide feedback from the output transistor to comparator 710. The drain terminal 724D of the low-side replica transistor 724 is coupled to the low-pass filter circuit 716 via switch 727. Switch 727 includes a terminal 727A coupled to the low-pass filter circuit 716, a terminal 727B coupled to the source terminal 722S of the high-side replica transistor 722, and a terminal 727C coupled to the output terminal 720C of the latch circuit 720. When the regulating circuit 700 is driving a high-impedance load, the switch 727 closes when the signal 718 is active to provide feedback from the replica transistor to the comparator 710.

[0035] Ramp generation circuit 712 is coupled to input terminal 710D of comparator circuit 710 via switch 730. Switch 730 includes terminal 730A coupled to input terminal 710D of comparator circuit 710, terminal 730B coupled to output terminal 712B of ramp generation circuit 712, and terminal 730C coupled to output terminal 720C of latch circuit 720. Switch 730 is open when signal 718 is active. Ramp generation circuit 712 generates a sawtooth ramp signal 719, the amplitude of which is proportional to the voltage on the power rail. Ramp generation circuit 712 includes input terminal 712A, which is coupled to output terminal 720C of latch circuit 720. Ramp generation circuit 712 is disabled when signal 718 is active. Ramp generation circuit 712 generates sawtooth ramp signal 719 to be compared with feedback voltage received via low-pass filter circuit 716 by comparator circuit 710. The voltage of the sawtooth ramp signal 719 is proportional to the voltage (Vin) on the power rail coupled to the high-side output transistor 702.

[0036] When the fixed-frequency enhanced voltage mode regulation circuit 700 operates in continuous conduction mode, enabling the ramp generation circuit 712 to generate a sawtooth ramp signal 719, switch 728 is open, and switch 730 is closed to allow the comparator circuit 710 to compare the feedback signal provided by the high-side replica transistor 722 and the low-side replica transistor 724 with the sawtooth ramp signal 719. When the fixed-frequency enhanced voltage mode regulation circuit 700 operates in discontinuous mode, the ramp generation circuit 712 is disabled, switch 728 is closed, and switch 730 is open to route the feedback signal provided by the high-side replica transistor 722 and the low-side replica transistor 724 to both input terminals 710C and 710D of the comparator circuit 710.

[0037] Figure 9 The signal generated in the fixed-frequency enhanced voltage mode regulation circuit 700 for discontinuous mode operation is shown. At 902, comparator circuit 710 activates signal 717 to charge inductor 706, resets latch circuit 720, and deactivates signal 718. When signal 718 is deactivated, ramp generation circuit 712 generates sawtooth ramp signal 719. At 904, signal 717 is deactivated, and inductor 706 discharges. At 906, inductor 706 discharges in the reverse direction of current, and latch circuit 720 is set to activate signal 718. Activation of signal 718 disables ramp generation circuit 712 and disconnects ramp generation circuit 712 from comparator circuit 710. Output voltage 723 decreases over time, and at 908, comparator circuit 710 activates signal 717 to recharge inductor 706. Figure 9The sequence shown is repeated to provide discontinuous mode operation, while the load powered by the fixed-frequency enhanced voltage mode regulation circuit 700 presents high impedance.

[0038] Compensation circuit 714, relative to compensation circuit 114, improves the phase and gain of the voltage feedback without increasing quiescent current consumption, thus expanding the range of suitable inductance and capacitance values ​​for inductor 706 and signal 718. Compensation circuit 714 includes an input terminal 714A coupled to the output 708B of voltage divider 708 and an input terminal 714B coupled to a reference voltage source 766. Reference voltage source 766 generates a reference voltage, which the compensation circuit compares with the feedback signal provided by voltage divider 708 to generate an error signal. Compensation circuit 714 also includes an output terminal 714C coupled to input terminal 710A of comparator circuit 710 and an output terminal 714D coupled to input terminal 710B of comparator circuit 710.

[0039] The compensation circuit 714 is implemented using current source 732, transistor 734, current source 736, transistor 738, transistor 740, transistor 742, current source 744, transistor 746, current source 748, transistor 750, transistor 752, and transistor 754. Transistor 750 includes a gate terminal 750G coupled to current source 748 and a drain terminal 750D coupled to output terminal 714D. Transistor 752 includes a drain terminal 752D coupled to drain terminal 750D of transistor 750, a source terminal 752S coupled to ground, and a gate terminal 752G coupled to drain terminal 752D of transistor 752 via resistor 758. Transistor 746 includes a gate terminal 746G coupled to input terminal 714A and a drain terminal 746D coupled to power rail and current source 744. Transistor 754 includes a source terminal 754S coupled to a source terminal 746S of transistor 746, a drain terminal 754D coupled to a gate terminal 750G of transistor 750, and a gate terminal 754G coupled to a source terminal 750S, a current source 744, a capacitor 764, and a resistor 762 of transistor 750.

[0040] Transistor 738 includes a gate terminal 738G coupled to a current source 736 and a drain terminal 738D coupled to an output terminal 714C. Transistor 740 includes a drain terminal 740D coupled to the drain terminal 738D of transistor 738, a source terminal 740S coupled to ground, and a gate terminal 740G coupled to the drain terminal 740D of transistor 740 via resistor 760. Transistor 734 includes a gate terminal 734G coupled to an input terminal 714B and a drain terminal 734D coupled to a power rail and a current source 732. Transistor 742 includes a source terminal 742S coupled to the source terminal 734S of transistor 734, a drain terminal 742D coupled to the gate terminal 738G of transistor 738, and a gate terminal 742G, which is coupled to the source terminal 738S, the current source 732, a capacitor 764, and a resistor 762 of transistor 738. The network comprising transistors 734, 742, and 738, as well as transistors 746, 754, and 750, is an example of a transconductance boost circuit with transistors 738 and 750 suitable for use in compensation circuit 714. Various other transconductance boost circuits can be employed in compensation circuit 714.

[0041] Figure 10 The loop gain and phase in the fixed-frequency boost voltage-mode regulation circuit 700 and the relationship between gain and phase and current in the fixed-frequency voltage-mode regulation circuit 100 are shown. More specifically, Figure 10 A fixed-frequency boost voltage-mode regulation circuit 700 is shown providing approximately 65 degrees of phase boost with approximately 450 nanoamps of current, while a fixed-frequency voltage-mode regulation circuit 100 uses approximately 4.5 microamps of current to provide approximately 65 degrees of phase boost. The cited current consumption diagrams are process-related and provided for comparative reference only. Similarly, the fixed-frequency boost voltage-mode regulation circuit 700 provides approximately 26 dB of gain boost with approximately 250 nanoamps of current, while the fixed-frequency voltage-mode regulation circuit 100 uses approximately 4.5 microamps of current to provide approximately 26 dB of gain boost. Therefore, the fixed-frequency boost voltage-mode regulation circuit 700 provides increased phase and gain boost, which extends the range of the output inductance and capacitance without increasing current consumption.

[0042] Figure 11A block diagram of server system 1100 is shown, which includes fixed-frequency enhanced voltage-mode regulation circuitry as described herein. Server system 1100 includes one or more compute nodes 1102. Each compute node 1102 includes one or more processors 1104 coupled to memory 1106, a network interface 1112, and one or more I / O interfaces 1114. In various embodiments, compute node 1102 may be a single-processor system including one processor 1104, or a multiprocessor system including several processors 1104 (e.g., two, four, eight, or another suitable number). Processor 1104 may be any suitable processor capable of executing instructions. For example, in various embodiments, processor 1104 may be a general-purpose or embedded microprocessor, a graphics processing unit (GPU), or a digital signal processor (DSP) implementing any of various instruction set architectures (ISAs). In a multiprocessor system, each of the processors 1104 may typically, but does not necessarily, implement the same ISA.

[0043] Memory 1106 may include a non-transitory computer-readable storage medium configured to store program instructions and / or data accessible to processor 1104. Memory 1106 may be implemented using any suitable memory technology, such as static random access memory (SRAM), synchronous dynamic RAM (SDRAM), non-volatile / flash memory, or any other type of memory.

[0044] Server system 1100 may also include an auxiliary storage device, which may be implemented using volatile or non-volatile storage devices and storage devices for storing information such as program instructions and / or data. The auxiliary storage device may comprise various types of computer-readable media accessible to computing node 1102. Computer-readable media may comprise storage media or memory media, such as semiconductor storage devices, magnetic or optical media (e.g., magnetic disks or CD / DVD-ROMs), or other storage technologies.

[0045] Network interface 1112 includes circuitry configured to allow data exchange between computing node 1102 and / or other devices coupled to the network. For example, network interface 1112 may be configured to allow data exchange between a first instance of server system 1100 and a second instance of server system 1100. Network interface 1112 may support communication via wired or wireless data networks.

[0046] I / O interface 1114 allows computing node 1102 to communicate with devices external to server system 1100. Devices coupled to server system 1100 via I / O interface 1114 may include one or more display terminals, keyboards, keypads, touchpads, scanning devices, voice or optical recognition devices, or any other devices suitable for inputting or retrieving data through computing node 1102. Multiple input / output devices may exist within computing system 800.

[0047] Power supply 1116 generates voltages to power the various components of compute node 1102. For example, power supply 1116 can power processor 1104, memory 1106, or any other component of compute node 1102. Power supply 1116 includes an implementation of fixed-frequency boost voltage mode regulation circuitry 700 to generate one or more voltages to power compute node 1102. Because compensation circuitry 714 allows for a reduction in the size of the inductors and output filter capacitors used in power supply 1116, the size and cost of compute node 1102 can be reduced. In fixed-frequency boost voltage mode regulation circuitry 700, duty cycle feedforward provides a fast response to changes in load current, and discontinuous mode operation improves the power efficiency of power supply 1116.

[0048] Compared to the fixed-frequency voltage-mode regulation circuit 100, the fixed-frequency enhanced voltage-mode regulation circuit 700 offers several advantages. The compensation circuit 714 provides gain and phase boost, which allows for an increased size range for the inductor 706 and the output capacitor, thus enabling the use of smaller, less expensive inductors. The duty cycle feedforward provided by the replica transistors 722 and 724 synthesizes the output voltage of the fixed-frequency enhanced voltage-mode regulation circuit 700 plus the output voltage drop, which improves the response of the fixed-frequency enhanced voltage-mode regulation circuit 700 to increased load current. Switches 728 and 730 allow the fixed-frequency enhanced voltage-mode regulation circuit 700 to provide discontinuous mode operation.

[0049] The term "coupled" is used throughout this specification. The term may encompass a connection, communication, or signaling path that achieves a functional relationship consistent with the description of this disclosure. For example, if device A generates a signal to control device B to perform an action, in a first instance, device A is coupled to device B via a direct connection, or in a second instance, device A is coupled to device B via an intermediate component C, provided that the intermediate component C does not alter the functional relationship between device A and device B such that device A controls device B via a control signal generated by device A.

[0050] The modifications are feasible in the described embodiments, and other embodiments are feasible within the scope of the claims.

Claims

1. A voltage regulation circuit, the voltage regulation circuit comprising: a first transistor and a second transistor; a switch output terminal coupled to a first terminal of the first transistor and a first terminal of the second transistor; a comparator circuit comprising an output terminal coupled to a second terminal of the first transistor and a second terminal of the second transistor; a third transistor comprising a first terminal coupled to the second terminal of the first transistor; a fourth transistor comprising: a first terminal coupled to the second terminal of the second transistor; and a second terminal coupled to a second terminal of the third transistor, a first input terminal of the comparator circuit, and a second input terminal of the comparator circuit; and a compensation circuit configured to provide an error signal to third and fourth input terminals of the comparator circuit.

2. The voltage regulation circuit of claim 1, the voltage regulation circuit further comprising: a latch circuit comprising: a first input terminal coupled to the output terminal of the comparator circuit; and a second input terminal coupled to a third terminal of the second transistor.

3. The voltage regulation circuit of claim 2, the voltage regulation circuit further comprising: a first switch comprising: a first terminal coupled to the first terminal of the first transistor; a second terminal coupled to the first input terminal of the comparator circuit; and a third terminal coupled to an output terminal of the latch circuit; and a second switch comprising: a first terminal coupled to the second terminal of the third transistor; a second terminal coupled to the first input terminal of the comparator circuit; and a third terminal coupled to the output terminal of the latch circuit.

4. The voltage regulation circuit of claim 2, the voltage regulation circuit further comprising: a switch comprising: a first terminal coupled to the first input terminal of the comparator circuit; a second terminal coupled to the second input terminal of the comparator circuit; and a third terminal coupled to an output terminal of the latch circuit.

5. The voltage regulation circuit of claim 4, wherein: the switch is a first switch; and the voltage regulation circuit further comprising: a second switch comprising: a first terminal coupled to the second input terminal of the comparator circuit; and a second terminal coupled to the output terminal of the latch circuit.

6. The voltage regulation circuit of claim 5, the voltage regulation circuit further comprising: a ramp generation circuit comprising: an input terminal coupled to the output terminal of the latch circuit; and an output terminal coupled to a third terminal of the second switch.

7. The voltage regulation circuit of claim 1, wherein the compensation circuit comprises: a first current source; a fifth transistor comprising: a first terminal coupled to the first current source; and a second terminal coupled to a first output terminal of the compensation circuit; a sixth transistor comprising: a first terminal coupled to the second terminal of the fifth transistor; and a second terminal coupled to the second terminal of the fifth transistor; a seventh transistor comprising: a first terminal coupled to a first input terminal of the compensation circuit; a second terminal coupled to a power supply rail; an eighth transistor comprising: a first terminal coupled to a third terminal of seventh transistor; a second terminal coupled to the first terminal of the fifth transistor; and a third input terminal coupled to a third terminal of the fifth transistor.

8. The voltage regulation circuit of claim 7, wherein the compensation circuit comprises: a second current source; a ninth transistor comprising: a first terminal coupled to the second current source; and a second terminal coupled to a second output terminal of the compensation circuit; a tenth transistor comprising: a first terminal coupled to the second terminal of the ninth transistor; and a second terminal coupled to the second terminal of the ninth transistor; an eleventh transistor comprising: a first terminal coupled to a second input terminal of the compensation circuit; a second terminal coupled to the power supply rail; a twelfth transistor comprising: a first terminal coupled to a third terminal of eleventh transistor; a second terminal coupled to the first terminal of the ninth transistor; and a third input terminal coupled to a third terminal of the ninth transistor.

9. A voltage regulation circuit, the voltage regulation circuit comprising: a switch output terminal; a high-side output transistor configured to drive the switch output terminal; a low-side output transistor configured to drive the switch output terminal; a high-side replica transistor coupled to the high-side output transistor; a low-side replica transistor coupled to the high-side replica transistor and the low-side output transistor; a comparator circuit having inputs coupled to the high-side replica transistor and the low-side replica transistor and configured to compare a signal received from both the high-side replica transistor and the low-side replica transistor to a ramp signal and having outputs coupled to the high-side replica transistor and the low-side replica transistor; and a latch circuit having an input coupled to the low-side output transistor, having an input coupled to the comparator circuit output, and configured to activate a control signal based on a current drawn by a load circuit being less than a threshold value.

10. The voltage regulation circuit of claim 9, further comprising: a first switch coupled to the latch circuit, the high-side output transistor, the low-side output transistor, and the comparator circuit and configured to connect the high-side output transistor and the low-side output transistor to the comparator circuit in response to the control signal; and a second switch coupled to the latch circuit, the high-side replica transistor, the low-side replica transistor, and the comparator circuit and configured to connect the high-side replica transistor and the low-side replica transistor to the comparator circuit in response to the control signal.

11. The voltage regulation circuit of claim 9, further comprising a switch coupled to the latch circuit, a first terminal of the comparator circuit, and a second terminal of the comparator circuit and configured to connect the first terminal of the comparator circuit and the second terminal of the comparator circuit in response to the control signal.

12. The voltage regulation circuit of claim 9, further comprising a ramp generation circuit coupled to the latch circuit and configured to generate the ramp signal in response to the control signal.

13. The voltage regulation circuit of claim 12, further comprising a switch coupled to the latch circuit and the ramp generation circuit and configured to pass the ramp signal to the comparator circuit in response to the control signal.

14. The voltage regulation circuit of claim 9, further comprising: a feedback terminal; and a compensation circuit coupled to the feedback terminal and the comparator circuit and configured to generate an error signal based on a feedback signal received from the feedback terminal and a reference voltage.

15. A switched mode power supply, comprising: a switch output terminal; a first transistor comprising a first terminal coupled to the switch output terminal; a second transistor comprising a first terminal coupled to the switch output terminal; a comparator circuit comprising an output terminal coupled to a second terminal of the first transistor and a second terminal of the second transistor; a third transistor, the third transistor including a first terminal coupled to the second terminal of the first transistor; a fourth transistor, the fourth transistor including: a first terminal coupled to the second terminal of the second transistor; and a second terminal coupled to a second terminal of the third transistor, a first input terminal of the comparator circuit, and a second input terminal of the comparator circuit; and a compensation circuit, the compensation circuit including: a first input terminal coupled to an output of a voltage divider circuit; a second input terminal coupled to a reference voltage source; a first output terminal coupled to a third input terminal of the comparator circuit; and a second output terminal coupled to a fourth input terminal of the comparator circuit.

16. The switched mode power supply of claim 15, further comprising: a latch circuit, the latch circuit including: a first input terminal coupled to the output terminal of the comparator circuit; and a second input terminal coupled to a third terminal of the second transistor.

17. The switched mode power supply of claim 16, further comprising: a first switch, the first switch including: a first terminal coupled to the first terminal of the first transistor; a second terminal coupled to the first input terminal of the comparator circuit; and a third terminal coupled to an output terminal of the latch circuit; and a second switch, the second switch including: a first terminal coupled to the second terminal of the third transistor; a second terminal coupled to the first input terminal of the comparator circuit; and a third terminal coupled to the output terminal of the latch circuit.

18. The switched mode power supply of claim 16, further comprising: a switch, the switch including: a first terminal coupled to the first input terminal of the comparator circuit; a second terminal coupled to the second input terminal of the comparator circuit; and a third terminal coupled to an output terminal of the latch circuit.

19. The switched mode power supply of claim 18, wherein: the switch is a first switch; and the voltage regulation circuit further includes: a second switch, the second switch including: a first terminal coupled to the second input terminal of the comparator circuit; and a second terminal coupled to the output terminal of the latch circuit; and a ramp generation circuit, the ramp generation circuit including: an input terminal coupled to the output terminal of the latch circuit; and an output terminal coupled to a third terminal of the second switch.

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