Voltage Reference Integrated Devices

Abstract

The present disclosure provides a reference voltage source integrated device, comprising: a reference voltage source generation module, the reference voltage source generation module generates an initial reference voltage; and a reference voltage output module, the reference voltage output module includes a voltage adjustment submodule, the voltage adjustment submodule increases the initial reference voltage to a predetermined voltage for output.

Description

Technical Field

[0001] The present disclosure belongs to the technical field of reference voltage sources, and in particular relates to a reference voltage source integrated device. Background Art

[0002] Reference voltage sources are widely used in integrated devices (eg, integrated circuit chips) because they can generate accurate and stable reference voltages.

[0003] However, the reference voltage source in the prior art still has the problem of low accuracy, for example, being affected by external factors of the voltage source or circuit structure. Summary of the invention

[0004] In order to solve at least one of the above technical problems, the present disclosure provides a reference voltage source integrated device.

[0005] The reference voltage source integrated device disclosed in the present invention is implemented through the following technical solutions.

[0006] According to one aspect of the present disclosure, there is provided a reference voltage source integrated device, comprising:

[0007] a reference voltage source generating module, the reference voltage source generating module generating an initial reference voltage; and a reference voltage output module, the reference voltage output module comprising a voltage adjusting submodule, the voltage adjusting submodule raising the initial reference voltage to a predetermined voltage for output.

[0008] According to the reference voltage source integrated device of at least one embodiment of the present disclosure, the voltage adjustment submodule of the reference voltage output module includes a sixth resistor and a seventh resistor, the second end of the seventh resistor is grounded, the first end of the seventh resistor is connected to the initial reference voltage output end of the reference voltage source generating module, the second end of the sixth resistor is connected to the first end of the seventh resistor, and the first end of the sixth resistor outputs the predetermined voltage.

[0009] According to at least one embodiment of the reference voltage source integrated device of the present disclosure, the reference voltage source generation module includes a first P-type field effect transistor, a second P-type field effect transistor, a third P-type field effect transistor, a fourth P-type field effect transistor, a first N-type field effect transistor, a second N-type field effect transistor, a first triode, a second triode, a third triode, a fourth triode, a first resistor, a second resistor, a third resistor and a fourth resistor;

[0010] The first end of the first P-type field effect transistor is connected to the device voltage terminal VDD of the reference voltage source integrated device; the second end of the first P-type field effect transistor is connected to the first end of the third P-type field effect transistor; the second end of the third P-type field effect transistor is connected to the first end of the first resistor; the second end of the first resistor is connected to the first end of the first N-type field effect transistor; the second end of the first N-type field effect transistor is connected to the collector of the third triode; the emitter of the third triode is connected to the collector of the first triode; the emitter of the first triode is connected to the first end of the third resistor, the second end of the third resistor is connected to the first end of the fourth resistor; the second end of the fourth resistor is grounded;

[0011] The first end of the second P-type field effect transistor is connected to the device voltage terminal VDD of the reference voltage source integrated device; the second end of the second P-type field effect transistor is connected to the first end of the fourth P-type field effect transistor; the second end of the fourth P-type field effect transistor is connected to the first end of the second N-type field effect transistor; the second end of the second N-type field effect transistor is connected to the collector of the fourth triode; the emitter of the fourth triode is connected to the first end of the second resistor, and the second end of the second resistor is connected to the collector of the second triode; the emitter of the second triode is connected to the first end of the fourth resistor;

[0012] The control end of the first P-type field effect transistor is connected to the control end of the second P-type field effect transistor; the control end of the third P-type field effect transistor is connected to the control end of the fourth P-type field effect transistor; the control end of the first P-type field effect transistor is connected to the second end of the third P-type field effect transistor; the control end of the third P-type field effect transistor is connected to the first end of the first N-type field effect transistor; the first end of the second N-type field effect transistor is connected to the control end of the second N-type field effect transistor; the base of the third transistor is connected to the base of the fourth transistor; the base of the first transistor is connected to the collector of the second transistor, and the base of the second transistor is connected to the collector of the first transistor.

[0013] According to at least one embodiment of the reference voltage source integrated device of the present disclosure, the reference voltage source generation module includes a first P-type field effect transistor, a second P-type field effect transistor, a third P-type field effect transistor, a fourth P-type field effect transistor, a first N-type field effect transistor, a second N-type field effect transistor, a first triode, a second triode, a third triode, a fourth triode, a first resistor, a second resistor, a third resistor and a fourth resistor;

[0014] The first end of the first P-type field effect transistor is connected to the device voltage end of the reference voltage source integrated device; the second end of the first P-type field effect transistor is connected to the first end of the third P-type field effect transistor; the second end of the third P-type field effect transistor is connected to the first end of the first resistor; the second end of the first resistor is connected to the first end of the first N-type field effect transistor; the second end of the first N-type field effect transistor is connected to the collector of the third triode; the emitter of the third triode is connected to the collector of the first triode; the emitter of the first triode is connected to the first end of the third resistor, the second end of the third resistor is connected to the first end of the fourth resistor; the second end of the fourth resistor is grounded;

[0015] The first end of the second P-type field effect transistor is connected to the device voltage end of the reference voltage source integrated device; the second end of the second P-type field effect transistor is connected to the first end of the fourth P-type field effect transistor; the second end of the fourth P-type field effect transistor is connected to the first end of the second N-type field effect transistor; the second end of the second N-type field effect transistor is connected to the collector of the fourth triode; the emitter of the fourth triode is connected to the first end of the second resistor, and the second end of the second resistor is connected to the collector of the second triode; the emitter of the second triode is connected to the first end of the fourth resistor;

[0016] The control end of the first P-type field effect transistor is connected to the control end of the second P-type field effect transistor; the control end of the third P-type field effect transistor is connected to the control end of the fourth P-type field effect transistor; the control end of the first P-type field effect transistor is connected to the second end of the third P-type field effect transistor; the control end of the third P-type field effect transistor is connected to the first end of the first N-type field effect transistor; the first end of the second N-type field effect transistor is connected to the control end of the second N-type field effect transistor; the base of the third transistor is connected to the base of the fourth transistor; the base of the first transistor is connected to the collector of the first transistor, and the base of the second transistor is connected to the collector of the second transistor.

[0017] According to the reference voltage source integrated device of at least one embodiment of the present disclosure, the voltage adjustment submodule of the reference voltage output module includes a first buffer, the second end of the first buffer is connected to the first end of the sixth resistor, the first end of the first buffer is connected to the device voltage end of the reference voltage source integrated device; the control end of the first buffer is connected to the second end of the fourth P-type field effect transistor.

[0018] According to the reference voltage source integrated device of at least one embodiment of the present disclosure, the first buffer is an N-type field effect transistor.

[0019] According to the reference voltage source integrated device of at least one embodiment of the present disclosure, a fifth resistor is connected between the first terminal of the first buffer and the device voltage terminal of the reference voltage source integrated device.

[0020] According to at least one embodiment of the reference voltage source integrated device of the present disclosure, it also includes a voltage suppression ratio adjustment module, which includes an eighth resistor, a ninth resistor and an amplifier, the predetermined voltage is input to the positive phase input terminal of the amplifier, the second end of the ninth resistor is grounded, the first end of the ninth resistor is connected to the second end of the eighth resistor, the reverse input terminal of the amplifier is connected to the first end of the ninth resistor, the first end of the eighth resistor is connected to the output terminal of the amplifier, and the voltage at the output terminal of the amplifier is used as the device voltage of the reference voltage source integrated device.

[0021] According to the reference voltage source integrated device of at least one embodiment of the present disclosure, the voltage adjustment submodule further includes an RC filtering module, and the RC filtering module performs RC filtering on the predetermined voltage.

[0022] According to the reference voltage source integrated device of at least one embodiment of the present disclosure, the voltage adjustment submodule further includes an LC filtering module, and the LC filtering module performs LC filtering on the predetermined voltage.

[0023] According to the reference voltage source integrated device of at least one embodiment of the present disclosure, the voltage adjustment submodule further includes an RC filtering module or an LC filtering module, and the RC filtering module or the LC filtering module performs RC filtering or LC filtering on the predetermined voltage.

[0024] According to the reference voltage source integrated device of at least one embodiment of the present disclosure, the voltage adjustment submodule of the reference voltage output module includes a sixth resistor, a seventh resistor, a first buffer, an eleventh resistor, a twelfth resistor and a second buffer;

[0025] The second end of the seventh resistor is grounded, the first end of the seventh resistor is connected to the initial reference voltage output end of the reference voltage source generating module, the second end of the sixth resistor is connected to the first end of the seventh resistor, the first end of the sixth resistor is connected to the second end of the first buffer, and the first end of the first buffer is connected to the device voltage end VDD of the reference voltage source integrated device via the fifth resistor;

[0026] The second end of the twelfth resistor is grounded, the first end of the twelfth resistor is connected to the second end of the eleventh resistor, the first end of the eleventh resistor is connected to the second end of the second buffer, the first end of the second buffer is connected to the device voltage terminal VDD of the reference voltage source integrated device via the tenth resistor, and the control end of the second buffer is connected to the control end of the first buffer; the control end of the first buffer and the control end of the second buffer are provided with a control voltage by the reference voltage source generation module;

[0027] The first end of the eleventh resistor outputs the predetermined voltage.

[0028] According to the reference voltage source integrated device of at least one embodiment of the present disclosure, the first buffer and the second buffer are both N-type field effect transistors.

[0029] According to the reference voltage source integrated device of at least one embodiment of the present disclosure, the resistance value of the sixth resistor is the same as the resistance value of the eleventh resistor, and the resistance value of the seventh resistor is the same as the resistance value of the twelfth resistor.

[0030] According to the reference voltage source integrated device of at least one embodiment of the present disclosure, the voltage adjustment submodule further includes a filter capacitor, and the filter capacitor performs filtering processing on the predetermined voltage.

[0031] According to at least one embodiment of the reference voltage source integrated device of the present disclosure, it also includes a voltage suppression ratio adjustment module, which includes a charge pump. The voltage taken from the reference voltage source generation module is boosted by the charge pump, and the voltage after the charge pump is boosted is used as the device voltage of the reference voltage source integrated device.

[0032] According to at least one embodiment of the reference voltage source integrated device disclosed herein, the voltage suppression ratio adjustment module further includes a voltage suppression ratio adjustment module, which includes a Boost boost circuit. The voltage taken from the reference voltage source generation module is boosted by the Boost boost circuit, and the voltage after the boost circuit is used as the device voltage of the reference voltage source integrated device. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The accompanying drawings illustrate exemplary embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. These drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification.

[0034] Figure 1 A schematic structural diagram of a reference voltage source integrated device according to an embodiment of the present disclosure.

[0035] Figure 2 A schematic structural diagram of a reference voltage source integrated device according to yet another embodiment of the present disclosure.

[0036] Figure 3 A schematic structural diagram of a reference voltage source integrated device according to yet another embodiment of the present disclosure.

[0037] Figure 4 A schematic structural diagram of a reference voltage source integrated device according to yet another embodiment of the present disclosure.

[0038] Figure 5 A schematic structural diagram of a reference voltage source integrated device according to yet another embodiment of the present disclosure.

[0039] Figure 6 A schematic structural diagram of a reference voltage source integrated device according to yet another embodiment of the present disclosure.

[0040] Figure 7 A schematic structural diagram of a reference voltage source integrated device according to yet another embodiment of the present disclosure.

[0041] Figure 8 A schematic structural diagram of a reference voltage source integrated device according to yet another embodiment of the present disclosure.

[0042] Fig. 9 A schematic structural diagram of a reference voltage source integrated device according to yet another embodiment of the present disclosure.

[0043] Fig.10 A schematic structural diagram of a reference voltage source integrated device according to yet another embodiment of the present disclosure.

[0044] Fig.11 A schematic structural diagram of a reference voltage source integrated device according to yet another embodiment of the present disclosure. DETAILED DESCRIPTION

[0045] The present disclosure is further described in detail below in conjunction with the accompanying drawings and implementations. It is understood that the specific implementations described herein are only used to explain the relevant content, rather than to limit the present disclosure. It should also be noted that, for ease of description, only the parts related to the present disclosure are shown in the accompanying drawings.

[0046] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in the present disclosure can be combined with each other. The technical solution of the present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0047] Unless otherwise specified, the exemplary embodiments / embodiments shown will be understood as providing exemplary features of various details of some ways in which the technical concept of the present disclosure can be implemented in practice. Therefore, unless otherwise specified, the features of the various embodiments / embodiments can be combined, separated, interchanged and / or rearranged without departing from the technical concept of the present disclosure.

[0048] The use of cross-hatching and / or shading in the accompanying drawings is generally used to make the boundaries between adjacent components clear. As such, unless otherwise specified, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for the specific materials, material properties, dimensions, proportions, commonalities between the components shown, and / or any other characteristics, attributes, properties, etc. of the components. In addition, in the accompanying drawings, the sizes and relative sizes of the components may be exaggerated for clarity and / or descriptive purposes. When the exemplary embodiments can be implemented differently, the specific process sequence can be performed in a different order than described. For example, two successively described processes can be performed substantially simultaneously or in an order opposite to the described order. In addition, the same figure numbers represent the same components.

[0049] When a component is referred to as being "on" or "over," "connected to," or "coupled to" another component, the component may be directly on, directly connected to, or directly coupled to the other component, or intervening components may be present. However, when a component is referred to as being "directly on," "directly connected to," or "directly coupled to" another component, there are no intervening components. For this purpose, the term "connected" may refer to a physical connection, an electrical connection, etc., with or without intervening components.

[0050] For descriptive purposes, the present disclosure may use spatially relative terms such as "under," "beneath," "under," "down," "over," "upper," "above," "higher," and "side (e.g., as in "sidewall")," to describe the relationship of one component to another (other) component as shown in the accompanying drawings. The spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, components described as "under" or "beneath" other components or features would subsequently be positioned "over" the other components or features. Thus, the exemplary term "under" can encompass both the "above" and "below" orientations. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0051] The terms used here are for the purpose of describing specific embodiments, and are not intended to be restrictive. As used here, unless the context clearly indicates otherwise, the singular forms "one (kind, person)" and "said (the)" are also intended to include plural forms. In addition, when the terms "comprise" and / or "include" and their variations are used in this specification, it is explained that there are stated features, integral bodies, steps, operations, parts, assemblies and / or their groups, but it is not excluded that there are or add one or more other features, integral bodies, steps, operations, parts, assemblies and / or their groups. It should also be noted that, as used here, the terms "substantially", "approximately" and other similar terms are used as approximate terms and not as degree terms, so that they are used to explain the inherent deviations of the measured values, calculated values ​​and / or the values ​​provided that will be recognized by those of ordinary skill in the art.

[0052] Figure 1 A schematic structural diagram of a reference voltage source integrated device according to an embodiment of the present disclosure. Figure 2 A schematic structural diagram of a reference voltage source integrated device according to yet another embodiment of the present disclosure. Figure 3 A schematic structural diagram of a reference voltage source integrated device according to yet another embodiment of the present disclosure. Figure 4 A schematic structural diagram of a reference voltage source integrated device according to yet another embodiment of the present disclosure. Figure 5 A schematic structural diagram of a reference voltage source integrated device according to yet another embodiment of the present disclosure. Figure 6 A schematic structural diagram of a reference voltage source integrated device according to yet another embodiment of the present disclosure. Figure 7 A schematic structural diagram of a reference voltage source integrated device according to yet another embodiment of the present disclosure. Figure 8 A schematic structural diagram of a reference voltage source integrated device according to yet another embodiment of the present disclosure. Fig. 9 A schematic structural diagram of a reference voltage source integrated device according to yet another embodiment of the present disclosure. Fig.10 A schematic structural diagram of a reference voltage source integrated device according to yet another embodiment of the present disclosure. Fig.11 A schematic structural diagram of a reference voltage source integrated device according to yet another embodiment of the present disclosure.

[0053] Combined with the following Figures 1 to 11 The reference voltage source integrated device disclosed in the present invention is described in detail.

[0054] According to an embodiment of the present disclosure, a reference voltage source integrated device, such as Figure 1 As shown, the reference voltage source integrated device 1 comprises:

[0055] A reference voltage source generating module 10, the reference voltage source generating module 10 generates an initial reference voltage VREF1; and,

[0056] The reference voltage output module 20 includes a voltage adjustment submodule, which increases the initial reference voltage VREF1 to a predetermined voltage VREF for output.

[0057] The device voltage of the reference voltage source integrated device 1 is VDD.

[0058] The reference voltage source integrated device 1 of this embodiment can increase the initial reference voltage VREF1 to any predetermined voltage VREF through the voltage adjustment submodule.

[0059] For the reference voltage source integrated device 1 of the above embodiment, preferably, Figures 1 to 3 As shown, the voltage adjustment submodule of the reference voltage output module 20 includes a sixth resistor 306 and a seventh resistor 307, the second end of the seventh resistor 307 is grounded, the first end of the seventh resistor 307 is connected to the output end of the initial reference voltage VREF1 of the reference voltage source generating module 10, the second end of the sixth resistor 306 is connected to the first end of the seventh resistor 307, and the first end of the sixth resistor 306 outputs a predetermined voltage VREF.

[0060] Preferably, the voltage adjustment submodule of the reference voltage output module 20 also includes a first buffer 107 (for example, an N-type field effect transistor), the second end (source end) of the first buffer 107 is connected to the first end of the sixth resistor 306, and the first end (drain end) of the first buffer 107 is connected to the device voltage end VDD of the reference voltage source integrated device 1; the control end (gate end) of the first buffer 107 is connected to the second end (drain end) of the fourth P-type field effect transistor 104.

[0061] The first buffer 107 may be an N-type field effect transistor.

[0062] In the above-mentioned various implementations, preferably, a fifth resistor 305 is connected between the first end of the first buffer 107 and the device voltage terminal VDD of the reference voltage source integrated device 1 .

[0063] For the reference voltage source integrated device 1 of each of the above embodiments, preferably, Figure 1 and Figure 3 As shown in the figure, the reference voltage source generation module 10 includes a first P-type field effect transistor 101, a second P-type field effect transistor 102, a third P-type field effect transistor 103, a fourth P-type field effect transistor 104, a first N-type field effect transistor 105, a second N-type field effect transistor 106, a first triode 201, a second triode 202, a third triode 203, a fourth triode 204, a first resistor 301, a second resistor 302, a third resistor 303 and a fourth resistor 304;

[0064] The first end (source end) of the first P-type field effect transistor 101 is connected to the device voltage end VDD of the reference voltage source integrated device 1; the second end (drain end) of the first P-type field effect transistor 101 is connected to the first end (source end) of the third P-type field effect transistor 103; the second end (drain end) of the third P-type field effect transistor 103 is connected to the first end of the first resistor 301; the second end of the first resistor 301 is connected to the first end (drain end) of the first N-type field effect transistor 105; the second end (source end) of the first N-type field effect transistor 105 is connected to the collector of the third triode 203; the emitter of the third triode 203 is connected to the collector of the first triode 201; the emitter of the first triode 201 is connected to the first end of the third resistor 303, and the second end of the third resistor 303 is connected to the first end of the fourth resistor 304; the second end of the fourth resistor 304 is grounded;

[0065] The first end (source end) of the second P-type field effect transistor 102 is connected to the device voltage end VDD of the reference voltage source integrated device 1; the second end (drain end) of the second P-type field effect transistor 102 is connected to the first end (source end) of the fourth P-type field effect transistor 104; the second end (drain end) of the fourth P-type field effect transistor 104 is connected to the first end (drain end) of the second N-type field effect transistor 106; the second end (source end) of the second N-type field effect transistor 106 is connected to the collector of the fourth triode 204; the emitter of the fourth triode 204 is connected to the first end of the second resistor 302, and the second end of the second resistor 302 is connected to the collector of the second triode 202; the emitter of the second triode 202 is connected to the first end of the fourth resistor 304;

[0066] The control end (gate end) of the first P-type field effect transistor 101 is connected to the control end (gate end) of the second P-type field effect transistor 102; the control end (gate end) of the third P-type field effect transistor 103 is connected to the control end (gate end) of the fourth P-type field effect transistor 104; the control end of the first P-type field effect transistor 101 is connected to the second end (drain end) of the third P-type field effect transistor; the control end (gate end) of the third P-type field effect transistor 103 is connected to the first end (drain end) of the first N-type field effect transistor 105; the first end (drain end) of the second N-type field effect transistor 106 is connected to the control end (gate end) of the second N-type field effect transistor 106; the base of the third triode 203 is connected to the base of the fourth triode 204; the base of the first triode 201 is connected to the collector of the second triode 202, and the base of the second triode 202 is connected to the collector of the first triode 201.

[0067] Figure 1 , 3 The structure of the reference voltage source generation module 10 in the above-mentioned embodiments can be applied to the reference voltage source integrated device 1 of each embodiment of the present disclosure.

[0068] Figure 2 The reference voltage source integrated device 1 adopts Figure 1 , 3 The structure of the reference voltage source generation module 10 in the embodiment of the present invention is different from the structure of the reference voltage source generation module 10, Figure 2 The structure of the reference voltage source generating module 10 in the embodiment can be applied to the reference voltage source integrated device 1 of each embodiment of the present disclosure.

[0069] like Figure 2 As shown, preferably, the reference voltage source generating module 10 includes a first P-type field effect transistor 101, a second P-type field effect transistor 102, a third P-type field effect transistor 103, a fourth P-type field effect transistor 104, a first N-type field effect transistor 105, a second N-type field effect transistor 106, a first triode 201, a second triode 202, a third triode 203, a fourth triode 204, a first resistor 301, a second resistor 302, a third resistor 303 and a fourth resistor 304;

[0070] The first end (source end) of the first P-type field effect transistor 101 is connected to the device voltage end VDD of the reference voltage source integrated device 1; the second end (drain end) of the first P-type field effect transistor 101 is connected to the first end (source end) of the third P-type field effect transistor 103; the second end (drain end) of the third P-type field effect transistor 103 is connected to the first end of the first resistor 301; the second end of the first resistor 301 is connected to the first end (drain end) of the first N-type field effect transistor 105; the second end (source end) of the first N-type field effect transistor 105 is connected to the collector of the third triode 203; the emitter of the third triode 203 is connected to the collector of the first triode 201; the emitter of the first triode 201 is connected to the first end of the third resistor 303, and the second end of the third resistor 303 is connected to the first end of the fourth resistor 304; the second end of the fourth resistor 304 is grounded;

[0071] The first end (source end) of the second P-type field effect transistor 102 is connected to the device voltage end VDD of the reference voltage source integrated device 1; the second end (drain end) of the second P-type field effect transistor 102 is connected to the first end (source end) of the fourth P-type field effect transistor 104; the second end (drain end) of the fourth P-type field effect transistor 104 is connected to the first end (drain end) of the second N-type field effect transistor 106; the second end (source end) of the second N-type field effect transistor 106 is connected to the collector of the fourth triode 204; the emitter of the fourth triode 204 is connected to the first end of the second resistor 302, and the second end of the second resistor 302 is connected to the collector of the second triode 202; the emitter of the second triode 202 is connected to the first end of the fourth resistor 304;

[0072] The control end (gate end) of the first P-type field effect transistor 101 is connected to the control end (gate end) of the second P-type field effect transistor 102; the control end (gate end) of the third P-type field effect transistor 103 is connected to the control end (gate end) of the fourth P-type field effect transistor 104; the control end of the first P-type field effect transistor 101 is connected to the second end (drain end) of the third P-type field effect transistor; the control end (gate end) of the third P-type field effect transistor 103 is connected to the first end (drain end) of the first N-type field effect transistor 105; the first end (drain end) of the second N-type field effect transistor 106 is connected to the control end (gate end) of the second N-type field effect transistor 106; the base of the third triode 203 is connected to the base of the fourth triode 204; the base of the first triode 201 is connected to the collector of the first triode 201, and the base of the second triode 202 is connected to the collector of the second triode 202.

[0073] like Figure 2 , 3 As shown in the above, the present disclosure provides a more preferred reference voltage source integrated device 1. The reference voltage source integrated device 1 further includes a voltage suppression ratio adjustment module 30 on the basis of the above-mentioned various embodiments. The voltage suppression ratio adjustment module 30 includes an eighth resistor 308, a ninth resistor 309 and an amplifier 401. A predetermined voltage VREF is input to the positive input terminal of the amplifier 401, the second end of the ninth resistor 309 is grounded, the first end of the ninth resistor 309 is connected to the second end of the eighth resistor 308, the reverse input terminal of the amplifier 401 is connected to the first end of the ninth resistor 309, the first end of the eighth resistor 308 is connected to the output terminal of the amplifier 401, and the voltage at the output terminal of the amplifier 401 is used as the device voltage AVDD of the reference voltage source integrated device 1.

[0074] For the reference voltage source integrated device 1 of each of the above embodiments, on the basis of each of the above embodiments, the voltage adjustment submodule further includes an RC filtering module, and the RC filtering module performs RC filtering on the predetermined voltage VREF. Figure 4 The RC filter module in the voltage adjustment submodule is shown.

[0075] For the reference voltage source integrated device 1 of each of the above embodiments, on the basis of each of the above embodiments, the voltage adjustment submodule further includes an LC filtering module, and the LC filtering module performs LC filtering on the predetermined voltage VREF. Figure 5 The LC filter module in the voltage adjustment submodule is shown.

[0076] Those skilled in the art should understand that in each of the above-mentioned implementation modes, the voltage adjustment submodule may include an RC filter module or an LC filter module, or may include an RC filter module and an LC filter module.

[0077] For the reference voltage source integrated device 1 of each of the above embodiments, alternative preferred embodiments are as follows: Figure 7 As shown, the voltage adjustment submodule of the reference voltage output module 20 includes a sixth resistor 306, a seventh resistor 307, a first buffer 107, an eleventh resistor 311, a twelfth resistor 312 and a second buffer 108;

[0078] The second end of the seventh resistor 307 is grounded, the first end of the seventh resistor 307 is connected to the output end of the initial reference voltage VREF1 of the reference voltage source generating module 10, the second end of the sixth resistor 306 is connected to the first end of the seventh resistor 307, the first end of the sixth resistor 306 is connected to the second end (source end) of the first buffer 107, and the first end (drain end) of the first buffer 107 is connected to the device voltage end VDD of the reference voltage source integrated device 1 via the fifth resistor 305;

[0079] The second end of the twelfth resistor 312 is grounded, the first end of the twelfth resistor 312 is connected to the second end of the eleventh resistor 311, the first end of the eleventh resistor 311 is connected to the second end (source end) of the second buffer 108, the first end (drain end) of the second buffer 108 is connected to the device voltage end VDD of the reference voltage source integrated device 1 via the tenth resistor 310, and the control end (gate end) of the second buffer 108 is connected to the control end (gate end) of the first buffer 107; the control end (gate end) of the first buffer 107 and the control end (gate end) of the second buffer 108 are provided with control voltage by the reference voltage source generation module 10;

[0080] The first terminal of the eleventh resistor 311 outputs a predetermined voltage VREF.

[0081] The control terminal (gate terminal) of the first buffer 107 and the control terminal (gate terminal) of the second buffer 108 may be connected to the drain terminal of the fourth P-type field effect transistor 104 .

[0082] For the reference voltage source integrated device 1 of the above embodiment, the first buffer 107 and the second buffer 108 may both be N-type field effect transistors.

[0083] For the reference voltage source integrated device 1 of the above embodiment, the resistance value of the sixth resistor 306 is the same as the resistance value of the eleventh resistor 311 , and the resistance value of the seventh resistor 307 is the same as the resistance value of the twelfth resistor 312 .

[0084] For the reference voltage source integrated device 1 of the above embodiment, the voltage adjustment submodule further includes a filter capacitor 501 , and the filter capacitor 501 performs filtering processing on the predetermined voltage VREF.

[0085] For the reference voltage source integrated device 1 of each of the above-mentioned embodiments, as an alternative preferred embodiment, the voltage suppression ratio adjustment module 30 includes a charge pump 701, and the voltage taken from the reference voltage source generation module 10 is boosted by the charge pump 701, and the voltage after the boosting by the charge pump 701 is used as the device voltage AVDD of the reference voltage source integrated device 1.

[0086] like Figure 8 As shown, the voltage taken from the reference voltage source generation module 10 is preferably taken from the collector of the second triode 201. According to an alternative embodiment of the present disclosure, as Fig.10 As shown, the voltage taken from the reference voltage source generation module 10 is preferably taken from the base of the third transistor 203. The charge pump 701 can be a charge pump in the prior art.

[0087] For the reference voltage source integrated device 1 of each of the above-mentioned embodiments, as an alternative preferred embodiment, the voltage suppression ratio adjustment module 30 includes a Boost circuit 801, and the voltage taken from the reference voltage source generation module 10 is boosted by the Boost circuit 801, and the voltage after the Boost circuit 801 is boosted serves as the device voltage AVDD of the reference voltage source integrated device 1.

[0088] like Fig. 9 As shown, the voltage taken from the reference voltage source generation module 10 is preferably taken from the collector of the second triode 201. According to an alternative embodiment of the present disclosure, as Fig.11 As shown, the voltage taken from the reference voltage source generation module 10 is preferably taken from the base of the third transistor 203 .

[0089] The Boost circuit 801 may be a Boost circuit in the prior art.

[0090] The reference voltage source integrated device 1 disclosed in the present invention has the characteristics of low offset and high power supply rejection ratio through the structural design of each of the above-mentioned embodiments.

[0091] In the description of this specification, the description with reference to the terms "one embodiment / method", "some embodiments / methods", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment / method or example are included in at least one embodiment / method or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment / method or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments / methods or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments / methods or examples described in this specification and the features of the different embodiments / methods or examples, unless they are contradictory.

[0092] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0093] Those skilled in the art should understand that the above embodiments are only for the purpose of clearly illustrating the present disclosure, and are not intended to limit the scope of the present disclosure. For those skilled in the art, other changes or modifications may be made based on the above disclosure, and these changes or modifications are still within the scope of the present disclosure.

Claims

1. A reference voltage source integrated device, characterized in that: include: A reference voltage source generating module, wherein the reference voltage source generating module generates an initial reference voltage; as well as a reference voltage output module, the reference voltage output module comprising a voltage adjustment submodule, the voltage adjustment submodule raising the initial reference voltage to a predetermined voltage for output, The voltage adjustment submodule of the reference voltage output module includes a sixth resistor and a seventh resistor, the second end of the seventh resistor is grounded, the first end of the seventh resistor is connected to the initial reference voltage output end of the reference voltage source generation module, the second end of the sixth resistor is connected to the first end of the seventh resistor, the first end of the sixth resistor outputs the predetermined voltage, and the voltage adjustment submodule also includes an RC filter module or an LC filter module, the RC filter module or the LC filter module performs RC filtering or LC filtering on the predetermined voltage, The reference voltage source generation module includes a first P-type field effect transistor, a second P-type field effect transistor, a third P-type field effect transistor, a fourth P-type field effect transistor, a first N-type field effect transistor, a second N-type field effect transistor, a first transistor, a second transistor, a third transistor, a fourth transistor, a first resistor, a second resistor, a third resistor and a fourth resistor; the first end of the first P-type field effect transistor is connected to the device voltage terminal VDD of the reference voltage source integrated device; the second end of the first P-type field effect transistor is connected to the first end of the third P-type field effect transistor; the second end of the third P-type field effect transistor is connected to the first end of the first resistor The first resistor is connected to the first end of the first N-type field effect transistor; the second end of the first N-type field effect transistor is connected to the collector of the third transistor; the emitter of the third transistor is connected to the collector of the first transistor; the emitter of the first transistor is connected to the first end of the third resistor, the second end of the third resistor is connected to the first end of the fourth resistor; the second end of the fourth resistor is grounded; the first end of the second P-type field effect transistor is connected to the device voltage terminal VDD of the reference voltage source integrated device; the second end of the second P-type field effect transistor is connected to the fourth P-type field effect transistor The first end of the fourth P-type field effect tube is connected; the second end of the fourth P-type field effect tube is connected to the first end of the second N-type field effect tube; the second end of the second N-type field effect tube is connected to the collector of the fourth triode; the emitter of the fourth triode is connected to the first end of the second resistor, and the second end of the second resistor is connected to the collector of the second triode; the emitter of the second triode is connected to the first end of the fourth resistor; the control end of the first P-type field effect tube is connected to the control end of the second P-type field effect tube; the control end of the third P-type field effect tube is connected to the control end of the fourth P-type field effect tube The control end of the first P-type field effect transistor is connected to the second end of the third P-type field effect transistor; the control end of the third P-type field effect transistor is connected to the first end of the first N-type field effect transistor; the first end of the second N-type field effect transistor is connected to the control end of the second N-type field effect transistor; the control end of the first N-type field effect transistor is connected to the control end of the second N-type field effect transistor; the base of the third transistor is connected to the base of the fourth transistor; the base of the first transistor is connected to the collector of the second transistor, and the base of the second transistor is connected to the collector of the first transistor.

2. A reference voltage source integrated device, characterized in that: include: A reference voltage source generating module, wherein the reference voltage source generating module generates an initial reference voltage; as well as a reference voltage output module, the reference voltage output module comprising a voltage adjustment submodule, the voltage adjustment submodule raising the initial reference voltage to a predetermined voltage for output, The voltage adjustment submodule of the reference voltage output module includes a sixth resistor and a seventh resistor, the second end of the seventh resistor is grounded, the first end of the seventh resistor is connected to the initial reference voltage output end of the reference voltage source generation module, the second end of the sixth resistor is connected to the first end of the seventh resistor, the first end of the sixth resistor outputs the predetermined voltage, and the voltage adjustment submodule also includes an RC filter module or an LC filter module, the RC filter module or the LC filter module performs RC filtering or LC filtering on the predetermined voltage, The reference voltage source generation module includes a first P-type field effect transistor, a second P-type field effect transistor, a third P-type field effect transistor, a fourth P-type field effect transistor, a first N-type field effect transistor, a second N-type field effect transistor, a first triode, a second triode, a third triode, a fourth triode, a first resistor, a second resistor, a third resistor and a fourth resistor; The first end of the first P-type field effect transistor is connected to the device voltage end of the reference voltage source integrated device; the second end of the first P-type field effect transistor is connected to the first end of the third P-type field effect transistor; the second end of the third P-type field effect transistor is connected to the first end of the first resistor; the second end of the first resistor is connected to the first end of the first N-type field effect transistor; the second end of the first N-type field effect transistor is connected to the collector of the third triode; the emitter of the third triode is connected to the collector of the first triode; the emitter of the first triode is connected to the first end of the third resistor, the second end of the third resistor is connected to the first end of the fourth resistor; the second end of the fourth resistor is grounded; The first end of the second P-type field effect transistor is connected to the device voltage end of the reference voltage source integrated device; the second end of the second P-type field effect transistor is connected to the first end of the fourth P-type field effect transistor; the second end of the fourth P-type field effect transistor is connected to the first end of the second N-type field effect transistor; the second end of the second N-type field effect transistor is connected to the collector of the fourth triode; the emitter of the fourth triode is connected to the first end of the second resistor, and the second end of the second resistor is connected to the collector of the second triode; the emitter of the second triode is connected to the first end of the fourth resistor; The control end of the first P-type field effect transistor is connected to the control end of the second P-type field effect transistor; the control end of the third P-type field effect transistor is connected to the control end of the fourth P-type field effect transistor; the control end of the first P-type field effect transistor is connected to the second end of the third P-type field effect transistor; the control end of the third P-type field effect transistor is connected to the first end of the first N-type field effect transistor; the first end of the second N-type field effect transistor is connected to the control end of the second N-type field effect transistor; the control end of the first N-type field effect transistor is connected to the control end of the second N-type field effect transistor; the base of the third transistor is connected to the base of the fourth transistor; the base of the first transistor is connected to the collector of the first transistor, and the base of the second transistor is connected to the collector of the second transistor.

3. The reference voltage source integrated device according to claim 1 or 2, characterized in that: The voltage adjustment submodule of the reference voltage output module includes a first buffer, the second end of the first buffer is connected to the first end of the sixth resistor, the first end of the first buffer is connected to the device voltage end of the reference voltage source integrated device; the control end of the first buffer is connected to the second end of the fourth P-type field effect transistor.

4. The reference voltage source integrated device according to claim 3, characterized in that: The first buffer is an N-type field effect transistor.

5. The reference voltage source integrated device according to claim 3, characterized in that: A fifth resistor is connected between the first terminal of the first buffer and the device voltage terminal of the reference voltage source integrated device.

6. The reference voltage source integrated device according to claim 1 or 2, characterized in that: It also includes a voltage suppression ratio adjustment module, which includes an eighth resistor, a ninth resistor and an amplifier, the predetermined voltage is input to the positive phase input terminal of the amplifier, the second end of the ninth resistor is grounded, the first end of the ninth resistor is connected to the second end of the eighth resistor, the reverse input terminal of the amplifier is connected to the first end of the ninth resistor, the first end of the eighth resistor is connected to the output terminal of the amplifier, and the voltage at the output terminal of the amplifier is used as the device voltage of the reference voltage source integrated device.

7. The reference voltage source integrated device according to claim 1, characterized in that: The voltage adjustment submodule of the reference voltage output module further includes a first buffer, an eleventh resistor, a twelfth resistor and a second buffer; The predetermined voltage outputted from the first end of the sixth resistor is connected to the second end of the first buffer, and the first end of the first buffer is connected to the device voltage terminal VDD of the reference voltage source integrated device via the fifth resistor; The second end of the twelfth resistor is grounded, the first end of the twelfth resistor is connected to the second end of the eleventh resistor, the first end of the eleventh resistor is connected to the second end of the second buffer, the first end of the second buffer is connected to the device voltage terminal VDD of the reference voltage source integrated device via the tenth resistor, and the control end of the second buffer is connected to the control end of the first buffer; the control end of the first buffer and the control end of the second buffer are provided with a control voltage by the reference voltage source generation module; The first end of the eleventh resistor outputs the predetermined voltage.

8. The reference voltage source integrated device according to claim 7, characterized in that: The first buffer and the second buffer are both N-type field effect transistors.

9. The reference voltage source integrated device according to claim 7, characterized in that: The resistance value of the sixth resistor is the same as the resistance value of the eleventh resistor, and the resistance value of the seventh resistor is the same as the resistance value of the twelfth resistor.

10. The reference voltage source integrated device according to claim 7, characterized in that: The voltage adjustment submodule further includes a filter capacitor, and the filter capacitor performs filtering processing on the predetermined voltage.

11. The reference voltage source integrated device according to claim 1 or 2, characterized in that: It also includes a voltage suppression ratio adjustment module, which includes a charge pump. The voltage taken from the reference voltage source generation module is boosted by the charge pump, and the voltage after the charge pump boosts is used as the device voltage of the reference voltage source integrated device.

12. The reference voltage source integrated device according to claim 1 or 2, characterized in that: It also includes a voltage suppression ratio adjustment module, which includes a Boost circuit. The voltage taken from the reference voltage source generation module is boosted by the Boost circuit, and the voltage after the Boost circuit is boosted is used as the device voltage of the reference voltage source integrated device.

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