Integrated Circuit Device, Operating Method Thereof, and Bias Generator Circuit

Abstract

Provided is an integrated circuit device. The integrated circuit device includes: a functional device including a selection device; and a bias generator circuit coupled to the selection device and configured to detect a leakage current of the functional device and generate a bias voltage based on the detected leakage current. The bias voltage is provided to the selection device to control the selection device.

Description

Technical Field

[0001] Embodiments of the present invention relate to an integrated circuit device, an operation method thereof, and a bias generator circuit. Background Art

[0002] Memory devices are used to store information in semiconductor devices and systems. A non-volatile memory device can store data even after the power supply is cut off. Resistive memory devices include magnetic random access memory (MRAM), resistive random access memory (RRAM), and phase-change memory (PCM). Such memory devices are subject to process-voltage-temperature (PVT) variations. To compensate for PVT variations, a constant negative bias is sometimes applied to access devices in various semiconductor memory devices. Summary of the Invention

[0003] Embodiments of the present invention provide an integrated circuit device, including: a functional device including a selection device; and a bias generator circuit coupled to the selection device and configured to detect a leakage current of the functional device and generate a bias voltage based on the detected leakage current; wherein the bias voltage is provided to the selection device to control the selection device.

[0004] Another embodiment of the present invention provides a bias generator circuit, including: a current comparator configured to compare a leakage current of a functional device with a reference current to generate a comparison result; and a bias generator coupled to the current comparator and configured to output a bias voltage to a selection device of the functional device; wherein the bias voltage is output based on the comparison result.

[0005] Another embodiment of the present invention provides a method of operating an integrated circuit device, including: providing a reference current; receiving a leakage current of a functional device during an off state; comparing the leakage current with the reference current; generating a negative bias voltage in response to the comparing of the leakage current with the reference current; and if the leakage current is greater than the reference current, applying the negative bias voltage to a selection device of the functional device to control the selection device. Brief Description of the Drawings

[0006] Aspects of the present disclosure are best understood when the following detailed description is read in conjunction with the accompanying drawings. Note that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figure 1 is a block diagram showing a memory device according to some embodiments.

[0008] Figure 2 is showing according to some embodiments Figure 1 a structural diagram of the memory device shown.

[0009] Figure 3 is showing according to some embodiments Figure 2 a structural diagram of the memory device shown.

[0010] Figure 4 is showing according to some embodiments Figure 2 a structural diagram of the memory device shown.

[0011] Figure 5 is showing according to some embodiments Figure 2 a structural diagram of the memory device shown.

[0012] Figure 6 is showing according to some embodiments Figure 1 and Figure 2 a circuit diagram of the negative bias generator circuit shown.

[0013] Figure 7A is showing according to some embodiments Figure 1 and Figure 2 a circuit diagram of the negative bias generator circuit shown.

[0014] Figure 7B is a Figure 7A timing diagram of the negative bias generator circuit shown according to some embodiments.

[0015] Figure 8 is showing according to some embodiments Figure 3 a structural diagram of the memory device shown.

[0016] Figure 9 is showing according to some embodiments Figure 8 a structural diagram of the memory device shown.

[0017] Figure 10 is showing according to some embodiments Figure 4 a structural diagram of the memory device shown.

[0018] Figure 11 is showing according to some embodiments Figure 3 a structural diagram of the memory device shown.

[0019] Figure 12 is a structural diagram showing a memory device according to some embodiments Figure 1 as shown.

[0020] Figure 13 is a flowchart showing an example of a method for operating a memory device according to some embodiments. DETAILED DESCRIPTION

[0021] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature are not in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in various instances. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0022] In addition, for ease of illustration, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature shown in the figures to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0023] In the present disclosure, an integrated circuit device (e.g., a memory device) having a self-activating negative bias generator circuit is provided. The self-activating negative bias generator circuit detects the leakage current (i.e., the off-state current) of the memory device and selectively turns on as needed in response to the detected leakage. Thus, additional power consumption at low-leakage corners is avoided. On the other hand, the lower leakage current results in a higher current on / off ratio, thereby improving the access performance of the memory device.

[0024] Figure 1 is a block diagram showing an integrated circuit device 100 according to some embodiments. Among other things, the integrated circuit device 100 includes a negative bias generator circuit 103 and a functional device 105. The leakage current (ILEAK ) 102 is received by the negative bias generator circuit 103. The negative bias generator circuit 103 generates a negative bias level voltage (VNEG) 108 based on the leakage current 102. Specifically, when the leakage current 102 is lower than a reference current (i.e., low leakage associated with the functional device 105), VNEG 108 is zero; when the leakage current 102 is equal to or higher than the reference current (i.e., higher leakage), VNEG 108 is a negative voltage. Thus, the self - activating negative bias generator circuit 103 detects the leakage current 102 of the functional device 105 and selectively turns on in response to the leakage associated with the functional device 105.

[0025] In some examples, the integrated circuit device 100 is a memory device that may include a plurality of memory cells (such as MRAM cells, RRAM cells, dynamic random access memory (DRAM) cells, etc.) arranged in an array formed by rows and columns. Word lines (WL) connect the memory cells in a given row, while bit lines (BL) (source lines (SL) in some examples) connect the memory cells in a given column. For example, a word line driver may be configured to output a word line selection signal to a selection device such as an access transistor to activate a row of memory cells.

[0026] For MRAM and other resistive memory devices, the word line swing is typically from ground to a positive bias. If a negative bias is used inappropriately due to PVT variations, this may cause the memory device to not turn off well. This, in turn, may cause the word line swing to affect access performance. Some conventional implementations may use a negative bias generator that operates continuously after power - on. Thus, such a conventional negative bias generator may consume additional power.

[0027] In some of the disclosed examples, if necessary due to the detected leakage, the functional device selectively receives the negative bias signal VNEG 108. Due to its self - activation and selectivity, VNEG 108 can be used as the word line on / off level for the memory and / or the substrate bias of the n - type selective transistor of the memory cell, which will be discussed below with reference to Figures 4 to 5 which will be discussed. Other uses of VNEG 108 are within the scope of the present disclosure. The detailed structures of the negative bias generator circuit 103 and the functional device 105 will be discussed below with reference to Figure 2 which will be discussed.

[0028] Figure 2is a structural diagram showing a memory device 101 according to some embodiments. Among other things, the negative bias generator circuit 103 includes a current comparator 107, a negative bias generator 109, a reference current 104, and a leakage current 102 received from a functional device 105. The current comparator 107 receives both the leakage current 102 and the reference current 104. The reference current 104 is a threshold current for determining the turn-on and turn-off of the negative bias generator 109. In some embodiments, the reference current 104 is a predetermined value. In some embodiments, the reference current 104 is configurable. The current comparator 107 compares the leakage current 102 with the reference current 104 and accordingly outputs a negative bias generator enable signal (EN) 106. The negative bias generator 109 receives EN 106 and accordingly generates VNEG 108. Thus, when the leakage current 102 is lower than the reference current 104, VNEG 108 is zero; when the leakage current 102 is equal to or higher than the reference current 104, VNEG 108 is a negative voltage. In some embodiments, the negative bias generator 109 can be on-chip. In some embodiments, the negative bias generator 109 can be an off-chip power supply.

[0029] On the other hand, among other things, Figure 2 the illustrated example functional device 105 includes a memory cell 111, a word line power supply 113, a word line driver 115, a bit line driver 121, and a source line driver 123. Among other things, the memory cell further includes a bulk device 117 and a selection device 119. In some embodiments, the bulk device can be a magnetoresistive material for MRAM. In some embodiments, the bulk device can be a resistive material for RRAM. In some embodiments, the bulk device can be a phase change material for PCM. In some embodiments, the bulk device can be a capacitor for DRAM.

[0030] The memory cell 111 is an example of one of a plurality of memory cells forming a memory cell array. For simplicity, Figure 2 only the memory cell 111 is shown; a typical memory cell array will include more memory cells. The plurality of memory cells can be arranged in rows and / or columns within the memory cell array. The memory cells within a row of the memory cell array are operatively coupled to a word line (WL), while the memory cells within a column of the memory cell array are operatively coupled to a bit line (BL) and a corresponding source line (SL). In some embodiments, each column corresponds to one source line. In some embodiments, multiple columns can share a common source line (CSL). The plurality of memory cells are respectively associated with addresses defined by the intersections of word lines (WLs) and bit lines (BLs).

[0031] As described above, the memory cell 111 includes a memory device 117 and a selection device 119. The word line power supply 113 supplies a voltage to the word line driver 115. The word line driver 115 generates a word line signal (WL) based on a word line address. The word line signal (WL) is supplied to the selection device 119. The selection device 119 is selectively turned on or off based on the word line signal (WL). In some embodiments, the selection device 119 is an n-type selection device. In some instances, the selection device 119 is an n-type field-effect transistor (FET). When the word line signal (WL) is at a logic high (i.e., “1”), the selection device 119 is turned on, and when the word line signal (WL) is at a logic low (i.e., “0”), the selection device 119 is turned off. In some embodiments, the selection device 119 is a p-type selection device. In some instances, the selection device 119 is a p-type FET. When the word line signal (WL) is at a logic low, the selection device 119 is turned on, and when the word line signal (WL) is at a logic high, the selection device 119 is turned off.

[0032] The memory device 117 is coupled to a bit line connected to the bit line driver 121. The selection device 119 is coupled to a source line connected to the source line driver 123. By activating the word line, the selection device 119 is turned on, enabling the source line to be coupled to the memory device 117. Thus, when the word line is activated, the memory device 117 is coupled between its corresponding bit line and source line. The memory device 117 has a resistance state that can be switched between a low resistance state and a high resistance state. The resistance state indicates a data value (e.g., “1” or “0”) stored in the memory device 117.

[0033] By selectively applying signals to the word lines, bit lines, and source lines of the memory cell array, formation, set, reset, and read operations can be performed on the selected memory cells (e.g., memory cell 111) among the plurality of memory cells. For example, in a write operation, a write current flows through the memory device 117, causing the memory device 117 to switch from a low resistance state to a high resistance state (and vice versa), whereby a data bit is written and stored in the memory cell 111. On the other hand, in a read operation, a read current flows through the memory device 117, and the read current corresponds to the high resistance state or low resistance state of the memory device 117. A sense amplifier (not shown) can compare the read current with a reference current to sense the data bit stored in the memory cell 111. The sense amplifier amplifies the level of the sensed data bit and outputs the amplified data bit, such that the data bit stored in the memory cell 111 can be read from the memory cell 111.

[0034] Figure 3is a structural diagram showing a memory device 101 according to some embodiments Figure 2 as shown in the memory device 101 Figure 3 All components of the memory device 101 shown in Figure 2 are the same as those shown in. In the example memory device 101, the selection device 119 is an n-type selection device, and VNEG 108 is used as the word line turn-off level of the memory. Specifically, VNEG 108 is provided to the word line driver 115

[0035] As described above, when the leakage current 102 is lower than the reference current 104, VNEG 108 is zero; when the leakage current 102 is equal to or higher than the reference current 104, VNEG 108 is a negative voltage. In the off state of the memory cell 111, VNEG 108 is the word line signal (WL). Therefore, in the off state of the memory cell 111, when the leakage current 102 is low, the word line signal (WL) is zero, and when the leakage current 102 is high, the word line signal (WL) is a negative voltage. The negative bias generator 109 is selectively turned on as needed in response to the leakage current 102. The negative voltage can well turn off the memory cell 111. At the same time, the additional power consumption at the low leakage corner is avoided. The lower leakage current results in a higher current on / off ratio, thus improving the access performance of the memory device

[0036] Figure 4 is a structural diagram showing a memory device 101 according to some embodiments Figure 2 as shown in the memory device 101 Figure 4 All components of the memory device 101 shown in Figure 2 are the same as those shown in. In the example memory device 101, VNEG 108 is used as the substrate bias of the n-type selective transistor. Specifically, VNEG108 is provided as the substrate bias to the n-type selection device

[0037] As described above, when the leakage current 102 is lower than the reference current 104, VNEG 108 is zero; when the leakage current 102 is equal to or higher than the reference current 104, VNEG 108 is a negative voltage. In the off state of the memory cell 111, the word line signal (WL) is at logic low, and the negative voltage as the substrate bias of the n-type selection device can firmly turn off the memory cell. The negative bias generator 109 is selectively turned on as needed in response to the leakage current 102. At the same time, the additional power consumption at the low leakage corner is avoided. The lower leakage current results in a higher current on / off ratio, thus improving the access performance of the memory device

[0038] Figure 5 is a structural diagram showing a memory device 101 according to some embodiments Figure 2 as shown in the memory device 101 Figure 5All components of the memory device 101 shown in Figure 2 are the same as the components shown in Figure 2 . In the example memory device 101, VNEG 108 is used as both the word line off level of the memory and the substrate bias of the n-type select transistor. Specifically, VNEG 108 is provided as the substrate bias to both the word line driver 115 and the n-type select device.

[0039] As described above, when the leakage current 102 is lower than the reference current 104, VNEG 108 is zero; when the leakage current 102 is equal to or higher than the reference current 104, VNEG 108 is a negative voltage. In the off state of the memory cell 111, VNEG 108 is the word line signal (WL). Therefore, in the off state of the memory cell 111, when the leakage current 102 is low, the word line signal (WL) is zero, and when the leakage current 102 is high, the word line signal (WL) is a negative voltage. The negative bias generator 109 is selectively turned on as needed in response to the leakage current 102. The negative voltage can well turn off the memory cell 111. On the other hand, in the off state of the memory cell 111, the word line signal (WL) is at logic low, and the negative voltage as the substrate bias of the n-type select device can firmly turn off the memory cell. Again, the negative bias generator 109 is selectively turned on as needed in response to the leakage current 102. At the same time, the additional power consumption at the low leakage corner is avoided. The lower leakage current results in a higher current on / off ratio, thus improving the access performance of the memory device.

[0040] Figure 6 is a circuit diagram showing the Figure 1 and Figure 2 negative bias generator circuit 103 shown in Figure 2 . As described above, the current comparator 107 receives both the leakage current 102 and the reference current 104, and compares the leakage current 102 with the reference current 104 to output the negative bias generator enable signal (EN) 106 accordingly. The negative bias generator 109 receives EN 106 and generates VNEG 108 accordingly.

[0041] Specifically, among other things, the current comparator 107 includes a reference current source 131, a p-channel metal oxide semiconductor (PMOS) transistor 133, a detector control 135, an n-channel metal oxide semiconductor (NMOS) transistor 137, and an odd number (e.g., M and M = 2M'+1, where M' is zero or a positive integer) of inverters 143. The reference current source 131 is coupled to the gate terminal of the PMOS transistor 133 and can provide a reference current source voltage V_RCS to the gate terminal of the PMOS transistor 133. When V_RCS is at the voltage supply level VDD, the PMOS transistor 133 is turned off; when V_RCS is at an analog voltage level or lower than VDD by more than the threshold voltage, the PMOS transistor 133 is turned on. The source terminal of the PMOS transistor 133 is coupled to the voltage supply VDD, and the drain terminal of the PMOS transistor 133 is coupled to node 141. When the PMOS transistor 133 is turned on, the reference current 104 flows through the PMOS transistor 133 to node 141.

[0042] The detector control 135 is coupled to the gate terminal of the NMOS transistor 137 and can provide a detection enable signal DET_EN to the gate terminal of the NMOS transistor 137. When DET_EN is at a logic high, the NMOS transistor 137 is turned on; when DET_EN is at a logic low, the NMOS transistor 137 is turned off. The drain terminal of the NMOS transistor 137 is coupled to node 141, and the source terminal of the NMOS transistor 137 is coupled to Figure 2 the leakage current source 139 of the functional device 105 shown in. It should be noted that the leakage current source can have multiple (e.g., N and N > 1) sources. When the NMOS transistor 137 is turned on, the leakage current 102 flows from node 141 through the NMOS transistor 137.

[0043] When the leakage current 102 is lower than the reference current 104, node 141 is at a logic high. EN 106 at node 145 is the complement of the signal at node 141 after passing through the odd number of inverters 143. Therefore, EN 106 is at a logic low. When the leakage current 102 is equal to or higher than the reference current 104, node 141 is at a logic low. Therefore, EN 106 is at a logic high.

[0044] Among other things, the negative bias generator 109 includes a VNEG level detector 153, a VNEG charge pump 155, an inverter 147, and an NMOS transistor 149. EN 106 is provided to the VNEG level detector 153. The VNEG level detector 153 generates a VNEG charge pump enable signal PUMP_EN based on EN 106. PUMP_EN is provided to the VNEG charge pump 155. The VNEG charge pump 155 outputs VNEG 108 at node 151 based on PUMP_EN. VNEG 108 is provided to another input of the VNEG level detector 153. On the other hand, EN 106 is also provided to the inverter 147, and the inverter 147 outputs an inverted signal (bar signal) of EN 106 (i.e., ENB). ENB is provided to the gate terminal of the NMOS transistor 149. The drain terminal of the NMOS transistor 149 is coupled to node 151, and the source terminal of the NMOS transistor 149 is coupled to ground.

[0045] As described above, when the leakage current 102 is lower than the reference current 104, EN 106 is at logic low. Therefore, the VNEG level detector 153 is deactivated, and PUMP_EN is at logic low. Therefore, the VNEG charge pump 155 is also deactivated. On the other hand, ENB is at logic high. Therefore, the NMOS transistor 149 is turned on. Therefore, VNEG 108 at node 151 is pulled down to ground.

[0046] As described above, when the leakage current 102 is equal to or higher than the reference current 104, EN 106 is at logic high. ENB is at logic low. Therefore, the NMOS transistor 149 is turned off, and VNEG 108 at node 151 is not pulled down to ground. On the other hand, the VNEG level detector 153 is activated, and when VNEG 108 is shallower than the target regulated voltage level, PUMP_EN is at logic high. Therefore, the VNEG charge pump 155 is also activated. Therefore, the VNEG charge pump 155 outputs VNEG108 as a negative voltage. In one embodiment, the VNEG charge pump 155 may include a cascade of diode / capacitor cells having a clock pulse input, and the capacitors are charged through the clock pulse input, and the output is pulled down to a negative voltage. Since VNEG 108 is provided as negative feedback to another input of the VNEG level detector 153, the negative bias generator 109 is regulated. In other words, the path from node 151 to another input of the VNEG level detector 153 is the regulation loop 152.

[0047] Figure 7A is a circuit diagram showing the Figure 1 and Figure 2 negative bias generator circuit 103 shown according to some embodiments.Figure 7B According to some embodiments Figure 7A The timing diagram of the negative bias generator circuit 103 shown above. As described above, the current comparator 107 receives both the leakage current 102 and the reference current 104, and compares the leakage current 102 with the reference current 104 to output a negative bias generator enable signal (EN) 106 accordingly. The negative bias generator 109 receives EN 106 and generates VNEG 108 accordingly.

[0048] Except for the following three differences Figure 7A the negative bias generator circuit 103 in Figure 6 is the same as the negative bias generator circuit 103 in Figure 6 In contrast to Figure 6 the detection enable signal DET_EN includes two clock signals: DET_EN1 and DET_EN2. In addition, Figure 7A the detector control 135 shown in

[0049] The clock generator 136 generates DET_EN1 and DET_EN2. DET_EN1 is provided to the gate terminal of the NMOS transistor 137 to control the on and off of the NMOS transistor 137. Referring to Figure 7A DET_EN1 is a periodic pulse signal with a period T CLOCK The pulse width is T H1 . T CLOCK can be calculated by the following equation:

[0050] T CLOCK = D * T H1 ,

[0051] where D is the duty cycle of DET_EN1. When DET_EN1 is at logic high (i.e., during T H1 the "active phase" 701), the NMOS transistor 137 is turned on, and the leakage current 102 is compared with the reference current 104; when DET_EN1 is at logic low (i.e., outside T H1 the "inactive phase" 703), the NMOS transistor 137 is turned off, and the leakage current 102 is not compared with the reference current 104.

[0052] Latch 157 is coupled between node 144 (i.e., the output of the odd-numbered inverters 143) and node 145 (i.e., where EN 106 is located). Specifically, the signal at node 144 and DET_EN2 are input into latch 157. When DET_EN2 is at logic low, latch 157 latches and holds the signal at node 144.

[0053] Referring Figure 7B , DET_EN2 is also a periodic pulse signal having a period T CLOCK . In other words, DET_EN2 has the same period T as DET_EN1 CLOCK . The pulse width is T H2 . T H1 is equal to or greater than T H2 . Therefore, latch 157 latches and holds the signal at node 144 no later than the transition from the active phase 701 to the inactive phase 703. In other words, latch 157 latches and holds the signal at node 144 for a sufficient length of time.

[0054] Since current comparator 107 compares leakage current 102 with reference current 104 only in the active phase 701, the direct current (DC) power consumption of current comparator 107 can be reduced. Specifically, the DC power consumption of current comparator 107 is proportional to (I LEAK / D). When the duty cycle D is very large, the DC power consumption of current comparator 107 can be significantly reduced.

[0055] Figure 8 is shown according to some embodiments Figure 3Structural diagram of the memory device 101 shown. The same components are denoted by the same reference numerals and will not be described further. In the exemplary memory device 101, VNEG 108 serves as the word line turn-off level of the memory. The memory cell device 117 is a magnetic tunnel junction (MTJ) 117, and the selection device 119 is an NMOS transistor 119. The word line driver 115 is an inverter 115. The MTJ 117 is a type of MRAM. The MTJ 117 includes two stacked layers 117a and 117c formed of magnetic materials and separated by a thin insulating film 117b. The pinned layer 117a is a magnetic layer permanently magnetized in a fixed magnetic field alignment direction, and the free layer 117c is a magnetic layer with variable magnetization. The free layer 117c can be magnetized in one of two orientations relative to the pinned layer 117a. The two orientations are characterized by significantly different series resistances through the stacked layers 117a and 117c of the MTJ 117. Specifically, the magnetic field orientation of the free layer 117c can be aligned to be the same as the magnetic field orientation of the pinned layer 117a (referred to as the "parallel state") or opposite to the magnetic field orientation of the pinned layer 117a (referred to as the "anti-parallel state"). The parallel alignment state has a relatively low resistance, and the anti-parallel alignment state has a relatively high resistance.

[0056] As described above, when the leakage current 102 is lower than the reference current 104, VNEG 108 is zero; when the leakage current 102 is equal to or higher than the reference current 104, VNEG 108 is a negative voltage.

[0057] The WL decoder 114 generates the word line enable signal WLB input to the inverter 115. VNEG 108 is provided as a low-level bias to the inverter 115, and the voltage VWL generated by the word line power supply 113 is provided as a high-level bias to the inverter 115. The output of the inverter 115 (i.e., WL) has a swing from VNEG 108 to VWL.

[0058] When the MRAM cell 111 is in the access state, WLB is at logic low, and the output of the inverter 115 (i.e., WL) is at logic high. In other words, WL has a VWL value higher than the threshold voltage of the NMOS transistor 119, which in turn turns on the NMOS transistor 119.

[0059] When the MRAM cell 111 is in the off state, the WLB is at logic high and the output of the inverter 115 (i.e., WL) is at logic low. In other words, WL has a value of VNEG 108. Therefore, in the off state of the memory cell 111, when the leakage current 102 is low, the word line signal (WL) is zero, and when the leakage current 102 is high, the word line signal (WL) is a negative voltage. The negative bias generator 109 is selectively turned on as needed in response to the leakage current 102. The negative voltage can effectively turn off the MRAM cell 111. At the same time, the additional power consumption at the low leakage corner is avoided. The lower leakage current results in a higher current on / off ratio, thus improving the access performance of the memory device.

[0060] Figure 9 is a structural diagram showing a Figure 8 memory device 101 according to some embodiments. The same components are denoted by the same reference numerals and will not be described again. The equivalent circuit of the MTJ 117 is represented as a resistor 117 having a resistance R MTJ The leakage current I MTJ flows through the MTJ 117.

[0061] As described above, when the MRAM cell 111 is in the off state, the WLB is at logic high and the output of the inverter 115 (i.e., WL) is at logic low. In other words, WL has a value of VNEG 108. Therefore, in the off state of the memory cell 111, when the leakage current 102 is low, the word line signal (WL) is zero, and when the leakage current 102 is high, the word line signal (WL) is a negative voltage. In one example, the negative voltage is -0.2V. At high temperatures (e.g., 50 °C, 100 °C, 150 °C), the leakage current I MTJ can be reduced by 1 to 2 orders of magnitude. On the other hand, the lower leakage current I MTJ results in a higher current on / off ratio, thus improving the access performance of the memory device. In one example, the on / off ratio can be increased by 1 to 2 orders of magnitude.

[0062] Figure 10 is a structural diagram showing a Figure 4 memory device 101 according to some embodiments. The same components are denoted by the same reference numerals and will not be described again. In the exemplary memory device 101, VNEG 108 is used as the substrate bias of the n-type select transistor. Specifically, VNEG 108 is provided as the substrate bias to the n-type select device.

[0063] The memory device 117 is an MTJ 117, and the select device 119 is an NMOS transistor 119. The word line driver 115 is an inverter 115. The MTJ 117 is a type of MRAM. The MTJ 117 includes two stacked layers 117a and 117c made of magnetic materials separated by a thin insulating film 117b. The pinned layer 117a is a magnetic layer permanently magnetized in a fixed magnetic field alignment direction, and the free layer 117c is a magnetic layer with variable magnetization. The free layer 117c can be magnetized in one of two orientations relative to the pinned layer 117a. The two orientations are characterized by significantly different series resistances through the stacked layers 117a and 117c of the MTJ 117. Specifically, the magnetic field orientation of the free layer 117c can be aligned to be the same as the magnetic field orientation of the pinned layer 117a (referred to as the "parallel state") or opposite to the magnetic field orientation of the pinned layer 117a (referred to as the "antiparallel state"). The parallel alignment state has a relatively low resistance, and the antiparallel alignment state has a relatively high resistance.

[0064] As described above, when the leakage current 102 is lower than the reference current 104, VNEG 108 is zero; when the leakage current 102 is equal to or higher than the reference current 104, VNEG 108 is a negative voltage.

[0065] The WL decoder 114 generates the word line enable signal WLB input to the inverter 115. Ground is coupled to the inverter 115 as a low-level bias, and the voltage VWL generated by the word line power supply 113 is provided to the inverter 115 as a high-level bias. The output of the inverter 115 (i.e., WL) has a swing from ground to VWL.

[0066] When the MRAM cell 111 is in the access state, WLB is at logic low, and the output of the inverter 115 (i.e., WL) is at logic high. In other words, WL has a VWL value higher than the threshold voltage of the NMOS transistor 119, which in turn turns on the NMOS transistor 119.

[0067] When the MRAM cell 111 is in the off state, WLB is at logic high, and the output of the inverter 115 (i.e., WL) is at logic low. In other words, WL has a value of zero. The negative voltage as the body bias of the n-type select device can firmly turn off the memory cell. The negative bias generator 109 is selectively turned on as needed in response to the leakage current 102. At the same time, the additional power consumption at the low leakage corner is avoided. The lower leakage current results in a higher current on / off ratio, thus improving the access performance of the memory device.

[0068] Figure 11 is shown in accordance with some embodiments Figure 3Structural diagram of the shown memory device 101. The same components are denoted by the same numbers and will not be described again. In the example memory device 101, VNEG 108 serves as a word line on the memory hierarchy. The bank device 117 is an MTJ 117, and the select device 119 is a PMOS transistor 119. The word line driver 115 is an inverter 115. The MTJ 117 is a type of MRAM. The MTJ 117 includes two stacked layers 117a and 117c made of magnetic materials separated by a thin insulating film 117b. The pinned layer 117a is a magnetic layer permanently magnetized in a fixed magnetic field alignment direction, and the free layer 117c is a magnetic layer with variable magnetization. The free layer 117c can be magnetized in one of two orientations relative to the pinned layer 117a. The two orientations are characterized by significantly different series resistances across the stacked layers 117a and 117c of the MTJ 117. Specifically, the magnetic field orientation of the free layer 117c can be aligned to be the same as the magnetic field orientation of the pinned layer 117a (referred to as the "parallel state") or opposite to the magnetic field orientation of the pinned layer 117a (referred to as the "anti-parallel state"). The parallel alignment state has a relatively low resistance, and the anti-parallel alignment state has a relatively high resistance.

[0069] Different from the above, when the leakage current 102 is lower than the reference current 104, VNEG 108 is a negative voltage; when the leakage current 102 is equal to or higher than the reference current 104, VNEG 108 is zero.

[0070] The WL decoder 114 generates a word line enable signal WLB input to the inverter 115. VNEG108 is provided to the inverter 115 as a low-level bias voltage, and the voltage VWL generated by the word line power supply 113 is provided to the inverter 115 as a high-level bias voltage. The output of the inverter 115 (i.e., WL) has a swing from VNEG 108 to VWL.

[0071] When the MRAM cell 111 is in the off state, WLB is at logic low, and the output of the inverter 115 (i.e., WL) is at logic high. In other words, WL has a VWL value higher than the threshold voltage of the PMOS transistor 119, which in turn turns off the NMOS transistor 119. The body bias voltage of the PMOS transistor 119 is generated by the VBL bias generator 120.

[0072] When the MRAM cell 111 is in the access state, the WLB is at a logic high, and the output of the inverter 115 (i.e., WL) is at a logic low. In other words, WL has a value of VNEG 108. Thus, in the access state of the memory cell 111, the word line signal (WL) is zero at the fast corner (i.e., associated with high carrier mobility) and is a negative voltage at the slow corner (i.e., associated with low carrier mobility). The negative bias generator 109 is selectively turned on only at the slow corner. The negative voltage at the slow corner can turn on the MRAM cell 111 well. At the same time, the additional power consumption at the fast corner is avoided. The lower leakage current results in a higher current on / off ratio, thereby improving the access performance of the memory device.

[0073] Figure 12 FIG. 4 is a structural diagram showing a semiconductor device 101 according to some embodiments. The same components are denoted by the same reference numerals and will not be described again. In the exemplary device 101, VNEG 108 is used as the NMOS logic gate off bias level.

[0074] VNEG 108 is provided as a bias to the inverter 115. The control 114 generates a control signal INB input to the inverter 115. The output IN of the inverter 115 is provided to the gate terminal of the NMOS transistor 119. The drain terminal and the substrate terminal of the NMOS transistor 119 are both coupled to ground. The source terminal of the NMOS transistor 119 is coupled to the functional device 124.

[0075] As described above, when the leakage current 102 is lower than the reference current 104, VNEG 108 is zero; when the leakage current 102 is equal to or higher than the reference current 104, VNEG 108 is a negative voltage.

[0076] When INB is at a logic high, IN is at a logic low, and the NMOS transistor 119 is turned off. In other words, IN has a value of VNEG 108. Thus, when the leakage current 102 is low, the off bias level of the NMOS transistor 119 is zero, and when the leakage current 102 is high, the off bias level of the NMOS transistor 119 is a negative voltage. The negative bias generator 109 is selectively turned on as needed in response to the leakage current 102. The negative voltage can turn off the NMOS transistor 119 well. At the same time, the additional power consumption at the low leakage corner is avoided. It will effectively reduce the off state current of the logic device.

[0077] Figure 13 FIG. 5 is a flow diagram showing a method for operating an integrated circuit device (e.g., Figure 2Flowchart of an example of method 1300 of the example memory device 101 shown. Note that example method 1300 is also applicable to other devices or structures. At step 1302, a reference current 104 is provided. At step 1304, the leakage current 102 of the functional device 105 during the off state is received. At step 1306, the leakage current is compared with the reference current. At step 1308, in response to the comparing of the leakage current with the reference current, a negative bias voltage is generated. At step 1310, if the leakage current is equal to or greater than the reference current, the negative bias voltage is applied to the selection device 119 of the functional device 105 to control the selection device 119.

[0078] According to some disclosed embodiments, an integrated circuit device is provided. The integrated circuit device includes: a functional device including a selection device; and a bias generator circuit coupled to the selection device and configured to detect a leakage current of the functional device and generate a bias voltage based on the detected leakage current. The bias voltage is provided to the selection device to control the selection device.

[0079] According to some embodiments, when the leakage current is less than the reference current, the bias voltage is zero, and when the leakage current is equal to or greater than the reference current, the bias voltage is a negative voltage.

[0080] According to some embodiments, when the leakage current is less than the reference current, the bias voltage is a negative voltage, and when the leakage current is equal to or greater than the reference current, the bias voltage is zero.

[0081] According to some embodiments, the bias generator circuit includes: a current comparator configured to compare the leakage current with the reference current and generate a first signal; and a negative charge pump coupled to the current comparator and configured to receive the first signal and generate the bias voltage based on the first signal.

[0082] According to some embodiments, the negative charge pump is configured to output a negative voltage if the leakage current is greater than the reference current.

[0083] According to some embodiments, the bias generator circuit further includes: a clock signal generator configured to generate a clock signal, wherein the current comparator is configured to compare the leakage current with the reference current in response to the clock signal.

[0084] According to some embodiments, the bias generator circuit further includes: a latch coupled between the current comparator and the bias generator and configured to latch the first signal in response to the clock signal.

[0085] According to some embodiments, the functional device includes a memory cell capable of responding to the selection device being connected to a word line, and the integrated circuit device further includes a word line driver configured to receive the bias voltage from the negative charge pump and output a word line signal to the selection device, wherein if the leakage current is greater than the reference current, the word line signal is the negative voltage.

[0086] According to some embodiments, the selection device includes a selection transistor having a gate terminal configured to receive the word line signal.

[0087] According to some embodiments, the selection transistor is configured to receive the bias voltage as a body bias voltage.

[0088] According to some embodiments, the selection device is an N-channel metal oxide semiconductor transistor.

[0089] According to some disclosed embodiments, a bias generator circuit is provided. The bias generator circuit includes: a current comparator configured to compare a leakage current of a functional device with a reference current to generate a comparison result; and a bias generator coupled to the current comparator and configured to output a bias voltage to a selection device of the functional device. The bias voltage is output based on the comparison result.

[0090] According to some embodiments, when the leakage current is less than the reference current, the bias voltage is zero, and when the leakage current is equal to or greater than the reference current, the bias voltage is a negative voltage.

[0091] According to some embodiments, the current comparator compares the leakage current with the reference current in response to a first enable signal.

[0092] According to some embodiments, the bias generator circuit further includes: a clock signal generator configured to generate a first clock signal, wherein the first clock signal has an active phase and an inactive phase, and the current comparator compares the leakage current with the reference current in the active phase and does not compare the leakage current with the reference current in the inactive phase.

[0093] According to some embodiments, the bias generator circuit further includes: a latch coupled between the current comparator and the bias generator and configured to latch the comparison result during a first period, wherein the active phase is within the first period.

[0094] According to some embodiments, the bias generator includes: a first transistor coupled between a ground terminal of the bias generator and an output node and having a gate terminal connected to the first enable signal.

[0095] According to some further disclosed embodiments, a method for operating an integrated circuit device is provided. The method includes: providing a reference current; receiving a leakage current of a functional device during an off state; comparing the leakage current with the reference current; generating a negative bias voltage in response to the comparing of the leakage current with the reference current; and applying the negative bias voltage to a selection device of the functional device to control the selection device if the leakage current is equal to or greater than the reference current.

[0096] According to some embodiments, where the selection device includes a selection transistor, the method further includes applying the negative bias voltage to a gate terminal of the selection transistor if the leakage current is greater than the reference current.

[0097] According to some embodiments, further including applying the negative bias voltage as a negative body bias to the selection transistor.

[0098] The features of several embodiments are outlined above so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should know that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or realize the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations thereto without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated circuit device, characterized in that, comprising: a functional device including a selection device connected to a word line; and a bias generator circuit coupled to the functional device and configured to detect a leakage current of the functional device and generate a bias voltage based on the detected leakage current; wherein the bias voltage is provided to the word line connected to the selection device to control the selection device, wherein the bias generator circuit includes: a current comparator configured to compare the leakage current with a reference current and generate a first signal; and a negative charge pump coupled to the current comparator and configured to receive the first signal and generate the bias voltage based on the first signal.

2. The integrated circuit device according to claim 1, characterized in that, wherein the selection device is an N-channel metal oxide semiconductor transistor, when the leakage current is less than the reference current, the bias voltage is zero, and when the leakage current is equal to or greater than the reference current, the bias voltage is a negative voltage.

3. The integrated circuit device according to claim 1, characterized in that, wherein the selection device is a P-channel metal oxide semiconductor transistor, when the leakage current is less than the reference current, the bias voltage is a negative voltage, and when the leakage current is equal to or greater than the reference current, the bias voltage is zero.

4. The integrated circuit device according to claim 1, characterized in that, wherein the negative charge pump is configured to output a negative voltage if the leakage current is greater than the reference current.

5. The integrated circuit device according to claim 2, characterized in that, wherein the bias generator circuit further includes: a clock signal generator configured to generate a clock signal, wherein the current comparator is configured to compare the leakage current with the reference current in response to the clock signal.

6. The integrated circuit device according to claim 5, characterized in that, wherein the bias generator circuit further includes: a latch coupled between the current comparator and the bias generator and configured to latch the first signal in response to the clock signal.

7. The integrated circuit device according to claim 1, characterized in that, wherein the integrated circuit device further includes a word line driver configured to receive the bias voltage from the negative charge pump and output a word line signal to the selection device, wherein if the leakage current is greater than the reference current, the word line signal is a negative voltage.

8. The integrated circuit device according to claim 7, characterized in that, wherein the selection device includes a selection transistor having a gate terminal configured to receive the word line signal.

9. The integrated circuit device according to claim 8, characterized in that, wherein the selection transistor is configured to receive the bias voltage as a body bias voltage.

10. A bias generator circuit, characterized in that, comprising: A current comparator configured to compare a leakage current of a functional device with a reference current to generate a comparison result, the functional device including a selection device connected to a word line; and a bias generator coupled to the current comparator and configured to output a bias voltage to the word line of the selection device connected to the functional device; wherein the bias voltage is output based on the comparison result, wherein the selection device is an N-channel metal oxide semiconductor transistor, and the bias generator is configured to output a negative voltage as the bias voltage if the leakage current is greater than the reference current.

11. The bias generator circuit according to claim 10, wherein, wherein the selection device is an N-channel metal oxide semiconductor transistor, when the leakage current is less than the reference current, the bias voltage is zero, and when the leakage current is equal to or greater than the reference current, the bias voltage is a negative voltage.

12. The bias generator circuit according to claim 11, wherein, wherein the current comparator compares the leakage current with the reference current in response to a first enable signal.

13. The bias generator circuit according to claim 11, wherein, wherein the bias generator circuit further includes: a clock signal generator configured to generate a first clock signal, wherein the first clock signal has an active phase and an inactive phase, and the current comparator compares the leakage current with the reference current in the active phase and does not compare the leakage current with the reference current in the inactive phase.

14. The bias generator circuit according to claim 13, wherein, wherein the bias generator circuit further includes: a latch coupled between the current comparator and the bias generator and configured to latch the comparison result during a first period, wherein the active phase is within the first period.

15. The bias generator circuit according to claim 12, wherein, wherein the bias generator includes: a first transistor coupled between a ground terminal of the bias generator and an output node and having a gate terminal connected to the first enable signal.

16. A method of operating an integrated circuit device, wherein, including: providing a reference current; receiving a leakage current of a functional device during an off state, the functional device including a selection device connected to a word line; comparing the leakage current with the reference current; generating a negative bias voltage in response to the comparing the leakage current with the reference current; and if the leakage current is greater than the reference current, applying the negative bias voltage to the word line of the selection device of the functional device to control the selection device, wherein the selection device is an N-channel metal oxide semiconductor transistor.

17. The method according to claim 16, wherein, Wherein the selection device includes a selection transistor, and the method further includes applying the negative bias voltage to a gate terminal of the selection transistor if the leakage current is greater than the reference current.

18. The method according to claim 17, wherein, further comprising applying the negative bias voltage as a negative substrate bias to the selection transistor.

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