Word line bias voltage generation circuit for NAND flash memory

Abstract

The present invention relates to a word line bias voltage generating circuit for a NAND flash memory, comprising: a high voltage generating unit for generating a high voltage; an erase control logic for outputting an erase voltage and a selection signal according to a block selection signal; a level converter for converting the voltage of the high voltage generating unit to generate a word line voltage in a programming mode; a word line voltage control unit for selecting the output of the level converter through a first high voltage switch to output as a word line bias voltage when the operation mode is not in an erase mode; and a second high voltage switch for outputting the erase voltage as a word line bias voltage according to the control of the erase control logic in the erase mode.

Description

Technical Field

[0001] The present invention relates to a word line bias voltage generating circuit of a NAND flash memory, and in particular to a word line bias voltage generating circuit of a NAND flash memory capable of providing a stable word line bias voltage. Background Art

[0002] Generally, flash memory is a non-volatile memory that retains data after power failure. It is often used as a portable storage device because of its small size, light weight, and strong resistance to mechanical shock, direct light, high temperature and moisture compared to branch media or optical media.

[0003] Flash memory is roughly divided into NAND flash memory and NOR flash memory. In NAND flash memory, address lines are set in units of blocks, while in NOR flash memory, address lines are set in units of cells.

[0004] Therefore, although the NAND flash memory has the disadvantage of being able to access only in blocks, it can significantly reduce the number of wirings compared to the NOR flash memory, thereby having the advantage of being able to achieve high density (high capacity).

[0005] Due to these characteristics of the NAND type flash memory, the NAND type flash memory is mainly used as a portable storage device.

[0006] The operation mode of the flash memory can be divided into a program mode for filling electrons in a floating gate, an erase mode for removing electrons, and a read mode for reading data.

[0007] The program mode is a process of tunneling or injecting electrons in the channel region into the floating gate by applying a high voltage to the control gate as a word line. Conversely, the erase mode is a process of moving electrons in the floating gate back to the channel region (substrate) by applying a high voltage to the substrate.

[0008] Flash memory cannot be overwritten in general, so the erase mode must be executed first before new data can be written.

[0009] In the read mode, data is determined by reading a change in a threshold voltage value according to the state of electrons in the floating gate.

[0010] As described above, for external devices and internal cell arrays, the flash memory needs to extract data through the bit lines in the read mode, and needs to apply a high voltage through the bit lines in the erase mode.

[0011] Flash memory is generally classified into NAND type and NOR type. In NAND type flash memory, address lines are set in units of blocks, while in NOR type flash memory, address lines are set in units of cells.

[0012] Therefore, although the NAND flash memory has the disadvantage of being able to access only in blocks, it can significantly reduce the number of wirings compared to the NOR flash memory, thereby having the advantage of being able to achieve higher density (higher capacity).

[0013] Due to such characteristics of the NAND type flash memory, the NAND type flash memory is mainly used as a portable storage device.

[0014] A card-type portable storage device having a built-in NAND flash memory is defined as a general-purpose NAND flash memory card.

[0015] An example of a NAND flash memory card structure is Korean Patent Publication No. 10-0648243 (grant date: November 14, 2006, invention title: Memory Card Using NAND Flash Memory).

[0016] As described in the above-mentioned authorized patent, the existing NAND flash memory card includes a controller for interconnecting the built-in NAND flash memory with a host device such as a computer.

[0017] That is, all NAND flash memory cards include a plurality of buffers and a controller as a circuit for converting instructions and addresses. According to the structural characteristics of the NAND flash memory as described above, conversion of instructions and addresses is required.

[0018] In programming mode, data from the controller is input into the memory cell array, and in read mode, data from the memory cell array is output to the controller.

[0019] In this way, data is input or output between the controller and the memory cell array, and at this time, the input and output of data are performed according to the cycle of the clock.

[0020] In addition, the NAND flash memory performs an erase operation in units of blocks, and as described above, the word line bias voltage applied to the word line varies according to the operation mode of the NAND flash memory.

[0021] The difference in bias voltage is generated by using a level shifter. The structure and function of the word line bias voltage generating circuit of the conventional NAND flash memory will be described in detail below.

[0022] Figure 1 This is a block diagram of a conventional NAND flash memory word line bias voltage generating circuit.

[0023] like Figure 1As shown, the word line bias voltage generating circuit of the existing NAND flash memory includes: a high voltage generating unit 100, which is used to generate a high voltage; a first level converter 400 and a second level converter 500, which are used to receive the high voltage of the high voltage generating unit 100 to output voltages according to modes respectively; an erase control logic 300, which is used to control the operation of the second level converter 500 to generate a word line voltage of an erase mode; and a word line voltage control unit 200, which is used to control the first high voltage switch 600 and the second high voltage switch 700 according to the selection signal of the high voltage generating unit 100, so as to select the voltage of the first level converter 400 or the voltage of the second level converter 500 and output it as a word line voltage (VWL).

[0024] Hereinafter, the structure and function of the word line bias voltage generating circuit of the conventional NAND flash memory having the above-mentioned structure will be described in more detail.

[0025] First, the high voltage generating section 100 generally generates a programming voltage. At this time, the voltage generated by the high voltage generating section 100 is provided to the first level shifter 400 and the second level shifter 500.

[0026] The first level converter 400 is used to provide a word line bias voltage in a program mode, and the second level converter 500 is used to provide a word line bias voltage in an erase mode.

[0027] That is, the first level converter 400 and the second level converter 500 both receive the voltage generated by the high voltage generating unit 100 and convert it into different word line bias voltages, wherein the second level converter 500 is controlled by the erase control logic 300 to generate the word line bias voltage in the erase mode.

[0028] Since the erase mode is usually performed in units of blocks, a word line bias voltage is generated for a block selected according to a block selection signal (BKSEL), and the erase control logic 300 applies a high voltage to a main body (not shown in the drawings) to perform the erase mode operation.

[0029] The word line voltage control unit 200 controls the first high voltage switch 600 and the second high voltage switch 700 to select and output the voltage of the first level shifter 400 or the voltage of the second level shifter 500 according to the mode.

[0030] That is, in the programming mode, the word line voltage control unit 200 controls the first high voltage switch 600 to output the output voltage of the first level converter 400 as the word line bias voltage (VWL), and in the erase mode, controls the second high voltage switch 700 to output the output voltage of the second level converter 500 as the word line bias voltage (VWL).

[0031] As described above, the conventional word line bias voltage generating circuit of the NAND flash memory adopts a method of selectively controlling the first high voltage switch 600 and the second high voltage switch 700 by using the word line voltage control unit 200 according to the programming mode or the erasing mode.

[0032] However, in the conventional word line bias voltage generating circuit of the NAND flash memory, the output voltage of the high voltage generating unit 100 is in a floating state in the erase mode, so the voltage of the control signal for controlling the second high voltage switch 700 is unstable.

[0033] Another problem is that the high voltage generating unit 100 is prone to generate noise, and there is a problem of voltage level instability due to the noise and the use of a high voltage switch. Summary of the invention

[0034] Technical issues

[0035] The technical problem to be solved by the present invention is to provide a word line bias voltage generating circuit for a NAND flash memory, which can block noise and eliminate the instability of the bias level.

[0036] Technical Solution

[0037] The word line bias voltage generating circuit of the NAND flash memory of the present invention for solving the above-mentioned technical problems comprises: a high voltage generating unit for generating a high voltage; an erase control logic for outputting an erase voltage and a selection signal according to a block selection signal; a level converter for converting the voltage of the high voltage generating unit to generate a word line voltage in a programming mode; a word line voltage control unit for selecting the output of the level converter through a first high voltage switch to output as a word line bias voltage when the operation mode is not in an erase mode; and a second high voltage switch for outputting the erase voltage as a word line bias voltage according to the control of the erase control logic in the erase mode.

[0038] Beneficial Effects

[0039] Since the present invention logically executes the switching control of the high voltage switch in the erase mode without using a level converter to change the voltage level of the high voltage generating unit, it has the effect of being unaffected by the noise generated by the high voltage generating unit during operation and eliminating the voltage instability phenomenon caused by the word line voltage control unit that performs control in a floating state. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 This is a block diagram of a conventional NAND flash memory word line bias voltage generating circuit.

[0041] Figure 2 It is a structural block diagram of a word line bias voltage generating circuit of a NAND flash memory of the present invention.

[0042] [Description of Reference Numerals]

[0043] 10: high voltage generating unit;

[0044] 20: word line voltage control unit;

[0045] 30: Erase control logic;

[0046] 40: Level converter;

[0047] 50: first high voltage switch;

[0048] 60: Second high voltage switch. DETAILED DESCRIPTION

[0049] Hereinafter, a word line bias voltage generating circuit for a NAND flash memory according to the present invention will be described in detail with reference to the accompanying drawings.

[0050] The embodiments provided by the present invention are to more fully describe the present invention to those skilled in the art, and the embodiments described below may be changed into other various forms, and the scope of the present invention is not limited to the following embodiments. On the contrary, these embodiments are provided to make the content of the present invention more thorough and complete, and to fully convey the concept of the present invention to those skilled in the art.

[0051] The terms used in this specification are only used for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in this specification, unless an exception is explicitly stated, the singular includes the plural form. In addition, the "comprise" and / or "comprising" used in this specification specifically refer to the existence of the mentioned shapes, numbers, steps, operations, components, elements and / or their combinations, and do not exclude the existence or addition of one or more other shapes, numbers, operations, components, elements and / or their combinations. As used in this specification, the term "and / or" includes any one of the listed items and all combinations of more than one.

[0052] The terms "first", "second", etc. used in this specification are used to describe various components, regions and / or parts, but it should be understood that these components, parts, regions, layers and / or parts are not limited by these terms. These terms do not imply any specific order, up or down, or superiority or inferiority, and are only used to distinguish one component, region or part from another component, region or part. Therefore, without departing from the teachings of the present invention, the first component, region or part described below may also refer to the second component, region or part.

[0053] Embodiments of the present invention will be described below with reference to the accompanying drawings that schematically illustrate embodiments of the present invention. In the accompanying drawings, variations in the shapes shown may be expected, depending on, for example, manufacturing techniques and / or tolerances. Therefore, it should be understood that embodiments of the present invention are not limited to the specific shapes of the regions shown in this specification, but should include variations in shape, for example, caused by manufacturing.

[0054] Figure 2 4 is a circuit diagram of a word line bias voltage generating circuit of a NAND flash memory according to a preferred embodiment of the present invention.

[0055] like Figure 2 As shown, the present invention includes: a high voltage generating unit 10, which is used to generate a high voltage; an erase control logic 30, which is used to output an erase voltage and a selection signal according to a block selection signal (BKSEL); a level converter 40, which is used to convert the voltage of the high voltage generating unit 10 to generate a word line voltage in a programming mode; a word line voltage control unit 20, when the operation mode is not in the erase mode, it is used to select the output of the level converter 40 through a first high voltage switch 50 to output it as a word line bias voltage (VWL); and a second high voltage switch 60, which is used to output the erase voltage as a word line bias voltage (VWL) according to the control of the erase control logic 30 in the erase mode.

[0056] Hereinafter, the structure and function of the word line bias voltage generating circuit of the NAND flash memory of the present invention having the above-mentioned structure will be described in more detail.

[0057] First, the high voltage generating section 10 generally generates a programming voltage. At this time, the voltage generated by the high voltage generating section 10 is provided to the level shifter 40.

[0058] The level shifter 40 is used to provide a word line bias voltage in the programming mode of operation.

[0059] Since the erase mode is usually performed in units of blocks, a word line bias voltage is generated for a block selected according to a block selection signal (BKSEL), and the erase control logic 30 is used to apply a high voltage to a main body (not shown) to perform the erase mode operation.

[0060] The word line voltage control section 20 controls the first high voltage switch 50 to select and output the voltage of the level shifter 40 according to the mode.

[0061] That is, the word line voltage control unit 20 controls the first high voltage switch 50 only in the programming mode to select the voltage of the level shifter 40 and output it as the word line bias voltage (VWL).

[0062] Different from this, in the erase mode, the erase control logic 30 generates an erase voltage and a selection signal, and the generated erase voltage is output as a word line bias voltage (VWL) through the second high voltage switch 60 .

[0063] Therefore, the word line bias voltage (VWL) in the erase mode does not generate noise due to the switching of the high voltage generating unit 10, and the input is generated by using logic without relying on the unstable switching control of the word line voltage control unit 20 in a floating state, thereby improving stability.

[0064] It will be apparent to those skilled in the art that the present invention is not limited to the above embodiments and the present invention can be implemented through various modifications and variations within the scope not departing from the technical spirit of the present invention.

Claims

1. A word line bias voltage generating circuit for a NAND flash memory, comprising: A high voltage generating unit for generating a high voltage; An erase control logic, which is used to output an erase voltage and a selection signal according to a block selection signal; a level converter for converting a voltage of the high voltage generating section to generate a word line voltage of a programming mode; a word line voltage control section for selecting the output of the level converter through a first high voltage switch to output as a word line bias voltage when the operation mode is not in the erase mode; as well as The second high voltage switch is used to output an erase voltage as a word line bias voltage under the control of the erase control logic in an erase mode.

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