Portable storage device and method of operating a portable storage device

Abstract

A portable storage device and a method of operating the same are provided. The portable storage device includes a nonvolatile memory device for storing data, a storage controller, and a bridge chip set. The bridge chip set is connected to a first connector of a host through a cable assembly, detects a resistance of the cable assembly, provides USB type information of the first connector to the storage controller based on the detected resistance, and provides USB version information associated with an established USB connection to the storage controller after the USB connection is established with the host. The storage controller selects one of a plurality of initialization modes based on the USB type information and the USB version information, selects a clock signal having a frequency that is less than or equal to an available maximum power level, and performs an initialization operation based on the selected clock signal within an internal reference time interval.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0154141, filed on November 27, 2019 with the Korean Intellectual Property Office (KIPO), the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] Exemplary embodiments generally relate to storage devices, and more specifically, to portable storage devices and methods of operating portable storage devices. Background Technology

[0004] Data transfer standards (such as Universal Serial Bus (USB)) are industrial data bus standards used for transferring digital data between electronic devices. The currently used USB 3.1 type offers transfer speeds approximately ten times faster than the USB 2.0 type. Therefore, the USB 3.1 type is commonly used for transferring high-definition content. Portable storage devices can connect to a variety of hosts that support various USB connectors. Summary of the Invention

[0005] An exemplary embodiment provides a portable storage device that is compatible with various host devices and capable of performing power throttling.

[0006] An exemplary embodiment provides a method for operating a portable storage device that is compatible with various host devices and capable of performing power throttling.

[0007] According to an exemplary embodiment, a portable storage device includes: a plurality of non-volatile storage devices configured to store data; a storage controller configured to control the plurality of non-volatile storage devices; and a bridge chipset connected to a first connector of a host via a cable assembly. The bridge chipset is configured to: detect the resistance of the cable assembly; provide the storage controller with Universal Serial Bus (USB) type information of the first connector based on the detected resistance; and, after establishing a USB connection with the host, provide the storage controller with USB version information associated with the established USB connection. The storage controller, independently of the host, is configured to: select one of a plurality of initialization modes based on the USB type information and the USB version information; select a clock signal having a frequency at which the power consumption of the selected clock signal is less than or equal to the maximum available power level associated with the selected initialization mode; and perform an initialization operation based on the selected clock signal within an internal reference time interval.

[0008] According to an exemplary embodiment, a method of operating a portable storage device includes: detecting the resistance of a cable assembly in a bridging chipset. The portable storage device includes: a plurality of non-volatile storage devices configured to store data; a storage controller configured to control the plurality of non-volatile storage devices; and the bridging chipset connected to a first connector of a host via the cable assembly, the cable assembly being connected to a second connector of the bridging chipset. The method further includes: determining Universal Serial Bus (USB) type information of the first connector based on the detected resistance; selecting one of a plurality of initialization modes in the storage controller, independently of the host, based on USB type information and USB version information associated with a USB connection established with the host; and performing power throttling based on the selected initialization mode.

[0009] According to an exemplary embodiment, a portable storage device includes: a plurality of non-volatile storage devices configured to store data; a storage controller configured to control the plurality of non-volatile storage devices; and a bridge chipset connected to a first connector of a host via a cable assembly. The bridge chipset is configured to: detect the resistance of the cable assembly; provide the storage controller with Universal Serial Bus (USB) type information of the first connector based on the detected resistance; and, after establishing a USB connection with the host, provide the storage controller with USB version information associated with the established USB connection. The bridge chipset includes a connection detector configured to detect the resistance of the cable assembly via a first pin of a plurality of pins in a second connector of the portable storage device, wherein the second connector is connected to the cable assembly. The storage controller includes: an interface unit configured to perform an interface connection between the host and the non-volatile storage devices; and a power controller configured to select one of a plurality of initialization modes based on the USB type information and the USB version information to perform the initialization operation. The bridging chipset is configured to: provide the USB type information to the storage controller via a first general-purpose input / output (GPIO) pin of the connection detector, wherein the first GPIO pin is hardwired to a second GPIO pin of the storage controller; and write the USB version information into a register in the Fast Peripheral Component Interconnect (PCIe) interface of the interface unit. The power controller is further configured to: select a clock signal with a frequency at which the power consumption of the selected clock signal is less than or equal to the maximum available power level associated with the selected initialization mode; and perform the initialization operation based on the selected clock signal within an internal reference time interval.

[0010] According to an exemplary embodiment, a portable storage device includes: a plurality of non-volatile storage devices configured to store data; a storage controller configured to control the plurality of non-volatile storage devices; and a bridging chipset connected to a first connector of a host via a cable assembly. The bridging chipset is configured to: detect the resistance of the cable assembly; provide connection information of the first connector to the storage controller based on the detected resistance; and, after establishing a connection with the host, provide version information associated with the established connection to the storage controller. The storage controller, independent of the host, is configured to: select one of a plurality of initialization modes based on the connection information and the version information; select a clock signal having a frequency at which the power consumption of the selected clock signal is less than or equal to the maximum available power level associated with the selected initialization mode; and perform an initialization operation based on the selected clock signal within an internal reference time interval.

[0011] Therefore, in the exemplary embodiment, the portable storage device can shorten the time interval of the initialization operation and optimize power by adaptively controlling power based on the USB type of the first connector of the host connected via the cable assembly and the USB version information between the portable storage device and the host. Additionally, the portable storage device can improve performance by controlling the frequency of the clock signal at the beginning of the initialization operation. Attached Figure Description

[0012] The above and other features of this disclosure will become more apparent from the detailed description of exemplary embodiments of this disclosure with reference to the accompanying drawings, wherein:

[0013] Figure 1 This is a block diagram illustrating a storage system according to an exemplary embodiment.

[0014] Figure 2 Showing according to an exemplary embodiment Figure 1 An example of a cable assembly.

[0015] Figure 3A Showing according to an exemplary embodiment Figure 1 The first connector in the process.

[0016] Figure 3B Showing according to an exemplary embodiment Figure 2 The plug in the middle.

[0017] Figure 3C This illustrates an exemplary embodiment. Figure 1 The table shows the types of cable assemblies.

[0018] Figure 4 This illustrates an exemplary embodiment. Figure 1 A block diagram of the host in the system.

[0019] Figure 5 This illustrates an exemplary embodiment. Figure 1 A block diagram of an example portable storage device.

[0020] Figure 6 This illustrates an exemplary embodiment. Figure 5 A block diagram of an example storage controller.

[0021] Figure 7 Showing according to an exemplary embodiment Figure 6 An example of an interface unit in a storage controller.

[0022] Figure 8 Showing according to an example embodiment Figure 6 An example of a power controller in a storage controller.

[0023] Figure 9 Showing according to an exemplary embodiment Figure 8 An example of a lookup table (LUT) in [the context of the text].

[0024] Figure 10 Showing according to an exemplary embodiment Figure 5 The operation of the storage controller in the system.

[0025] Figure 11 This illustrates an exemplary embodiment. Figure 5 The timing diagram of the operation of the storage controller in the image.

[0026] Figure 12 Showing according to an exemplary embodiment Figure 5 The operation of the connection detector in the process.

[0027] Figure 13 This illustrates an exemplary embodiment. Figure 5 A block diagram of one of several non-volatile storage devices in a portable storage device.

[0028] Figure 14 This illustrates an exemplary embodiment. Figure 13 A block diagram of the storage cell array.

[0029] Figure 15 This illustrates an exemplary embodiment. Figure 14 A perspective view of one of the multiple storage blocks.

[0030] Figure 16 This illustrates an exemplary embodiment. Figure 15 The equivalent circuit diagram of the storage block.

[0031] Figure 17 This is a flowchart illustrating a method for operating a portable storage device according to an exemplary embodiment.

[0032] Figure 18 This is a block diagram illustrating a storage system according to an exemplary embodiment. Detailed Implementation

[0033] Exemplary embodiments of the present disclosure will be described more fully below with reference to the accompanying drawings. Throughout the drawings, the same reference numerals may refer to the same elements.

[0034] It will be understood that the terms “first,” “second,” “third,” etc., are used herein to distinguish one element from another, and the elements are not limited by these terms. Thus, a “first” element in an exemplary embodiment may be described as a “second” element in another exemplary embodiment.

[0035] It should be understood that, unless the context explicitly indicates otherwise, the description of a feature or aspect within each exemplary embodiment should generally be considered applicable to other similar features or aspects in other exemplary embodiments.

[0036] Unless the context clearly indicates otherwise, the singular forms of “a,” “one,” and “the” are intended to include the plural forms as used herein.

[0037] In this document, when a value is described as approximately equal to another value, or substantially the same as another value, or substantially equal to another value, it should be understood that the values ​​are the same, that the values ​​are equal to each other within the range of measurement error, or, as those skilled in the art will understand, that if they are measurably unequal, they are sufficiently close in value to be functionally equal to each other. For example, the term “approximately” as used herein includes the value and refers to a value within an acceptable deviation range for that particular value, taking into account the measurement problem and the error associated with a particular number of measurements (i.e., the limitations of the measurement system). For example, as those skilled in the art will understand, “approximately” can mean within one or more standard deviations. Furthermore, it should be understood that although a parameter may be described herein as having a “approximately” particular value, according to exemplary embodiments, the parameter may be exactly that particular value or close to that particular value within the measurement error as those skilled in the art will understand.

[0038] Figure 1 This is a block diagram illustrating a storage system according to an exemplary embodiment.

[0039] Reference Figure 1 The storage system 10 may include a host 100 and a portable storage device 200.

[0040] The host 100 and the portable storage device 200 can be electrically connected to each other and can communicate with each other via a Universal Serial Bus (USB) cable assembly 30. The USB cable assembly 30 may also be referred to as cable assembly 30.

[0041] In an exemplary embodiment, the host 100 can be connected to the cable assembly 30 via the first connector 110, and the portable storage device 200 can be connected to the cable assembly 30 via the second connector 210.

[0042] Host 100 may include at least one of the following: smartphone, tablet PC, mobile phone, video phone, e-book reader, desktop PC, laptop computer, netbook computer, workstation, server, personal digital assistant (PDA), portable multimedia player (PMP), MP3 player, medical device, camera, or wearable device.

[0043] In an exemplary embodiment, host 100 may include at least one of a variety of medical devices, such as various portable medical measurement devices (e.g., blood glucose measuring devices, heart rate measuring devices, or body temperature measuring devices), magnetic resonance angiography (MRA) devices, magnetic resonance imaging (MRI) devices, computed tomography (CT) devices, imaging devices, or ultrasound devices. In an exemplary embodiment, host 100 may include, for example, navigation devices, Global Navigation Satellite System (GNSS) receivers, event data loggers (EDR), flight data loggers (FDR), automotive infotainment devices, navigation electronics (e.g., navigation devices or gyrocompasses), avionics, security devices, in-vehicle host units, industrial or household robots, drones, automated teller machines (ATMs), or point-of-sale (POS) devices.

[0044] The first connector 110 can also be referred to as the first socket, and the second connector 210 can also be referred to as the second socket.

[0045] The host 100 can provide commands (CMD) and addresses (ADDR) to the portable storage device 200 via the cable assembly 30, and can also exchange data (DTA) with the portable storage device 200 via the cable assembly 30.

[0046] exist Figure 1 In this embodiment, portable storage device 200 is shown as a solid-state drive (SSD) device as an example. However, the exemplary embodiment is not limited thereto. For example, according to the exemplary embodiment, portable storage device 200 can be any kind of portable storage device.

[0047] Portable storage device 200 may include a bridge chipset 220 (also referred to herein as bridge chipset circuitry), a storage controller 300 (also referred to herein as storage controller circuitry), and a storage medium 400. Storage medium 400 may include multiple non-volatile storage devices. Multiple non-volatile storage devices may be used as storage media for portable storage device 200.

[0048] In an exemplary embodiment, multiple non-volatile storage devices 400a to 400k (see...) Figure 5 All of these can include flash memory or vertical NAND storage devices. The storage controller 300 can control multiple non-volatile storage devices 400a. Each of the 400k.

[0049] When the bridging chipset 220 is connected to the first connector 110 of the host 100 via the cable assembly 30, the bridging chipset 220 can receive power from the host 100 and can detect the resistance of the cable assembly 30. Furthermore, the bridging chipset 220 can determine the USB type of the cable assembly 30 and / or the first connector 110 based on the detected resistance, and can provide USB type information indicating the determined USB type to the storage controller 300.

[0050] The bridge chipset 220 can notify the storage controller 300 of USB type information by selectively switching general-purpose input / output (GPIO) pins based on detected resistance.

[0051] Additionally, when a USB connection is established between the portable storage device 200 and the host 100 (e.g., when a USB link is established between the host 100 and the portable storage device 200), the bridge chipset 220 can provide the storage controller 300 with USB version information that indicates the USB protocol information between the host 100 and the portable storage device 200.

[0052] The storage controller 300, independent of the host 100, can select one of several initialization modes based on USB type and USB version information. It can select a clock signal with a frequency at which the power consumption is less than or equal to the maximum available power level associated with the selected initialization mode, and can perform initialization operations on the storage medium 400 based on the selected clock signal within an internal reference time interval. That is, the power consumption of the selected clock signal with said frequency is less than or equal to the maximum available power level supported by the selected initialization mode.

[0053] That is, the storage controller 300 can select the frequency of the clock signal to be provided to the hardware modules in the storage controller 300 so that the power target level associated with the selected initialization mode is not exceeded.

[0054] Figure 2 An exemplary embodiment is shown. Figure 1 Example of cable assembly 30.

[0055] Reference Figure 2 The cable assembly 30 may include a cable 31, a first overmold 33, a second overmold 33-1, a first plug 35, and a second plug 35-1.

[0056] The first plug 35 can be connected to the cable 31 through the first covering mold 33, and the second plug 35-1 can be connected to the cable 31 through the second covering mold 33-1.

[0057] Figure 3A An exemplary embodiment is shown. Figure 1 The first connector 110 in the middle. Figure 3B An exemplary embodiment is shown. Figure 2 The plug in.

[0058] Reference Figure 3A The first connector 110, which can be connected to the first plug 35, may include 24 pins A1 to A12 and B1 to B12. Pins may also be referred to as contacts.

[0059] The first set of pins A1 to A12 and the second set of pins B1 to B12 can be arranged symmetrically with respect to the center portion of the first plug 35.

[0060] For example, the first connector 110 may include: first GND pins A1, A12, B1 and B12, first USB 3.1 transmitter pins A2, A3, B2 and B3, first USB 3.1 receiver pins A10, A11, B10 and B11, first VBUS pins A4, A9, B4 and B9, first CC (configuration channel) pins A5 and B5, first USB 2.0 signal pins A6, A7, B6 and B7, and first side pins A8 and B8.

[0061] Reference Figure 3B The first plug 35 or the second plug 35-1 may include 24 pins A1 to A12 and B1 to B12 corresponding to the respective pins of the first connector 110.

[0062] For example, the first plug 35 or the second plug 35-1 may include: second GND pins A1, A12, B1 and B12, second USB 3.1 transmitter pins A2, A3, B2 and B3, second USB 3.1 receiver pins A10, A11, B10 and B11, second VBUS pins A4, A9, B4 and B9, second CC pin A5, VCONN pin B5, second USB 2.0 signal pins A6 and A7, and second side pins A8 and B8.

[0063] The first USB 3.1 transmitter pins A2, A3, B2, and B3 of the first connector 110 can be connected to the second USB 3.1 receiver pins A10, A11, B10, and B11 of the first plug 35, and the first USB 3.1 receiver pins A10, A11, B10, and B11 of the first connector 110 can be connected to the second USB 3.1 transmitter pins A2, A3, B2, and B3 of the first plug 35, thereby transmitting or receiving data between the first connector 110 and the first plug 35 or the second plug 35-1 according to the USB 3.1 protocol. Each of the first CC pins A5 and B5 of the first connector 110 can be connected to the second CC pin A5 or VCONN pin B5 of the first plug 35 or the second plug 35-1.

[0064] The configuration of the first connector 110 and the first plug 35 or the second plug 35-1 is based on an example of USB Type-C. The configuration of the first connector 110 and the first plug 35 or the second plug 35-1 can be changed according to the USB type.

[0065] In an exemplary embodiment, the pin assignment of the second connector 210 may be the same as or similar to the pin assignment of the first connector 110.

[0066] In an exemplary embodiment, the host 100, which supports a USB interface, can define the insertion direction of the first plug 35 connected to the first connector 110 and whether the portable storage device 200 connected to the first connector 110 via the cable assembly 30 is used as a USB device or as a USB host by measuring the voltage of the CC pin (identification pin) of the host 100.

[0067] That is, the CC (CC1 or CC2) pin can be used for at least one of the following operations: detecting the connection of the portable storage device 200 through the cable assembly 30, determining the insertion direction of the first plug 35, and managing the configuration of the storage system 10 (e.g., managing the configuration of the host 100 and the portable storage device 200).

[0068] In order to identify the insertion direction of the first plug 35 and determine whether the external device connected to the first connector 110 and cable assembly 30 is a USB device or a USB host by measuring the voltage on the CC pin, a specific current can be continuously applied to the CC pin. The specific current that can be provided by the host 100 can vary depending on the USB type of the first connector 110.

[0069] Figure 3C This illustrates an exemplary embodiment. Figure 1 The table shows the types of cable assemblies.

[0070] Reference Figure 3C The (USB) type of cable assembly 30 conforms to “TYPE C TO C” as indicated by reference numeral 36, “TYPE C TO STANDARD A” as indicated by reference numeral 37, or “TYPE C TO CEPTACLE B” as indicated by reference numeral 38.

[0071] In an exemplary embodiment, Figure 1 The cable assembly 30 in the memory is not compatible with the USB type. In this case, the bridging chipset 220 can detect the resistance of the cable assembly 30, provide connection information of the first connector 110 to the storage controller 300 based on the detected resistance, and provide version information associated with the established connection to the storage controller 300 after establishing a connection with the host 100. Independent of the host 100, the storage controller 300 can select one of several initialization modes based on the connection information and version information, select a clock signal with a frequency whose power consumption is less than or equal to the maximum available power level associated with the selected initialization mode, and perform initialization operations based on the selected clock signal within an internal reference time interval.

[0072] Figure 4 This illustrates an exemplary embodiment. Figure 1 Block diagram of host 100.

[0073] Reference Figure 4 The host 100 may include a central processing unit (CPU) 120, a read-only memory (ROM) 125, a main memory 130, a storage interface (I / F) 140, a user interface 150, and a bus 160.

[0074] Bus 160 can refer to the data transmission channel between the CPU 120, ROM 125, main memory 130, storage interface 140 and user interface 150 of host 100.

[0075] ROM 125 can store various applications. For example, it can store applications that support storage protocols such as Advanced Technology Attachment (ATA), Small Computer System Interface (SCSI), Embedded Multimedia Card (eMMC), and / or Unix File System (UFS).

[0076] Main memory 130 can temporarily store data or programs.

[0077] User interface 150 may be a physical or virtual medium for exchanging information between a user and host 100, computer programs, etc., and may include physical hardware and logical software. For example, user interface 150 may include: an input device that allows the user to manipulate host 100, and an output device for outputting the processing results of the user's input.

[0078] CPU 120 can control the overall operation of host 100. CPU 120 can generate commands for storing data in portable storage device 200 or requests (or commands) for reading data from portable storage device 200 by using applications stored in ROM 125, and can send requests to portable storage device 200 via storage interface 140.

[0079] Figure 5 This illustrates an exemplary embodiment. Figure 1 A block diagram of an example of a portable storage device 200.

[0080] Reference Figure 5 The portable storage device 200 may include a second connector 210 connected to the cable assembly 30, a bridging chipset 220, a storage controller 300, and a storage medium 400.

[0081] Storage medium 400 may include multiple non-volatile storage devices 400a 400k (where k is an integer greater than 2). The storage controller 300 can be connected to multiple non-volatile storage devices 400a via multiple channels CHG1-CHGk (where k is an integer greater than 2). 400k.

[0082] The second connector 210 may include multiple pins, and the multiple pins may include: a cable bus power (VBUS) pin 211 for power supply, CC1 pin 212 and CC2 pin 213 for exchanging setting information with the host 100, and a ground pin 214.

[0083] The bridging chipset 220 can be connected to the second connector 210. The bridging chipset 220 may include an interface converter 230 (also referred to herein as an interface converter circuit) and a connection detector 240 (also referred to herein as a connection detector circuit).

[0084] Interface converter 230 can perform interface conversion between host 100 and storage controller 300. For example, interface converter 230 can convert the interface of host 100 into an interface compatible with multiple non-volatile storage devices 400a. A 400k interface, or it can be compatible with multiple non-volatile memory devices 400a. The 400k interface is converted to a 100k interface on the host.

[0085] The connection detector 240 is connected to the CC1 pin 212. When the cable assembly 30 is connected to the first connector 110 of the host 100, in response to the application of power to the cable assembly 30, it detects the resistance between the cable assembly 30 and the first connector 110, determines the USB type of the cable assembly 30 and the first connector 110 based on the detected resistance, and provides the storage controller 300 with USB type information (UTI) indicating the USB type of the cable assembly 30 and the first connector 110.

[0086] When cable assembly 30 is connected to the first connector 110 of host 100 and power is applied to cable assembly 30, a specific current applied to the CC1 pin of the first connector 110 is supplied to the CC1 pin 212 through cable assembly 30, and a voltage based on this current is induced at the CC1 pin 212. Connection detector 240 can detect the resistance between cable assembly 30 and first connector 110 by detecting the voltage at CC1 pin 212.

[0087] The connection detector 240 can determine the USB type of the cable assembly 30 and the first connector 110 based on a comparison of the detected resistance with a threshold. In an exemplary embodiment, when the detected resistance is less than or equal to the threshold, the connection detector 240 can determine the USB type of the first connector 110 as USB Type-C, and when the detected resistance is greater than the threshold, the connection detector 240 can determine the USB type of the first connector 110 as USB Type-A.

[0088] In an exemplary embodiment, the connection detector 240 can provide USB type information UTI to the power controller 360 of the storage controller 300 via the first GPIO pin 221. The connection detector 240 can selectively switch the voltage of the first GPIO pin 221 based on the detected resistance. In an exemplary embodiment, the bridge chipset 220 can provide the USB type information UTI as a sideband signal to the power controller 360 by selectively switching the voltage of the first GPIO pin 221, and the bridge chipset 220 can write USB version information as an in-band signal into register 352, which is further described below.

[0089] When the detected resistance is less than or equal to the threshold, the connection detector 240 can notify the storage controller 300 that the USB type of the first connector 110 is USB Type-C by maintaining the voltage level of the first GPIO pin 221 at the first level.

[0090] When the detected resistance is greater than the threshold, the connection detector 240 can notify the storage controller 300 that the USB type of the first connector 110 is USB Type-A by switching the voltage of the first GPIO pin 221 from the first level to the second level.

[0091] The storage controller 300 may include a power controller 360 (which may also be referred to herein as a power controller circuit) and an interface unit 350 (which may also be referred to herein as an interface circuit). The interface unit 350 may include a register 352. Register 352 may be a vendor-specific register (VSR).

[0092] The power controller 360 can be connected to the second GPIO pin 301 of the storage controller 300. The second GPIO pin 301 can be hardwired to the first GPIO pin 221 via wire 290.

[0093] After establishing a connection with the host 100, the connection detector 240 can provide the storage controller 300 with USB version information (UVI) associated with the established connection.

[0094] The connectivity detector 240 can write the USB version information (UVI) into register 352, and can obtain the USB version information (UVI) by referencing register 352 in response to a write event in register 352. The bridge chipset 220 and the storage controller 300 can communicate with each other via sideband communication through the first GPIO pin 221 and the second GPIO pin 301. The connectivity detector 240 and register 352 in the interface unit 350 can communicate with each other via in-band communication and through a Fast Non-Volatile Memory (NVMe) interface.

[0095] The power controller 360 can select one of several initialization modes based on USB type information (UTI) and USB version information (UVI), and can perform initialization operations based on a selected clock signal with a frequency whose power consumption is less than or equal to the maximum available power level associated with the selected initialization mode.

[0096] Figure 6 This illustrates an exemplary embodiment. Figure 5 A block diagram of an example of the storage controller 300.

[0097] Reference Figure 6 The storage controller 300 may include a processor 310, an error correction code (ECC) engine 320 (which may also be referred to herein as an ECC engine circuit), a buffer 330 (which may also be referred to herein as a buffer circuit), a randomizer 335 (which may also be referred to herein as a randomizer circuit), a ROM 340, an interface unit 350 (which may also be referred to herein as an interface circuit), a power controller 360 (which may also be referred to herein as a power controller circuit), and a non-volatile memory (NVM) controller 345 (which may also be referred to herein as a non-volatile memory controller circuit), which are connected to each other via a bus 305.

[0098] Processor 310 controls the overall operation of memory controller 300. Processor 310 may include multiple cores.

[0099] Multiple cores can execute with non-volatile memory devices 400a 400k associated control operations. At least one of the multiple cores can process commands provided by the host 100, at least one of the multiple cores can perform address mapping and garbage collection using the flash translation layer (FTL), and at least one of the multiple cores can control the non-volatile memory device 400a through the non-volatile memory controller 345. 400k.

[0100] Non-volatile storage device 400a A 400k memory cell may have the following physical characteristics: the threshold voltage distribution varies due to factors such as programming elapsed time, temperature, programming interference, and read interference. For example, due to the above reasons, the data stored in the non-volatile memory device 400a... The data in the 400k file may be corrupted.

[0101] The storage controller 300 utilizes various error correction techniques to correct such errors. For example, the storage controller 300 may include an ECC engine 320. The ECC engine 320 can correct errors in non-volatile storage device 400a. An error occurred in the data stored in 400k.

[0102] ROM 340 stores firmware for various information used in the operation of the storage controller 300. Buffer 330 can store data from non-volatile memory device 400a. Data provided by 400k.

[0103] Randomizer 335 will be stored in non-volatile memory device 400a Data randomization in 400k. For example, randomizer 335 can randomize the data to be stored in non-volatile memory device 400a in word lines. Randomize the data in 400k.

[0104] Data randomization can be performed to process data so that the programming states of the memory cells connected to the word lines have the same proportion.

[0105] For example, if the memory cell connected to a word line is a multilevel cell (MLC) that stores 2 bits of data per cell, then each memory cell has an erase state and one of the first to third programming states.

[0106] In this case, randomizer 335 can randomize the data such that the number of memory cells in an erase state, the number of memory cells in a first programming state, the number of memory cells in a second programming state, and the number of memory cells in a third programming state are the same or substantially the same in the memory cells connected to a word line. For example, the memory cells storing randomized data have an equal number of programming states.

[0107] Randomizer 335 also supports non-volatile memory device 400a The 400k data read is derandomized.

[0108] Interface unit 350 can execute between host 100 and non-volatile storage device 400a Interface connections between 400k.

[0109] The interface unit 350 includes a register 352, and the register 352 can store USB version information UVI.

[0110] The power controller 360 can receive USB type information (UTI), select one of several initialization modes based on the USB type information (UTI) and USB version information (UVI), and perform power throttling to regulate the power level consumed in the initialization operation associated with the selected initialization mode.

[0111] The non-volatile memory controller 345 can receive commands CMD and addresses ADDR, and can control the non-volatile memory device 400a based on the commands CMD and addresses ADDR. 400k.

[0112] Figure 7 An exemplary embodiment is shown. Figure 6 An example of the interface unit 350 in the storage controller 300.

[0113] Reference Figure 7 The interface unit 350 may include a Fast Peripheral Component Interconnect (PCIe) interface 351, a Fast Non-Volatile Memory (NVMe) interface 353, and an interface controller 355. The PCIe interface 351 may include a register 352.

[0114] The interface controller 355 can control the PCIe interface 351 and the NVMe interface 353.

[0115] PCIe interface 351 can be a communication path for sending and receiving commands and data according to the PCIe protocol. NVMe interface 353 can be a communication path for sending and receiving commands and data according to the NVMe protocol. The PCIe protocol can support the NVMe protocol. Therefore, NVMe interface 353 can send / receive commands and data via PCIe interface 351.

[0116] Figure 8 An exemplary embodiment is shown. Figure 6 An example of the power controller 360 in the storage controller 300.

[0117] Reference Figure 8 The power controller 360 may include control logic 361 (which may also be referred to herein as control logic circuitry), an initial mode lookup table (LUT) 370, a clock generator 380 (which may also be referred to herein as clock generator circuitry), and selection circuitry 390. The initial mode LUT 370 may also be referred to as LUT or power throttling LUT.

[0118] The clock generator 380 may include phase-locked loop (PLL) circuits 381 and 383, and the selection circuit 390 may include multiplexers (MUX) 391, 392, 393 and 394.

[0119] exist Figure 8 For ease of illustration, a processor 310 comprising multiple cores 311, 312 and 313, and a non-volatile memory controller 345 are also shown.

[0120] Core 311 can process commands provided by host 100, core 312 can perform address mapping and garbage collection using FTL, and core 313 can control non-volatile memory device 400a through non-volatile memory controller 345. 400k.

[0121] Control logic 361 can access LUT 370 based on USB type information UTI and USB version information UTI, and can generate selection signals SS1, SS2, SS3 and SS4 by referring to the corresponding power targets.

[0122] LUT 370 can store information about power targets associated with multiple initialization modes. In an exemplary embodiment, LUT 370 can store information about the frequency of clock signals provided to cores 311, 312, and 313, system bus 305, and nonvolatile memory controller 345 in each of the multiple initialization modes.

[0123] PLL circuit 381 can generate a basic clock signal CLK1 with a first frequency, and generate frequency-divided clock signals CLKD11 and CLKD12 by dividing the basic clock signal CLK1.

[0124] PLL circuit 383 can generate a basic clock signal CLK2 with a second frequency, and generate frequency-divided clock signals CLKD21 and CLKD22 by dividing the basic clock signal CLK2.

[0125] Multiplexer 391 can select one of the basic clock signal CLK1 and the frequency division clock signals CLKD11 and CLKD12 as a first selected clock signal SCLK1 in response to the first selection signal SS1, and can provide the first selected clock signal SCLK1 to cores 311 and 313.

[0126] Multiplexer 392 can select one of the basic clock signal CLK1 and the divided clock signals CLKD11 and CLKD12 as the second selected clock signal SCLK2 in response to the second selection signal SS2, and can provide the second selected clock signal SCLK2 to the system bus 305.

[0127] Multiplexer 393 can select one of the basic clock signal CLK2 and the frequency division clock signals CLKD21 and CLKD22 as the third selected clock signal SCLK3 in response to the third selection signal SS3, and can provide the third selected clock signal SCLK3 to core 312.

[0128] Multiplexer 394 can select one of the basic clock signal CLK2 and the divided clock signals CLKD21 and CLKD22 as the fourth selected clock signal SCLK4 in response to the fourth selection signal SS4, and can provide the fourth selected clock signal SCLK4 to the non-volatile memory controller 345.

[0129] Figure 9 An exemplary embodiment is shown. Figure 8 Example of LUT 370 in the example.

[0130] Reference Figure 9 LUT 370 may include entries 371, 372, and 373 corresponding to multiple initialization modes associated with multiple power targets, including at least a first power target, a second power target, and a third power target. Entrance 371 may store a second power target HIGH associated with USB Type-C, entry 372 may store a third power target MIDDLE associated with USB Type-A and USB 3.0 or later, and entry 373 may store a first power target LOW associated with USB Type-A and USB 2.0.

[0131] The first to third power targets LOW, HIGH, and MIDDLE may include information about the operating frequency of clock signals provided to hardware components such as cores 311, 312, and 313, system bus 305, and nonvolatile memory controller 345, based on USB type information and USB version information of the first connector 110 and / or cable assembly 30.

[0132] For example, the second power target HIGH may include information about the operating frequency of the clock signals provided to cores 311, 312, and 313, system bus 305, and nonvolatile memory controller 345 when the USB type of the first connector 110 corresponds to USB Type-C.

[0133] For example, the third power target MIDDLE may include information about the operating frequency of the clock signals provided to cores 311, 312, and 313, system bus 305, and nonvolatile memory controller 345 when the USB type of the first connector 110 corresponds to USB Type-A and the USB version associated with the established connection corresponds to USB 3.0 or later.

[0134] For example, the first power target LOW may include information about the operating frequency of the clock signals provided to cores 311, 312, and 313, system bus 305, and nonvolatile memory controller 345 when the USB type of the first connector 110 corresponds to USB Type A and the USB version associated with the established connection corresponds to USB 2.0.

[0135] Control logic 361 can generate selection signals SS1, SS2, SS3 and SS4 by referring to information about the operating frequency of the clock signal associated with each power target, and can provide selection signals SS1, SS2, SS3 and SS4 to multiplexers 391, 392, 393 and 394.

[0136] Figure 10 An exemplary embodiment is shown. Figure 5 The operation of the storage controller 300.

[0137] Reference Figures 5 to 10 In an exemplary embodiment, when power is applied to the portable storage device 200, the power controller 360 performs an initialization operation (S110) by setting the power target to a first power target corresponding to a default value. The power controller 360 selects a first initialization mode from a plurality of initialization modes that corresponds to the first power target. Since the power controller 360 cannot obtain the USB type information of the first connector 110 and the USB version information associated with the established connection when power is applied to the portable storage device 200, the power controller 360 performs the initialization operation by setting the first power target from a plurality of power targets. The first power target may have the lowest power level among the plurality of power targets.

[0138] The connection detector 240 in the bridging chipset 220 detects the resistance of the cable assembly 30 by detecting the voltage of the CC1 pin 212 (S120). The connection detector 240 determines whether the voltage of the CC1 pin 212 is less than or equal to the threshold based on a comparison between the voltage of the CC1 pin 212 and a threshold (S130).

[0139] When the voltage at pin 212 of CC1 is less than or equal to a threshold ("Yes" in S130), the USB type of cable assembly 30 is USB Type-C, and power controller 360 performs an initialization operation by setting the power target to a second power target (HIGH) (S140). Power controller 360 selects a second initialization mode corresponding to the second power target from a plurality of initialization modes. The second power target can have the highest power level among the plurality of power targets.

[0140] When the voltage of the CC1 pin 212 is greater than the threshold ("No" in S130), the USB type of the cable assembly 30 is USB Type A, so the connection detector 240 determines whether the USB version information (e.g., USB link) corresponds to USB 3.0 or higher (S150).

[0141] When the USB version information corresponds to USB 3.0 or higher ("Yes" in S150), the power controller 360 performs an initialization operation by setting the power target to the third power target (MIDDLE) (S160). The power controller 360 selects the third initialization mode from a plurality of initialization modes that corresponds to the third power target. The third power target can have a power level greater than the minimum power level and less than the maximum power level, so the third power target can also be referred to as a medium or intermediate power target.

[0142] When the USB version information does not correspond to USB 3.0 or higher ("No" in S150), the power controller 360 maintains the first initialization mode.

[0143] Figure 11 This illustrates an exemplary embodiment. Figure 5 The timing diagram of the initialization operation of the storage controller 300 in the diagram.

[0144] Reference Figures 5 to 9 and Figure 11 When power is applied to the portable storage device 200 at the first time point T11, the connection detector 240 detects the resistance of the cable assembly 30 by detecting the voltage of the CC1 pin 212 to determine the USB type of the cable assembly 30. The USB type of the cable assembly 30 can be detected at the second time point T12.

[0145] When the USB type of cable assembly 30 corresponds to USB Type-C (as shown by reference numeral 375 in the attached figure), the open operation is completed at the fourth time point T14. In this case, the power target is set to the second power target (HIGH).

[0146] The connection detector 240 detects the USB version information at the third time point T13.

[0147] When the USB type of cable assembly 30 corresponds to USB Type-A and the USB version information corresponds to USB 3.0 or higher (as shown by reference numeral 376 in the attached figure), the open-circuit operation is completed at the fifth time point T15. In this case, the power target is set to the third power target (MIDDLE).

[0148] When the USB type of cable assembly 30 corresponds to USB Type-A and the USB version information corresponds to USB 2.0 (as shown by reference numeral 377 in the attached figure), the open-circuit operation is completed at the sixth time point T16. In this case, the power target is set to the first power target (LOW).

[0149] Figure 12 An exemplary embodiment is shown. Figure 5 The operation of the connection detector 240 in the middle.

[0150] Reference Figures 5 to 9 and Figure 12 At the first time point T21, power is applied to the portable storage device 200.

[0151] During the first time interval INT11 from the second time point T22 to the fourth time point T24 after power is applied, the bridge chipset 220 (connection detector 240) maintains the voltage of the first GPIO pin 221 at a first level (high level). At the third time point T23 within the first time interval INT11, the reset of the memory controller 300 is released, and the memory controller 300 begins operation. At the fourth time point T24, the bridge chipset 220 changes the voltage level of the first GPIO pin 221 to a second level (low level) different from the first level, maintains the voltage level of the first GPIO pin 221 at the second time interval INT12 from the fourth time point T24 to the fifth time point T25 at the second level, and changes the voltage level of the first GPIO pin 221 back to the first level at the fifth time point T25.

[0152] The power controller 360 prepares to detect the voltage of the second GPIO pin 301 in response to the voltage of the first GPIO pin 211 changing to the first level at the fifth time point T25, and after the third time interval INT13 from the fifth time point T25 to the sixth time point T26, the power controller 360 determines the USB type of the cable assembly 30 based on the voltage level of the second GPIO pin 301.

[0153] When the voltage of the CC1 pin 212 is less than or equal to the threshold, the connection detector 240 can notify the storage controller 300 that the USB type of the first connector 110 is USB Type-C by maintaining the voltage level of the first GPIO pin 221 at the first level during the third time interval INT13.

[0154] When the voltage of the CC1 pin 212 is greater than the threshold, the connection detector 240 can notify the storage controller 300 that the USB type of the first connector 110 is USB Type-A by changing the voltage level of the first GPIO pin 221 to the second level and maintaining the voltage level of the first GPIO pin 221 at the second level during the third time interval INT13.

[0155] During the fourth time interval INT14, from the seventh time point T27 to the eighth time point T28, the connection detector 240 changes or maintains the voltage level of the first GPIO pin 221 to the second level, changes the voltage level of the first GPIO pin 221 to the first level, and writes the USB version information UVI into the register 352 of the PCIe interface 351 at the eighth time point T28. The storage controller 300 determines the USB version in response to the write event in the register 352 at the ninth time point T29. That is, the connection detector 240 can notify the storage controller 300 of the USB type of the first connector 110 and / or cable assembly 30 by changing the voltage level of the first GPIO pin 221 to the first level or by maintaining the voltage level of the first GPIO pin 221 at the second level during the third time interval INT13.

[0156] The time interval from the point when the power is applied to the ninth time point T29 can correspond to an internal reference time interval, and the internal reference time interval can be less than or equal to 10 seconds.

[0157] Figure 13 This illustrates an exemplary embodiment. Figure 5 A block diagram of one of the non-volatile storage devices in the portable storage device 200. For ease of illustration, Figure 13 Only the non-volatile storage device 400a is shown. In an exemplary embodiment, Figure 5 The non-volatile storage devices 400a to 400k in the portable storage device 200 can all have Figure 13 The configuration shown.

[0158] Reference Figure 13 The non-volatile storage device 400a includes a memory cell array 430, an address decoder 460, a page buffer circuit 410, a data input / output (I / O) circuit 420, a control circuit 450, and a voltage generator 470.

[0159] The memory cell array 430 can be coupled to the address decoder 460 via a serial select line SSL, multiple word lines WL, and a ground select line GSL. Additionally, the memory cell array 430 can be coupled to the page buffer circuit 410 via multiple bit lines BL. The memory cell array 430 may include multiple memory cells coupled to multiple word lines WL and multiple bit lines BL. The memory cell array 430 may also include multiple memory cells coupled to multiple word lines WL stacked in a vertical direction perpendicular to the substrate.

[0160] Figure 14 This illustrates an exemplary embodiment. Figure 13 Block diagram of the storage cell array 430.

[0161] Reference Figure 14 The storage cell array 430 may include multiple storage blocks BLK1 to BLKz (where z is an integer greater than 2). In an exemplary embodiment, by Figure 13 The address decoder 460 selects storage blocks BLK1 to BLKz. For example, the address decoder 460 can select storage block BLK corresponding to the block address from storage blocks BLK1 to BLKz.

[0162] Figure 15 This illustrates an exemplary embodiment. Figure 14 A perspective view of one of the storage blocks BLK1 to BLKz. In an exemplary embodiment, Figure 14 Storage blocks BLK1 to BLKz can all have the following characteristics: Figure 15 The configuration of the storage block BLKi is shown.

[0163] Reference Figure 15 The storage block BLKi includes a structure extending along the first to the third direction from D1 to D3.

[0164] A substrate 611 is provided. For example, the substrate 611 may have a first type (e.g., a first conductivity type) of well. For example, the substrate 611 may have a p-well formed by implanting a group 3 element such as boron (B). A plurality of doped regions 811 to 814 extending along a first direction D1 are disposed in / on the substrate 611. For example, the plurality of doped regions 811 to 814 may have a second type (e.g., a second conductivity type) different from the first type of the substrate 611. In an exemplary embodiment, the first to fourth doped regions 811 to 814 have an n-type.

[0165] In the region of substrate 611 located between the first doped region 811 and the second doped region 812, a plurality of insulating materials 612 extending along the second direction D2 are sequentially disposed along the third direction D3. For example, the plurality of insulating materials 612 may be disposed along the third direction D3 and may be spaced apart by a specific distance. Exemplarily, the insulating material 612 may include an insulating material such as an oxide layer. However, the insulating material 612 is not limited thereto.

[0166] In the region of substrate 611 located between the first doped region 811 and the second doped region 812, a plurality of pillars 613 are sequentially disposed along the second direction D2, penetrating the insulating material 612 along the third direction D3. For example, the plurality of pillars 613 can penetrate the insulating material 612 to contact the substrate 611.

[0167] For example, each pillar 613 may include a variety of materials. For example, the channel layer 614 of each pillar 613 may include a silicon material of a first type. For example, the channel layer 614 of each pillar 613 may include a silicon material of the same type as the substrate 611. In an exemplary embodiment, the channel layer 614 of each pillar 613 includes p-type silicon. The internal material 615 of each pillar 613 includes an insulating material. For example, the internal material 615 of each pillar 613 may include an insulating material such as silicon oxide. However, the internal material 615 is not limited thereto. For example, the internal material 615 of each pillar 613 may include an air gap.

[0168] In the region between the first doped region 811 and the second doped region 812, an insulating layer 616 is disposed along the exposed surfaces of the insulating material 612, the pillar 613, and the substrate 611. Exemplarily, the insulating layer 616 disposed on the exposed surface of the uppermost insulating material 612 along the third direction D3 can be removed.

[0169] A plurality of first conductive materials 711 to 791 are disposed on the exposed surface of the insulating layer 616 between the first doped region 811 and the second doped region 812. For example, the first conductive material 711 extending along the second direction D2 is disposed between the substrate 611 and the insulating material 612 adjacent to the substrate 611.

[0170] A first conductive material extending along the first direction D1 is disposed between an insulating layer 616 located at the top of a specific insulating material and an insulating layer 616 located at the bottom of a specific insulating material 612 within the insulating material 612. For example, a plurality of first conductive materials 721 to 781 extending along the first direction D1 are disposed between the insulating material 612, and it is understood that the insulating layer 616 is disposed between the insulating material 612 and the first conductive materials 721 to 781. The first conductive materials 721 to 791 may include metallic materials.

[0171] A structure identical to that on the first doped region 811 and the second doped region 812 can be provided in the region between the second doped region 812 and the third doped region 813. In the region between the second doped region 812 and the third doped region 813, there are a plurality of insulating materials 612 extending along the first direction D1, a plurality of columnar members 613 arranged sequentially along the second direction D2 and penetrating the plurality of insulating materials 612 along the third direction D3, an insulating layer 616 provided on the exposed surfaces of the plurality of insulating materials 612 and the plurality of columnar members 613, and a plurality of first conductive materials 713 to 793 extending along the first direction D1.

[0172] In the region between the third doped region 813 and the fourth doped region 814, a structure identical to that on the first doped region 811 and the second doped region 812 may be provided. In the region between the third doped region 813 and the fourth doped region 814, a plurality of insulating materials 612 extending along the first direction D1, a plurality of columnar members 613 arranged sequentially along the second direction D2 and penetrating the plurality of insulating materials 612 along the third direction D3, an insulating layer 616 provided on the exposed surfaces of the plurality of insulating materials 612 and the plurality of columnar members 613, and a plurality of first conductive materials 713 to 793 extending along the first direction D1.

[0173] Drains 820 are respectively disposed on a plurality of pillars 613. Second conductive materials 831 to 833 extending along a first direction D1 are disposed on the drains 820. The second conductive materials 831 to 833 are disposed along a second direction D2 and spaced apart by a specific distance. The second conductive materials 831 to 833 are respectively connected to the drains 820 in corresponding regions. The drains 820 and the second conductive materials 831 to 833 extending along the first direction D1 can be connected via each contact plug. The second conductive materials 831 to 833 may include metallic materials. The second conductive materials 831 to 833 may include conductive materials such as polycrystalline silicon. However, the second conductive materials 831 to 833 are not limited to these.

[0174] Figure 16 This illustrates an exemplary embodiment. Figure 15 The equivalent circuit diagram of the storage block BLKi.

[0175] Figure 16 The memory block BLKi can be formed on the substrate in a three-dimensional (or vertical) structure. For example, multiple strings of memory cells included in the memory block BLKi can be formed in a direction perpendicular to the substrate.

[0176] Reference Figure 16The memory block BLKi may include memory cell strings NS11 to NS33 coupled between bit lines BL1, BL2, and BL3 and the common source line CSL. Each memory cell string NS11 to NS33 may include a string select transistor SST, multiple memory cells MC1 to MC12, and a ground select transistor GST.

[0177] The serial select transistor SST can be connected to the corresponding serial select lines SSL1 to SSL3. Multiple memory cells MC1 to MC12 can be connected to their respective word lines WL1 to WL12. The ground select transistor GST can be connected to the corresponding ground select lines GSL1 to GSL3. The serial select transistor SST can be connected to the corresponding bit lines BL1, BL2, and BL3, and the ground select transistor GST can be connected to the common source line CSL.

[0178] Word lines with the same height (e.g., WL1) can be connected together, and ground select lines GSL1 to GSL3 and serial select lines SSL1 to SSL3 can be separated.

[0179] Return to reference Figure 13 The control circuit 450 can receive command (signal) CMD and address (signal) ADDR from the storage controller 300, and control the erase, programming and read operations of the non-volatile storage device 400a based on the command signal CMD and the address signal ADDR.

[0180] For example, control circuit 450 can generate control signal CTL for controlling voltage generator 470 based on command signal CMD, and can generate row address R_ADDR and column address C_ADDR based on address signal ADDR. Control circuit 450 can provide row address R_ADDR to address decoder 460 and column address C_ADDR to data input / output circuit 420. In addition, control circuit 450 can generate control signal PCTL for controlling page buffer circuit 410.

[0181] Address decoder 460 can be coupled to memory cell array 430 via serial select line SSL, multiple word lines WL and ground select line GSL.

[0182] Voltage generator 470 can generate word line voltage VWL based on control signal CTL using a first operating voltage VOP1 for the operation of non-volatile memory device 400a. Word line voltage VWL can be applied to multiple word lines WL via address decoder 460.

[0183] Page buffer circuit 410 can be coupled to memory cell array 430 via multiple bit lines BL. Page buffer circuit 410 may include multiple page buffers. In an exemplary embodiment, a page buffer may be connected to one bit line, or a page buffer may be connected to two or more bit lines. Page buffer circuit 410 may temporarily store data to be programmed into a selected page or data read from a selected page. Page buffer circuit 410 may be controlled in response to control signal PCTL from control circuit 450.

[0184] Data input / output circuit 420 can be coupled to page buffer circuit 410 via data line DL. During programming operations, data input / output circuit 420 can receive programming data DTA from memory controller 300 and provide programming data DTA to page buffer circuit 410 based on column address C_ADDR received from control circuit 450. During read operations, data input / output circuit 420 can provide read data DTA stored in page buffer circuit 410 to memory controller 300 based on column address C_ADDR received from control circuit 450.

[0185] Figure 17 This is a flowchart illustrating a method for operating a portable storage device according to an exemplary embodiment.

[0186] Reference Figures 1 to 17 A method for operating a portable storage device 200 is provided, the portable storage device 200 including: a plurality of non-volatile storage devices 400a to 400k for storing data, a storage controller 300 for controlling the plurality of non-volatile storage devices 400a to 400k, and a bridging chipset 220 connected to a first connector 110 of a host 100 via a cable assembly 30, the cable assembly 30 being connected to a second connector 210 of the bridging chipset 220.

[0187] According to the method in the exemplary embodiment, when power is applied to the portable storage device 200, the bridging chipset 220 detects the resistance of the cable assembly 30 (S210). The connection detector 240 in the bridging chipset 220 detects the resistance of the cable assembly 30 by detecting the voltage of the CC1 pin 212 of the second connector 210.

[0188] The connection detector 240 in the bridging chipset 220 determines the USB type of the first connector 110 based on the detected resistance (S220) and provides the power controller 360 in the storage controller 300 with USB type information UTI associated with the USB type of the first connector 110. After a USB connection is established between the portable storage device 200 and the host 100, the connection detector 240 in the bridging chipset 220 provides the storage controller 300 with USB version information UVI associated with the established USB connection.

[0189] The bridge chipset 220 provides USB type information UTI to the storage controller 300 through the first GPIO pin and writes USB version information UVI into register 352 in the PCIe interface 351 of the interface unit 350 included in the storage controller 300.

[0190] The power controller 360 selects one of several initialization modes based on the USB type information UTI and the USB version information UVI (S230), and can perform an initialization operation based on the selected initialization mode (S240). The power controller 360 can perform power throttling based on the selected initialization mode so that the power target level associated with the selected initialization mode is not exceeded.

[0191] Power throttling can be associated with the following operation: selecting, based on USB type and version information, the frequency of a high-performance clock signal to be provided to hardware components such as cores 311, 312, and 313, system bus 305, and non-volatile memory controller 345, such that the power target level associated with the selected initialization mode is not exceeded. A high-performance clock signal indicates that such a clock signal can optimize power.

[0192] Therefore, the portable storage device 200 can shorten the time interval of initialization operations and can adaptively control power based on the USB type of the first connector 110 of the host 100 connected via the cable assembly 30 and the USB version information between the portable storage device 200 and the host 100, thereby optimizing power.

[0193] In the comparative example, the storage device can adjust the frequency of the clock signal after the initialization operation is completed. However, the portable storage device 200 according to the exemplary embodiment can improve the performance at the beginning of the initialization operation.

[0194] Figure 18 This is a block diagram illustrating a storage system according to an exemplary embodiment.

[0195] Reference Figure 18The storage system 1000 includes a host 1100 and a portable storage device 1200.

[0196] The host 1100 and the portable storage device 1200 can be connected to each other via the cable assembly 1010.

[0197] The host 1100 includes an application 1110, a device driver 1120, a host controller 1130, a buffer random access memory (RAM) 1140, and a storage interface 1101. The host controller 1130 includes a command manager 1131, a host direct memory access (DMA) 1132, and a power manager 1133.

[0198] During operation, system-level commands (e.g., write commands) are generated by the application 1110 and device driver 1120 of host 1100 and then provided to the command manager 1131 of host controller 1130.

[0199] Command manager 1131 can be used to generate corresponding portable storage device commands (e.g., corresponding commands or command sets consistent with the protocol implemented by storage system 1000) provided to portable storage device 1200 using device driver 1120.

[0200] Commands generated by command manager 1131 can also be provided to host DMA 1132, which sends the commands to portable storage device 1200 via storage interface 1101. Storage interface 1101 may include a first connector (e.g., first connector 110) and can be connected to cable assembly 1010 via the first connector 110.

[0201] Portable storage device 1200 includes a non-volatile storage device (NVM) 1210, a device controller 1230, a buffer RAM 1240, and a host interface 1201. The device controller 1230 may include a central processing unit (CPU) 1231, a device DMA 1232, a flash DMA 1233, a command manager 1234, a buffer manager 1235, a flash translation layer (FTL) 1236, a flash manager 1237, and a power controller (PCON) 1238.

[0202] Commands transferred from host 1100 to portable storage device 1200 can be provided to device DMA 1232 via host interface 1201. Host interface 1201 may include a second connector (e.g., second connector 210) and bridge chipset (BCS) 1205. Bridge chipset 1205 may employ... Figure 5 The bridging chipset 220 in the middle.

[0203] Then, the device DMA 1232 can transmit the received command to the command manager 1234. The command manager 1234 can be used to allocate storage space in the buffer RAM 1240 to receive the corresponding write data through the buffer manager 1235. Once the portable storage device 1200 is ready to receive write data, the command manager 1234 can send a transmission "ready" signal to the host 1100.

[0204] After receiving the transmission ready signal, host 1100 will transfer write data to portable storage device 1200. Write data can be transferred to portable storage device 1200 using host DMA 1132 and storage interface 1101.

[0205] The portable storage device 1200 can then use the device DMA 1232 and buffer manager 1235 to store the received write data in buffer RAM 1240. The write data stored in buffer RAM 1240 can then be provided to flash manager 1237 via flash DMA 1233. Flash manager 1237 can be used to program the write data according to the address of the non-volatile storage device 1210 derived from the address mapping table by flash translation layer 1236.

[0206] Once the data transfer and programming are complete, the portable storage device 1200 can send a response to the host 1100 to notify the host 1100 that the write command has been successfully executed. Based on the received response signal, the host 1100 indicates to the device driver 1120 and the application 1110 that the command has been completed, and thereafter terminates the execution of the operation corresponding to the command.

[0207] As described above, the host 1100 and the portable storage device 1200 can exchange data and corresponding control signals (e.g., ready signals and response signals) via data lines (e.g., data lines DIN and DOUT). Additionally, the host 1100 can provide the portable storage device 1200 with commands CMD and addresses ADDR.

[0208] The power controller 1238 can be used Figure 8 The power controller 360 in the middle.

[0209] Therefore, in the portable storage device 1200 in the storage system 1000, the bridging chipset 1205 can detect the resistance of the cable assembly 1010 in response to power being applied from the host 1100 to the portable storage device 1200 via the cable assembly 1010, and can determine the USB type of the first connector 110 based on the detected resistance.

[0210] Furthermore, when a USB connection is established between the host 1100 and the portable storage device 1200, the portable storage device 1200 can obtain USB version information. The power controller 1238 can select one of several initialization modes based on the USB type and USB version information, and can perform initialization operations based on the selected initialization mode. Therefore, the portable storage device 1200 can shorten the time interval of initialization operations and optimize power by adaptively controlling power based on the USB type and USB version information.

[0211] Portable storage devices or storage systems according to exemplary embodiments can be packaged using various package types or package configurations.

[0212] Exemplary embodiments of this disclosure can be applied to various portable storage devices and various electronic devices connected to portable storage devices.

[0213] As is conventional in the art of this disclosure, exemplary embodiments are described and illustrated in terms of functional blocks, units, and / or modules. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuitry such as logic circuits, discrete components, microprocessors, hardwired circuits, storage elements, wiring connections, etc., and can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where these blocks, units, and / or modules are implemented by microprocessors or the like, they can be programmed using software (e.g., microcode) to perform the various functions discussed herein, and may optionally be driven by firmware and / or software. Alternatively, each block, unit, and / or module may be implemented by dedicated hardware, or implemented as a combination of dedicated hardware for performing some functions and processors (e.g., one or more programmed microprocessors and associated circuitry) for performing other functions. Furthermore, without departing from the scope of the invention, each block, unit, and / or module of the exemplary embodiments may be physically divided into two or more interacting and discrete blocks, units, and / or modules. Furthermore, without departing from the scope of this disclosure, the blocks, units, and / or modules of the exemplary embodiments may be physically combined into more complex blocks, units, and / or modules.

[0214] As those skilled in the art will understand, aspects of this disclosure can be implemented as a system, method, or computer program product. Therefore, aspects of this disclosure can take the form of a completely hardware embodiment, a completely software embodiment (including firmware, built-in software, microcode, etc.), or an embodiment combining software and hardware aspects that are generally referred to herein as a “circuit,” “module,” “unit,” or “system.” Furthermore, aspects of this disclosure can take the form of a computer program product contained in one or more computer-readable media, having computer-readable program code on one or more computer-readable media. If implemented in software, functionality can be stored as one or more instructions or code on or transmitted thereon on a tangible, non-transitory computer-readable medium.

[0215] In this document, the term "circuit" can refer to either analog or digital circuits. In the case of digital circuits, digital circuits can be hardwired to perform corresponding tasks, such as digital processors that execute instructions to perform those tasks. Examples of such processors include application-specific integrated circuits (ASICs) and field-programmable gate arrays (FPGAs).

[0216] In exemplary embodiments of this disclosure, a three-dimensional (3D) memory array is provided. The 3D memory array is monolithically formed in one or more physical levels of an array of memory cells having active regions disposed above a silicon substrate and circuitry associated with the operation of those memory cells, regardless of whether such associated circuitry is above or within the substrate. The term "monolithically" means that each level of the array is deposited directly on top of the layer of each level below it. In exemplary embodiments of this disclosure, the 3D memory array includes vertically oriented vertical NAND strings such that at least one memory cell is located above another memory cell. At least one memory cell may include a charge trapping layer. The following patent documents, which are incorporated herein by reference, describe suitable configurations of three-dimensional memory arrays, wherein the three-dimensional memory array is configured as multiple levels and shares word lines and / or bit lines between these levels: U.S. Patent Nos. 7,679,133, 8,553,466, 8,654,587, 8,559,235 and U.S. Patent Publication No. 2011 / 0233648.

[0217] Although this disclosure has been specifically shown and described with reference to exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of this disclosure as defined by the appended claims.

Claims

1. A portable storage device, comprising: Multiple non-volatile storage devices are configured to store data; A storage controller configured to control the plurality of non-volatile storage devices; as well as A bridging chipset, which is connected to the host's first connector via a cable assembly. The bridging chipset includes a connection detector configured to detect the resistance of the cable assembly via a first pin of a plurality of pins in the second connector of the portable storage device. The second connector is connected to the cable assembly, and the first pin corresponds to the first CC pin among the plurality of pins in the second connector, where CC refers to the configuration channel. The bridging chipset is configured as follows: Based on the detected resistance, the storage controller is provided with the Universal Serial Bus (USB) type information of the first connector; and After establishing a USB connection with the host, the storage controller is provided with USB version information associated with the established USB connection. The storage controller is configured independently of the host as follows: Based on the USB type information and the USB version information, select one of several initialization modes; A clock signal with a frequency is selected, at which the power consumption of the selected clock signal is less than or equal to the maximum available power level associated with the selected initialization mode; and Initialization is performed based on the selected clock signal within the internal reference time interval.

2. The portable storage device according to claim 1, wherein, The first CC pin is used for at least one of the following operations: detecting the connection of the portable storage device, determining the insertion direction of the plug, and managing the configuration of the portable storage device and the host through the cable assembly; and The bridging chipset is configured to provide the USB type information to the storage controller via a first GPIO pin, where GPIO stands for General Purpose Input / Output.

3. The portable storage device according to claim 2, in, The connectivity detector is also configured to, During the first time interval after power is applied, the voltage level of the first GPIO pin, which is hardwired to the second GPIO pin of the memory controller, is maintained at the first level; During a second time interval following the first time interval, the voltage level of the first GPIO pin is changed to a second level different from the first level; and At a point in time within a third time interval following the second time interval, the voltage level of the first GPIO pin is changed to the first level. The storage controller is further configured as follows: After the third time interval has elapsed, the USB type information is determined based on the voltage level of the second GPIO pin; During the fourth time interval following the third time interval, the USB type information is written into the register in the storage controller; and The USB version information is determined in response to a write event in the register.

4. The portable storage device according to claim 3, wherein, The connection detector is configured to: maintain the voltage level of the first GPIO pin at the first level during the third time interval by comparing the voltage of the first CC pin with a threshold, thereby notifying the storage controller that the USB type of the first connector is USB-C.

5. The portable storage device according to claim 3, wherein, The connection detector is also configured to: change the voltage level of the first GPIO pin from the first level to the second level during the third time interval by comparing the voltage of the first CC pin with a threshold, thereby notifying the storage controller that the USB type of the first connector is USB Type A.

6. The portable storage device according to claim 1, wherein, The internal reference time interval is less than or equal to 10 seconds.

7. The portable storage device according to claim 1, wherein, Each of the plurality of non-volatile memory devices includes a memory cell array, and the memory cell array includes a plurality of memory cells coupled to a plurality of word lines stacked in a vertical direction perpendicular to the substrate.

8. A portable storage device, comprising: Multiple non-volatile storage devices are configured to store data; A storage controller configured to control the plurality of non-volatile storage devices; as well as A bridging chipset, which is connected to the host's first connector via a cable assembly. The bridging chipset is configured as follows: Detect the resistance of the cable assembly; Based on the detected resistance, the storage controller is provided with the Universal Serial Bus (USB) type information of the first connector; and After establishing a USB connection with the host, the storage controller is provided with USB version information associated with the established USB connection. The storage controller is configured independently of the host as follows: Based on the USB type information and the USB version information, select one of several initialization modes; A clock signal with a frequency is selected, at which the power consumption of the selected clock signal is less than or equal to the maximum available power level associated with the selected initialization mode; and Initialization is performed based on the selected clock signal within the internal reference time interval. The storage controller includes: An interface unit, configured to perform an interface connection between the host and the non-volatile storage device; and A power controller configured to select one of the plurality of initialization modes based on the USB type information and the USB version information to perform the initialization operation; The connection detector located in the bridging chipset is configured as follows: The USB type information is provided to the storage controller via the first GPIO pin of the connection detector, where GPIO stands for General Purpose Input / Output, and the first GPIO pin is hardwired to the second GPIO pin of the storage controller; and The USB version information is written into the register of the PCIe interface in the interface unit.

9. The portable storage device according to claim 8, wherein, The bridging chipset and the memory controller are configured to communicate with each other via sideband communication through the first GPIO pin and the second GPIO pin; and The connection detector and the register in the PCIe interface are configured to communicate with each other via in-band communication and through a fast non-volatile memory interface.

10. The portable storage device according to claim 8, wherein, The power controller is also configured to: Based on the USB type information and the USB version information in the register, select the clock signal having the specified frequency; and Perform power throttling to adjust the power level consumed in the selected initialization mode.

11. The portable storage device according to claim 8, wherein, The power controller includes a lookup table configured to store information about multiple power targets associated with the plurality of initialization modes, the plurality of power targets including at least a first power target, a second power target, and a third power target; and The power controller is further configured to perform the initialization operation by selecting a first initialization mode corresponding to the first power target from the plurality of initialization modes before receiving the USB type information and the USB version information; The first power target has the lowest power level among the plurality of power targets.

12. The portable storage device according to claim 11, wherein, The power controller is further configured to: in response to the USB type information indicating that the USB type of the first connector corresponds to USB Type-C, perform the initialization operation by selecting a second initialization mode corresponding to the second power target from the plurality of initialization modes. The second power target has the highest power level among the plurality of power targets.

13. The portable storage device according to claim 11, wherein, The power controller is also configured to: In response to the USB type information indicating that the first connector does not correspond to USB Type-C, determine whether the USB version information corresponds to USB 3.0 or a later version; and In response to the USB version information corresponding to USB 3.0 or later, the initialization operation is performed by selecting a third initialization mode corresponding to the third power target from among the plurality of initialization modes. The third power target is greater than the first power target and less than the largest power target among the plurality of power targets.

14. The portable storage device according to claim 8, wherein, The memory controller includes multiple cores configured to perform control operations associated with the non-volatile memory device. The power controller includes: A clock generator configured to: generate a basic clock signal and generate a divided clock signal by dividing the basic clock signal, and provide the basic clock signal and the divided clock signal to the plurality of cores as selected clock signals; A selection circuit, configured to select a chosen clock signal provided to the plurality of cores in response to a selection signal; and The control logic is configured to generate the selection signal based on the USB type information and the USB version information.

15. The portable storage device according to claim 14, wherein, The control logic is also configured to generate a selection signal in response to the USB type information indicating that the first connector corresponds to USB Type-C, such that a clock signal is selected having a frequency associated with an initialization mode corresponding to the maximum power target among the plurality of initialization modes.

16. The portable storage device according to claim 14, wherein, The control logic is also configured to, in response to the USB type information indicating that the first connector does not correspond to USB Type-C and the USB version information corresponding to USB 3.0 or later, generate a selection signal such that a clock signal having a frequency associated with an initialization mode corresponding to an intermediate power target among the plurality of initialization modes is selected. The intermediate power target is greater than the minimum power target and less than the maximum power target.

17. The portable storage device according to claim 14, wherein, The control logic is further configured to: in response to the USB type information indicating that the first connector does not correspond to USB Type-C and the USB version information does not correspond to USB 3.0 or later, generate a selection signal such that a clock signal having a frequency associated with the initialization mode corresponding to the minimum power target among the plurality of initialization modes is selected.

18. A method of operating a portable storage device, wherein, The portable storage device includes: a plurality of non-volatile storage devices configured to store data, a storage controller configured to control the plurality of non-volatile storage devices, and a bridge chipset connected to a first connector of a host computer via a cable assembly, the cable assembly being connected to a second connector of the bridge chipset. The method includes: The resistance of the cable assembly is detected in the bridging chipset by detecting the voltage of the configuration channel pins in the second connector; The Universal Serial Bus (USB) type information of the first connector is determined based on the detected resistance. Independent of the host, the storage controller selects one of several initialization modes based on the USB type information and the USB version information associated with the USB connection established with the host; and Power throttling is performed based on the selected initialization mode.

19. The method of claim 18, wherein, The bridging chipset is configured as follows: The USB type information is provided to the storage controller via a first general purpose input / output pin; and The USB version information is written into a register in the Fast Peripheral Component Interconnect interface of the interface unit included in the storage controller.

20. A portable storage device, comprising: Multiple non-volatile storage devices are configured to store data; A storage controller configured to control the plurality of non-volatile storage devices; as well as A bridging chipset, which is connected to the host's first connector via a cable assembly. The bridging chipset includes a connection detector configured to detect the resistance of the cable assembly via a first pin of a plurality of pins in the second connector of the portable storage device. The second connector is connected to the cable assembly, and the first pin corresponds to the first configuration channel CC pin among the plurality of pins in the second connector. The bridging chipset is configured as follows: The connection information of the first connector is provided to the storage controller based on the detected resistance; and After establishing a connection with the host, the storage controller is provided with version information associated with the established connection. The storage controller is configured independently of the host as follows: Select one of several initialization modes based on the connection information and the version information; A clock signal with a frequency is selected, at which the power consumption of the selected clock signal is less than or equal to the maximum available power level associated with the selected initialization mode; and Initialization is performed based on the selected clock signal within the internal reference time interval.

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