Metal Selection Structure of Semiconductor Devices

Abstract

A metal selection structure of a semiconductor device may include: a plurality of through-holes, which connect a first metal wire set in a first metal layer to a second metal wire set in a second metal layer set above the first metal layer, and are configured to constitute a plurality of nodes of a selection circuit; and an identification pattern, which is set between the first metal layer and the second metal layer and has a different layout structure from the through-holes.

Description

Technical Field

[0001] Various embodiments relate generally to semiconductor technology and, more particularly, to a metal option structure in a semiconductor device. Background Art

[0002] In order to facilitate the design, manufacturing and test processes, various option circuits are configured in the semiconductor device, and the semiconductor device is designed to select and change the circuit by changing the option metal through mask repair. For example, in order to manufacture x8 products and x16 products together on the same production line, the x16 product is first manufactured on the production line. Then, when the x8 product is manufactured, the option metal is changed through the mask repair process to realize the 8x structure. Summary of the invention

[0003] Various embodiments are directed to a semiconductor device having a metal selection structure that can reduce failures that may occur during a mask repair process for changing a selected metal and help improve repair efficiency.

[0004] In one embodiment, a metal selection structure of a semiconductor device may include: a plurality of through-holes connecting a first metal wire disposed in a first metal layer to a second metal wire disposed in a second metal layer disposed above the first metal layer and configured to constitute a plurality of nodes of a selection circuit; and an identification pattern disposed between the first metal layer and the second metal layer and having a different layout structure from the through-holes. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a circuit diagram showing a metal selection structure of a semiconductor device according to one embodiment of the present disclosure.

[0006] Figure 2 It is shown that before repairing the metal selection structure Figure 1 Layout diagram of one implementation of a metal selection structure.

[0007] Figure 3 It is shown that after the metal selection structure is repaired Figure 2 Layout diagram of the metal selection structure.

[0008] Figure 4 It is shown that before repairing the metal selection structure Figure 1 Layout diagram of one implementation of a metal selection structure.

[0009] Figure 5 It is shown that after the metal selection structure is repaired Figure 4 Layout diagram of the metal selection structure.

[0010] Figure 6 is a circuit diagram showing a metal selection structure of a semiconductor device according to one embodiment of the present disclosure.

[0011] Figure 7 It is shown that before repairing the metal selection structure Figure 6 Layout diagram of one implementation of a metal selection structure.

[0012] Figure 8 It is shown that after the metal selection structure is repaired Figure 7 Layout diagram of the metal selection structure.

[0013] Fig. 9 It is shown that before repairing the metal selection structure Figure 6 Layout diagram of one implementation of a metal selection structure.

[0014] Fig.10 It is shown that after the metal selection structure is repaired Fig. 9 Layout diagram of the metal selection structure.

[0015] Fig.11 is a layout diagram showing a metal selection structure of a semiconductor device according to one embodiment of the present disclosure.

[0016] Fig.12 is a block diagram illustrating an electronic system having a semiconductor device according to an embodiment of the present disclosure.

[0017] Fig.13 is a block diagram illustrating a memory card including a semiconductor device according to one embodiment of the present disclosure. DETAILED DESCRIPTION

[0018] The advantages and features of the present invention and the methods for achieving these advantages and features will be clearly described by the following embodiments and with reference to the accompanying drawings. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but can be implemented in various different ways. The exemplary embodiments of the present disclosure convey the scope of the present disclosure to those skilled in the art.

[0019] The numerical values, dimensions, ratios, angles, and number of elements given in the drawings describing the embodiments of the present disclosure are merely illustrative and not restrictive. Throughout the specification, the same reference numerals represent the same elements. When describing the present disclosure, when it is determined that the detailed description of the known related art may obscure the main points or clarity of the present disclosure, its detailed description will be omitted. It should be understood that the terms "including", "having", "comprising", etc. used in the specification and claims should not be interpreted as being limited to the items listed thereafter, unless otherwise specifically stated. When using an indefinite article or a definite article (e.g., "one", "the") when referring to a singular noun, unless otherwise specifically stated, the article may include the plural form of the noun.

[0020] Even if not explicitly stated, elements in the embodiments of the present disclosure should be construed as including error tolerances.

[0021] In addition, when describing the components of the present disclosure, terms such as first, second, A, B, (a), (b) may be used. These terms are only to distinguish one component from another component, rather than to imply or suggest the essence, grade, order or quantity of the component. If a component is described as "connected", "coupled" or "linked" to another component, it can be represented that the component can not only be directly "connected", "coupled" or "linked", but also indirectly "connected", "coupled" or "linked" via a third component. When describing the positional relationship (such as "element A on element B", "element A above element B", "element A below element B" and "element A next to element B"), another element C can be set between element A and element B, unless the term "directly" or "immediately" is explicitly used. When describing the positional relationship, for example, when describing the positional relationship between two components such as "up", "above", "down" or "next to", as long as terms such as "directly" or "immediately" are not used, one or more other components can be located between the two components.

[0022] In addition, the elements in the embodiments of the present disclosure are not limited by these terms. These terms are only used to distinguish one element from another element. Therefore, as used herein, within the technical concept of the present disclosure, the first element may be the second element.

[0023] In addition, the features of the various exemplary embodiments of the present disclosure may be coupled, combined, or separated in part or in whole. Various interactions and operations may be performed technically. The various exemplary embodiments may be implemented individually or in combination.

[0024] Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings. In the accompanying drawings, two directions substantially parallel to the top surface of the substrate and intersecting each other are defined as a first direction FD and a second direction SD, respectively, and a direction extending vertically from the top surface of the substrate is defined as a vertical direction. The first direction FD and the second direction SD may substantially intersect each other vertically to form a plane substantially parallel to the top surface of the substrate. The vertical direction may correspond to a direction perpendicular to the first direction FD and the second direction SD. In the accompanying drawings, the direction indicated by an arrow and the direction opposite thereto represent the same direction.

[0025] Figure 1 is a circuit diagram showing a metal selection structure of a semiconductor device according to one embodiment of the present disclosure.

[0026] Figure 2 It is shown that before repairing the metal selection structure Figure 1 Layout diagram of one implementation of a metal selection structure.

[0027] Figure 3 It is shown that after the metal selection structure is repaired Figure 2 Layout diagram of the metal selection structure.

[0028] Reference Figures 1 to 3 , the metal selection structure may include a plurality of first metal lines 11 to 13 disposed in a first metal layer M1; a plurality of second metal lines 21 to 23 disposed in a second metal layer M2; and a plurality of vias VIA1. The plurality of vias VIA1 may extend in a vertical direction and connect the first metal lines 11 to 13 and the second metal lines 21 to 23. The plurality of vias VIA1 may constitute nodes INPUT_A, INPUT_B, and OUT of the selection circuit. The first metal layer M1 may be a metal layer disposed at a lower level than the second metal layer M2 in a vertical direction. The first metal layer M1 and the second metal layer M2 may be disposed adjacent to each other in a vertical direction.

[0029] The selected area may include a first area R1 and a second area R2 arranged along a first direction FD, and a third area R3 arranged between the first area R1 and the second area R2. The first metal wires 11 to 13, the second metal wires 21 to 23, and the through hole VIA1 may be arranged in the first area R1 and the second area R2. The first metal wires 11 to 13, the second metal wires 21 to 23, and the through hole VIA1 may not be arranged in the third area R3. The first metal wires 11 to 13 extend along the first direction and may have ends arranged adjacent to each other. The first metal wires 11 to 13 may have ends that terminate at or near the boundary between the first area R1 and the third area R3, or terminate near the boundary between the second area R2 and the third area R3.

[0030] The first metal lines 11 to 13 may extend in a first direction FD. From a top view in a vertical direction, the second metal lines 21 to 23 may extend in a second direction SD and intersect or cross the first metal lines 11 to 13. The input node INPUT_A may be disposed at an intersection between the first metal line 11 and the second metal line 21, and may connect the first metal line 11 and the second metal line 21. The input node INPUT_B may be disposed at an intersection between the first metal line 13 and the second metal line 23, and may connect the first metal line 13 and the second metal line 23. The output node OUT may be disposed at an intersection between the first metal line 12 and the second metal line 22, and may connect the first metal line 12 and the second metal line 22.

[0031] An identification pattern 310 having a different layout structure from the through hole VIA1 may be provided. The identification pattern 310 may extend vertically from the first metal layer M1 to the second metal layer M2. During the mask repair process for changing or repairing the selected metal, the identification pattern 310 may be used as a guide for identifying the nodes INPUT_A, INPUT_B, and OUT of the selected circuit. The nodes INPUT_A, INPUT_B, and OUT of the selected circuit have the same or substantially the same or similar structures and are all arranged in the selected metal region. Therefore, it may be difficult to identify the positions of the nodes INPUT_A, INPUT_B, and OUT of the selected circuit during the mask repair process for changing the selected metal. If the mask repair process is performed without identifying the positions of the nodes INPUT_A, INPUT_B, and OUT of the selected circuit, a short circuit fault or an open circuit fault may occur, which may reduce the repair efficiency. The identification pattern 310 that can be used to identify the nodes INPUT_A, INPUT_B, and OUT of the selected circuit may be set to suppress the faults that may occur during the mask repair process for changing the selected metal.

[0032] The identification pattern 310 may be configured as a combination of a plurality of via patterns 311 to 313. In one embodiment, the via patterns 311 to 313 constituting the identification pattern 310 may be disposed in the third region R3 and may be connected to respective ends of the first metal lines 11 to 13 at or near a boundary of the third region R3. Figure 2 and Figure 3 As shown, the through hole patterns 311 to 313 constituting the recognition pattern 310 may include a line through hole pattern 311 and dot through hole patterns 312 and 313. The shape of the recognition pattern 310 is not limited to such line and dot patterns but may be changed or selected to facilitate recognition or patterning.

[0033] Figure 2An example is shown in which a metal is selected to be arranged or configured to connect the output node OUT and the input node INPUT_A. Figure 2 , the through hole 40 can be extended from the first metal layer M1 to the second metal layer M2 in the vertical direction. The through hole 40 can be connected to the through hole pattern 311 and the through hole pattern 312, the through hole pattern 311 is connected to the output node OUT through the first metal line 12, and the through hole pattern 312 is connected to the input node INPUT_A through the first metal line 11. Therefore, a routing path connecting the output node OUT and the input node INPUT_A can be configured. In this case, the through hole patterns 311 and 312 included in the identification pattern 310 can be included in the routing path connecting the output node OUT and the input node INPUT_A.

[0034] Return to reference Figure 1 and Figure 3 , after configuring Figure 2 After the routing path is determined, the selected metal may be changed by a mask repair process to connect the output node OUT to the input node INPUT_B. During the mask repair process for changing the selected metal, the identification pattern 310 may be used as a guide for identifying the nodes INPUT_A, INPUT_B, and OUT in the selected circuit. That is, the positions of the nodes INPUT_A, INPUT_B, and OUT of the selected circuit may be identified and located based on the identification pattern 310. Then, using the identified position information, the selected metal may be removed. Figure 2 The selected through hole 40 (such as Figure 3 A) is shown in the figure to disconnect the output node OUT from the input node INPUT_A. Then, an optional via 41 may be provided between the via pattern 311 connected to the output node OUT through the first metal line 12 and the via pattern 313 connected to the input node INPUT_B through the first metal line 13. After repairing, the optional via 41 may connect the via patterns 311 and 313 to form a routing path connecting the output node OUT and the input node INPUT_B.

[0035] Figure 4 It is shown that before repairing the metal selection structure Figure 1 Layout diagram of one implementation of a metal selection structure. Figure 5 It is shown that after the metal selection structure is repaired Figure 4 Layout diagram of the metal selection structure.

[0036] Reference Figure 4 and Figure 5, a connection line 51 may be provided in the first metal layer M1, which is not directly connected to the nodes INPUT_A, INPUT_B, and OUT of the selection circuit. The connection line 51 may extend along the first direction and may be connected to the first metal line 12 through a via pattern 311 as a part of the identification pattern 310. The via pattern 311 may be used as a bridge connecting the first metal line 12 and the connection line 51. The via pattern 311 may be defined as a bridge-type via pattern.

[0037] Figure 4 FIG. 1 shows an embodiment in which the selected metal is arranged or configured to connect the output node OUT and the input node INPUT_A. Figure 4 , the optional via 42 may be disposed at the intersection between the first metal line 12 and the second metal line 21. The optional via 41 may extend in a vertical direction and connect the first metal line 12 and the second metal line 21. Thus, a routing path connecting the output node OUT and the input node INPUT_A may be configured.

[0038] Return to reference Figure 1 and Figure 5 , after configuring Figure 4 After the routing path is determined, the optional metal may be changed or reconfigured by a mask repair process to connect the output node OUT and the input node INPUT_B. During the mask repair process for changing the optional metal, the identification pattern 310 may be used as a guide for identifying the nodes INPUT_A, INPUT_B, and OUT of the optional circuit. That is, the positions of the nodes INPUT_A, INPUT_B, and OUT of the optional circuit may be identified and located using the identification pattern 310. Then, based on the identified position information, the optional metal may be removed. Figure 4 The selected through hole 42 (such as Figure 5 B) to disconnect the output node OUT from the input node INPUT_A. The optional via 43 may be provided at the intersection between the connection line 51 and the second metal line 23. The optional via 43 may connect the connection line 51 and the second metal line 23, which are included in the routing path connecting the output node OUT and the input node INPUT_B.

[0039] In reference Figures 1 to 5 In the described embodiments, a metal selection structure having two input nodes INPUT_A and INPUT_B and one output node OUT has been described. However, the metal selection structure may be different or changed in various ways depending on the shape, complexity, configuration, nature, etc. of the selected circuit. Figures 6 to 10An embodiment of a metal selection structure having three input nodes and one output node is described, however, it should be understood that the present disclosure is not limited to the number of input nodes and output nodes described herein. Through the implementation of different features of the disclosed recognition pattern, the present disclosure can contemplate any number of input nodes and output nodes.

[0040] Figure 6 is a circuit diagram showing a metal selection structure of a semiconductor device according to one embodiment of the present disclosure.

[0041] Figure 7 It is shown that before repairing the metal selection structure Figure 6 Layout diagram of one implementation of a metal selection structure.

[0042] Figure 8 It is shown that after the metal selection structure is repaired Figure 7 Layout diagram of the metal selection structure.

[0043] Reference Figures 6 to 8 , the metal selection structure may include three input nodes INPUT_A, INPUT_B and INPUT_C and one output node OUT. The via VIA1 may extend from the first metal layer M1 to the second metal layer M2 in a vertical direction. The via VIA1 may constitute the input nodes INPUT_A, INPUT_B and INPUT_C and the output node OUT of the selection circuit.

[0044] A plurality of first metal lines 11 to 14 extending along the first direction may be disposed in the first metal layer M1 and may be connected to different vias VIA1. A plurality of second metal lines 21 to 24 extending along the second direction may be disposed in the second metal layer M2 and may be connected to corresponding vias VIA1. Coupling lines 52 and 53 extending along the first direction, which may be disposed in the first metal layer M1, are not directly connected to the vias VIA1.

[0045] Return to reference Figure 7, the first metal wires 11 to 14 and the second metal wires 21 to 24, the connection wires 52 and 53, and the nodes INPUT_A, INPUT_B, INPUT_C, and OUT may be set in the first region R1 and the second region R2. In the third region R3, the first metal wires 11 to 14 and the second metal wires 21 to 24, the connection wires 52 and 53, and the nodes INPUT_A, INPUT_B, INPUT_C, and OUT may not be set. The first metal wires 11 to 14 may have ends or end portions that are set adjacent to each other. For example, the first metal wires 11 and 12 may have ends that terminate at or near the boundary between the first region R1 and the third region R3, and the first metal wires 13 and 14 may have end portions that terminate at or near the boundary between the second region R2 and the third region R3.

[0046] The first metal wires 11 to 14 and the connecting wires 52 and 53 may extend in the first direction FD. From a top view in the vertical direction, the second metal wires 21 to 24 may intersect or cross the first metal wires 11 to 14 and the connecting wires 52 and 53 while extending in the second direction SD. The input node INPUT_A may be set at the intersection between the first metal wire 11 and the second metal wire 21, and may connect the first metal wire 11 and the second metal wire 21. The input node INPUT_B may be set at the intersection between the first metal wire 13 and the second metal wire 23, extend between the first metal wire 13 and the second metal wire 23 in the vertical direction, and may connect the first metal wire 13 and the second metal wire 23. The input node INPUT_C may be set at the intersection between the first metal wire 14 and the second metal wire 24, extend between the first metal wire 14 and the second metal wire 24 in the vertical direction, and may connect the first metal wire 14 and the second metal wire 24. The output node OUT may be disposed at an intersection between the first metal line 12 and the second metal line 22 , extend between the first metal line 12 and the second metal line 22 in a vertical direction, and may connect the first metal line 12 and the second metal line 22 .

[0047] An identification pattern 320 having a different layout structure from the via VIA1 may be provided. The identification pattern 310 may extend vertically from the first metal layer M1 to the second metal layer M2. During a mask repair process for changing or repairing the selected metal, the identification pattern 320 may be used as a guide for identifying nodes INPUT_A, INPUT_B, INPUT_C, and OUT of the selected circuit.

[0048] The recognition pattern 320 may be configured as a combination of a plurality of via patterns 321 to 324. In one embodiment, the via patterns 321 to 324 constituting the recognition pattern 320 may be disposed in the third region R3 and may be connected to respective end portions of the first metal lines 11 to 14 of the metal layer M1. Figure 7 and Figure 8 As shown, the through hole patterns 321 to 324 constituting the recognition pattern 320 may include line through hole patterns 321 and 322 and dot through hole patterns 323 and 324. The shape of the recognition pattern 320 is not limited to such line and dot patterns and may be changed or selected to facilitate recognition or patterning processing.

[0049] The connection line 52 may be connected to the first metal line 12 through the via pattern 321, and the connection line 53 may be connected to the first metal line 14 through the via pattern 322. The via pattern 321 may function as a bridge connecting the first metal line 12 and the connection line 52, and the via pattern 322 may function as a bridge connecting the first metal line 14 and the connection line 53.

[0050] Figure 7 FIG. 1 shows an embodiment in which the selected metal is arranged or configured to connect the output node OUT and the input node INPUT_C. Figure 7 , the optional through hole 44 may be disposed or formed at the intersection between the second metal line 22 and the connection line 53, and may connect the second metal line 22 and the connection line 53. Therefore, a routing path connecting the output node OUT and the input node INPUT_C may be configured.

[0051] Return to reference Figure 6 and Figure 8 , after configuring Figure 7 After the routing path is determined, the selected metal may be changed by a mask repair process to connect the output node OUT and the input node INPUT_B. During the mask repair process, the identification pattern 320 may be used as a guide for identifying the nodes INPUT_A, INPUT_B, INPUT_C, and OUT in the selected circuit. That is, the positions of the nodes INPUT_A, INPUT_B, INPUT_C, and OUT of the selected circuit may be identified and located based on the identification pattern 320. Then, using the identified position information, the selected metal may be removed. Figure 7 The selected through hole 44 (such as Figure 8 C in the figure) to disconnect the output node OUT from the input node INPUT_C. The optional via 45 may be provided at the intersection between the connection line 52 and the second metal line 23. The optional via 45 may connect the connection line 52 and the second metal line 23, and may be included in the routing path connecting the output node OUT and the input node INPUT_B.

[0052] Fig. 9 It is shown that before repairing the metal selection structure Figure 6 Layout diagram of one implementation of a metal selection structure. Fig.10 It is shown that after the metal selection structure is repaired Fig. 9 Layout diagram of the metal selection structure.

[0053] Reference Fig. 9 and Fig.10 , the via VIA1 may extend from the first metal layer M1 to the second metal layer M2 in a vertical direction. The via VIA1 may constitute nodes INPUT_A, INPUT_B, INPUT_C, and OUT of the selection circuit. A plurality of first metal lines 11 to 14 may be disposed in the first metal layer M1 and may be connected to corresponding vias VIA1. A plurality of second metal lines 21 to 24 may be disposed in the second metal layer M2 and may be connected to corresponding vias VIA1. A connection line 54 may be disposed in the first metal layer M1 and not directly connected to the via VIA1.

[0054] The first metal wires 11 to 14 and the connection wires 54 may extend in the first direction FD. From a top view, the second metal wires 21 to 24 may intersect or cross the first metal wires 11 to 14 and the connection wires 54 while extending in the second direction SD.

[0055] The input node INPUT_A may be disposed at an intersection between the first metal line 11 and the second metal line 21, and may connect the first metal line 11 and the second metal line 21. The input node INPUT_B may be disposed at an intersection between the first metal line 13 and the second metal line 23, and may connect the first metal line 13 and the second metal line 23. The input node INPUT_C may be disposed at an intersection between the first metal line 14 and the second metal line 24, and may connect the first metal line 14 and the second metal line 24. The output node OUT may be disposed at an intersection between the first metal line 12 and the second metal line 22, and may connect the first metal line 12 and the second metal line 22.

[0056] Between the first metal layer M1 and the second metal layer M2, an identification pattern 330 having a different layout structure from the via VIA1 may be provided. The identification pattern 330 may be used as a guide for identifying nodes INPUT_A, INPUT_B, INPUT_C, and OUT of the selection circuit during a mask repair process for changing or repairing the selection metal.

[0057] The recognition pattern 330 may include a plurality of via patterns 331 to 334. In one embodiment, the via patterns 331 to 334 constituting the recognition pattern 330 may be connected to ends or end portions of the first metal lines 11 to 14. The coupling line 54 may be connected to the first metal line 11 through the via pattern 331.

[0058] Fig. 9 FIG. 1 shows an embodiment in which the selected metal is arranged or configured to connect the output node OUT and the input node INPUT_C. Fig. 9 , the optional via 46 may be disposed or formed between the via pattern 334 and the via pattern 333, the via pattern 334 extending along the second direction and connected to the output node OUT through the first metal line 12, and the via pattern 333 connected to the input node INPUT_C through the first metal line 14. The optional via 46 may connect the via pattern 334 and the via pattern 333. Therefore, a routing path connecting the output node OUT and the input node INPUT_C may be configured.

[0059] Return to reference Figure 6 and Fig.10 , after configuring Fig. 9 After the routing path of the selected circuit is formed, the selected metal of the present disclosure can be changed or reconfigured by a mask repair process to connect the output node OUT and the input node INPUT_B. During the mask repair process, the identification pattern 330 can be used as a guide for identifying the nodes INPUT_A, INPUT_B, INPUT_C, and OUT in the selected circuit. That is, the positions of the nodes INPUT_A, INPUT_B, INPUT_C, and OUT of the selected circuit can be identified based on the identification pattern 330.

[0060] Then, using the identified location information, you can remove Fig. 9 The selected through hole 46 (such as Fig.10 D in the figure) to disconnect the output node OUT from the input node INPUT_C. The optional via 47 may be disposed between the via pattern 334 and the via pattern 332, the via pattern 334 being connected to the output node OUT through the first metal line 12, and the via pattern 332 being connected to the input node INPUT_B through the first metal line 13. The optional via 47 and the via patterns 334 and 332 may be included in a routing path connecting the output node OUT and the input node INPUT_B.

[0061] In this article, refer to Figures 1 to 10 In the described embodiments, the identification pattern may be configured as a combination of via patterns connected to the end portion of the first metal line, but the embodiments contemplated by the present disclosure are not limited thereto. Fig.11 Another embodiment of the recognition pattern is shown.

[0062] Reference Fig.11 , the selected metal is set to connect the output node OUT and the input node INPUT_A. Specifically, the selected via 48 can be set between the first metal line 11 connected to the input node INPUT_A and the first metal line 12 connected to the output node OUT, and can connect the first metal line 11 and the first metal line 12. Therefore, a routing path connecting the output node OUT and the input node INPUT_A can be configured.

[0063] Between the first metal layer M1 and the second metal layer M2, an identification pattern 340 having a layout or cross-sectional structure different from the via VIA1 may be provided. For example, the via VIA1 may have a rectangular layout structure or cross-sectional shape, and the identification pattern 340 may have a cross-shaped layout structure.

[0064] The first dummy metal line 60 may be disposed in the first metal layer M1, and the second dummy metal line 70 may be disposed in the second metal layer M2. The first dummy metal line 60 may be disposed in parallel or substantially parallel to the first metal lines 11 to 13 extending in the first direction, and may not be connected to the first metal lines 11 to 13. The second dummy metal line 70 may be disposed in parallel or substantially parallel to the second metal lines 21 to 23 extending in the second direction, and may not be connected to the second metal lines 21 to 23. In a top view, the first dummy metal line 60 and the second dummy metal line 70 may intersect or cross each other, and the identification pattern 340 may be disposed at the intersection between the first dummy metal line 60 and the second dummy metal line 70 extending vertically. According to the present embodiment, the identification pattern 340 may be electrically separated from the first metal lines 11 to 13, the second metal lines 21 to 23, and the through hole VIA1.

[0065] The embodiments disclosed herein describe an identification pattern for identifying nodes of a selected circuit. Therefore, during a mask repair process for changing the selected metal, a reference pattern for identifying nodes of a selected circuit can be set to accurately identify the location of the node, thereby not only reducing possible failures during the repair process, but also improving the repair efficiency.

[0066] The semiconductor device described above can be used in various electronic systems and packaging modules.

[0067] Fig.12 is a block diagram illustrating an electronic system having a semiconductor device according to an embodiment of the present disclosure. Fig.13 is a block diagram illustrating a memory card including a semiconductor device according to one embodiment of the present disclosure.

[0068] Reference Fig.12, the semiconductor device according to the embodiments disclosed herein may be applied to an electronic system 710. The electronic system 710 may include a controller 711, an input / output unit 712, and a memory 713. The controller 711, the input / output unit 712, and the memory 713 may be electrically coupled to each other through a bus 715 providing a data movement path.

[0069] For example, the controller 711 may include at least one microprocessor, at least one digital signal processor, at least one microcontroller, or at least one logic circuit capable of performing the same functions as these components. According to the disclosed embodiment, the memory 713 may include at least one semiconductor device. The input / output unit 712 may include at least one selected from a keypad, a keyboard, a display device, a touch screen, etc. As a device for storing data, the memory 713 may store data and / or execute commands, etc., to be executed by the controller 711.

[0070] The memory 713 may include a volatile memory device such as a DRAM and / or a non-volatile memory device such as a flash memory. For example, the flash memory may be installed in an information processing system of a mobile terminal such as a desktop computer. The flash memory may be composed of a solid state drive (SSD). In this case, the electronic system 710 may stably store a large amount of data in the flash memory system.

[0071] The electronic system 710 may further include an interface 714 configured to be able to send data to and receive data from a communication network. The interface 714 may be of a wired type or a wireless type. For example, the interface 714 may include an antenna, a wired transceiver, or a wireless transceiver.

[0072] The electronic system 710 may be understood as a mobile system, a personal computer, an industrial computer, or a logic system that performs various functions. For example, the mobile system may be any one of a personal digital assistant (PDA), a portable computer, a tablet computer, a mobile phone, a smart phone, a wireless phone, a laptop computer, a memory card, a digital music system, and an information transmission / reception system.

[0073] If the electronic system 710 is a device capable of performing wireless communications, the electronic system 710 can be used for communication systems such as code division multiple access (CDMA), global system for mobile communications (GSM), North American digital cellular (NADC), enhanced time division multiple access (E-TDMA), wideband code division multiple access (WCDMA), CDMA2000, long term evolution (LTE), and wireless broadband Internet (Wibro).

[0074] Reference Fig.13, the semiconductor device according to the disclosed embodiment may be provided in the form of a memory card 800. For example, the memory card 800 may include a memory 810 such as a nonvolatile memory device and a memory controller 820. The memory 810 and the memory controller 820 may store data or read stored data.

[0075] The memory 810 may include at least one of nonvolatile memory devices to which the semiconductor device according to the embodiment is applied, and the memory controller 820 may control the memory 810 to read stored data or store data in response to a read / write request from the host 830 .

[0076] Although various embodiments have been described above, those skilled in the art will appreciate that the described embodiments are merely exemplary, and therefore, the semiconductor device described herein should not be limited based on the described embodiments.

[0077] CROSS-REFERENCE TO RELATED APPLICATIONS

[0078] This application claims the priority of Korean Patent Application No. 10-2019-0152944 filed in the Korean Intellectual Property Office on November 26, 2019, the entire contents of which are incorporated herein by reference.

Claims

1. A metal selection structure for a semiconductor device, the metal selection structure comprising: a plurality of through holes, the plurality of through holes respectively connecting a plurality of first metal wires disposed in a first metal layer to a plurality of second metal wires disposed in a second metal layer, and configured to constitute a plurality of nodes of a selection circuit, the second metal layer being disposed above the first metal layer; as well as An identification pattern extends from the first metal layer to the second metal layer and has a layout structure different from that of the through hole.

2. The metal selection structure according to claim 1, wherein: The recognition pattern includes a plurality of through-hole patterns.

3. The metal selection structure according to claim 1, wherein: The recognition pattern includes a dot-type through-hole pattern and a line-type through-hole pattern.

4. The metal selection structure according to claim 2, wherein: One end portions of the first metal lines are disposed adjacent to each other, and each of the one end portions is connected to one of the plurality of via patterns.

5. The metal selection structure according to claim 4, wherein: At least one of the plurality of via patterns is included in a routing path connecting at least two of the plurality of nodes. 6 . The metal selective structure of claim 5 , further comprising a selective via disposed between the first metal layer and the second metal layer and connecting at least two via patterns in the routing path among the plurality of via patterns. 7 . The metal selective structure of claim 2 , further comprising a connection line disposed in the first metal layer and connected to one of the plurality of via patterns.

8. The metal selection structure according to claim 7 further comprises a selection via, wherein the selection via is arranged between the connecting line and one of the plurality of second metal lines to connect the connecting line and the one of the second metal lines, and constitutes a routing path connecting a selected node of the plurality of nodes.

9. The metal selection structure according to claim 1, wherein: The recognition pattern includes a via pattern electrically separated from the plurality of first metal lines and the plurality of second metal lines.

10. The metal selection structure according to claim 9, further comprising: a first dummy metal line, wherein the first dummy metal line is disposed in the first metal layer; as well as a second dummy metal line, the second dummy metal line being disposed in the second metal layer and intersecting the first dummy metal line, Wherein, the via pattern is disposed at an intersection between the first dummy metal line and the second dummy metal line.

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