A charging control circuit and device

Abstract

The application discloses a charging control circuit and equipment. The circuit comprises a first parallel charging module, a second parallel charging module and a power management module connected with a power socket. The power management module is connected with a charge pump module through an NMOS tube N1, and the power management module is connected with a battery through an NMOS tube N2. The circuit further comprises a central processing unit for controlling the NMOS tube N1 and the NMOS tube N2, and a power identification module connected with the central processing unit. The design scheme of the two charging powers compatible with each other is realized, the cost is saved, the product function richness is increased, and the user demand that the extreme pursuit of the charging rate and the comprehensive control performance of the mobile phone temperature rise are balanced is solved.

Description

Technical Field

[0001] This invention relates to the field of mobile communications, and more particularly to a charging control circuit and device. Background Technology

[0002] In current technology, with the continuous development of smart terminal devices, users have increasingly higher requirements for battery charging and battery life in smartphones and other smart terminal devices. However, the development of smartphones is limited by battery technology, making the battery a bottleneck for users. Larger screens and higher resolutions significantly increase power consumption, leading to frequent charging and a reduced user experience. To address this issue, major mobile phone manufacturers have increased charging power to shorten charging time and improve user experience. According to the latest designs from chip suppliers, the theoretical maximum charging power can reach 120W, which can greatly shorten charging time, but this comes at the cost of high costs. Furthermore, 120W charging will result in significant heat loss, causing the phone to overheat rapidly, also leading to a poor user experience.

[0003] Therefore, how to balance technology and efficiency in the product development process, and how to better meet users by combining different charging designs to avoid all users having to buy 120W charging devices, is a key challenge. This involves achieving a design that is compatible with both high-power and medium-power charging, thereby addressing the user demand for a balance between the pursuit of maximum charging speed and the overall control of phone temperature rise. Summary of the Invention

[0004] To address the aforementioned technical deficiencies in the prior art, this invention proposes a charging control circuit. The circuit includes: a first parallel charging module, a second parallel charging module, and a power management module connected to a power socket. The power management module is connected to a charge pump module via an NMOS transistor N1 and to a battery via an NMOS transistor N2. The circuit also includes a central processing unit (CPU) for controlling the NMOS transistors N1 and N2, and a power identification module connected to the CPU.

[0005] Optionally, the power identification module identifies the charging power input to the power socket, the charging power including a first charging power and a second charging power, wherein the first charging power is greater than the second charging power.

[0006] Optionally, when the power socket receives the first charging power, the first port of the central processing unit is set to low output, and the second port of the central processing unit is set to high output, so as to turn off the NMOS transistor N1 and turn on the NMOS transistor N2.

[0007] Optionally, when the NMOS transistor N1 is off and the NMOS transistor N2 is on, the voltage is boosted by the charge pump module, and the battery is charged simultaneously by the first parallel charging module, the second parallel charging module and the power management module.

[0008] Optionally, when the power socket receives the second charging power, the first port of the central processing unit is set to high output, and the second port of the central processing unit is set to low output, so as to turn on the NMOS transistor N1 and turn off the NMOS transistor N2.

[0009] Optionally, when the NMOS transistor N1 is turned on and the NMOS transistor N2 is turned off, the boost of the charge pump module is turned off, and the battery is charged simultaneously through the first parallel charging module, the second parallel charging module and the power management module.

[0010] Optionally, the battery is composed of two cells connected in series.

[0011] Optionally, the charge pump module is used to boost the output voltage of the power management chip by multiplying it.

[0012] Optionally, the first charging power is 120W, and the second charging power is 66W.

[0013] The present invention also proposes an apparatus comprising a charging control circuit as described in any of the preceding claims.

[0014] The charging control circuit and device of this invention, by proposing a charging control circuit, includes a first parallel charging module, a second parallel charging module, and a power management module connected to a power socket. The power management module is connected to a charge pump module via an NMOS transistor N1 and to a battery via an NMOS transistor N2. The circuit also includes a central processing unit (CPU) for controlling the NMOS transistors N1 and N2, and a power identification module connected to the CPU. This achieves a design scheme compatible with two charging power levels, saves costs, increases product functionality, and addresses the user need for a balance between maximizing charging speed and balancing overall phone temperature control performance. Attached Figure Description

[0015] The present invention will be further described below with reference to the accompanying drawings and embodiments. In the accompanying drawings:

[0016] Figure 1 This is a block diagram of the first embodiment of the charging control circuit of the present invention;

[0017] Figure 2 This is a circuit diagram of the second embodiment of the charging control circuit of the present invention. Detailed Implementation

[0018] It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the invention.

[0019] In the following description, the use of suffixes such as "module," "part," or "unit" to denote elements is solely for the purpose of illustrative purposes and has no specific meaning in itself. Therefore, "module," "part," or "unit" may be used interchangeably.

[0020] Example 1

[0021] Figure 1 This is a block diagram of the first embodiment of the charging control circuit of the present invention. This embodiment proposes a charging control circuit, which includes: a first parallel charging module, a second parallel charging module, and a power management module connected to a power socket. The power management module is connected to a charge pump module via an NMOS transistor N1, and to a battery via an NMOS transistor N2. The circuit also includes a central processing unit for controlling the NMOS transistors N1 and N2, and a power identification module connected to the central processing unit.

[0022] In this embodiment, considering that the heat loss of 120W charging in the prior art is far higher than the heat generation capacity of existing designs, the phone's temperature will rise rapidly, leading to a poor user experience. Therefore, to balance technology and efficiency during product development, this embodiment uses different charging designs to better meet user needs and avoid requiring all users to purchase 120W charging devices. Thus, this embodiment proposes a design that is compatible with both high-power and medium-power charging, thereby addressing the user's need to balance the pursuit of maximum charging speed with the overall control performance of phone temperature rise.

[0023] Specifically, in this embodiment, considering that the above-mentioned 120W charging design requires two batteries connected in series and using a high voltage and high current method, this embodiment uses a charge pump module to double the output voltage of the power management chip, thereby achieving the voltage of the series-connected batteries. Specifically, a single battery is 4.42V, and a dual battery is 8.84V. The normal output voltage of the power management chip in this embodiment will be provided to the system to supply the voltage required for normal operation.

[0024] Specifically, in this embodiment, considering that the 120W charging design and the 66W charging design can be distinguished in hardware through general-purpose input / output (GPIO), in this embodiment, the different charging power designs are distinguished when the software is initially downloaded to the PCB. When the power identification module identifies that it is a 120W configuration, the GPIO_ON setting on the central processing unit (CPU) side is set to low, and the GPIO_OFF setting is set to high. NMOS transistor N1 is turned off, and NMOS transistor N2 is turned on, so that all three channels can charge the battery, thereby reducing the current of a single channel and making the heat generation more uniform. When using three parallel charging channels, this is done in order to better achieve current balance, thermal balance, and comprehensive consideration of PCB area.

[0025] Specifically, in this embodiment, when the power identification module detects 65W power charging, the GPIO_ON setting on the CPU side is set to high, and the GPIO_OFF setting is set to low. This turns on NMOS transistor N1 and turns off NMOS transistor N2, thereby turning off the charge pump boost circuit. 66W charging can be achieved using a single battery, and three-way parallel charging is still used.

[0026] The beneficial effect of this embodiment is that by proposing a charging control circuit, the circuit includes a first parallel charging module, a second parallel charging module, and a power management module connected to a power socket. The power management module is connected to a charge pump module via an NMOS transistor N1 and to a battery via an NMOS transistor N2. The circuit also includes a central processing unit (CPU) for controlling the NMOS transistors N1 and N2, and a power identification module connected to the CPU. This achieves a design scheme compatible with two charging power levels, saves costs, increases the richness of product functions, and solves the user need for a balance between extreme charging speed and overall temperature control performance of the mobile phone.

[0027] Example 2

[0028] Figure 2 This is a circuit diagram of the second embodiment of the charging control circuit of the present invention. Based on the above embodiment, optionally, in this embodiment, the charging and data matching design is implemented by key matching (VDM code), that is, the designed key matching (VDM code) determines whether the current device is plugged into a 66W charger or a 120W charger.

[0029] Optionally, in this embodiment, when a 120W charger is plugged in, VBUS outputs 20V / 6A, and the VBUS_EN signal is at a high level. In order to power other modules of the mobile phone system, the BUCK driver module, together with N-type MOSFETs N6 / N7, power inductor L1, and filter capacitor C6, forms a step-down BUCK circuit, which outputs 4.2V voltage to the system modules.

[0030] Optionally, in this embodiment, when charging at 120W, the system sets VBAT_EN=1, GPIO_OFF=1, GPIO_OFF=0, GPIO_OFF=1, CP1_EN=CP2_EN=1, that is, turns on PMOS transistors N8 / N15 / N5 / N4 and turns off N5.

[0031] Optionally, in this embodiment, when charging at 120W, two circuits are connected in series to form a high-voltage, high-current charging circuit for better charging efficiency. The circuit is designed according to the 9V / 11A standard, where the remaining power is designed to account for system losses.

[0032] Optionally, in this embodiment, devices N2 / N3 / C0 / C1 / N0 / N1 form a Charge Pump boost circuit. The purpose of the above design is to charge the battery by doubling the system voltage VPH.

[0033] Alternatively, in this embodiment, the working principle of the above design is as follows:

[0034] First, CP_CLKO and CP_CLK1 are non-overlapping clock signals. In the diagram, N2 and N3 are NMOS transistors, P6 and P7 are PMOS transistors, and C0 / C1 are charging and discharging capacitors.

[0035] Optionally, in this embodiment, at the beginning of operation, when CP_CLKO is low and CP_CLK1 is high, the voltage at point B is VPH, which turns on N2, raising the voltage at point A to VPH, and N3 is off. When CP_CLKO is high and CP_CLK1 is low, the voltage at point A is 2VPH, which turns on P7 (a diode connected by PMOS transistors) and turns off P6, making the voltage at point C 2VPH-Vth(P7). When CP_CLKO is low and CP_CLK1 is high, the voltage at point B is raised to 2VPH, turning off N2, and the voltage at point A returns to VPH. At this time, P6 (a diode connected by PMOS transistors) turns on and P7 is off, so the output voltage at point VBAT is 2vin-VPH(P6). CP_CLKO and CP_CLK1 continue to work in this way without overlapping, so that the voltage at point VBAT remains unchanged at 2vin-Vth(P6 / P7), thus achieving the voltage doubling function.

[0036] Optionally, in this embodiment, N-type MOSFETs N9 / N10 / N11 / N12 and capacitors C2 / C4, and N-type MOSFETs N13 / N14 / N15 / N16 and capacitors C3 / C5, form two 1 / 2 charge pump circuits. This means the voltage is halved, and the current is doubled. The purpose of this design is to convert the input voltage VBUS, which is too high, to battery voltage. Its working principle is as follows (taking the left 1 / 2 charge pump as an example):

[0037] Optionally, in this embodiment, CP1_CLKO and CP1_CLK1 are non-overlapping clock signals. When CP1_CLKO is high and CP1_CLK1 is low, NMOS transistors N8 and N10 are turned on, while N9 and N11 are turned off. VBUS charges capacitor C2, and the output VBAT = VBUS - VC2. When CP1_CLKO is low and CP1_CLK1 is high, NMOS transistors N8 and N10 are turned off, while N9 and N11 are turned on. The charge accumulated in capacitor C2 is directly discharged to the load, and the output VBAT = VC2. Combining this with the charging formula, we can obtain VBAT = 1 / 2VBUS. C4 plays a role in stabilizing the output voltage. CP1_CLKO and CP1_CLK1 work repeatedly without overlap, so that the voltage at point VBAT is always 1 / 2VBUS and remains unchanged, thus realizing the 1 / 2d voltage function.

[0038] Then, when the 66W charger is plugged in, the VBUS output is configured to 11V / 6A. Since the power is low, the voltage does not need to be connected in series, thus obtaining a 4V / 12A configuration. At this time, GPIO_OFF=0 and GPIO_ON=1, that is, N4 is turned off and N5 is turned on, that is, the Charge-Pump voltage of twice the voltage is turned off to prevent the voltage doubling from damaging the battery. Other working principles are the same as those of 120W charging.

[0039] Optionally, in this embodiment, the purpose of designing three parallel charging channels is that charging with a single channel at a high power of 120W is a dangerous design that poses a risk of combustion. Therefore, the three parallel charging channels in this embodiment are a design that balances safety and economy after evaluation.

[0040] Optionally, in this embodiment, the charging power input to the power socket is identified by the power identification module. The charging power includes a first charging power and a second charging power, wherein the first charging power is greater than the second charging power.

[0041] Optionally, in this embodiment, when the power socket receives the first charging power, the first port of the central processing unit is set to low output, and the second port of the central processing unit is set to high output, so as to turn off the NMOS transistor N1 and turn on the NMOS transistor N2.

[0042] Optionally, in this embodiment, when the NMOS transistor N1 is off and the NMOS transistor N2 is on, the voltage is boosted by the charge pump module, and the battery is charged simultaneously by the first parallel charging module, the second parallel charging module and the power management module.

[0043] Optionally, in this embodiment, when the power socket receives the second charging power, the first port of the central processing unit is set to high output, and the second port of the central processing unit is set to low output, so as to turn on the NMOS transistor N1 and turn off the NMOS transistor N2.

[0044] Optionally, in this embodiment, when the NMOS transistor N1 is turned on and the NMOS transistor N2 is turned off, the boost of the charge pump module is turned off, and the battery is charged simultaneously through the first parallel charging module, the second parallel charging module and the power management module.

[0045] Optionally, in this embodiment, the battery is composed of two cells connected in series.

[0046] Optionally, in this embodiment, the charge pump module is used to boost the output voltage of the power management chip by multiplying it.

[0047] Optionally, in this embodiment, the first charging power is 120W and the second charging power is 66W.

[0048] Example 3

[0049] The present invention also proposes an apparatus comprising a charging control circuit as described in any of the preceding claims.

[0050] It should be noted that the above-described device embodiments and method embodiments belong to the same concept. The specific implementation process can be found in the method embodiments, and the technical features in the method embodiments are also applicable to the device embodiments, which will not be repeated here.

[0051] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0052] The sequence numbers of the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0053] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0054] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims. All of these forms are within the protection scope of the present invention.

Claims

1. A charging control circuit, characterized in that, The circuit includes: a first parallel charging module, a second parallel charging module, and a power management module connected to a power socket. The power management module is connected to a charge pump module via an NMOS transistor N1 and to a battery via an NMOS transistor N2. The circuit also includes a central processing unit for controlling the NMOS transistors N1 and NMOS transistor N2, and a power identification module connected to the central processing unit. The power identification module identifies the charging power input to the power socket, and the charging power includes a first charging power and a second charging power, wherein the first charging power is greater than the second charging power. When the first charging power is input into the power socket, the first port of the central processing unit is set to low output and the second port of the central processing unit is set to high output to turn off the NMOS transistor N1 and turn on the NMOS transistor N2. When NMOS transistor N1 is off and NMOS transistor N2 is on, the voltage is boosted by the charge pump module, and the battery is charged simultaneously by the first parallel charging module, the second parallel charging module and the power management module. When the power socket receives the second charging power, the first port of the central processing unit is set to high output and the second port of the central processing unit is set to low output to turn on the NMOS transistor N1 and turn off the NMOS transistor N2. When NMOS transistor N1 is turned on and NMOS transistor N2 is turned off, the boost function of the charge pump module is turned off, and the battery is charged simultaneously through the first parallel charging module, the second parallel charging module and the power management module. The battery is composed of two cells connected in series. The charge pump module is used to boost the output voltage of the power management module by voltage multiplication. The first charging power is 120W, and the second charging power is 66W.

2. An electronic device, characterized in that, The electronic device includes the charging control circuit as described in claim 1.

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