Method for manufacturing an integrated circuit including nanosheets and computing system

Abstract

A method of manufacturing an integrated circuit including nanosheets and a computing system are provided. The method of manufacturing the integrated circuit includes: generating layout data of the integrated circuit by placing and routing standard cells that define the integrated circuit, the standard cells including nanosheets; generating timing analysis data by performing timing analysis of the integrated circuit using the layout data; and regenerating the layout data of the integrated circuit by re-placing and re-routing the standard cells that define the integrated circuit based on the timing analysis data and the shape of the nanosheets of the placed standard cells.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10 - 2019 - 0157686, filed on November 29, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] The present inventive concept relates to an integrated circuit, and more particularly, to a method of manufacturing an integrated circuit including nanosheets and a computing system. Background art

[0004] Integrated circuits can be designed based on standard cells. Specifically, a layout of an integrated circuit can be generated by laying out standard cells according to data defining the integrated circuit and routing between the laid - out standard cells. Recently, as the configuration of integrated circuits has become more complex and semiconductor manufacturing processes have become more miniaturized, a large number of semiconductor devices have been integrated in integrated circuits. According to the miniaturization of semiconductor manufacturing processes, standard cells including patterns formed in multiple layers can include patterns with reduced sizes, and the sizes of the standard cells can also be reduced. Therefore, instances of standard cells included in an integrated circuit can be greatly affected by their adjacent structures (i.e., the layout), which can be referred to as local layout effect (LLE) or layout - dependent effect (LDE). Summary of the invention

[0005] Embodiments of the present inventive concept relate to a method of manufacturing an integrated circuit including nanosheets and a computing system, and can provide a method of manufacturing an integrated circuit that can reduce process variations and a computing system.

[0006] According to some embodiments of the present inventive concept, there is provided a method of manufacturing an integrated circuit, the method including: generating layout data of the integrated circuit by laying out and routing standard cells defining the integrated circuit, the standard cells including nanosheets; generating timing analysis data by performing timing analysis of the integrated circuit using the layout data; and regenerating the layout data of the integrated circuit by re - laying out and re - routing the standard cells defining the integrated circuit based on the timing analysis data and the shapes of the nanosheets of the laid - out standard cells.

[0007] According to some embodiments of the inventive concept, a method of manufacturing an integrated circuit is provided. The method includes: generating layout data of the integrated circuit by laying out and wiring standard cells that define the integrated circuit, where the standard cells include nanosheets; extracting, based on the layout data, target cells included in a clock path in the standard cells; and regenerating the layout data of the integrated circuit by re-laying out and re-wiring the standard cells that define the integrated circuit based on shapes of the nanosheets in the target cells and shapes of the nanosheets in adjacent cells that are arranged adjacent to the target cells in the standard cells.

[0008] According to some embodiments of the inventive concept, a computing system for manufacturing an integrated circuit is provided. The computing system includes: a processor; and a memory coupled to the processor and including computer-readable program code embedded in the memory, the computer-readable program code being executable by the processor to perform operations including: generating layout data of the integrated circuit by laying out and wiring standard cells that define the integrated circuit by using a standard cell library, where the standard cells include nanosheets; performing timing analysis of the integrated circuit by using the layout data to generate timing analysis data; regenerating the layout data of the integrated circuit by re-laying out and re-wiring the standard cells that define the integrated circuit based on the timing analysis data and shapes of the nanosheets of the laid-out standard cells; and re-performing the timing analysis of the integrated circuit by using the regenerated layout data. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments of the inventive concept will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a flowchart illustrating a method of designing an integrated circuit according to some example embodiments of the inventive concept;

[0011] Figure 2 is a flowchart illustrating a method of designing an integrated circuit according to some example embodiments of the inventive concept;

[0012] Figure 3 is a top view of cells included in an integrated circuit according to some example embodiments of the inventive concept;

[0013] Figure 4 is along Figure 3 a cross-sectional view taken along line Y1-Y2 in

[0014] Figure 5Ais a top view of a cell included in an integrated circuit showing some example embodiments according to the inventive concept;

[0015] Figure 5B is a diagram showing that the timing characteristics of a target cell according to some example embodiments according to the inventive concept change according to the shape of nanosheets of adjacent cells;

[0016] Figure 6 is a top view of a cell included in an integrated circuit showing some example embodiments according to the inventive concept;

[0017] Figure 7A and Figure 7B is a top view of a cell included in an integrated circuit showing some example embodiments according to the inventive concept;

[0018] Figure 8A and Figure 8B is a top view of a cell included in an integrated circuit showing some example embodiments according to the inventive concept;

[0019] Figure 9 is a flowchart of a method of designing an integrated circuit showing some example embodiments according to the inventive concept;

[0020] Figure 10 is a diagram of an integrated circuit showing some example embodiments according to the inventive concept;

[0021] Figure 11A and Figure 11B is showing some example embodiments according to the inventive concept Figure 9 of the LLE change model;

[0022] Figure 12 is a flowchart of a method of designing an integrated circuit showing some example embodiments according to the inventive concept;

[0023] Figure 13 is a flowchart of a method of designing an integrated circuit showing some example embodiments according to the inventive concept;

[0024] Figure 14 is a flowchart of a method of manufacturing an integrated circuit showing some example embodiments according to the inventive concept; and

[0025] Figure 15 is a block diagram of a computing system including a memory for storing a program according to some example embodiments according to the inventive concept.

[0026] For ease of explanation, the accompanying drawings herein may not be drawn to scale, and their components may be enlarged or reduced. Detailed Description

[0027] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used for the same elements, and redundant descriptions thereof will be omitted. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It should be noted that although no specific description is made, aspects described with respect to one embodiment can be combined in different embodiments. That is, all embodiments and / or features of any embodiment can be combined in any manner and / or combination.

[0028] Figure 1 is a flowchart showing a method of designing an integrated circuit according to some example embodiments of the inventive concept. Figure 1 The flowchart S10 may include blocks S100 to S500.

[0029] Referring to Figure 1 , a method of designing an integrated circuit according to some embodiments of the inventive concept, as an operation for designing a layout of an integrated circuit, may be performed by using a tool for designing an integrated circuit. In some embodiments, the tool for designing an integrated circuit may be a program (e.g., Figure 15 's 1400_1), which may include a plurality of instructions to be executed by a processor (e.g., Figure 15 's 1100). Accordingly, the method of designing an integrated circuit may be referred to as a computer-implemented method for integrated circuit design.

[0030] In block S100, a synthesis operation may be performed. For example, block S100 may be performed by a processor by using a synthesis tool. "Synthesis" may be an operation of generating a netlist by converting input data about an integrated circuit into a hardware form of logic gates, which may be referred to as "logic synthesis". "Input data" may be an abstract form of the behavior of an integrated circuit, e.g., data defined at the register transfer level (RTL). A "netlist" may be generated from the RTL code by using a standard cell library (e.g., Figure 14 's D20), and the "netlist" may be a gate-level netlist. In an example embodiment, the RTL code may be provided as an input file to the synthesis tool, and the netlist may be output as an output file in the synthesis tool.

[0031] In block S200, a layout and routing (hereinafter referred to as "placement & routing (P&R)") of standard cells defining an integrated circuit may be performed. For example, block S200 may be performed by a processor by using a P&R tool. By using a standard cell library (e.g., Figure 14In D20), by laying out standard cells that define an integrated circuit according to a netlist and routing the nets included in the laid-out standard cells, layout data for the integrated circuit can be generated. For example, the layout data can be data in the Graphic Design System (GDS) II format. In an exemplary embodiment, the netlist can be provided to a P&R tool as an input file, and layout data can be output as an output file in the P&R tool.

[0032] In this document, a "net" can represent an equipotential in an equivalent circuit diagram of an integrated circuit and can correspond to an interconnect in the integrated circuit layout. An interconnect can correspond to a wiring structure including at least one metal layer and at least one via that are electrically connected to each other. Thus, the interconnect can electrically connect the output pin of a standard cell to the input pin, and by creating the interconnect, the standard cell can be routed.

[0033] In block S300, timing analysis of the integrated circuit can be performed. For example, block S300 can be performed by a processor using a static timing analysis (STA) tool. Timing analysis data D11 can be output as an output file in the STA tool.

[0034] "Timing analysis" can refer to the following operations: determining whether the timing paths included in the integrated circuit satisfy timing constraints, and then, based on the result of the determination of the timing path timing constraints, selecting, among the timing paths, the timing paths or timing critical paths in which the total timing delay from the input (i.e., the starting point) to the output (i.e., the ending point) of the integrated circuit exceeds the timing constraints. The timing constraints can include setup timing constraints and hold timing constraints.

[0035] In block S400, P&R can be re-executed based on the shape of the nanosheets included in the standard cells. When P&R is re-executed, layout data regarding the integrated circuit can be regenerated. For example, block S400 can be performed by a processor by referring to the standard cell library D20 and using a P&R tool.

[0036] In an exemplary embodiment, among the standard cells laid out based on the timing analysis data D11, the standard cells included in the timing critical path can be extracted as target cells, and the shape of the nanosheets of the target cells can be compared with the shape of the nanosheets of the adjacent cells laid out adjacent to the target cells. According to the comparison result, the adjacent cells laid out adjacent to the target cells can be replaced with other cells, or fill cells can be inserted between the target cells and the adjacent cells. Block S400 will be described in detail with reference to the accompanying drawings such as Figure 4 of.

[0037] When re - performing P&R, layout data of the integrated circuit can be regenerated, and in block S500, timing analysis of the integrated circuit can be re - performed by using the regenerated layout data. For example, block S500 can be executed by a processor by using a STA tool.

[0038] The method of manufacturing an integrated circuit according to some embodiments of the inventive concept can reduce process variations that may occur based on the shape of nanosheets included in standard cells by re - performing the P&R operation based on the shape of the nanosheets. Accordingly, the possibility of violating the timing constraints of the integrated circuit can be reduced, and thus, the timing characteristics can be improved.

[0039] Figure 2 is a flowchart showing a method of designing an integrated circuit according to some example embodiments of the inventive concept, and further shows Figure 1 an example embodiment of block S400 of Figure 2 The flowchart S400 of

[0040] Referring to Figure 2 , in block S410, target cells included in a timing - critical path can be extracted by using timing - analysis data D11. For example, in a timing - analysis operation (e.g., Figure 1 S300 of

[0041] ), a timing - critical path having a time slack lower than a reference can be extracted from timing paths included in the integrated circuit, and in block S410, target cells can be extracted among the standard cells included in the extracted timing - critical path. For example, a clock path can be included in the timing - critical path. Figure 1 Figure 14 In block S420, it can be determined whether the width of the nanosheets of the extracted target cells is the same as the width of the nanosheets of adjacent cells adjacent to the layout of the target cells. For example, the width of the nanosheets of a first adjacent cell adjacent to the layout of the target cell in a first direction (e.g., +X direction) can be compared with the width of the nanosheets of the target cell, and the width of the nanosheets of a second adjacent cell adjacent to the layout of the target cell in a direction opposite to the first direction (e.g., -X direction) can be compared with the width of the nanosheets of the target cell. When the width of the nanosheets of the extracted target cells is the same as the width of the nanosheets of adjacent cells adjacent to the layout of the target cells, block S400 can be terminated, and processing operations of the integrated circuit can be performed according to the layout data (e.g.,

[0042] D30 inWhen the width of the nanosheet of the extracted target cell is different from the width of the nanosheet of an adjacent cell adjacent to the layout of the target cell, at block S430, it is possible to determine whether the adjacent cell of the target cell is included in a timing critical path by using timing analysis data D11. When the adjacent cell of the target cell is not included in the timing critical path, at block S440, the adjacent cell can be replaced with a standard cell that can perform the same or similar functions as the adjacent cell and can have the same shape as the target cell in the adjacent region. The replaced standard cell can be re-layout adjacent to the target cell. For example, when the width of the nanosheet of a first adjacent cell adjacent to the layout of the target cell in the +X direction is different from the width of the nanosheet of the target cell, and the first adjacent cell is not included in the timing critical path, the first adjacent cell can be replaced with a standard cell that can perform the same or similar functions as the first adjacent cell and can include a nanosheet having the same width as the nanosheet of the target cell in the adjacent region.

[0043] When the adjacent cell of the target cell is included in the timing critical path, at block S450, a fill cell can be inserted between the target cell and the adjacent cell. For example, when the width of the nanosheet of the adjacent cell is different from the width of the nanosheet of the target cell and the adjacent cell is included in the timing critical path, a fill cell can be inserted between the target cell and the adjacent cell. In some embodiments, the fill cell can include a nanosheet that has the same shape as the nanosheet of the target cell in the adjacent region adjacent to the target cell and has the same shape as the nanosheet of the adjacent cell in the adjacent region adjacent to the adjacent cell.

[0044] When the adjacent cell is included in the timing critical path and the adjacent cell is replaced with another cell, the timing characteristics of the timing critical path including the adjacent cell can change in the direction of increasing the size of the timing margin. Therefore, by inserting a fill cell between the adjacent cell and the target cell, it is possible to reduce or prevent the timing characteristics of the timing critical path including the adjacent cell from changing excessively.

[0045] However, the method of manufacturing an integrated circuit according to the inventive concept is not limited to performing the operations of blocks S430, S440, and S450. The method of manufacturing an integrated circuit according to some embodiments of the inventive concept may further include: if the width of the nanosheet of the extracted target cell is different from the width of the nanosheet of the adjacent cell, inserting a fill cell between the target cell and the adjacent cell without checking whether the adjacent cell of the target cell is included in the timing critical path.

[0046] At block S460, the interconnects can be re-generated according to the layout of the changed standard cell. Therefore, the layout data can be re-generated.

[0047] Figure 3 is a top view of units CT, CPR, and CPL included in an integrated circuit showing some example embodiments according to the inventive concept. Figure 4 is a cross-sectional view taken along line Y1-Y2 in Figure 3 .

[0048] As used herein, the plane formed by the X-axis and the Y-axis may be referred to as a horizontal plane, and a component disposed in the +Z direction with respect to another component may be referred to as being above the other component, and a component disposed in the -Z direction with respect to another component may be referred to as being below or beneath the other component. In the drawings, for ease of illustration, only some layers may be shown, and for ease of understanding, vias may be shown even though they are located beneath the patterns of the metal layers.

[0049] Referring to Figure 3 and Figure 4 , the integrated circuit may include a target unit CT, a first adjacent unit CPR, and a second adjacent unit CPL. The first adjacent unit CPR may be disposed adjacent to the target unit CT in the +X direction, and the second adjacent unit CPL may be disposed adjacent to the target unit CT in the -X direction. That is, for example, the first adjacent unit CPR may be disposed on the right side of the target unit CT, and the second adjacent unit CPL may be disposed on the left side of the target unit CT. In an example embodiment, the target unit CT may be a standard cell included in a timing critical path.

[0050] A diffusion break defining the standard cell may be formed between the target unit CT, the first adjacent unit CPR, and the second adjacent unit CPL. The diffusion break may electrically insulate the target unit CT, the first adjacent unit CPR, and the second adjacent unit CPL from each other. The diffusion break may include a dual diffusion break (DDB) and a single diffusion break (SDB) based on its structure. In an example embodiment, the diffusion break included in the integrated circuit may be a single diffusion break.

[0051] The target unit CT, the first adjacent unit CPR, and the second adjacent unit CPL may be formed on a substrate SUB and may include a first nanosheet N1 and a second nanosheet N2 extending in the X-axis direction. In an example embodiment, the first nanosheet N1 may be disposed on an N-well NW doped with an N-type impurity.

[0052] The first nanosheet N1 and the second nanosheet N2 can be used as the channel of a transistor. For example, the first nanosheet N1 can be doped with an N-type impurity and can form part of a P-channel metal-oxide-semiconductor (PMOS) transistor. In contrast, the second nanosheet N2 can be doped with a P-type impurity and can form part of an N-channel metal-oxide-semiconductor (NMOS) transistor. In an exemplary embodiment, the first nanosheet N1 and the second nanosheet N2 can include Si, Ge, or SiGe. In an exemplary embodiment, the first nanosheet N1 and the second nanosheet N2 can include InGaAs, InAs, GaSb, InSb, or a combination thereof.

[0053] Both the first nanosheet N1 and the second nanosheet N2 can include patterns formed in a plurality of layers stacked in the Z direction. For example, both the first nanosheet N1 and the second nanosheet N2 can include a layer having a conductive channel material. In Figure 4 , the first nanosheet N1 is shown as including a pattern in three layers formed on a substrate SUB, but embodiments of the inventive concept are not limited thereto. The number of patterns formed on different layers included in the first nanosheet N1 and the second nanosheet N2 can be variably changed.

[0054] The first nanosheet N1 included in the target cell CT can extend in the X-axis direction and have a first width W1 in the Y-axis direction. The second nanosheet N2 included in the target cell CT can extend in the X-axis direction and have a second width W2 in the Y-axis direction. In an exemplary embodiment, the first width W1 can be the same as the second width W2.

[0055] The first nanosheet N1 included in the first adjacent cell CPR can extend in the X-axis direction and have a first width WR1 in the Y-axis direction. The second nanosheet N2 included in the first adjacent cell CPR can extend in the X-axis direction and have a second width WR2 in the Y-axis direction. The first nanosheet N1 included in the second adjacent cell CPL can extend in the X-axis direction and have a first width WL1 in the Y-axis direction. The second nanosheet N2 included in the second adjacent cell CPL can extend in the X-axis direction and have a second width WL2 in the Y-axis direction.

[0056] In an exemplary embodiment, the widths of the nanosheets of units arranged adjacent to each other may be the same. For example, the first width W1 of the first nanosheet N1 of the target unit CT may be the same as the first width WR1 of the first nanosheet N1 of the first adjacent unit CPR, and may be the same as the first width WL1 of the first nanosheet N1 of the second adjacent unit CPL. Additionally, for example, the second width W2 of the second nanosheet N2 of the target unit CT may be the same as the second width WR2 of the second nanosheet N2 of the first adjacent unit CPR, and may be the same as the second width WL2 of the second nanosheet N2 of the second adjacent unit CPL. In the exemplary embodiment, in Figure 1 the block S200 of Figure 2 when laying out and routing the target unit CT, the first adjacent unit CPR, and the second adjacent unit CPL, the operations of the blocks S430 to S460 of

[0057] may not be performed. The target unit CT, the first adjacent unit CPR, and the second adjacent unit CPL may include gate lines GL formed on the substrate SUB and extending in the Y-axis direction. In the exemplary embodiment, the gate lines GL may include a layer containing a work function metal and a gap-fill metal film. For example, the layer containing a work function metal may include one or more of the following metals: Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and Pd, and the gap-fill metal film may include a W film and / or an Al film. In the exemplary embodiment, the gate lines GL may include a stacked structure of TiAlC / TiN / W, a stacked structure of TiN / TaN / TiAlC / TiN / W, and / or a stacked structure of TiN / TaN / TiN / TiAlC / TiN / W.

[0058] The gate lines GL may be formed to be close to or surround a part of the first nanosheet N1 and the second nanosheet N2. A gate insulating film GI may be formed between the gate lines GL and the first nanosheet N1. In the exemplary embodiment, the gate insulating film GI may include a silicon oxide film, a silicon oxynitride film, a high-k dielectric film having a higher dielectric constant than the silicon oxide film, or a combination thereof. For example, the gate insulating film GI may include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconia, alumina, an HfO2 - Al2O3 alloy, or a combination thereof, but the embodiments of the inventive concept are not limited thereto.

[0059] To supply power to the units, power lines extending in the X-axis direction may be laid out. For example, the target unit CT, the first adjacent unit CPR, and the second adjacent unit CPL may share the first power line PL1 and the second power line PL2, and may be powered through the first power line PL1 and the second power line PL2. In Figure 3Among them, the first power line PL1 and the second power line PL2 are shown and described as patterns of the M1 layer, but the exemplary embodiments of the inventive concept are not limited thereto. In an exemplary embodiment, the power lines may be formed as patterns of a wiring layer (e.g., M2 layer) located above the M1 layer. In an exemplary embodiment, a first power supply voltage VDD may be applied to the first power line PL1, and a second power supply voltage VSS may be applied to the second power line PL2.

[0060] Figure 5A is a top view showing a standard cell CT, a first adjacent cell CPRa, and a second adjacent cell CPL included in an integrated circuit according to an exemplary embodiment of the inventive concept, and further shows Figure 2 an exemplary embodiment of the block S420. Figure 5B is a diagram showing that the timing characteristics of a target unit change based on the shape of nanosheets of adjacent units according to some embodiments of the inventive concept. Figure 6 is a top view showing a unit CT, CPRa, CF, and CPL included in an integrated circuit according to some exemplary embodiments of the inventive concept, and further shows Figure 2 an exemplary embodiment of the block S450. In Figure 5A and Figure 6 the description, a repeated description of reference numerals identical to those of Figure 3 will be omitted.

[0061] Referring to Figure 5A , in a P&R operation (e.g., Figure 1 S200), the target unit CT may be placed, the first adjacent unit CPRa may be placed adjacent to the target unit CT in the +X direction starting from the target unit CT, and the second adjacent unit CPL may be placed adjacent to the target unit CT in the -X direction starting from the target unit CT. The first nanosheet N1 included in the first adjacent unit CPRa may extend in the X-axis direction and have a first width WR1a in the Y-axis direction, and the second nanosheet N2 included in the first adjacent unit CPRa may extend in the X-axis direction and have a second width WR2 in the Y-axis direction.

[0062] In an exemplary embodiment, the first width W1 of the first nanosheet N1 of the target unit CT may be different from the first width WR1a of the first nanosheet N1 of the first adjacent unit CPRa. For example, the first width WR1a of the first nanosheet N1 of the first adjacent unit CPRa may be smaller than the first width W1 of the first nanosheet N1 of the target unit CT. A jog pattern may be formed in the first nanosheet N1 in an adjacent region A where the target unit CT and the first adjacent unit CPRa are adjacent to each other.

[0063] However, embodiments of the inventive concept are not limited thereto, and a first width WR1a of a first nanosheet N1 of a first adjacent unit CPRa may be greater than a first width W1 of a first nanosheet N1 of a target unit CT. In other embodiments, a second width W2 of a second nanosheet N2 of the target unit CT may be different from a second width WR2a of a second nanosheet N2 of the first adjacent unit CPRa.

[0064] According to the comparative example, if a processing operation (e.g., Figure 14 of block S40) on the target unit CT and the first adjacent unit CPRa in which the concavo-convex pattern is formed is performed without performing operation S400, then due to process variations, with respect to the first nanosheet N1 of the target unit CT in operation S10 of the design flow chart of Figure 1 , the width of the first nanosheet N1 of the target unit PCT in the operation of block S40 may be reduced at an adjacent region A. In addition, with respect to the first nanosheet N1 of the first adjacent unit CPRa in operation S10 of the design flow chart of Figure 1 , the width of the first nanosheet N1 of the first adjacent unit PCPRa in the operation of block S40 may be increased at the adjacent region A. That is, in the adjacent region A, the first nanosheet N1 of the target unit PCT may have a first width W1' different from the first width W1 in a region other than the adjacent region A, and the first nanosheet N1 of the first adjacent unit PCPRa may have a first width WR1a' different from the first width WR1a in a region other than the adjacent region A. Accordingly, due to such process variations, the delay of a timing path including the target unit PCT or a timing path including the first adjacent unit PCPRa may be changed, which may result in a violation of the timing constraint of the timing path.

[0065] Referring to Figure 5A and Figure 5B , for example, the target unit PCT may be used as an inverter CTC. A delay D of the target unit PCT that inputs an input signal and then outputs an output signal may be a sum of a delay D0 of the target unit CT without considering process variations and a change in delay (+dD or -dD) according to process variations. Accordingly, when the operation of block S400 is not performed according to the comparative example, the timing characteristics of the timing path analyzed in a timing analysis step (e.g., Figure 1 of S300) may be different from the timing characteristics of the actual timing path after the integrated circuit is manufactured. In particular, for a timing critical path, the possibility of violating the timing constraint may be further increased.

[0066] Referring to Figure 4 and Figure 5A, the target cell CT included in the timing critical path among the standard cells laid out in the P&R box S200 may experience process variations due to the first adjacent cell CPRa in the adjacent layout. Thus, a method of manufacturing an integrated circuit according to some embodiments of the inventive concept may include: re-performing P&R (S400) based on the shapes of the first nanosheet N1 and the second nanosheet N2 included in the target cell CT, the first adjacent cell CPRa, and the second adjacent cell CPL. When the first adjacent cell CPRa is not included in the timing critical path, the first adjacent cell CPRa may be replaced with Figure 3 the first adjacent cell CPR (S440). By replacing Figure 5A the first adjacent cell CPRa with Figure 3 the first adjacent cell CPR, the first width W1 of the first nanosheet N1 of the target cell CT and the first width WR1 of the first nanosheet N1 of the first adjacent cell CPR in the adjacent layout may be equal to each other. Thus, the change in the delay of the target cell CT due to process variations can be reduced.

[0067] However, embodiments of the inventive concept are not limited thereto. A concavo-convex pattern may be formed in the second nanosheet N2 in the adjacent region where the target cell CT and the first adjacent cell CPRa are adjacent to each other, and when the first adjacent cell CPRa is not included in the timing critical path, Figure 5A the first adjacent cell CPRa may be replaced with Figure 3 the first adjacent cell CPR. Thus, the second width WR2 of the second nanosheet N2 of the first adjacent cell CPR may be the same as the second width W2 of the second nanosheet N2 of the target cell CT.

[0068] Referring to Figure 4 , Figure 5A and Figure 6 , when the first width WR1a of the first nanosheet N1 of the first adjacent cell CPRa is different from the first width W1 of the first nanosheet N1 of the target cell CT, and the first adjacent cell CPRa is included in the timing critical path, a fill cell CF may be inserted between the target cell CT and the first adjacent cell CPRa (S450).

[0069] The fill cell CF may include a first nanosheet N1 as follows: the first nanosheet N1 has the same width as the first width W1 of the first nanosheet N1 of the target cell CT in a region adjacent to the target cell CT, and has the same width as the first width WR1a of the first nanosheet N1 of the first adjacent cell CPRa in a region adjacent to the first adjacent cell CPRa. In addition, the fill cell CF may include a second nanosheet N2 as follows: the second nanosheet N2 has the same width as the second width W2 of the second nanosheet N2 of the target cell CT in a region adjacent to the target cell CT, and has the same width as the second width WR2 of the second nanosheet N2 of the first adjacent cell CPRa in a region adjacent to the first adjacent cell CPRa. That is, an uneven pattern may be formed in the first nanosheet N1 in the fill cell CF.

[0070] However, embodiments of the inventive concept are not limited thereto, and even when the second width WR2 of the second nanosheet N2 of the first adjacent cell CPRa is different from the second width W2 of the second nanosheet N2 of the target cell CT, and the first adjacent cell CPRa is included in a timing critical path, a fill cell may be inserted between the target cell CT and the first adjacent cell CPRa. In addition, the fill cell may include a second nanosheet N2 as follows: the second nanosheet N2 has the same width as the second width W2 of the second nanosheet N2 of the target cell CT in a region adjacent to the target cell CT, and has the same width as the second width WR2 of the second nanosheet N2 of the first adjacent cell CPRa in a region adjacent to the first adjacent cell CPRa. That is, an uneven pattern may be formed in the second nanosheet N2 in the fill cell.

[0071] Therefore, a method of manufacturing an integrated circuit according to some embodiments of the inventive concept may reduce process variations that may occur during a processing operation of the integrated circuit due to manufacturing a target cell, and may reduce the possibility of violating a timing constraint of a timing critical path including the target cell CT.

[0072] Figure 7A is a top view of cells CT, CPRb, and CPL included in an integrated circuit according to some example embodiments of the inventive concept, and further shows an example embodiment of Figure 2 the block S420. Figure 7B is a top view of cells CT, CPRb, CFb, and CPL included in an integrated circuit according to some example embodiments of the inventive concept, and further shows an example embodiment of Figure 2 the block S450. In Figure 7A and Figure 7B the description, a repeated description of reference numerals identical to those of Figure 3 will be omitted.

[0073] Referring to Figure 7A , in a P&R operation (e.g., Figure 1 S200), the target cell CT can be laid out, the first adjacent cell CPRb can be laid out adjacent to the target cell CT in the +X direction starting from the target cell CT, and the second adjacent cell CPL can be laid out adjacent to the target cell CT in the -X direction starting from the target cell CT. The first nanosheet N1 included in the first adjacent cell CPRb can extend in the X-axis direction and have a first width WR1a in the Y-axis direction. The second nanosheet N2 included in the first adjacent cell CPRb can extend in the X-axis direction and have a second width WR2a in the Y-axis direction.

[0074] In an exemplary embodiment, the first width W1 of the first nanosheet N1 of the target cell CT can be different from the first width WR1a of the first nanosheet N1 of the first adjacent cell CPRb. For example, the first width WR1a of the first nanosheet N1 of the first adjacent cell CPRb can be smaller than the first width W1 of the first nanosheet N1 of the target cell CT. In an exemplary embodiment, the second width W2 of the second nanosheet N2 of the target cell CT can be different from the second width WR2a of the second nanosheet N2 of the first adjacent cell CPRb. For example, the second width WR2a of the second nanosheet N2 of the first adjacent cell CPRb can be smaller than the second width W2 of the second nanosheet N2 of the target cell CT. However, embodiments of the inventive concept are not limited thereto. The first width WR1a of the first nanosheet N1 of the first adjacent cell CPRb can be greater than the first width W1 of the first nanosheet N1 of the target cell CT, and the second width WR2a of the second nanosheet N2 of the first adjacent cell CPRb can be greater than the second width W2 of the second nanosheet N2 of the target cell CT. Accordingly, an uneven pattern can be formed in each of the first nanosheet N1 and the second nanosheet N2 in the adjacent region where the target cell CT and the first adjacent cell CPRb are adjacent to each other.

[0075] Referring to Figure 4 and Figure 7A , among the standard cells laid out in the P&R operation S200, the target cell CT included in the timing critical path may experience a process variation due to the first adjacent cell CPRb with the adjacent layout. Accordingly, a method of manufacturing an integrated circuit according to some embodiments of the inventive concept can include: re-performing P&R (S400) based on the shapes of the first nanosheet N1 and the second nanosheet N2 included in the target cell CT, the first adjacent cell CPRb, and the second adjacent cell CPL. When the first adjacent cell CPRb is not included in the timing critical path, the first adjacent cell CPRb can be replaced with Figure 3the first adjacent unit CPR (S440). By replacing the first adjacent unit CPRb of Figure 7A with the first adjacent unit CPR of Figure 3 the first width W1 of the first nanosheet N1 of the target unit CT and the first width WR1 of the first nanosheet N1 of the first adjacent unit CPR may be equal to each other, and the second width W2 of the second nanosheet N2 of the target unit CT and the second width WR2 of the second nanosheet N2 of the first adjacent unit CPR may be equal to each other. Accordingly, a change in delay due to process variations associated with the target unit CT can be reduced.

[0076] Referring to Figure 4 、 Figure 7A and Figure 7B when the shapes of the first nanosheet N1 and the second nanosheet N2 of the first adjacent unit CPRb are different from the shapes of the nanosheets N1 and N2 of the target unit CT, and the first adjacent unit CPRb is included in a timing critical path, a fill unit CFb may be inserted between the target unit CT and the first adjacent unit CPRb (S450).

[0077] The fill unit CFb may include the following first nanosheet N1: the first nanosheet N1 has the same width as the first width W1 of the first nanosheet N1 of the target unit CT in a region adjacent to the target unit CT, and has the same width as the first width WR1a of the first nanosheet N1 of the first adjacent unit CPRb in a region adjacent to the first adjacent unit CPRb. In addition, the fill unit CFb may include the following second nanosheet N2: the second nanosheet N2 has the same width as the second width W2 of the second nanosheet N2 of the target unit CT in a region adjacent to the target unit CT, and has the same width as the second width WR2a of the second nanosheet N2 of the first adjacent unit CPRb in a region adjacent to the first adjacent unit CPRb. That is, a concavo-convex pattern may be formed in the first nanosheet N1 and the second nanosheet N2 of the fill unit CFb.

[0078] Figure 8A is a top view of units CT, CPRa, and CPLa included in an integrated circuit according to an exemplary embodiment of the inventive concept, and further shows an exemplary embodiment of Figure 2 the block S420. Figure 8B is a top view of units CT, CPRa, CFR, CFL, and CPLa included in an integrated circuit according to an exemplary embodiment of the inventive concept, and further shows an exemplary embodiment of Figure 2 the block S450. In the descriptions of Figure 8A and Figure 8B a description of will be omitted regarding Figure 3Repeated description of the same reference numerals.

[0079] Referring to Figure 8A , in the P&R operation (e.g., Figure 1 S200), the target cell CT can be laid out, the first adjacent cell CPRa can be laid out adjacent to the target cell CT in the +X direction starting from the target cell CT, and the second adjacent cell CPLa can be laid out adjacent to the target cell CT in the -X direction starting from the target cell CT. The first nanosheet N1 included in the first adjacent cell CPRa can extend in the X-axis direction and have a first width WR1a in the Y-axis direction, and the first nanosheet N1 included in the second adjacent cell CPLa can extend in the X-axis direction and have a first width WL1a in the Y-axis direction.

[0080] In an exemplary embodiment, the first width W1 of the first nanosheet N1 of the target cell CT can be different from the first width WR1a of the first nanosheet N1 of the first adjacent cell CPRa. In an exemplary embodiment, the first width W1 of the first nanosheet N1 of the target cell CT can be different from the first width WL1a of the first nanosheet N1 of the second adjacent cell CPLa. For example, the first width WR1a of the first nanosheet N1 of the first adjacent cell CPRa and the first width WL1a of the first nanosheet N1 of the second adjacent cell CPLa can be less than the second width W1 of the first nanosheet N1 of the target cell CT. Concave-convex patterns can be formed in the first nanosheet N1 in the adjacent regions where the target cell CT and the first adjacent cell CPRa are adjacent to each other and in the adjacent regions where the target cell CT and the second adjacent cell CPLa are adjacent to each other. However, embodiments of the inventive concept are not limited thereto, and the first width WR1a of the first nanosheet N1 of the first adjacent cell CPRa can be greater than the first width W1 of the first nanosheet N1 of the target cell CT, and the first width WL1a of the first nanosheet N1 of the second adjacent cell CPLa can be greater than the first width W1 of the first nanosheet N1 of the target cell CT.

[0081] Referring to Figure 4 and Figure 8A , among the standard cells laid out in the P&R operation of block S200, the target cell CT included in the timing critical path may undergo process variations due to the first adjacent cell CPRa and the second adjacent cell CPLa arranged adjacent to it. Therefore, a method of manufacturing an integrated circuit according to some embodiments of the inventive concept may include: re-performing P&R (S400) based on the shapes of the first nanosheet N1 and the second nanosheet N2 included in the target cell CT, the first adjacent cell CPRa, and the second adjacent cell CPLa. For example, when the first adjacent cell CPRa is not included in the timing critical path, the first adjacent cell CPRa can be replaced withFigure 3 In addition, when the second neighboring cell CPLa is not included in the timing critical path, the second neighboring cell CPLa may be replaced by Figure 3 The second adjacent cell CPL (S440).

[0082] By Figure 8A The first adjacent unit CPRa and the second adjacent unit CPLa are replaced by Figure 3 The first width W1 of the first nanosheet N1 of the target cell CT and the first width WR1 of the first nanosheet N1 of the first neighboring cell CPR and the second neighboring cell CPL may be equal to each other, and the first width W1 of the first nanosheet N1 of the target cell CT and the first width WL1 of the first nanosheet N1 of the second neighboring cell CPL may be equal to each other. Therefore, the change of the delay due to the process variation associated with the target cell CT can be reduced.

[0083] However, embodiments of the inventive concept are not limited thereto, and when the second width W2 of the second nanosheet N2 of the target cell CT is different from the second width WR2 of the second nanosheet N2 of the first neighboring cell CPRa and the first neighboring cell CPRa is not included in the timing critical path, Figure 8A The first adjacent unit CPRa is replaced by Figure 3 In addition, when the second width W2 of the second nanosheet N2 of the target cell CT is different from the second width WL2 of the second nanosheet N2 of the second neighboring cell CPLa and the second neighboring cell CPLa is not included in the timing critical path, Figure 8A The second adjacent unit CPLa is replaced by Figure 3 The second adjacent cell CPL (S440). Figure 4 , Figure 8A and Figure 8B , when the shapes of the nanosheets N1 and N2 of the first adjacent cell CPRa are different from the shapes of the nanosheets N1 and N2 of the target cell CT and the first adjacent cell CPRa is included in the timing critical path, the first filling cell CFR may be inserted between the target cell CT and the first adjacent cell CPRa (S450). In addition, when the shapes of the nanosheets N1 and N2 of the second adjacent cell CPLa are different from the shapes of the nanosheets N1 and N2 of the target cell CT and the second adjacent cell CPLa is included in the timing critical path, the second filling cell CFL may be inserted between the target cell CT and the second adjacent cell CPLa (S450).

[0084] The first fill cell CFR may include a first nanosheet N1 as follows: the first nanosheet N1 has the same width as the first width W1 of the first nanosheet N1 of the target cell CT in a region adjacent to the target cell CT, and has the same width as the first width WR1a of the first nanosheet N1 of the first adjacent cell CPRa in a region adjacent to the first adjacent cell CPRa. The second fill cell CFL may include a first nanosheet N1 as follows: the first nanosheet N1 has the same width as the first width W1 of the first nanosheet N1 of the target cell CT in a region adjacent to the target cell CT, and has the same width as the first width WL1a of the first nanosheet N1 of the second adjacent cell CPLA in a region adjacent to the second adjacent cell CPLA. That is, an uneven pattern may be formed in the first nanosheet N1 in the first fill cell CFR and the second fill cell CFL.

[0085] However, embodiments of the inventive concept are not limited thereto. When the second width W2 of the second nanosheet N2 of the target cell CT is different from the second width WR2 of the second nanosheet N2 of the first adjacent cell CPRa and the first adjacent cell CPRa is included in a timing critical path, a first fill cell CFR may be inserted between the target cell CT and the first adjacent cell CPRa (S450). In such an embodiment, the first fill cell may include a second nanosheet N2 in which an uneven pattern is formed. In addition, when the second width W2 of the second nanosheet N2 of the target cell CT is different from the second width WL2 of the second nanosheet N2 of the second adjacent cell CPLA and the second adjacent cell CPLA is included in a timing critical path, a second fill cell CFL may be inserted between the target cell CT and the second adjacent cell CPLA (S450). In such an embodiment, the second fill cell may include a second nanosheet N2 in which an uneven pattern is formed.

[0086] Figure 9 is a flowchart illustrating a method of designing an integrated circuit according to some example embodiments of the inventive concept, and further illustrates Figure 1 an example embodiment of block S500. Figure 10 is a diagram illustrating an integrated circuit according to some example embodiments of the inventive concept, and further illustrates Figure 9 an example embodiment of flowchart S500. Figure 9 The flowchart S500 may include blocks S501 to S507. For example, the operations of the flowchart S500 may be performed by a processor using an STA tool.

[0087] Referring to Figure 9 and Figure 10, in block S501, timing paths can be extracted from standard cells of multiple layouts. For example, multiple timing paths can include a data path DP, a clock path, etc. In block S501, the data path DP can be selected. Although embodiments of the inventive concept are described with respect to the selection of the data path DP, it should be understood that such embodiments can be equivalently applied to the clock path as well.

[0088] For example, an integrated circuit can include a first unit C1 to a fifth unit C5, and the data path DP can be defined as a timing path from the clock pin of the first unit C1, which is a launch flip-flop, to the data input pin of the fifth unit C5, which is a capture flip-flop. In Figure 10 this, for ease of description, the second unit C2 to the fourth unit C4 are shown as inverters, but according to different embodiments of the inventive concept, the second unit C2 to the fourth unit C4 can be implemented using various types of logic gates. In addition, although Figure 10 it is shown that four units (the first unit C1 to the fourth unit C4) are included in the data path DP, embodiments of the inventive concept are not limited thereto, and in various embodiments of the inventive concept, the number of units included in the data path DP can be different.

[0089] In block S503, the unit delay of each target unit included in the timing path can be extracted by using a timing model D12. For example, the delay of each of the first unit C1 to the fourth unit C4 included in the data path DP can be extracted, that is, the first delay D1, the second delay D2, the third delay D3, and the fourth delay D4.

[0090] In an example embodiment, the timing model D12 can include the timing characteristic information of each standard cell, and can include the timing characteristic information reflecting LLE through adjacent cells adjacent to the layout of each standard cell. For example, the timing model D12 can be generated by using a simulation tool (e.g., spice (Simulation program with integrated circuit emphasis)) to extract the spice netlist from the layout of the standard cell and extract the timing characteristics of the standard cell (e.g., delay characteristics, capacitance of input / output, etc.). Specifically, the timing model D12 can be generated from a layout including the standard cell and a dummy wiring structure surrounding the standard cell (e.g., back-end-of-line (BEOL), front-end-of-line (FEOL)), and thus, the timing model D12 can reflect the LLE of the standard cell through the dummy wiring structure.

[0091] In block S505, by using the LLE variation model D13, the cell delay of each target cell can be corrected based on the shape of the nanosheets of the adjacent cells of the target cell. In an exemplary embodiment, the LLE variation model D13 may include a correction factor (e.g., a derating factor) for the cell delay of a standard cell according to the shape of the nanosheets of the adjacent cells adjacent to the standard cell layout. In block S505, the correction factor corresponding to each target cell can be obtained from the LLE variation model D13, and the cell delay of each target cell can be corrected by using the obtained correction factor. For example, the first correction factor a1 to the fourth correction factor a4 corresponding to the first cell C1 to the fourth cell C4 included in the data path DP can be obtained by using the LLE variation model D13. By using the first correction factor a1 to the fourth correction factor a4, the delay of each cell included in the data path DP can be corrected, and the corrected first delay a1·D1, the corrected second delay a2·D2, the corrected third delay a3·D3, and the corrected fourth delay a4·D4 can be extracted.

[0092] In an exemplary embodiment, when the width of the nanosheet of the standard cell is the same as the width of the nanosheet of the adjacent cell, the correction factor may be 1, and the greater the difference between the width of the nanosheet of the standard cell and the width of the nanosheet of the adjacent cell, the smaller the correction factor and the farther away from 1. When the shape of the nanosheet of the target cell is different from the shape of the nanosheet of the adjacent cell adjacent to the target cell layout, due to process variations, the cell delay of the target cell may be different from the cell delay extracted in block S503. Therefore, by using the LLE variation model D13, the cell delay of each target cell can be corrected based on the shapes of the nanosheets of the target cell and the adjacent cell.

[0093] In block S507, the delay of the timing path can be calculated by using the corrected cell delay of each target cell. In an exemplary embodiment, the delay of the timing path can be calculated by adding the corrected cell delays of each target cell. For example, the delay of the data path DP can be calculated by adding the corrected first delay a1·D1, the corrected second delay a2·D2, the corrected third delay a3·D3, and the corrected fourth delay a4·D4. The method of manufacturing an integrated circuit according to some embodiments of the inventive concept can correct the delay of each target cell based on the shapes of the nanosheets of the target cell and the adjacent cell included in the timing path, thereby more accurately extracting the delay of the timing path. Therefore, the timing analysis of the integrated circuit can be more accurate.

[0094] Figure 11A and Figure 11B are diagrams illustrating some exemplary embodiments according to the inventive concept Figure 9Diagram of the LLE variation model D13.

[0095] Referring to Figure 11A , the LLE variation model D13 may include a first lookup table D13a. The first lookup table D13a may include information about cell delay correction factors a11 to a14, a21 to a24, a31 to a34, and a41 to a44 of a specific standard cell according to the types of adjacent cells adjacent to the specific standard cell layout. For example, the first lookup table D13a may include information about correction factors a11 to a14, a21 to a24, a31 to a34, and a41 to a44, and the correction factors a11 to a14, a21 to a24, a31 to a34, and a41 to a44 may vary based on a first adjacent cell and a second adjacent cell, where the first adjacent cell is arranged adjacent to the right side (e.g., +X direction) of a specific standard cell, and the second adjacent cell is arranged adjacent to the left side (e.g., -X direction) of the specific standard cell. Each first adjacent cell included in the first lookup table D13a may include nanosheets having different shapes, and each second adjacent cell included in the first lookup table D13a may include nanosheets having different shapes.

[0096] Referring to Figure 11B , the LLE variation model D13 may include a second lookup table D13b. The second lookup table D13b may include information about cell delay correction factors a11' to a14', a21' to a24', a31' to a34', and a41' to a44' of a specific standard cell according to the nanosheets of adjacent cells adjacent to the specific standard cell layout. For example, the second lookup table D13b may include information about correction factors a11' to a14', a21' to a24', a31' to a34', and a41' to a44', and the correction factors a11' to a14', a21' to a24', a31' to a34', and a41' to a44' may vary according to the widths of the nanosheets of the first adjacent cell and the second adjacent cell, where the first adjacent cell is arranged adjacent to the right side (e.g., +X direction) of a specific standard cell, and the second adjacent cell is arranged adjacent to the left side (e.g., -X direction) of the specific standard cell.

[0097] Referring to Figure 11A and Figure 11B , a method of manufacturing an integrated circuit according to some embodiments of the inventive concept may correct the cell delay of each target cell included in a timing path by using at least one of the first lookup table D13a and the second lookup table D13b. Accordingly, the delay of the timing path may be extracted more accurately, and the timing analysis of the integrated circuit may be more accurate.

[0098] Figure 12A flowchart showing a method of designing an integrated circuit according to some example embodiments of the inventive concept. Figure 12 The flowchart S10a may include block S100, block S200, block S250, and block S300. In Figure 12 the description, repeated descriptions of reference numerals identical to those of Figure 1 the drawings will be omitted.

[0099] Referring to Figure 12 , in block S100, a synthesis operation may be performed, and in block S200, P&R may be performed on standard cells defining the integrated circuit. After performing the operation of block S200, in block S250, P&R may be re - performed based on the shape of nanosheets included in the standard cells. For example, block S250 may be performed by a processor using a P&R tool.

[0100] In an example embodiment, in block S250, standard cells included in a clock path among the standard cells laid out in block S200 may be extracted as target cells, and the shape of the nanosheets of the target cells may be compared with the shape of the nanosheets of adjacent cells laid out adjacent to the target cells. Filler cells may be inserted between the target cells and the adjacent cells according to the comparison result. Example operations of block S250 will be described in detail with reference to Figure 13 .

[0101] In block S300, timing analysis of the integrated circuit may be performed, and the analysis result may be generated as timing analysis data. The timing analysis may be performed based on layout data generated according to the re - performed P&R. In an example embodiment, block S300 may include Figure 9 block S500. In an example embodiment, after performing the operation of block S300, the operations of Figure 1 and Figure 4 block S400 may be further performed.

[0102] According to some embodiments of the inventive concept, a method of manufacturing an integrated circuit may reduce process variations that may occur based on the shape of nanosheets by re - performing a P&R operation based on the shape of nanosheets included in standard cells. Accordingly, the possibility of violating the timing constraints of the integrated circuit may be reduced, thereby improving timing characteristics.

[0103] Figure 13 A flowchart showing a method of designing an integrated circuit according to some example embodiments of the inventive concept, and further showing an example embodiment of Figure 12 block S250. Figure 13 Step S250 of

[0104] Referring to Figure 13, at block S251, target cells included in the clock path can be extracted. For example, the clock path can be extracted by using the layout data generated at block S200 of Figure 12 , and the target cells included in the clock path can be extracted.

[0105] At block S253, the width of the nanosheet of the extracted target cell can be compared with the width of the nanosheet of an adjacent cell adjacent to the layout of the target cell. For example, the width of the nanosheet of a first adjacent cell that can be adjacent to the layout of the target cell in the +X direction can be compared with the width of the nanosheet of the target cell, and the width of the nanosheet of a second adjacent cell that can be adjacent to the layout of the target cell in the -X direction can be compared with the width of the nanosheet of the target cell. When the width of the nanosheet of the extracted target cell is the same as the width of the nanosheet of an adjacent cell adjacent to the layout of the target cell, the operation of block S253 can be terminated, and the operation of Figure 12 block S300 can be executed.

[0106] When the width of the nanosheet of the extracted target cell is different from the width of the nanosheet of an adjacent cell adjacent to the layout of the target cell, at block S255, fill cells can be inserted between the target cell and the adjacent cell. For example, when the width of the nanosheet of a first adjacent cell that is adjacent to the layout of the target cell in the +X direction is different from the width of the nanosheet of the target cell, a fill cell (e.g., Figure 6 CF of Figure 7B CFb of Figure 8B and CFR of Figure 8B one of them) can be inserted between the target cell and the first adjacent cell. In addition, for example, when the width of the nanosheet of a second adjacent cell that is adjacent to the layout of the target cell in the -X direction is different from the width of the nanosheet of the target cell, a fill cell (e.g., CFL of

[0107]

[0108] Figure 14 is a flowchart showing a method of manufacturing an integrated circuit according to some example embodiments of the inventive concept.

[0109] The standard cell library D20 can include information about a plurality of standard cells, e.g., function information, characteristic information, layout information, etc. For example, it can include information about the following cells: Figure 3 standard cells CT, CPR, and CPL of Figure 5A first adjacent cell CPRa of Figure 6 fill cell CF ofFigure 7A the first adjacent unit CPRb, Figure 7B the padding unit CFb, Figure 8A the second adjacent unit CPLa, and Figure 8B the padding units CFR and CFL.

[0110] Referring Figure 14 , in block S10 ( Figure 1 the flowchart S10), operations for designing an integrated circuit can be performed, and layout data D30 can be generated. For example, such operations can be performed in a processor by using a tool for designing an integrated circuit. In an exemplary embodiment, Figure 14 block S10 can include Figure 1 the flowchart S10 and Figure 12 operations in at least one of the flowchart S10a.

[0111] In block S20, optical proximity correction (OPC) can be performed. OPC can refer to an operation of forming a pattern having a desired shape by correcting a distortion phenomenon (such as refraction) caused by light characteristics in a lithography process included in a semiconductor process for manufacturing an integrated circuit, and the pattern on the mask can be determined by applying OPC to the layout data D30.

[0112] In block S30, an operation of manufacturing a mask can be performed. For example, patterns formed in multiple layers can be defined according to the layout data D30, and at least one mask (or photomask) for forming the patterns in each of the multiple layers can be manufactured.

[0113] In block S40, an operation of manufacturing an integrated circuit can be performed. For example, an integrated circuit can be manufactured by patterning multiple layers by using at least one mask manufactured in block S30. Block S40 can include operations of blocks S41 and S42.

[0114] In block S41, a FEOL process can be performed. The FEOL process can refer to a process of forming individual devices (such as transistors, capacitors, resistors, etc.) on a substrate during the manufacture of an integrated circuit. For example, the FEOL process can include operations such as planarizing and cleaning a wafer, forming trenches, forming wells, forming gate lines, and forming source and drain electrodes.

[0115] At block S42, a BEOL process may be performed. The BEOL process may refer to a process of interconnecting various devices (e.g., transistors, capacitors, resistors, etc.) during the manufacture of an integrated circuit. For example, the BEOL process may include: siliciding gate regions, source regions, and drain regions, adding dielectrics, planarizing, forming vias, adding metal layers, forming vias, forming a passivation layer, etc. Thereafter, the integrated circuit may be packaged in a semiconductor package and may be used as part of various applications.

[0116] Figure 15 FIG. is a block diagram of a computing system 1000 including a memory for storing a program according to some example embodiments of the inventive concept. According to an example embodiment of the inventive concept, the operations of designing an integrated circuit as Figure 1 flowchart S10 and Figure 12 flowchart S10a of

[0117] The computing system 1000 may include a stationary computing system, such as a desktop computer, a workstation, a server, etc., or may be a portable computing system, such as a laptop computer. As Figure 15 shown, the computing system 1000 may include a central processing unit (CPU) 1100, an input / output device 1200, a network interface 1300, a random access memory (RAM) 1400, a read-only memory (ROM) 1500, and a storage device 1600. The CPU 1100, the input / output device 1200, the network interface 1300, the RAM 1400, the ROM 1500, and the storage device 1600 may be connected to a bus 1700 and may communicate with each other via the bus 1700.

[0118] The CPU 1100 may be referred to as a processing unit or a processor and may include cores capable of executing any instruction set (e.g., Intel Architecture-32 (IA-32), 64-bit extended IA-32, x86-64, Power PC, Sparc, MIPS, ARM, IA-64, etc.), such as a microprocessor, an application processor (AP), a digital signal processor (DSP), or a graphics processing unit (GPU). For example, the CPU 1100 may access a memory such as the RAM 1400 or the ROM 1500 via the bus 1700 and may execute instructions stored in the RAM 1400 or the ROM 1500. As Figure 15As shown, according to some example embodiments of the inventive concept, the RAM 1400 may store the program 1400_1 or at least a part thereof, and the program 1400_1 may cause the CPU 1100 to perform one or more operations for designing an integrated circuit. That is, the program 1400_1 may include a plurality of instructions executable by the CPU 1100, and the plurality of instructions included in the program 1400_1 may cause the CPU 1100 to perform operations for designing an integrated circuit according to the example embodiments of the inventive concept.

[0119] Even when the power supplied to the computing system 1000 is cut off, the storage device 1600 does not lose the stored data. For example, the storage device 1600 may include non-volatile memories such as electrically erasable programmable read-only memory (EEPROM), flash memory, phase change random access memory (PRAM), resistive random access memory (RRAM), nano-floating gate memory (NFGM), polymer random access memory (PoRAM), magnetic random access memory (MRAM), and ferroelectric random access memory (FRAM), and may also include storage media such as magnetic tapes, optical discs, and magnetic disks. In addition, the storage device 1600 may be removed from the computing system 1000.

[0120] The storage device 1600 may store the program 1400_1, and before the program 1400_1 is executed by the CPU 1100, the program 1400_1 or at least a part thereof from the storage device 1600 may be loaded into the RAM 1400. The storage device 1600 may store files written in a programming language, and the program 1400_1 or at least a part thereof generated by a compiler or the like may be loaded into the RAM 1400.

[0121] The storage device 1600 may store data to be processed by the CPU 1100 or data processed by the CPU 1100. That is, the CPU 1100 may generate new data by processing the data stored in the storage device 1600 according to the program 1400_1, and may store the generated new data in the storage device 1600. For example, the storage device 1600 may store the Figure 1 timing analysis data D11 processed by the program 1400_1, and may store the Figure 14 layout data D30 generated by the program 1400_1.

[0122] The storage device 1600 may store the database 1600_1, and the database 1600_1 may include information for designing an integrated circuit. For example, the database 1600_1 may include Figure 9 the timing model D12 of Figure 9 the LLE change model D13 of Figure 11AThe first lookup table D13a of Figure 11B the second lookup table D13b of Figure 14 and the standard cell library D20 of

[0123] The input / output device 1200 may include input devices such as a keyboard, a pointing device, etc., and may include output devices such as a display device, a printer, etc. For example, a user may trigger or cause the CPU 1100 to execute the program 1400_1 through the input / output device 1200, and may check Figure 1 the timing analysis data D11 of Figure 14 the layout data D30 of

[0124] The network interface 1300 may provide access to a network external or outside the computing system 1000. For example, the network may include multiple computing systems and communication links, where the communication links may include wired links, optical links, wireless links, or any other type of link. The Figure 1 timing analysis data D11 of Figure 14 and / or the layout data D30 of

[0125] Although the inventive concept has been specifically shown and described with reference to embodiments of the inventive concept, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A method of manufacturing an integrated circuit, the method comprising: Generating layout data of the integrated circuit by laying out and routing standard cells that define the integrated circuit, the standard cells including nanosheets; Generating timing analysis data by performing timing analysis of the integrated circuit using the layout data; And Regenerating the layout data of the integrated circuit by re - laying out and re - routing the standard cells that define the integrated circuit based on the timing analysis data and the shape of the nanosheets of the laid - out standard cells; Wherein, the regenerating the layout data of the integrated circuit further comprises: Extracting target cells included in a timing critical path from a plurality of standard cells based on the timing analysis data; When the width of the nanosheets in the adjacent region of the target cell is different from the width of the nanosheets in an adjacent cell adjacent to the target cell in the standard cell, regenerating the layout data of the integrated circuit by re - laying out and re - routing the standard cells.

2. The method of manufacturing an integrated circuit according to claim 1, wherein, The regenerating the layout data of the integrated circuit further comprises: When the width of the nanosheets in the target cell is different from the width of the nanosheets in an adjacent cell adjacent to the target cell in the standard cell, inserting a fill cell between the target cell and the adjacent cell.

3. The method of manufacturing an integrated circuit according to claim 2, wherein, In a first region of the fill cell adjacent to the target cell, a first width of the nanosheets in the fill cell is equal to the width of the nanosheets in the target cell, and in a second region of the fill cell adjacent to the adjacent cell, a second width of the nanosheets in the fill cell is equal to the width of the nanosheets in the adjacent cell.

4. The method of manufacturing an integrated circuit according to claim 2, wherein, The inserting the fill cell comprises: Determining whether the adjacent cell is included in the critical path; and Inserting the fill cell when the adjacent cell is included in the critical path.

5. The method of manufacturing an integrated circuit according to claim 1, wherein, The regenerating the layout data of the integrated circuit further comprises: When the widths of the respective nanosheets in the adjacent regions of the target cell and an adjacent cell adjacent to the target cell in the standard cell are different from each other, replacing the adjacent cell with a standard cell in the standard cell that performs the same function as the adjacent cell and has replacement nanosheets with a width the same as the width of the nanosheets in the adjacent region of the target cell.

6. The method of manufacturing an integrated circuit according to claim 1, wherein, The method further comprises: after regenerating the layout data of the integrated circuit, re - performing the timing analysis of the integrated circuit using the regenerated layout data.

7. The method of manufacturing an integrated circuit according to claim 6, wherein, The re - performing the timing analysis comprises: Extracting timing paths using the regenerated layout data; Extracting the cell delay of each of the standard cells included in the timing paths; Correcting the cell delay based on the shape of the nanosheets in a standard cell adjacent to the standard cell included in the timing path in the standard cell; and The delay of the timing path is calculated by summing the corrected cell delays.

8. The method of manufacturing an integrated circuit according to claim 7, wherein, The correcting the cell delay includes: obtaining a correction factor corresponding to each of the standard cells included in the timing path through a local layout effect variation model; and correcting the cell delay by using the obtained correction factor.

9. The method of manufacturing an integrated circuit according to claim 8, wherein, The local layout effect variation model includes a first look-up table, the first look-up table including information on the cell delay correction factor of the specific standard cell according to the type of the adjacent cells adjacent to the layout of the specific standard cell, and wherein, the correction factor is obtained from the first look-up table.

10. The method of manufacturing an integrated circuit according to claim 8, wherein, The local layout effect variation model includes a second look-up table, the second look-up table including information on the cell delay correction factor of the specific standard cell according to the width of the nanosheets in the adjacent cells adjacent to the layout of the specific standard cell, and wherein, the correction factor is obtained from the second look-up table.

11. A method of manufacturing an integrated circuit, the method including: generating layout data of the integrated circuit by laying out and wiring the standard cells defining the integrated circuit, the standard cells including nanosheets; extracting, based on the layout data, target cells included in a clock path in the standard cells; and regenerating the layout data of the integrated circuit by re-laying out and re-wiring the standard cells defining the integrated circuit based on the shape of the nanosheets in the target cells and the shape of the nanosheets in the adjacent cells adjacent to the layout of the target cells in the standard cells, wherein, the regenerating the layout data of the integrated circuit further includes: when the width of the nanosheets in the target cells is different from the width of the nanosheets in the adjacent cells adjacent to the layout of the target cells, regenerating the layout data of the integrated circuit by re-laying out and re-wiring the standard cells.

12. The method of manufacturing an integrated circuit according to claim 11, wherein, The regenerating the layout data of the integrated circuit further includes: when the width of the nanosheets in the target cells is different from the width of the nanosheets in the adjacent cells adjacent to the layout of the target cells, inserting filling cells between the target cells and the adjacent cells.

13. The method of manufacturing an integrated circuit according to claim 12, wherein, In a first region of the filling cells adjacent to the layout of the target cells, a first width of the nanosheets in the filling cells is equal to the width of the nanosheets in the target cells, and in a second region of the filling cells adjacent to the layout of the adjacent cells, a second width of the nanosheets in the filling cells is equal to the width of the nanosheets in the adjacent cells.

14. The method of manufacturing an integrated circuit according to claim 11, the method further comprising: After regenerating the layout data of the integrated circuit, timing analysis data is generated by performing timing analysis of the integrated circuit by using the regenerated layout data.

15. The method of manufacturing an integrated circuit according to claim 14, wherein, The performing timing analysis includes: extracting timing paths by using the regenerated layout data; extracting the cell delay of each of the standard cells included in the timing paths; Correct the cell delay based on the shape of the nanosheets in the standard cells that are adjacent to the standard cells included in the timing path; and Calculate the delay of the timing path by summing the corrected cell delays.

16. The method of manufacturing an integrated circuit according to claim 15, wherein, The correcting the cell delay includes: obtaining a correction factor corresponding to each of the standard cells included in the timing path through a local layout effect variation model, and correcting the cell delay by using the obtained correction factor.

17. A computing system for manufacturing an integrated circuit, the computing system comprising: A processor; And A memory coupled to the processor and including computer-readable program code embedded in the memory, the computer-readable program code being executable by the processor to perform operations including the following: Generate layout data of the integrated circuit by using a standard cell library to layout and route the standard cells defining the integrated circuit, the standard cells including nanosheets; Perform timing analysis of the integrated circuit by using the layout data to generate timing analysis data; Regenerate the layout data of the integrated circuit by re-layouting and re-routing the standard cells defining the integrated circuit based on the timing analysis data and the shape of the nanosheets of the laid-out standard cells; And Re-perform the timing analysis of the integrated circuit by using the regenerated layout data, Wherein, the re-performing the timing analysis of the integrated circuit includes: Extract timing paths by using the regenerated layout data; Extract the cell delay of each standard cell included in the timing path; Correct the cell delay based on the shape of the nanosheets in the standard cells that are adjacent to the standard cells included in the timing path; and Calculate the delay of the timing path by summing the corrected cell delays.

18. The computing system according to claim 17, wherein, The operations further include re-layouting the standard cells defining the integrated circuit, Wherein, the re-layouting the standard cells includes: Extract target cells included in the timing critical path in the standard cells based on the timing analysis data; and When the width of the nanosheets in the target cells is different from the width of the nanosheets in the adjacent cells adjacent to the target cells in the standard cells, insert fill cells between the target cells and the adjacent cells by using the standard cell library.

19. The computing system according to claim 17, wherein, The operations further include re-layouting the standard cells defining the integrated circuit, Wherein, the re-layouting the standard cells includes: Extract target cells included in the timing critical path in the standard cells based on the timing analysis data; and When the widths of the respective nanosheets in the adjacent regions of the target unit and the adjacent unit adjacent to the target unit in the standard unit are different from each other, replace the adjacent unit with a standard unit in the standard unit: the standard unit performs the same function as the adjacent unit and has replacement nanosheets with widths the same as those of the nanosheets in the adjacent region of the target unit.

20. The computing system according to claim 17, the computing system further includes a local layout effect change model stored in the memory, the local layout effect change model includes at least one of a first look-up table and a second look-up table, and the operation further includes: correcting the cell delay by using the local layout effect change model, wherein the first look-up table includes information about a cell delay correction factor of the specific standard unit according to the type of the adjacent unit adjacent to the layout of the specific standard unit, and wherein the second look-up table includes information about a cell delay correction factor of the specific standard unit according to the width of the nanosheet in the adjacent unit adjacent to the layout of the specific standard unit.

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