Semiconductor device, packaging structure and method for preparing packaging structure

Abstract

The present disclosure provides a semiconductor device, a packaging structure and a method for preparing the packaging structure, which relate to the field of semiconductor packaging technology. The packaging structure includes a chipset, a conductive film layer, a lead and a packaging layer, wherein: the chipset includes a plurality of chip units stacked in a vertical direction, and each chip unit has a groove formed at least at one end; the conductive film layer is conformed to the surface of the groove; the lead is connected to the conductive film layer at one end and extends to the outside of the chip unit at the other end; the packaging layer is at least provided between each chip unit and is used to fix and connect each chip. The packaging structure disclosed in the present disclosure can reduce the size of the packaging structure and increase the storage capacity.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor packaging technology, and in particular to a semiconductor device, a packaging structure, and a method for preparing the packaging structure. Background Art

[0002] With the development of semiconductor technology, the size of semiconductor devices is getting smaller and smaller, and the requirements for the capacity of semiconductor devices are getting higher and higher. Therefore, the preparation of high-capacity, small-size semiconductor components has become the focus of research in recent years. Since semiconductor components are directly exposed to the external environment, it is easy to cause structural damage, so the packaging of semiconductor components is very important.

[0003] In order to increase the capacity of semiconductor components in the packaging structure, it is usually necessary to stack multiple chip units together and connect the chip units to external circuits through wires. However, since the wires need to be bent after being led out to connect to the external circuit, sufficient space needs to be left between two adjacent chip units for the wires to bend, which makes the packaging structure thicker and is not conducive to reducing the size of the packaging structure.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] The purpose of the present disclosure is to overcome the deficiencies in the above-mentioned prior art and to provide a semiconductor device, a packaging structure and a method for preparing the packaging structure, which can reduce the size of the packaging structure and increase the storage capacity.

[0006] According to one aspect of the present disclosure, there is provided a packaging structure, including:

[0007] A chipset, comprising a plurality of chip units stacked in a vertical direction, wherein at least one end of each chip unit is formed with a groove;

[0008] A conductive film layer conforming to the surface of the groove;

[0009] A lead, one end of which is connected to the conductive film layer and the other end of which extends to the outside of the chip unit;

[0010] The packaging layer is at least arranged between the chip units and is used to fix and connect the chip units.

[0011] In an exemplary embodiment of the present disclosure, the lead includes a bump and a wire, the bump is in contact with the conductive film layer, the wire is connected to a side of the bump away from the conductive film layer and extends to the outside of the chip unit.

[0012] In an exemplary embodiment of the present disclosure, the bump is connected to a side wall of the groove, and the wire extends outward along an extension direction of the chip unit.

[0013] In an exemplary embodiment of the present disclosure, the bump is connected to the bottom of the groove, and the wire is bent in the groove and extends outward along the extension direction of the chip unit.

[0014] In an exemplary embodiment of the present disclosure, the conductive film layer extends to the top surface of the chip unit and covers the bonding pad on the top surface of the chip unit.

[0015] In an exemplary embodiment of the present disclosure, the packaging structure further includes:

[0016] A substrate, the chipset is disposed on the substrate, and the encapsulation layer is disposed between the substrate and the chipset, and is used to fix the chipset to the substrate;

[0017] The substrate includes a conductor, and the other end of the lead is connected to the conductor.

[0018] In an exemplary embodiment of the present disclosure, the width of the groove is 10 um to 60 um, and the depth of the groove is 30 um to 60 um.

[0019] In an exemplary embodiment of the present disclosure, the thickness of the encapsulation layer is 10 um.

[0020] According to one aspect of the present disclosure, there is provided a method for preparing a packaging structure, comprising:

[0021] Forming a chipset, wherein the chipset comprises a plurality of chip units stacked in a vertical direction, and each of the chip units has a groove formed at least at one end;

[0022] forming a conductive film layer, wherein the conductive film layer conforms to the surface of the groove;

[0023] forming a lead, wherein one end of the lead is connected to the conductive film layer, and the other end extends to the outside of the chip unit;

[0024] A packaging layer is formed, wherein the packaging layer is at least disposed between the chip units and is used to fix and connect the chip units.

[0025] According to one aspect of the present disclosure, a semiconductor device is provided, comprising any one of the packaging structures described above.

[0026] The semiconductor device, packaging structure and preparation method of the packaging structure disclosed in the present invention, on the one hand, can stack multiple chip units in the vertical direction, which helps to improve the storage capacity. And the packaging layer can be used to fix the connection between two adjacent chip units, so that each chip unit can be sealed independently to avoid signal interference, and each chip unit can be prevented from being polluted or oxidized by external water vapor or impurities. On the other hand, the lead can be connected to the conductive film layer, and the electrical signal in the chip unit can be transmitted to the lead through the conductive film layer, and then the chip unit can be connected to the external circuit through the lead to achieve signal transmission. In this process, since the conductive film is conformed to the surface of the groove, the end of the wire connected to the conductive film layer is also connected to the groove, and it can be bent in the groove. Therefore, there is no need to leave a bending space between two adjacent chip units, and the thickness of the packaging layer between the two adjacent chip units can be reduced, thereby reducing the overall thickness of the packaging structure and reducing the size of the packaging structure.

[0027] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0029] Figure 1 Schematic diagram of the packaging structure in the related art.

[0030] Figure 2 Schematic diagram of the packaging structure of an embodiment of the present disclosure.

[0031] Figure 3 It is a schematic diagram of a chip unit covered with a conductive film layer according to an embodiment of the present disclosure.

[0032] Figure 4 This is a schematic diagram of the lead wire of the first embodiment of the present disclosure.

[0033] Figure 5 This is a schematic diagram of leads in a second embodiment of the present disclosure.

[0034] Figure 6 This is a schematic diagram of leads according to a third embodiment of the present disclosure.

[0035] Figure 7 The present invention is a flowchart of a method for preparing a packaging structure according to an embodiment of the present invention.

[0036] Figure 8 It is a schematic structural diagram of the substrate according to an embodiment of the present disclosure.

[0037] Fig. 9 It is a schematic diagram of the structure after a groove is formed on a substrate according to an embodiment of the present disclosure.

[0038] Fig.10 It is a schematic diagram of the structure of the embodiment of the present disclosure after removing the conductive film layer on the side of the pad away from the groove.

[0039] Fig.11 It is a schematic diagram of the structure of forming chip units by cleaving a substrate in an embodiment of the present disclosure.

[0040] In the figure: 100, substrate; 200, packaging layer; 300, chip unit; 1, chip unit; 11, groove; 12, solder pad; 2, conductive film layer; 3, lead; 31, bump; 32, wire; 4, packaging layer; 5, substrate; 6, solder ball. DETAILED DESCRIPTION

[0041] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present invention will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted.

[0042] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0043] The terms "a", "an", "the" and "said" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to indicate an open-ended inclusive meaning and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc. The terms "first", "second" and "third" are used only as labels and are not intended to limit the quantity of their objects.

[0044] In related technologies, such as Figure 1As shown, the commonly used packaging structure mainly includes a substrate 100, a chip unit 300 and a packaging layer 200. In order to ensure the capacity of the packaging structure, multiple chip units 300 can be stacked on the substrate 100, and two adjacent chip units 300 can be packaged through the packaging layer 200. In order to increase the capacity of the packaging structure without increasing the thickness of the packaging structure, the chip unit 300 usually adopts a method of stacking multiple chips in an offset manner and staggered wiring. However, staggered stacking makes the lateral size of the chip larger when the chip size remains unchanged, and there is no support under the edge area of ​​the chip, so that the chips are all in a suspended state, which is easy to cause cracks.

[0045] The present disclosure provides a packaging structure such as Figure 2 As shown, the packaging structure may include a chipset, a conductive film layer, a lead 3 and a packaging layer, wherein:

[0046] The chip set may include a plurality of chip units stacked in a vertical direction, and each chip unit may have a groove formed at at least one end;

[0047] The conductive film layer can conform to the groove surface;

[0048] One end of the lead 3 may be connected to the conductive film layer, and the other end may extend to the outside of the chip unit;

[0049] The packaging layer may be at least disposed between the chip units and may be used to fix and connect the chip units.

[0050] The packaging structure disclosed in the present invention, on the one hand, can stack multiple chip units in the vertical direction, which helps to increase the storage capacity. And two adjacent chip units can be fixedly connected by the packaging layer, so that each chip unit can be independently sealed to avoid signal interference, and each chip unit can be prevented from being polluted or oxidized by external water vapor or impurities. On the other hand, the lead 3 can be connected to the conductive film layer, and the electrical signal in the chip unit can be transmitted to the lead 3 through the conductive film layer, and then the chip unit can be connected to the external circuit through the lead 3 to achieve signal transmission. In this process, since the conductive film is conformed to the surface of the groove, the end of the wire connected to the conductive film layer is also connected to the groove, and it can be bent in the groove. Therefore, there is no need to leave a bending space between two adjacent chip units, and then the thickness of the packaging layer between two adjacent chip units can be reduced, thereby reducing the overall thickness of the packaging structure and reducing the size of the packaging structure.

[0051] The following is a detailed description of each part of the packaging structure of the embodiment of the present disclosure:

[0052] like Figure 2As shown, the chipset can be used in an integrated circuit. For example, it can be used in a dynamic random access memory (DRAM). In order to achieve a low driving voltage, the size of the DRAM needs to be reduced as much as possible. The chip unit 1 is the core component of the DRAM. During packaging, in order to reduce the size of the DRAM while ensuring the storage capacity, multiple chip units 1 can be stacked in a vertical direction to form a chipset. For example, the number of chip units 1 in the chipset can be 3, 4, 5, 6 or 7. Of course, it can also be other numbers, which are not specifically limited here.

[0053] Each chip unit 1 in the chipset may be a sheet-like structure, and its shape may be rectangular, circular, elliptical or irregular, and is not specifically limited here. The thickness of each chip unit 1 may be the same or different, and is not specifically limited here. The thickness of the chip unit 1 may be 40um to 80um. For example, it may be 40um, 50um, 60um, 70um or 80um. Of course, it may be other thicknesses, which are not listed here one by one. In one embodiment, each chip unit 1 may have the same thickness, and may be 60um. Of course, each chip unit 1 may also be other thicknesses, and is not specifically limited here.

[0054] Each chip unit 1 may be formed with a groove at least at one end. For example, the groove may be formed at one end of the chip unit 1, or at both ends of the chip unit 1, without any special limitation. The width of the groove may be much smaller than the width of the suspended area of ​​the chip unit 100 in the suspended state in the related art, thereby avoiding the chip unit 1 from cracking and extending the service life of the chip unit 1. When the groove is formed at one end of each chip unit 1, in the process of stacking each chip unit 1, the grooves of two adjacent chip units 1 may be aligned in the vertical direction, and the orthographic projection of the chip unit 1 located above in the two adjacent chip units 1 coincides with the orthographic projection of the chip unit located below. Of course, the grooves of two adjacent chip units 1 may also be placed in a left-right offset manner, without any special limitation. When the grooves are formed at both ends of each chip unit 1, in the process of stacking each chip unit 1, the grooves at the left and right ends of the two adjacent chip units 1 may be aligned.

[0055] The groove can be a groove-like structure formed by the top of the chip unit 1 being recessed inward, and its cross-section can be rectangular, trapezoidal, semicircular or irregular, without special limitation here. The recess depth of the groove can be less than the thickness of the chip unit 1. For example, the recess depth can be 30um to 60um. For example, it can be 30um, 40um, 50um or 60um. Of course, it can also be other depths, which are not listed here. The width of the groove can be 10um to 60um. For example, it can be 10um, 20um, 30um, 40um, 50um or 60um. Of course, it can also be other widths, which are not listed here.

[0056] It should be noted that the groove can also be a groove-like structure formed by the inward depression of the side wall of the chip unit 1, and the depression depth can be 10um to 60um, for example, it can be 10um, 20um, 30um, 40um, 50um or 60um; the depression width can be 30um to 60um, for example, it can be 30um, 40um, 50um or 60um. Of course, it can also be other depths or widths, which are not specifically limited here.

[0057] In one embodiment, a groove may be formed at at least one end of each chip unit 1 by using a dry etching process or a wet etching process. Figure 3 As shown, the groove 11 may be a groove-like structure formed by the inward depression of the top of the chip unit 1, the depth of which may be 60um, the width of which may be 30um, the cross-section of which may be an inverted trapezoidal shape, and may have inclined side walls, which helps to reduce angular stress and ensure the signal transmission effect of the chip unit 1. At the same time, it can also be used to increase the contact area between the bump 31 and the conductive film layer 2, so that the lead 3 can be in good contact with the chip unit 1 when in use, thereby ensuring the signal transmission effect.

[0058] The conductive film layer 2 can be conformed to the surface of the groove 11. It can be a thin film formed on the surface of the groove 11. The thickness of the film can range from 0.4um to 10nm. For example, it can be 0.4um, 1um, 4um, 8um or 10um. Of course, it can also be other thicknesses, as long as it can be used to transmit the electrical signal in the chip unit 1, and there is no special limitation here. The material of the conductive film layer 2 can be metal. For example, it can be copper or aluminum. Of course, it can also be other materials that can be used for conductivity, and there is no special limitation here. The conductive film layer 2 can be formed on the side wall of the groove 11 by vacuum evaporation or electroplating. The conductive film layer 2 can also extend to the top surface of the chip unit 1 and can cover the pad 12 on the top surface of the chip unit 1, so that the electrical signal in the pad 12 can be transmitted to the conductive film layer 2, so that the electrical signal in the pad 12 can be transmitted to the external circuit through the conductive film layer 2.

[0059] One end of the lead 3 can be connected to the conductive film layer 2, and the other end can extend to the outside of the chip unit 1. That is, the lead 3 can be connected to the inside of the groove 11 and can be connected to the conductive film layer 2, and can be used to transmit the electrical signal in the conductive film layer 2 to the external circuit. The lead 3 can be made of a conductive material, for example, it can be a metal material, for example, it can be a metal such as tungsten, copper, aluminum, etc., and can also be other metals with good conductive properties, which are not specifically limited here. Of course, the lead 3 can also be other materials, for example, it can also be non-metallic materials such as polysilicon, which are not listed here one by one.

[0060] In one embodiment, if Figure 4-Figure 6 As shown, the lead 3 may include a bump and a wire, wherein:

[0061] The bump can be in contact with the conductive film layer 2 and can be located on the side of the conductive film layer 2 away from the chip unit 1. The bump 31 can be a solder ball formed by a welding process. For example, the bump 31 can be fixed to the conductive film layer 2 by a pressure welding process. Of course, the bump can also be fixedly connected to the conductive film layer 2 by an electroplating process. The connection method between the bump and the conductive film layer 2 is not specifically limited here. In order to ensure the quality of signal transmission, the bump can be a physical structure, which can be circular, square or irregular in shape, and is not specifically limited here. The bump can be a metal material. For example, it can be copper, gold, aluminum or tungsten. Of course, the bump can also be other materials, which are not listed here one by one.

[0062] The convex point can be formed in the groove 11 and does not protrude from the end of the groove 11. For example, it can be formed at the bottom of the groove 11 or on the side wall of the groove 11, which is not particularly limited here. The convex point can be a point-shaped entity or can include multiple point-shaped entities stacked in sequence. In order to avoid contact resistance between multiple point-shaped entities, the multiple point-shaped entities can be an integrated structure.

[0063] The wire can be connected to the side of the bump away from the conductive film layer 2 and can extend to the outside of the chip unit 1. It can be used to transmit the electrical signal received in the bump to the external circuit. Figure 4 As shown, the groove 11 can be a groove-shaped structure formed by the top surface of the chip unit 1 being recessed inward, the bump 31 can be connected to the bottom of the groove 11, the wire 32 can extend from the surface of the bump 31 away from the bottom of the groove 11 to the top surface of the groove 11, and can be bent below the top surface of the groove 11, and can extend to the outside of the chip unit 1 along the lateral extension direction of the chip unit 1, so that no bending space is required between two adjacent chip units 1, and the distance between two adjacent chip units 1 can be reduced, thereby reducing the overall thickness of the packaging structure, thereby achieving the purpose of reducing the size of the packaging structure. In the second embodiment, as Figure 5As shown, the bump 31 can be connected to the side wall of the groove 11, and the wire 32 can extend from the side of the bump 31 away from the side wall of the groove 11 to the outside of the chip unit 1 along the lateral extension direction of the chip unit 1. In the third embodiment, as Figure 6 As shown, the groove 11 may be in an inverted trapezoidal structure, the bump 31 may be connected to the side wall of the groove 11, and the wire 32 may extend from the side of the bump 31 away from the side wall of the groove 11 to the outside of the chip unit 1 along the lateral extension direction of the chip unit 1. At this time, the contact area between the bump 31 and the conductive film layer 2 is large, and the lead 3 can be in good contact with the chip unit 1 when in use, ensuring the signal transmission effect.

[0064] It should be noted that the wire 32 and the bump 31 may be in an integrated structure, or the bump 31 and the wire 32 may be fixed by welding or bonding, etc., which is not particularly limited here.

[0065] In order to avoid the chip units 1 from colliding or wearing each other and affecting the performance of each chip unit 1, the chip units 1 arranged in layers can be fixed to each other through the packaging layer 4. Specifically, the packaging layer 4 may include a multi-layer structure. For example, it may be 2 layers, 3 layers, 4 layers, 5 layers or 6 layers. Of course, it can also be other layers, which are not specifically limited here. In addition, the packaging layer 4 can be at least arranged between two adjacent chip units 1, and can form a sandwich structure with the chip unit 1. The number of packaging layers 4 can be determined according to the number of chip units 1. For example, when there are 3 chip units 1, the number of packaging layers 4 can be at least two layers, and the two layers can be defined as the first packaging layer and the second packaging layer respectively. The first packaging layer can be formed on the first chip unit 1, the second chip unit 1 is fixed on the first packaging layer, and then the second packaging layer is formed on the second chip unit 1. Finally, the third chip unit 1 is fixed on the second packaging layer. Accordingly, when there are 4 chip units 1, the number of packaging layers 4 can be at least 3 layers. Of course, the chip units 1 can also be other numbers, and accordingly, the packaging layer 4 can also be other numbers, which are not specifically limited here.

[0066] like Figure 2 As shown, the encapsulation layer 4 may be provided at least between two adjacent chip units 1, and may be used to fix and connect each chip unit 1. The encapsulation layer 4 may be an encapsulation glue, which may be used to bond two adjacent chip units 1 together, and may prevent the two adjacent chip units 1 from interacting with each other and causing wear, and may also be used to seal each chip unit 1 independently, and prevent it from directly contacting the outside world, and prevent the chip unit 1 from being oxidized by external water vapor and oxidizing substances, thereby extending the service life of the chip unit 1. In one embodiment, the thickness of the encapsulation layer 4 may be 10um. Of course, the encapsulation layer 4 may also be set to other thicknesses according to actual needs, for example, it may also be 5um, 15um, 20um or 25um, etc., and is not specifically limited here.

[0067] The packaging structure of the embodiment of the present disclosure may also include a substrate 5, on which the chipset may be disposed, and a packaging layer 4 may also be disposed between the substrate 5 and the chipset, which may be used to fix the chipset to the substrate 5, and to seal the chip unit 1 at the bottom to prevent the chip unit 1 at the bottom from being exposed to the external environment and being damaged. The substrate 5 may be composed of a polymer material, for example, epoxy resin, and of course, may also be a substrate 5 composed of other polymer materials, which is not particularly limited here.

[0068] The substrate 5 may include a conductor, and the chipset may be fixed outside the conductor so that the other end of the lead 3 may be connected to the conductor, and then the electrical signal may be transmitted to the conductor through the wire 32, and connected to the external circuit through the conductor, so as to transmit the electrical signal to the outside of the package structure. In one embodiment, the groove 11 may be formed at one end of each chip unit 1, and when the grooves 11 of two adjacent chip units 1 are aligned in the vertical direction, the leads 3 may be formed in the grooves 11 of each chip unit 1 that are aligned with each other. At this time, each lead 3 may extend to the same side of the chipset and may be respectively connected to the conductor on the substrate 5. Of course, the grooves 11 of two adjacent chip units 1 may also be placed in a left-right offset position. At this time, the leads 3 of two adjacent chip units 1 may extend to the left and right sides of the chipset and may be respectively connected to the conductor on the substrate 5. In another embodiment, the grooves 11 can be formed at the two ends of each chip unit 1, and the grooves 11 at the left and right ends of two adjacent chip units 1 can be aligned in the vertical direction. At this time, the leads 3 of the two adjacent chip units 1 can extend to the left and right sides of the chip group and can be respectively connected to the conductors on the substrate 5.

[0069] The embodiment of the present disclosure may further include a plurality of solder balls 6 , which may be disposed on a side of the substrate 5 away from the chipset, and the electrical signals in the chip unit 1 may be transmitted to an external circuit via the solder balls 6 .

[0070] The present disclosure also provides a method for preparing a packaging structure. Figure 7 As shown, the preparation method may include:

[0071] Step S110, forming a chipset, wherein the chipset includes a plurality of chip units stacked in a vertical direction, and each of the chip units has a groove formed at at least one end;

[0072] Step S120, forming a conductive film layer, wherein the conductive film layer conforms to the surface of the groove;

[0073] Step S130, forming a lead, wherein one end of the lead is connected to the conductive film layer, and the other end extends to the outside of the chip unit;

[0074] Step S140 , forming a packaging layer, wherein the packaging layer is at least disposed between the chip units and is used to fix and connect the chip units.

[0075] The specific details of the method for preparing the packaging structure according to the embodiment of the present disclosure are described in detail below.

[0076] In step S110 , a chip set is formed. The chip set includes a plurality of chip units 1 stacked in a vertical direction, and a groove 11 is formed at at least one end of each chip unit 1 .

[0077] The chipset can be used in an integrated circuit. For example, it can be used in a dynamic random access memory (DRAM). In order to achieve a low driving voltage, the size of the DRAM needs to be reduced as much as possible. The chip unit 1 is the core component of the DRAM. During packaging, in order to reduce the size of the DRAM while ensuring the storage capacity, multiple chip units 1 can be stacked in a vertical direction to form a chipset. For example, the number of chip units 1 in the chipset can be 3, 4, 5, 6 or 7. Of course, it can also be other numbers, which are not specifically limited here.

[0078] In one embodiment, if Figure 8-Figure 11 As shown, the chip substrate with the pad 12 can be cleaved to form a chip unit 1. In this process, a groove 11 can be formed in the middle of the chip substrate, and a conductive film layer 2 covering the groove 11 can be formed in the groove 11. The conductive film layer 2 can be conformed to the groove 11 and can cover the surface of the pad 12 in the substrate. The conductive film layer 2 on the side of the pad 12 away from the groove 11 can be removed by an etching process, and the substrate can be cleaved in the middle of the groove 11 to form a chip unit 1. It should be noted that the dotted line in the figure is a schematic diagram of the cleavage position. The chip unit after cleavage, such as Figure 3 shown.

[0079] Each chip unit 1 can be stacked and bonded together in the vertical direction by bonding. A groove 11 can be formed at the end of each chip unit 1 by a photolithography process. Specifically, each chip unit 1 can have a groove 11 formed at at least one end. For example, the groove 11 can be formed at one end of the chip unit 1, or the grooves 11 can be formed at both ends of the chip unit 1, without special limitation. When the groove 11 is formed at one end of each chip unit 1, the grooves 11 of two adjacent chip units 1 can be aligned in the vertical direction during the stacking of each chip unit 1, or the grooves 11 of two adjacent chip units 1 can be staggered left and right, without special limitation. When the grooves 11 are formed at both ends of each chip unit 1, the grooves 11 at the left and right ends of two adjacent chip units 1 can be aligned respectively during the stacking of each chip unit 1.

[0080] In one embodiment, a groove 11 can be formed at at least one end of each chip unit 1 by using a dry etching or wet etching process. The groove 11 can be a groove-like structure formed by the top of the chip unit 1 being recessed inward. The depth can be 60um and the width can be 30um. The cross-section can be an inverted trapezoid and can have inclined side walls, which helps to reduce angular stress and ensure the signal transmission effect of the chip unit 1.

[0081] In step S120 , a conductive film layer 2 is formed, and the conductive film layer 2 conforms to the surface of the groove 11 .

[0082] A conductive film layer 2 can be formed on the side wall of the groove 11 by chemical vapor deposition or vacuum evaporation. The conductive film layer 2 can also extend to the top surface of the chip unit 1 and can cover the soldering pad 12 on the top surface of the chip unit 1, so that the electrical signal in the soldering pad 12 can be transmitted to the conductive film layer 2, so as to facilitate the transmission of the electrical signal in the soldering pad 12 to the external circuit through the conductive film layer 2.

[0083] In step S130 , a lead 3 is formed, one end of the lead 3 is connected to the conductive film layer 2 , and the other end of the lead 3 extends to the outside of the chip unit 1 .

[0084] The lead 3 can be formed on the surface of the conductive film layer 2 away from the chip unit 1 through a pressure welding process. Of course, the lead 3 can also be fixedly connected to the conductive film layer 2 through an electroplating process. No special limitation is made here on the connection method between the lead 3 and the conductive film layer 2.

[0085] One end of the lead 3 can be connected to the conductive film layer 2, and the other end can extend to the outside of the chip unit 1. That is, the lead 3 can be connected to the inside of the groove 11 and can be connected to the conductive film layer 2, and can be used to transmit the electrical signal in the conductive film layer 2 to the external circuit. The lead 3 can be made of a conductive material, for example, it can be a metal material, for example, it can be a metal such as tungsten, copper, aluminum, etc., and can also be other metals with good conductive properties, which are not specifically limited here. Of course, the lead 3 can also be other materials, for example, it can also be non-metallic materials such as polysilicon, which are not listed here one by one.

[0086] In step S140 , a packaging layer 4 is formed. The packaging layer 4 is at least disposed between the chip units 1 to fix and connect the chip units 1 .

[0087] In order to avoid mutual collision or wear of the chip units 1 and thus affect the performance of the chip units 1, the chip units 1 arranged in each layer can be fixed to each other by the encapsulation layer 4. The encapsulation layer 4 can be formed by spin coating, coating, inkjet or screen printing. The encapsulation layer 4 may include a multi-layer structure. For example, it may be 2 layers, 3 layers, 4 layers, 5 layers or 6 layers. Of course, it may also be other numbers of layers, which are not specifically limited here. In addition, the encapsulation layer 4 may be arranged at least between two adjacent chip units 1, and may form a sandwich structure with the chip unit 1. The number of the encapsulation layer 4 may be determined according to the number of the chip units 1. For example, when there are 3 chip units 1, the number of the encapsulation layer 4 may be at least two layers, and the two layers may be defined as the first encapsulation layer and the second encapsulation layer, respectively. A first packaging layer can be formed on the first chip unit 1, the second chip unit 1 can be fixed on the first packaging layer, and then a second packaging layer can be formed on the second chip unit 1, and finally the third chip unit 1 can be fixed on the second packaging layer. Accordingly, when there are 4 chip units 1, the number of packaging layers 4 can be at least 3. Of course, the number of chip units 1 can also be other numbers, and accordingly, the number of packaging layers 4 can also be other numbers, which is not specifically limited here.

[0088] The present disclosure also provides a semiconductor device, including the packaging structure of any of the above embodiments. The semiconductor device can be a memory chip, for example, a DRAM (Dynamic Random Access Memory), and of course, can also be other semiconductor devices, which are not listed here. The beneficial effects of the semiconductor device can refer to the beneficial effects of the above packaging structure, which are not repeated here.

[0089] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A packaging structure, characterized in that: include: A chipset, comprising a plurality of chip units stacked in a vertical direction, each of the chip units having at least one end formed with a groove, and the orthographic projections of the plurality of chip units in the vertical direction completely overlapping; A conductive film layer conforming to the surface of the groove; A lead, one end of which is connected to the conductive film layer, and the other end of which extends to the outside of the chip unit; the lead includes a bump and a wire, the bump is in contact with and connected to the conductive film layer, the wire is connected to a side of the bump away from the conductive film layer, and extends to the outside of the chip unit; the groove is a groove-shaped structure formed by the top surface of the chip unit being recessed inward, the bump can be connected to the bottom of the groove, the wire extends from the surface of the bump away from the bottom of the groove to the top surface of the groove, and is bent below the top surface of the groove; The packaging layer is at least arranged between the chip units and is used to fix and connect the chip units.

2. The packaging structure according to claim 1, characterized in that: The bump is connected to the bottom of the groove, and the wire is bent in the groove and extends outward along the extension direction of the chip unit.

3. The packaging structure according to claim 1, characterized in that: The conductive film layer extends to the top surface of the chip unit and covers the bonding pad on the top surface of the chip unit.

4. The packaging structure according to claim 1, characterized in that: The packaging structure further includes: A substrate, the chipset is disposed on the substrate, and the encapsulation layer is disposed between the substrate and the chipset, and is used to fix the chipset to the substrate; The substrate includes a conductor, and the other end of the lead is connected to the conductor.

5. The packaging structure according to claim 1, characterized in that: The width of the groove is 10um~60um, and the depth of the groove is 30um~60um.

6. The packaging structure according to claim 1, characterized in that: The thickness of the encapsulation layer is 10 um.

7. A method for preparing a packaging structure, characterized in that: include: A chipset is formed, wherein the chipset comprises a plurality of chip units stacked in a vertical direction, and each of the chip units has a groove formed at at least one end; and the orthographic projections of the plurality of chip units in the vertical direction completely overlap forming a conductive film layer, wherein the conductive film layer conforms to the surface of the groove; A lead is formed, one end of the lead is connected to the conductive film layer, and the other end extends to the outside of the chip unit; the lead includes a bump and a wire, the bump is in contact with the conductive film layer, the wire is connected to the side of the bump away from the conductive film layer, and extends to the outside of the chip unit; the groove is a groove-shaped structure formed by the top surface of the chip unit being recessed inward, the bump can be connected to the bottom of the groove, the wire extends from the surface of the bump away from the bottom of the groove to the top surface of the groove, and is bent below the top surface of the groove; A packaging layer is formed, wherein the packaging layer is at least disposed between the chip units and is used to fix and connect the chip units.

8. A semiconductor device, characterized in that: The packaging structure comprises the packaging structure described in any one of claims 1 to 6.

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