Over-temperature Protection Circuit for Low-power Chips

Abstract

The present invention provides an over-temperature protection circuit for a low-power chip, including: a first current mirror, a second current mirror, a third current mirror, NMOS transistors NM1, NM2, a triode Q1, NMOS transistors NM3, an operational amplifier AMP, NMOS transistors NM4, NM5, NM6, NM7, an inverter INV1 and an inverter INV2. The non-inverting input terminal of the operational amplifier AMP is connected to the drain of the NMOS transistor NM1, and the inverting input terminal is connected to the source of the NMOS transistor NM6. The voltage at the non-inverting input terminal of the operational amplifier AMP is a voltage negatively correlated with temperature, and the voltage at the inverting input terminal is a voltage positively correlated with temperature. The output terminal is connected to the inverter INV1. The inverter INV1 and the inverter INV2 are connected in series. The output signal VC_N of the inverter INV1 is sent to the gate of the NMOS transistor NM2, and the output signal VC_P of the inverter INV2 is sent to the gate of the NMOS transistor NM3. By comparing the magnitudes of the voltages at the non-inverting and inverting input terminals of the operational amplifier AMP, the output terminal of the operational amplifier AMP outputs a high level or a low level, thereby changing the on / off states of the NMOS transistor NM2 and the NMOS transistor NM3, and controlling the normal operation of the chip or the protection and shutdown of the chip.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and more particularly, to an over-temperature protection circuit for low-power chips. Background Art

[0002] The over-temperature protection circuit of a chip is a commonly used protection circuit that always needs to be turned on. If the chip continuously operates in a high-temperature environment, there will be a risk of burning out the internal devices of the chip. Therefore, the over-temperature protection circuit provides a protection action when the temperature is too high and has a certain hysteresis function. When the temperature drops to a safe value, the chip resumes normal operation.

[0003] The traditional over-temperature protection circuit of a chip is as Figure 1 shown. A current (INTAT) that is negatively correlated with temperature is mirrored through a current mirror and flows through two resistors, thereby generating a voltage (VNTAT) that is negatively correlated with temperature. The non-inverting input terminal of the operational amplifier AMP used as a comparator is connected to a bandgap reference voltage (Vref) that is independent of temperature, and the inverting input terminal is connected to a voltage with a negative temperature coefficient. The output VC of the operational amplifier is connected to the gate terminal of the NMOS transistor NM1, and at the same time, VC also serves as an over-temperature protection signal. When the temperature is relatively low and over-temperature does not occur, Vref < VNTAT, VC is at a low level, NM1 is cut off, and the resistor R1 is connected to the circuit, and the chip operates normally; when the temperature continuously rises and exceeds the over-temperature point, Vref > VNTAT, VC jumps from a low level to a high level, NM1 conducts, and the resistor R1 is short-circuited, and the chip is protected and turned off. Since the resistor R1 is short-circuited, only when the temperature drops to a value lower than the over-temperature point will VC return to a low level, enabling the chip to resume normal operation.

[0004] However, the over-temperature protection circuits of existing chips are not applicable in low-power application environments. In low-power applications, the current must be very small. At this time, a relatively high voltage needs to be generated by flowing through a resistor, which will inevitably require the resistance value of the resistor to become very large, and then the layout area will inevitably increase sharply.

[0005] In order to solve the problem that in a low-power application environment, that is, for the over-temperature protection circuit in a low-power chip, if designed according to the existing technology, the layout area will inevitably be too large, the present invention proposes an over-temperature protection circuit with a simple structure, extremely low power consumption, and no need for resistors, which greatly reduces the layout area. Summary of the Invention

[0006] The object of the present invention is to provide an over-temperature protection circuit for low-power chips, which greatly reduces the layout area, and has a simple structure and extremely low power consumption.

[0007] Over-temperature protection circuit for a low-power chip, comprising: a first current mirror, a second current mirror, a third current mirror, NMOS transistor NM1, NMOS transistor NM2, bipolar transistor Q1, NMOS transistor NM3, operational amplifier AMP, NMOS transistor NM4, NMOS transistor NM5, NMOS transistor NM6, NMOS transistor NM7, inverter INV1 and inverter INV2. The NMOS transistor NM1 and the NMOS transistor NM2 are connected in series, the bipolar transistor Q1 and the NMOS transistor NM3 are connected in series, the NMOS transistor NM1 and the NMOS transistor NM2 are connected in parallel with the bipolar transistor Q1 and the NMOS transistor NM3 and then connected in series with the first current mirror. The NMOS transistor NM4 and the NMOS transistor NM5 are connected in series and then connected in series with the second current mirror. The NMOS transistor NM6 and the NMOS transistor NM7 are connected in series and then connected in series with the third current mirror. The source of the NMOS transistor NM7 is connected to the source of the NMOS transistor NM4. The non-inverting input terminal (VNTAT) of the operational amplifier AMP is connected to the drain of the NMOS transistor NM1. The inverting input terminal (VPTAT) of the operational amplifier AMP is connected to the source of the NMOS transistor NM6. The voltage at the non-inverting input terminal of the operational amplifier AMP is a voltage negatively correlated with temperature, and the voltage at the inverting input terminal of the operational amplifier AMP is a voltage positively correlated with temperature. The output terminal of the operational amplifier AMP is connected to the inverter INV1. The inverter INV1 and the inverter INV2 are connected in series. The output signal VC_N of the inverter INV1 goes to the gate of the NMOS transistor NM2, and the output signal VC_P of the inverter INV2 goes to the gate of the NMOS transistor NM3. By comparing the magnitudes of the voltages at the non-inverting and inverting input terminals of the operational amplifier AMP, the output terminal of the operational amplifier AMP outputs a high level or a low level, thereby changing the on / off states of the NMOS transistor NM2 and the NMOS transistor NM3, and controlling the normal operation of the chip or the protection and shutdown of the chip.

[0008] In some embodiments, all MOS transistors are enhancement-mode MOS transistors.

[0009] Furthermore, the NMOS transistors NM1, NM4, NM5, NM6 and NM7 operate in the subthreshold region.

[0010] In some embodiments, the PMOS transistors PM1 and PM2 form a first current mirror with a cascode structure, the PMOS transistors PM3 and PM4 form a second current mirror with a cascode structure, and the PMOS transistors PM5 and PM6 form a third current mirror with a cascode structure, which is used to improve the replication accuracy of the current mirror. The gates of the first current mirror, the second current mirror and the third current mirror are respectively connected to the voltage biases of VB1 and VB2 to provide current biases for each branch.

[0011] Further, the gates of PMOS transistor PM1, PMOS transistor PM3, and PMOS transistor PM5 are connected to the voltage bias of VB1, and the gates of PMOS transistor PM2, PMOS transistor PM4, and PMOS transistor PM6 are connected to the voltage bias of VB2.

[0012] Further, the ratio of the width-to-length ratio (current ratio) of the second current mirror to the third current mirror is 1:M, where M > 0.

[0013] In some embodiments, NMOS transistors NM2 and NM3 are NMOS transistors used as switching transistors. The control signal of NMOS transistor NM2 is VC_N, the control signal of NMOS transistor NM3 is VC_P, NMOS transistor NM1 is connected in a diode structure, and transistor Q1 is connected in a diode structure.

[0014] Further, the gate and drain of NMOS transistor NM1 are connected.

[0015] In some embodiments, the ratio of the width-to-length ratio of NMOS transistor NM4 to NMOS transistor NM5 is 1:K1, and the ratio of the width-to-length ratio of NMOS transistor NM6 to NMOS transistor NM7 is 1:K2.

[0016] Further, the gate and drain of NMOS transistor NM4 are connected, and the gate and drain of NMOS transistor NM6 are connected.

[0017] In some embodiments, the output signal VC_N of inverter INV1 and the output signal VC_P of inverter INV2 respectively change the on / off states of NMOS transistor NM2 and NMOS transistor NM3 to generate hysteresis, and at the same time are input to the backend digital circuit to provide an over-temperature protection action.

[0018] Further, when the temperature does not exceed the over-temperature point, the voltage at the non-inverting terminal of comparator operational amplifier AMP is greater than the voltage at the inverting terminal, VNTAT > VPTAT. The output of comparator operational amplifier AMP is high level, the output signal VC_N of inverter INV1 is low level, the output signal VC_P of inverter INV2 is high level, NMOS transistor NM2 is cut off, the path where NMOS transistor NM1 is located is disconnected, NMOS transistor NM3 is turned on, and transistor Q1 is connected to the circuit, and the chip operates normally.

[0019] Further, when the temperature rises above the over-temperature point, the voltage at the non-inverting terminal of the comparator operational amplifier AMP is less than the voltage at the inverting terminal, VNTAT < VPTAT. The output of the comparator operational amplifier AMP jumps from a high level to a low level. The output signal VC_N of the inverter INV1 jumps to a high level, and the output signal VC_P of the inverter INV2 jumps to a low level. The NMOS transistor NM2 conducts, and the NMOS transistor NM1 is connected to the circuit. The NMOS transistor NM3 is cut off, and the branch where the triode Q1 is located is open-circuited, thereby indicating that the system is over-temperature and triggering a protection action, and the chip is protected and shut down.

[0020] Further, when the temperature drops below the over-temperature point, the signal VC_N is at a low level, the signal VC_P is at a high level, and the chip resumes normal operation.

[0021] In some embodiments, the voltage between the source of the NMOS transistor NM7 and the source of the NMOS transistor NM4 is V1, and the value of V1 is VGS5 - VGS4, where VGS5 is the voltage between the gate and the source of the NMOS transistor NM5, and VGS4 is the voltage between the gate and the source of the NMOS transistor NM4. The specific expression of V1 is S1:

[0022]

[0023] where n is the subthreshold slope correction factor, V T is the thermal voltage, K1 is the ratio of the width to length of the NMOS transistor NM4 to the NMOS transistor NM5, I5 is the current flowing through the NMOS transistor NM5, and I4 is the current flowing through the NMOS transistor NM4.

[0024] Similarly, the expression S2 of the voltage VNTAT at the non-inverting terminal of the comparator operational amplifier AMP and the calculation expression of the voltage VPTAT at the inverting terminal of the comparator operational amplifier AMP can be obtained.

[0025] Further, the expression of the voltage VPTAT at the inverting terminal of the comparator operational amplifier AMP is S2:

[0026] VPTAT = nV T ln(M * K1 * K2) (S2)

[0027] where n is the subthreshold slope correction factor, V T is the thermal voltage, M is the ratio of the width to length of the third current mirror to the second current mirror, K1 is the ratio of the width to length of the NMOS transistor NM4 to the NMOS transistor NM5, and K2 is the ratio of the width to length of the NMOS transistor NM6 to the NMOS transistor NM7.

[0028] Further, when the temperature does not exceed the over-temperature point, the voltage V at the non-inverting terminal of the comparator operational amplifier AMP NTAT1= VBE, where VBE is the voltage between the emitter and the base of the triode Q1.

[0029] Further, when the temperature rises above the over-temperature point, the voltage V at the non-inverting terminal of the comparator operational amplifier AMP NTAT2 The expression for S3 is:

[0030]

[0031] Where, V GS1 is the voltage between the gate and the source of the NMOS transistor NM1, V th1 is the threshold voltage of the NMOS transistor NM1, n is the subthreshold slope correction factor, V T is the thermal voltage, I D is the current flowing through the NMOS transistor NM1 at this time, W is the conductive channel width of the NMOS transistor NM1, L is the conductive channel length of the NMOS transistor NM1, μ n is the electron mobility, C OX is the gate oxide capacitance per unit area of the NMOS transistor NM1.

[0032] Further, it can be seen from the expression S3 that by controlling the value of ID, the magnitude of the hysteresis can be controlled. The larger the ID, the larger the hysteresis; the smaller the ID, the smaller the hysteresis. Only when the temperature drops below the over-temperature point, VC returns to the low level, enabling the chip to work properly again.

[0033] Further, when the temperature continues to rise and does not exceed the over-temperature point TH, due to the cut-off of the NMOS transistor NM2 and the conduction of the NMOS transistor NM3, the voltage VNTAT at the non-inverting terminal of the comparator operational amplifier AMP changes according to the expression of VNTAT1, and the VPTAT voltage value also increases with the increase of temperature, and the chip works properly; when the temperature continues to rise to the over-temperature point TH, VPTAT = VNTAT = VT1; if the temperature continues to rise, at this time the output voltage of the comparator operational amplifier AMP jumps to the low level. Due to the conduction of the NMOS transistor NM2 and the cut-off of the NMOS transistor NM3, the voltage VNTAT at the non-inverting terminal of the comparator operational amplifier AMP changes according to the expression of VNTAT2, and at the same time indicates that the system has overheated, causing the chip to make corresponding protection actions; only when the temperature drops to TL can the condition of VPTAT = VNTAT = VT2 be satisfied, and only when the temperature drops below TL, the output of the comparator operational amplifier AMP returns to the high level again, and the chip can work properly again.

[0034] The over-temperature protection circuit for low-power chips of the present application does not use resistors, solving the problem of large resistor layout area in low-power chips. Moreover, all common MOS transistors and bipolar transistors are used, and there are no special requirements for the temperature characteristics of the bias current used, no need to use a bandgap reference voltage as the input of the comparator, and no special requirements for the process used. The number of devices used is small, the number of circuit branches is small, and the structure is simple. All currents used in the circuit proposed by the present invention are in the nanoampere level, and the overall power consumption of the circuit is very low, achieving the purpose of low power consumption. By utilizing the temperature characteristics of the VGS of the MOS transistor and the VBE of the bipolar transistor operating in the subthreshold region, and by utilizing the NMOS transistor operating in the subthreshold region, a voltage positively correlated with temperature is generated. Combining the on / off of the switching transistor, low-power over-temperature protection and hysteresis functions are achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 FIG. 6 is an over-temperature protection circuit of a chip in the prior art.

[0036] Figure 2 FIG. 10 is an over-temperature protection circuit for low-power chips of the present application.

[0037] Figure 3 FIG. 14 is a schematic diagram of the working process of the over-temperature protection circuit for low-power chips of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0038] The following embodiments are described to assist in understanding the present invention. It is not intended and should not in any way be construed as limiting the scope of protection of the present invention.

[0039] In the following description, those skilled in the art will recognize that throughout this discussion, components may be described as separate functional units (which may include sub-units), but those skilled in the art will recognize that various components or portions thereof may be divided into separate components or integrated together (including being integrated within a single system or component).

[0040] In addition, the connections between components or systems within the drawings are not intended to be limited to direct connections. Instead, the data between these components may be modified, reformatted, or otherwise changed by intermediate components. Additionally, additional or fewer connections may be used. It should also be noted that the terms "coupled", "connected", or "input" should be understood to include direct connections, indirect connections through one or more intermediate devices, and wireless connections.

[0041] Embodiment 1:

[0042] The over-temperature protection circuit for low-power chips, as Figure 2 - Figure 3As shown in the figure, it includes: a first current mirror, a second current mirror, a third current mirror, an NMOS transistor NM1, an NMOS transistor NM2, a triode Q1, an NMOS transistor NM3, an operational amplifier AMP, an NMOS transistor NM4, an NMOS transistor NM5, an NMOS transistor NM6, an NMOS transistor NM7, an inverter INV1 and an inverter INV2. The NMOS transistor NM1 and the NMOS transistor NM2 are connected in series. The triode Q1 and the NMOS transistor NM3 are connected in series. The NMOS transistor NM1 and the NMOS transistor NM2 are connected in parallel with the triode Q1 and the NMOS transistor NM3 and then connected in series with the first current mirror. The NMOS transistor NM4 and the NMOS transistor NM5 are connected in series and then connected in series with the second current mirror. The NMOS transistor NM6 and the NMOS transistor NM7 are connected in series and then connected in series with the third current mirror. The source of the NMOS transistor NM7 is connected to the source of the NMOS transistor NM4. The non-inverting input terminal (VNTAT) of the operational amplifier AMP is connected to the drain of the NMOS transistor NM1. The inverting input terminal (VPTAT) of the operational amplifier AMP is connected to the source of the NMOS transistor NM6. The voltage at the non-inverting input terminal of the operational amplifier AMP is a voltage negatively correlated with temperature. The voltage at the inverting input terminal of the operational amplifier AMP is a voltage positively correlated with temperature. The output terminal of the operational amplifier AMP is connected to the inverter INV1. The inverter INV1 and the inverter INV2 are connected in series. The output signal VC_N of the inverter INV1 goes to the gate of the NMOS transistor NM2. The output signal VC_P of the inverter INV2 goes to the gate of the NMOS transistor NM3. By comparing the magnitudes of the voltages at the non-inverting and inverting input terminals of the operational amplifier AMP, the output terminal of the operational amplifier AMP outputs a high level or a low level, thereby changing the on-off states of the NMOS transistor NM2 and the NMOS transistor NM3, and controlling the normal operation of the chip or the chip being protected and turned off.

[0043] The NMOS transistor NM2 and the NMOS transistor NM3 are NMOS transistors used as switching transistors. The control signal of the NMOS transistor NM2 is VC_N, and the control signal of the NMOS transistor NM3 is VC_P. The NMOS transistor NM1 is connected in a diode structure, and the triode Q1 is connected in a diode structure. The gate and the drain of the NMOS transistor NM1 are connected. The ratio of the width-to-length ratio of the NMOS transistor NM4 to the NMOS transistor NM5 is 1:K1, and the ratio of the width-to-length ratio of the NMOS transistor NM6 to the NMOS transistor NM7 is 1:K2. The gate and the drain of the NMOS transistor NM4 are connected, and the gate and the drain of the NMOS transistor NM6 are connected.

[0044] The output signal VC_N of the inverter INV1 and the output signal VC_P of the inverter INV2 respectively change the on / off states of the NMOS transistor NM2 and the NMOS transistor NM3 to generate hysteresis, and at the same time are input into the subsequent digital circuit to provide an over-temperature protection action. When the temperature does not exceed the over-temperature point, the voltage at the non-inverting terminal of the comparator operational amplifier AMP is greater than the voltage at the inverting terminal, VNTAT > VPTAT. The output of the comparator operational amplifier AMP is at a high level. The output signal VC_N of the inverter INV1 is at a low level, and the output signal VC_P of the inverter INV2 is at a high level. The NMOS transistor NM2 is cut off, the path where the NMOS transistor NM1 is located is disconnected, the NMOS transistor NM3 is turned on, and the triode Q1 is connected to the circuit, and the chip works normally. When the temperature rises above the over-temperature point, the voltage at the non-inverting terminal of the comparator operational amplifier AMP is less than the voltage at the inverting terminal, VNTAT < VPTAT. The output of the comparator operational amplifier AMP jumps from a high level to a low level. The output signal VC_N of the inverter INV1 jumps to a high level, and the output signal VC_P of the inverter INV2 jumps to a low level. The NMOS transistor NM2 is turned on, the NMOS transistor NM1 is connected to the circuit, the NMOS transistor NM3 is cut off, and the branch where the triode Q1 is located is open-circuited, so as to indicate that the system is over-temperature and trigger a protection action, and the chip is protected and turned off. When the temperature drops below the over-temperature point, the signal VC_N is at a low level, the signal VC_P is at a high level, and the chip works normally again.

[0045] The voltage between the source of the NMOS transistor NM7 and the source of the NMOS transistor NM4 is V1, and the value of V1 is VGS5 - VGS4. VGS5 is the voltage between the gate and the source of the NMOS transistor NM5, and VGS4 is the voltage between the gate and the source of the NMOS transistor NM5. The specific expression of V1 is S1:

[0046]

[0047] where n is the subthreshold slope correction factor, V T is the thermal voltage, K1 is the ratio of the width to the length of the NMOS transistor NM4 and the NMOS transistor NM5, I5 is the current flowing through the NMOS transistor NM5, and I4 is the current flowing through the NMOS transistor NM4. The expression S2 of the voltage VNTAT at the non-inverting terminal of the comparator operational amplifier AMP and the calculation expression of the voltage VPTAT at the inverting terminal of the comparator operational amplifier AMP can be obtained.

[0048] The expression of the voltage VPTAT at the inverting terminal of the comparator operational amplifier AMP is S2:

[0049] VPTAT = nV T ln(M * K1 * K2) (S2)

[0050] where n is the subthreshold slope correction factor, VT is the thermal voltage, M is the ratio of the width to length of the third current mirror to the second current mirror, K1 is the ratio of the width to length of NMOS transistor NM4 to NMOS transistor NM5, and K2 is the ratio of the width to length of NMOS transistor NM6 to NMOS transistor NM7.

[0051] When the temperature does not exceed the over-temperature point, the voltage V at the non-inverting terminal of the comparator operational amplifier AMP NTAT1 = VBE, where VBE is the voltage between the emitter and base of transistor Q1. When the temperature rises above the over-temperature point, the voltage V at the non-inverting terminal of the comparator operational amplifier AMP NTAT2 has the expression S3:

[0052]

[0053] where, V GS1 is the voltage between the gate and source of NMOS transistor NM1, V th1 is the threshold voltage of NMOS transistor NM1, n is the sub-threshold slope correction factor, V T is the thermal voltage, I D is the current flowing through NMOS transistor NM1 at this time, W is the conductive channel width of NMOS transistor NM1, L is the conductive channel length of NMOS transistor NM1, μ n is the electron mobility, C OX is the gate oxide capacitance per unit area of NMOS transistor NM1. It can be seen from expression S3 that by controlling the value of ID, the amount of hysteresis can be controlled. The larger ID is, the larger the amount of hysteresis is, and the smaller ID is, the smaller the amount of hysteresis is. Only when the temperature drops to a level lower than the over-temperature point, will VC return to the low level and the chip will resume normal operation.

[0054] When the temperature continues to rise and does not exceed the over-temperature point TH, due to the cut-off of NMOS transistor NM2 and the conduction of NMOS transistor NM3, the voltage VNTAT at the non-inverting terminal of the comparator operational amplifier AMP changes according to the expression of VNTAT1, and the VPTAT voltage value also increases with the increase of temperature, and the chip operates normally; when the temperature continues to rise to the over-temperature point TH, VPTAT = VNTAT = VT1; if the temperature continues to rise, at this time the output voltage of the comparator operational amplifier AMP jumps to the low level. Due to the conduction of NMOS transistor NM2 and the cut-off of NMOS transistor NM3, the voltage VNTAT at the non-inverting terminal of the comparator operational amplifier AMP changes according to the expression of VNTAT2, and at the same time indicates that the system has overheated, causing the chip to make corresponding protection actions; only when the temperature drops to TL can the condition of VPTAT = VNTAT = VT2 be satisfied, and only when the temperature drops to a level lower than TL will the output of the comparator operational amplifier AMP return to the high level again and the chip can resume normal operation.

[0055] All MOS transistors are enhancement-mode MOS transistors. NMOS transistors NM1, NM4, NM5, NM6, and NM7 operate in the subthreshold region. PMOS transistors PM1 and PM2 form a first current mirror with a common-source common-gate structure, PMOS transistors PM3 and PM4 form a second current mirror with a common-source common-gate structure, and PMOS transistors PM5 and PM6 form a third current mirror with a common-source common-gate structure to improve the replication accuracy of the current mirror. The gates of the first, second, and third current mirrors are respectively connected to the voltage biases of VB1 and VB2 to provide current biases for each branch. The gates of PMOS transistors PM1, PM3, and PM5 are connected to the voltage bias of VB1, and the gates of PMOS transistors PM2, PM4, and PM6 are connected to the voltage bias of VB2. The ratio of the aspect ratios (current ratios) of the second current mirror to the third current mirror is 1:M, where M>0.

[0056] The over-temperature protection circuit for a low-power chip in this application does not use resistors, solving the problem of large resistor layout area in low-power chips. Moreover, all common MOS transistors and bipolar transistors are used, and there are no special requirements for the temperature characteristics of the bias current used, no need to use a bandgap reference voltage as the input of the comparator, and no special requirements for the process used. Few devices and circuit branches are used, and the structure is simple. All currents used in the circuit proposed by the present invention are in the nanoampere range, and the overall power consumption of the circuit is very low, achieving the purpose of low power consumption. By utilizing the temperature characteristics of the VGS of MOS transistors operating in the subthreshold region and the VBE of bipolar transistors, and by using NMOS transistors operating in the subthreshold region, a PTAT voltage is generated. Combining the on / off of the switching transistors, low-power over-temperature protection and hysteresis functions are achieved.

[0057] Although this application has disclosed multiple aspects and embodiments, other aspects and embodiments will be obvious to those skilled in the art. Without departing from the concept of this application, several modifications and improvements can still be made, and these all fall within the protection scope of this application. The multiple aspects and embodiments disclosed in this application are only for illustrative purposes and are not intended to limit this application. The actual protection scope of this application is subject to the claims.

Claims

1. An over-temperature protection circuit for a low-power chip, characterized in that, Including: The first current mirror, the second current mirror, NMOS transistor NM1, NMOS transistor NM2, bipolar transistor Q1, NMOS transistor NM3, operational amplifier AMP, NMOS transistor NM4, NMOS transistor NM5, NMOS transistor NM6, NMOS transistor NM7, inverter INV1 and inverter INV2. PMOS transistors PM1, PM3 and PM5 form the first current mirror with a cascode structure. PMOS transistors PM2, PM4 and PM6 form the second current mirror with a cascode structure. The first current mirror is connected to the power supply through the source of PMOS transistor PM1. The first current mirror is connected to the source of PMOS transistor PM6 through the drain of PMOS transistor PM5. The drain of PMOS transistor PM6 is connected to the drain of NMOS transistor NM6. The source of NMOS transistor NM6 is connected to the drain of NMOS transistor NM7. The gates of NMOS transistor NM6 and NMOS transistor NM7 are connected and then connected to the drain of PMOS transistor PM6. NMOS transistors NM2 and NM3 are NMOS transistors used as switching transistors. The control signal of NMOS transistor NM2 is VC_N, and the control signal of NMOS transistor NM3 is VC_P. NMOS transistor NM1 is connected in a diode structure, and bipolar transistor Q1 is connected in a diode structure. The second current mirror is connected to the drain of NMOS transistor NM1 through the drain of PMOS transistor PM2. The source of NMOS transistor NM1 is connected to the drain of NMOS transistor NM2. The gate of NMOS transistor NM1 is connected to the drain of PMOS transistor PM2. The source of NMOS transistor NM2 is grounded. Bipolar transistor Q1 and NMOS transistor NM3 are in series. The emitter of bipolar transistor Q1 is connected to the drain of NMOS transistor NM1. The collector of bipolar transistor Q1 is connected to the drain of NMOS transistor NM3. The base of bipolar transistor Q1 is connected to the drain of NMOS transistor NM3. The source of NMOS transistor NM3 is grounded.The source of the PMOS transistor PM4 is connected to the drain of the PMOS transistor PM3. The drain of the PMOS transistor PM4 is connected to the drain of the NMOS transistor NM4. The source of the NMOS transistor NM4 is connected to the drain of the NMOS transistor NM5. The source of the NMOS transistor NM5 is connected to the source of the NMOS transistor NM3. The source of the NMOS transistor NM7 is connected to the source of the NMOS transistor NM4. The gates of the NMOS transistors NM4 and NM5 are connected and then connected to the drain of the PMOS transistor PM4. The non-inverting input terminal of the operational amplifier AMP is connected to the drain of the NMOS transistor NM1. The inverting input terminal of the operational amplifier AMP is connected to the source of the NMOS transistor NM6. The voltage at the non-inverting input terminal of the operational amplifier AMP is a voltage negatively correlated with temperature. The voltage at the inverting input terminal of the operational amplifier AMP is a voltage positively correlated with temperature. The output terminal of the operational amplifier AMP is connected to the inverter INV1. The inverter INV1 is connected in series with the inverter INV2. The output signal VC_N of the inverter INV1 is sent to the gate of the NMOS transistor NM2. The output signal VC_P of the inverter INV2 is sent to the gate of the NMOS transistor NM3. By comparing the magnitudes of the voltages at the non-inverting and inverting input terminals of the operational amplifier AMP, the output terminal of the operational amplifier AMP outputs a high level or a low level, thereby changing the on / off states of the NMOS transistors NM2 and NM3, controlling the normal operation of the chip or protecting the chip and turning it off. All MOS transistors are enhancement-mode MOS transistors. The NMOS transistors NM1, NM4, NM5, NM6, and NM7 operate in the subthreshold region. The gates of the PMOS transistors PM1 and PM2 are respectively connected to the voltage biases of VB1 and VB2 to provide current biases for each branch. The ratio of the width-to-length ratio of the PMOS transistors PM3 and PM5 is 1:M, where M > 0. The ratio of the width-to-length ratio of the PMOS transistors PM4 and PM6 is 1:M, where M > 0. The ratio of the width-to-length ratio of the NMOS transistors NM4 and NM5 is 1:K1. The ratio of the width-to-length ratio of the NMOS transistors NM6 and NM7 is 1:K2. The output signal VC_N of the inverter INV1 and the output signal VC_P of the inverter INV2 respectively change the on / off conditions of the NMOS transistors NM2 and NM3 to generate hysteresis and are simultaneously input to the subsequent digital circuit to provide over-temperature protection action. When the temperature does not exceed the over-temperature point, the voltage at the non-inverting input terminal of the comparison operational amplifier AMP is greater than the voltage at the inverting input terminal, VNTAT > VPTAT. The output of the comparison operational amplifier AMP is a high level. The output signal VC_N of the inverter INV1 is a low level. The output signal VC_P of the inverter INV2 is a high level. The NMOS transistor NM2 is cut off, the path where the NMOS transistor NM1 is located is disconnected, the NMOS transistor NM3 is turned on, and the triode Q1 is connected to the circuit, and the chip operates normally;When the temperature rises above the over-temperature point, the voltage at the non-inverting input of the comparator operational amplifier AMP is less than the voltage at the inverting input, VNTAT < VPTAT. The output of the comparator operational amplifier AMP jumps from high level to low level. The output signal VC_N of the inverter INV1 jumps to high level, and the output signal VC_P of the inverter INV2 jumps to low level. The NMOS transistor NM2 conducts, and the NMOS transistor NM1 is connected to the circuit. The NMOS transistor NM3 is cut off, and the branch where the triode Q1 is located is open-circuited, so as to indicate that the system is over-temperature and trigger a protection action, and the chip is protected and shut down. When the temperature drops below the over-temperature point, the signal VC_N is at low level and the signal VC_P is at high level, and the chip resumes normal operation.

2. The over-temperature protection circuit for a low-power chip as claimed in claim 1, wherein The voltage between the source of the NMOS transistor NM7 and the source of the NMOS transistor NM4 is V1, and the value of V1 is VGS5 - VGS4. VGS5 is the voltage between the gate and the source of the NMOS transistor NM5, and VGS4 is the voltage between the gate and the source of the NMOS transistor NM4. The specific expression of V1 is S1: (S1) where n is the subthreshold slope correction factor, V T is the thermal voltage, K1 is the ratio of the width to length of NMOS transistor NM4 to that of NMOS transistor NM5, I5 is the current flowing through NMOS transistor NM5, and I4 is the current flowing through NMOS transistor NM4.

3. The over-temperature protection circuit for a low-power chip according to claim 1, characterized in that The expression for comparing the voltage VPTAT at the inverting terminal of the operational amplifier AMP is S2: (S2) where n is the subthreshold slope correction factor, V T is the thermal voltage, M is the ratio of the width-to-length of the third current mirror to the second current mirror, K1 is the ratio of the width-to-length of NMOS transistor NM4 to NMOS transistor NM5, and K2 is the ratio of the width-to-length of NMOS transistor NM6 to NMOS transistor NM7.

4. The over-temperature protection circuit for a low-power chip according to claim 1, characterized in that, When the temperature does not exceed the over-temperature point, compare the voltage V at the non-inverting terminal of the operational amplifier AMP NTAT1 = VBE, where VBE is the voltage between the emitter and the base of the triode Q1.

5. The over-temperature protection circuit for a low-power chip according to claim 1, characterized in that, When the temperature rises above the over-temperature point, the voltage V at the non-inverting terminal of the comparator operational amplifier AMP NTAT2 has the expression S3: （S3） Among them, V GS1 is the voltage between the gate and the source of the NMOS transistor NM1, V th1 is the threshold voltage of the NMOS transistor NM1, n is the subthreshold slope correction factor, V T is the thermal voltage, I D is the current flowing through the NMOS transistor NM1 at this time, W is the conductive channel width of the NMOS transistor NM1, L is the conductive channel length of the NMOS transistor NM1, is the electron mobility, is the gate oxide capacitance per unit area of the NMOS transistor NM1.

6. The over-temperature protection circuit for a low-power chip according to claim 5, characterized in that, By controlling the value of ID, the amount of hysteresis can be controlled. The larger ID is, the larger the amount of hysteresis is; the smaller ID is, the smaller the amount of hysteresis is. Only when the temperature drops below the overtemperature point, VC will return to the low level and the chip will work properly again.

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