Computer readable medium storing code for generating wafer map and computing device including the same

Abstract

A non-transitory computer-readable medium storing program code comprising an image generation model that, when executed, causes a processor to: input input data comprising sampled data of some of a plurality of semiconductor dies of a wafer to a generator network of the image generation model and output a wafer map indicative of the plurality of semiconductor dies; and input the wafer map output from the generator network to a discriminator network of the image generation model and discriminate the wafer map.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0153770, filed on November 26, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the inventive concept described herein relate to a non-transitory computer-readable medium and a computing device including the non-transitory computer-readable medium storing program code for generating chip diagrams based on a generative adversarial network. Background Technology

[0004] Wafer maps can indicate various characteristics of multiple semiconductor dies formed on a wafer. Wafer maps can be used to select multiple semiconductor dies and check yield. However, methods that generate wafer maps based on measurements from all semiconductor dies can be too costly and / or time-consuming. Artificial neural networks can be used in various fields such as machine learning, selection, reasoning, prediction, recognition, analysis, translation, and diagnostics. For example, artificial neural networks can be used to generate, analyze, or identify images. Furthermore, artificial neural networks can be used in semiconductor manufacturing processes. Summary of the Invention

[0005] Some exemplary embodiments of the inventive concept provide a non-transitory computer-readable medium and a computing device including the non-transitory computer-readable medium storing program code for generating wafer patterns based on a generative adversarial network.

[0006] According to an example embodiment, a non-transitory computer-readable medium storing program code including an image generation model, which, when executed, causes a processor to: input input data of sampled data of some of a plurality of semiconductor dies including a wafer into a generator network of the image generation model and output a wafer pattern indicating the plurality of semiconductor dies; and input the wafer pattern output from the generator network into a discriminator network of the image generation model and discriminate the wafer pattern.

[0007] According to an example embodiment, a non-transitory computer-readable medium storing program code including an image generation model, which, when executed, causes a processor to: learn a discriminator network of the image generation model such that the discriminator network identifies a first wafer image including a plurality of sampled values ​​measured from a plurality of semiconductor dies of a wafer as genuine and identifies a second wafer image output by a generator network of the image generation model from some of the plurality of sampled values ​​as fake; and learn a generator network such that the discriminator network identifies the second wafer image output by the generator network as genuine.

[0008] According to an example embodiment, a computing device includes a processor configured to execute an image generation model stored in a memory. The processor: performs training on a discriminator network of the image generation model, such that the discriminator network identifies a first wafer image of the first wafer, including a plurality of first sample values ​​measured from a plurality of first semiconductor dies of a first wafer, as genuine, and identifies a second wafer image of the first wafer output from a generator network of the image generation model, from some of the plurality of first sample values ​​input thereto, as fake; performs training on a generator network, such that the discriminator network identifies the second wafer image output from the generator network as genuine; and inputs some of the second sample values ​​measured from some of the plurality of second semiconductor dies of a second wafer into the generator network and generates a third wafer image of the second wafer. Attached Figure Description

[0009] The above and other objects and features of the inventive concept will become apparent from the detailed description of exemplary embodiments of the inventive concept with reference to the accompanying drawings.

[0010] Figure 1 A chip monitoring system according to an example embodiment of the inventive concept is shown.

[0011] Figure 2 Example embodiments based on the inventive concept are shown in detail. Figure 1 Image generation model.

[0012] Figure 3 The schematic diagram shows the wafer pattern through... Figure 2 The process of the discriminator network processing.

[0013] Figure 4 Schematic illustration of where the input vector passes through Figure 2 The process of generator network processing.

[0014] Figure 5 Detailed examples of embodiments based on the inventive concept are shown. Figure 1 Image generation model.

[0015] Figure 6 Schematic illustration of the input array passing through Figure 5 The process of generator network processing.

[0016] Figure 7 Detailed examples of embodiments based on the inventive concept are shown. Figure 1 Image generation model.

[0017] Figure 8 Detailed examples of embodiments based on the inventive concept are shown. Figure 1 Image generation model.

[0018] Figure 9 Showing a true image of the sample wafer and a reference Figures 5 to 8 The image generation model described generates pseudo-images.

[0019] Figure 10 Show Figure 9 The error between real and fake images.

[0020] Figure 11 Detailed examples of embodiments based on the inventive concept are shown. Figure 1 Image generation model.

[0021] Figure 12 Showing a real image of any other chip and by Figure 11 The pseudo-image generated by the image generation model.

[0022] Figure 13 It is a flowchart illustrating the operation, in which a processor according to an example embodiment of the inventive concept learns an image generation model stored in memory, executes the learned image generation model, and generates a wafer image. Detailed Implementation

[0023] Hereinafter, some exemplary embodiments of the inventive concept will be described in detail and clearly to the extent that those skilled in the art can readily implement the inventive concept.

[0024] Figure 1 A wafer monitoring system according to an example embodiment of the inventive concept is shown. The wafer monitoring system 10 may be referred to as a "wafer testing system," a "wafer pattern generation system," a "semiconductor manufacturing process monitoring system," or a "semiconductor manufacturing system." The wafer monitoring system 10 may include testing equipment 13 and / or a computing device 14.

[0025] Test equipment 13 can test wafer 11 and generate a wafer pattern of wafer 11. Multiple semiconductor dies 12 can be set or implemented on wafer 11. Test equipment 13 can test and measure the characteristics of the multiple semiconductor dies 12. For example, test equipment 13 can measure various characteristics of the multiple semiconductor dies 12, such as gate-induced drain leakage (GIDL), drain-induced barrier reduction (DIBL), current, power, operating frequency, threshold voltage, latency, timing margin, and / or lifetime, and can generate a wafer pattern indicating the characteristics of the multiple semiconductor dies 12. Test equipment 13 can sample the characteristics of the multiple semiconductor dies 12. The characteristics of the multiple semiconductor dies 12 sampled by test equipment 13 can correspond to multiple sampled values ​​SV (or "measured values").

[0026] A wafer pattern can correspond to an image comprising multiple pixels PX. The multiple pixels PX can be represented by multiple sampled values ​​SV, which are characteristics of multiple semiconductor dies measured by test equipment 13, using brightness indicators. A pixel can be referred to as a "shot". For example, the sampled value SV of the semiconductor die 12 corresponding to a relatively dark pixel PX can be different from the sampled value SV of the semiconductor die 12 corresponding to a relatively bright pixel PX. Semiconductor dies 12 corresponding to pixels PX with similar brightness can have similar sampled values ​​SV. The wafer pattern can indicate multiple sampled values ​​SV at locations of the multiple semiconductor dies 12 mapped onto wafer 11.

[0027] exist Figure 1 An example is shown where the number of semiconductor dies 12 on wafer 11 is equal to the number of sampled values ​​SV on the wafer pattern, but the number of semiconductor dies 12 and the number of sampled values ​​SV can be different. For example, a sampled value can indicate the average or representative value of the characteristics of two or more semiconductor dies. The number of semiconductor dies 12 and the number of sampled values ​​SV can be different, and the inventive concept is not limited to this. Figure 1 The example shown. The dimensions of wafer 11 and the dimensions of the wafer pattern can be the same or different, and the dimensions of the wafer pattern can be scaled up or down based on the dimensions of wafer 11 at a given ratio.

[0028] In some embodiments, each of the plurality of semiconductor dies 12 may be used to implement: a memory device, such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a thyristor random access memory (TRAM) device, a NAND flash memory device, a NOR flash memory device, a resistive random access memory (RRAM) device, a ferroelectric random access memory (FRAM) device, a phase-change random access memory (PRAM) device, or a magnetic random access memory (MRAM) device; a processing device, such as a central processing unit (CPU), an image signal processing unit (ISP), a digital signal processing unit (DSP), a graphics processing unit (GPU), a vision processing unit (VPU), or a neural processing unit (NPU); a system-on-a-chip (SoC); an application-specific integrated circuit (ASIC); or a field-programmable gate array (FPGA).

[0029] The computing device 14 can communicate with the test device 13. The computing device 14 may include a processor 15 and a memory 16. The computing device 14 may be referred to as an "electronic device" or an "image generation device." The processor 15, as a hardware device, can execute the image generation model 100 stored in the memory 16. For example, the processor 15 may include a buffer memory shared by homogeneous or heterogeneous cores such as a CPU, ISP, DSP, GPU, VPU, and NPU. The processor 15 can run processing and arithmetic operations associated with instructions describing the program code of the image generation model 100, such as fetching, executing, requesting data, and / or storing data. The computing device 14 may include one or more processors.

[0030] The memory 16 may be a non-transitory computer-readable medium storing program code for an image generation model 100 executable by the processor 15 (i.e., the hardware device). For example, the memory 16 may be implemented using the various memory devices described above, and the computing device 14 may include one or more memories. Furthermore, the memory 16 may be implemented by an external device capable of communicating with the computing device 14.

[0031] The image generation model 100, stored in memory 16 and executed by processor 15, may include a generator network 110 and / or a discriminator network 120. The generator network 110 may be referred to as a "generator" or "generation unit," and the discriminator network 120 may be referred to as a "discriminator" or "discriminator unit." For example, the image generation model 100 may be a generative adversarial network (GAN) including generator network 110 and discriminator network 120. Processor 15 may provide input data to generator network 110, and generator network 110 may generate and output pseudo-images based on the input data. Processor 15 may input real images to discriminator network 120. For another example, processor 15 may input pseudo-images to discriminator network 120. Discriminator network 120 may distinguish whether the input image is real or fake (or may classify the input image as a real image or a pseudo-image). For example, discriminator network 120 may perform binary classification on the input image.

[0032] In some embodiments, the test device 13 can test all semiconductor dies 12 on the wafer 11, generate a wafer image including multiple pixels PX indicating multiple sample values ​​SV of the multiple semiconductor dies 12, and send the wafer image to the computing device 14. In some example embodiments, the test device 13 can test a first semiconductor die 12 among the multiple semiconductor dies 12 on the wafer 11 (testing a first semiconductor die 12 corresponding to some of the multiple semiconductor dies 12 on the wafer 11), generate sample values ​​SV of the first semiconductor die 12, and send the sample values ​​SV of the first semiconductor die 12 to the computing device 14. In some embodiments, the computing device 14 can generate the wafer image by referring to the sampled data. Although not explicitly stated in Figure 1 As shown, the computing device 14 may also include interface circuitry that requests or receives wafer diagrams or sampling data from the wafer 11 under the control of the processor 15.

[0033] In some embodiments, the generator network 110 may include multiple nodes. The multiple nodes may form an input layer IL, multiple hidden layers HL, and / or an output layer OL. Each of the multiple nodes may store weights and biases. The generator network 110 can be learned or trained when the processor 15 updates the weights and biases. The discriminator network 120 may also include multiple nodes. The multiple nodes may form an input layer IL, multiple hidden layers HL, and / or an output layer OL. Each of the multiple nodes may store weights and biases. The discriminator network 120 can be learned or trained when the processor 15 updates the weights and biases. For example, a node may be referred to as a "neuron" or a "perceptron".

[0034] For example, processor 15 can input a wafer pattern as a real image into discriminator network 120. This wafer pattern is generated by test equipment 13 that measures all semiconductor dies 12 on wafer 11 and includes multiple sampled values ​​SV measured from all semiconductor dies 12. Discriminator network 120 can distinguish whether the input image is real or fake. Processor 15 can learn discriminator network 120 so that discriminator network 120 identifies real images as real. Processor 15 can also learn discriminator network 120 to identify wafer patterns output from generator network 110 as fake (e.g., pseudo-images).

[0035] At the beginning of learning, when the discriminator network 120 identifies a real image as fake (or a fake image as real), the processor 15 can update or adjust the weights or biases of the nodes of the discriminator network 120 (e.g., backpropagation) based on the identification result. When the discriminator network 120 has completed learning, it can identify a real image as real or a fake image as fake. The nodes of the input layer IL of the discriminator network 120 can receive real or fake images, the nodes of the hidden layer HL of the discriminator network 120 can perform various operations on the real or fake images input through the input layer IL (e.g., convolution, pooling, downsampling, multiplication, addition, and / or activation operations), and the output layer OL of the discriminator network 120 can output a signal indicating whether the input image is real or fake.

[0036] For example, processor 15 can input multiple sampled values ​​SV generated by test equipment 13 that only measures the second semiconductor dies among the multiple semiconductor dies 12 on wafer 11 (measuring only some of the second semiconductor dies among the multiple semiconductor dies 12) as input data to generator network 110. Generator network 110 can generate and output wafer patterns based on or from the input data. As mentioned above, the wafer pattern generated by generator network 110 can be a pseudo-image. The size of the wafer pattern generated by generator network 110 can be equal to the size of the wafer pattern generated by test equipment 13. Processor 15 can perform learning on generator network 110 such that the wafer pattern output from generator network 110 is identified as real by discriminator network 120. For example, processor 15 can start learning generator network 110 after discriminator network 120 has completed learning. At the beginning of learning, when the discriminator network 120 identifies the wafer image output from the generator network 110 as fake (or as a spurious image), the processor 15 can update or adjust the weights or biases of the nodes in the generator network 110 (e.g., backpropagation). When the generator network 110 has completed its learning, the discriminator network 120 can identify the wafer image output from the generator network 110 as real (or as a real image), or it can identify the wafer image output from the generator network 110 as having approximately a 50% probability of being real or approximately a 50% probability of being fake. The discriminator network 120 may not be able to accurately distinguish whether the wafer image output from the generator network 110 is real or fake. For example, the generator network 110 may forge the discriminator network 120. The nodes of the input layer IL of the generator network 110 can receive input data, the nodes of the hidden layer HL of the generator network 110 can perform various operations on the input data input through the input layer IL (e.g., convolution operation, deconvolution operation, depooling operation, upsampling operation, multiplication operation, addition operation and / or activation operation), and the output layer OL of the generator network 110 can output a wafer pattern.

[0037] With advancements in semiconductor manufacturing processes, multiple wafers 11 can be manufactured. Wafer maps of multiple wafers 11 are required for testing and selection. In some embodiments, the test equipment 13 generates wafer maps of all wafers 11 (e.g., a complete enumeration) based on measurements from semiconductor dies of all wafers 11, which requires significant time and / or cost. Therefore, according to an exemplary embodiment of the inventive concept, the test equipment 13 may not test all wafers 11, but rather test a few sample wafers 11, and can send sample wafer maps of the sample wafers 11 to the computing device 14. The processor 15 can utilize the sample wafer maps as training data. The processor 15 can input the sample wafer maps into a discriminator network 120 and perform learning on the discriminator network 120. The processor 15 can input some of the sampled values ​​SV from the sample wafer maps into a generator network 110 and perform learning on the generator network 110. When processor 15 completes the learning of discriminator network 120 and generator network 110 using training data, test device 13 can test only some of the plurality of semiconductor dies 12 of each of the remaining wafers 11 except for sample wafer 11, and can send sampled data including sampled values ​​SV measured from said semiconductor dies 12 to computing device 14. Processor 15 can input the sampled values ​​SV as input data to generator network 110, and generator network 110 can generate and output wafer images of the remaining wafers 11 from the sampled values ​​SV. After the learning of discriminator network 120 and generator network 110 is completed, test device 13 can test only some sample wafers 11 instead of all wafers 11, and can generate wafer images of the sample wafers 11, and computing device 14 can execute image generation model 100 and can generate wafer images of the remaining wafers 11. Compared with the case where test device 13 tests all wafers 11 and generates wafer images, using image generation model 100 of computing device 14 can reduce time and / or cost.

[0038] In some embodiments, the image generation model 100 may be stored as program code (i.e., software) in memory 16 and may be executed by processor 15. In some example embodiments, computing device 14 may include circuitry in which generator network 110 and discriminator network 120 of image generation model 100 are physically implemented and in hardware. In some embodiments, image generation model 100 may be implemented in hardware, software, or a combination thereof.

[0039] Figure 2 Example embodiments based on the inventive concept are shown in detail. Figure 1 Image generation model 100a is an image generation model. Figure 1An example of an image generation model 100 is provided. Processor 15 can input a real wafer image sent from test device 13 as a real wafer image into discriminator network 120, and can learn discriminator network 120. Processor 15 can generate an input vector including some of the full sample values ​​SV of the real wafer image. Processor 15 can input the input vector as input data into generator network 110, and can learn generator network 110. After generator network 110 has completed learning, processor 15 can generate an input vector including some of the sample values ​​SV of any other wafer 11 sent from test device 13, and can input the input vector as input data into generator network 110. Generator network 110 can generate and output wafer images based on other wafers 11. Because the wafer image output from generator network 110 is not a wafer image generated by test device 13, the wafer image output from generator network 110 corresponds to a pseudo wafer image.

[0040] For example, processor 15 can generate an input vector that includes only some sampled values ​​SV, or it can generate an input vector that includes any other values ​​different from the sampled values ​​SV. Processor 15 can set any other value to a predetermined value, such as a value adjacent to the sampled values ​​SV, or a coordinate value indicating the position of some semiconductor dies 12 on the wafer 11 from which the sampled values ​​SV are measured. Alternatively, any other value can correspond to random noise. The input vector can be a one-dimensional vector of any size. Processor 15 can input the input vector as input data to generator network 110.

[0041] Processor 15 can provide test device 13 with the locations of some semiconductor dies 12 on wafer 11, or coordinates indicating those locations, from which it measures some sampled values ​​SV. For example, interface circuitry of computing device 14 can send the locations of some semiconductor dies 12, or coordinates indicating those locations, to test device 13. After the learning of discriminator network 120 and generator network 110 is completed by processor 15, test device 13 can test some semiconductor dies 12 on any other wafer 11 based on the locations of some semiconductor dies 12 sent from computing device 14, and can send sampled data including some of the sampled values ​​SV measured from some semiconductor dies 12 to computing device 14. Test device 13 can repeatedly test some semiconductor dies 12 on other wafers 11 based on the locations of some semiconductor dies 12 sent from computing device 14, and can repeatedly send sampled data including some of the sampled values ​​SV measured from some semiconductor dies 12 to computing device 14. The locations of some semiconductor dies 12 on wafer 11 from which it measures some sampled values ​​SV are not limited to... Figure 2In the example shown, processor 15 can randomly select some locations of semiconductor die 12.

[0042] Figure 3 The schematic diagram shows the wafer pattern through... Figure 2 The process of the discriminator network processing. Figure 3 Reference Figure 2 Described.

[0043] Processor 15 can input either a real or fake wafer image into discriminator network 120. As the wafer image passes through multiple layers of discriminator network 120, its size (or scale) can gradually decrease. For example, the operation of discriminator network 120 can be similar to that of a convolutional neural network (CNN). Discriminator network 120 can extract features from the wafer image and can distinguish whether the wafer image is real or fake.

[0044] The discriminator network 120 can apply filters (or kernels or matrices) to the wafer image, repeatedly perform convolution operations (Conv1) on the sampled values ​​of the wafer image corresponding to the filters and the filter values, and generate feature maps. For example, Figure 1 The nodes of the discriminator network 120 can form a convolutional layer Conv1 to perform the aforementioned convolutional operations. The discriminator network 120 can scale down the feature map size (or scale) by repeatedly performing average pooling or max pooling operations on the feature map output from the convolutional layer Conv1, which is input from the wafer image. For example, Figure 1 The nodes of the discriminator network 120 can form pooling layers for performing the aforementioned pooling operation. Pooling can be referred to as "downsampling". The wafer map can pass through multiple convolutional layers Conv1 to Conv4 and multiple pooling layers of the discriminator network 120 under the control of the processor 15, and the number of layers is not limited to... Figure 3 The example shown. A convolutional layer and a pooling layer can be collectively referred to as a convolutional / pooling layer.

[0045] To input the output data (or feature maps) into the fully connected layers, the discriminator network 120 can reshape or transform the size (or scale) of the output data (or feature maps) that pass through multiple convolutional layers Conv1 to Conv4 and multiple pooling layers. If unnecessary, Figure 3 The reshaping or transformation operation can be omitted. The discriminator network 120 can activate the output data passing through multiple convolutional layers Conv1 to Conv4 and multiple pooling layers, and can output a signal indicating whether the wafer pattern is real or fake. For example, Figure 1 The nodes of the discriminator network 120 can form a fully connected layer to perform the above activation operation.

[0046] Figure 4Schematic illustration of where the input vector passes through Figure 2 The process of generator network processing. Figure 4 Reference Figure 2 and Figure 3 Described.

[0047] Processor 15 can input an input vector into generator network 110. As the input vector passes through multiple layers of generator network 110, the size (or scale) of the input vector can be gradually increased (or expanded). For example, the operation of generator network 110 can be the opposite of the operation of discriminator network 120 and can be similar to the operation of deconvolutional neural network. Generator network 110 can scale the size of the input vector to the size of a real wafer image.

[0048] To feed the input vector into the layers of the generator network 110, the processor 15 can reshape or transform the size (or scale) of the input vector. If unnecessary, Figure 4 The reshaping or transformation operation can be omitted. The generator network 110 can increase the size (or scale) of the input vector by repeatedly performing unpooling operations on the input vector. Unpooling can be referred to as "upsampling". For example, Figure 1 The nodes of the generator network 110 can form a depooling layer for performing the aforementioned depooling operation. The generator network 110 can repeatedly perform deconvolution operations (or transpose convolution operations) on the feature map (or output data) output from the depooling layer, and can generate feature maps. For example, Figure 1 The nodes of the generator network 110 can form deconvolution layers to perform the aforementioned deconvolution operation. The input vector can pass through multiple unpooling layers and multiple deconvolution layers Deconv1 to Deconv4 of the generator network 110 under the control of the processor 15, and the number of layers is not limited to this. Figure 4 The example shown. A depooling layer and a deconvolution layer can be collectively referred to as a depooling / deconvolution layer. Generator network 110 can output a wafer pattern by allowing the input vector to pass through multiple depooling layers and multiple deconvolution layers.

[0049] Figure 5 Detailed examples of embodiments based on the inventive concept are shown. Figure 1 Image generation model 100b is an image generation model. Figure 1 An example of image generation model 100 is provided. The differences between image generation model 100b and image generation model 100a will be described in detail.

[0050] Processor 15 may not generate an input vector, but instead generate an input array comprising some of the sampled values ​​SV from the actual wafer pattern. Processor 15 may input the input array as input data to generator network 110 and may perform learning on generator network 110. After generator network 110 has completed learning, processor 15 may generate an input array comprising some of the sampled values ​​SV from any other wafer 11 sent from test device 13, and may input the input array as input data to generator network 110. Generator network 110 may generate and output wafer patterns based on other wafers 11.

[0051] For example, processor 15 may arrange some sampled values ​​SV on the input array based on the positions of some semiconductor dies 12 on the wafer 11 from which it measures the sampled values ​​SV. The values ​​based on the sampled values ​​SV may be the sampled values ​​SV themselves, or they may be values ​​adjacent to the sampled values ​​SV. For example, processor 15 may reshape or set the size of the input array, including the sampled values ​​SV and predetermined values ​​or based on the values ​​of the sampled values ​​SV, to the size of the wafer pattern. For example, the input array may be a two-dimensional vector corresponding to the size of the wafer pattern.

[0052] Figure 6 Schematic illustration of the input array passing through Figure 5 The process of generator network processing. Figure 6 Reference Figures 3 to 5 Described.

[0053] Processor 15 can input an input array into generator network 110. As the input array passes through multiple layers of generator network 110, the size (or scale) of the input array can be gradually reduced or expanded. Before inputting the input array into generator network 110, processor 15 can reshape or set the size of the input array to the dimensions of the wafer pattern.

[0054] In some embodiments, the generator network 110 can operate similarly to a CNN. The generator network 110 can apply filters to the input array, repeatedly perform convolution operations (Conv1 to Conv4) on the sampled values ​​of the input array corresponding to the filters and the values ​​of the filters, and generate feature maps. As described above, even when performing convolution operations, the generator network 110 can maintain the size of the input array and the feature map without reducing or expanding them. For example, the generator network 110 can apply padding to the input array and the feature map. Figure 1The nodes of the generator network 110 can form convolutional layers Conv1 to perform the convolution operations described above. The input array can pass through multiple convolutional layers Conv1 to Conv4 of the generator network 110 under the control of the processor 15, and the number of layers is not limited to this. Figure 6 The example shown.

[0055] In some example embodiments, the generator network 110 can operate similarly to a deconvolutional neural network. The generator network 110 can generate feature maps by repeatedly performing deconvolution operations (or transpose convolution operations) on the input array. For example, Figure 1 The nodes of the generator network 110 can form deconvolution layers that perform the deconvolution operation described above. The input array can pass through multiple deconvolution layers of the generator network 110 under the control of the processor 15. In some embodiments, Figure 6 The generator network 110 may not perform depooling or upsampling operations on the input array. Furthermore, the generator network 110 may not include a reference array. Figure 3 The fully connected layer is described.

[0056] Figure 7 Detailed examples of embodiments based on the inventive concept are shown. Figure 1 Image generation model 100c is an image generation model. Figure 1 An example of image generation model 100 is provided. The differences between image generation model 100c and image generation model 100b will be described in detail.

[0057] Processor 15 can generate input data including an input array and coordinate values ​​(X1, Y1), (X2, Y2), and (X3, Y3), which indicate the positions of some semiconductor dies 12 on wafer 11 from which some sampled values ​​SV are measured, and processor 15 can input the input data to generator network 110. For example, coordinate values ​​(X1, Y1), (X2, Y2), and (X3, Y3) can be based on a Cartesian coordinate system.

[0058] Figure 8 Detailed examples of embodiments based on the inventive concept are shown. Figure 1 Image generation model. Image generation model 100d is... Figure 1 An example of image generation model 100 is provided. The differences between image generation model 100d and image generation model 100b will be described in detail.

[0059] Processor 15 can generate input data including an input array and coordinate values ​​(r1, θ1), (r2, θ2), and (r3, θ3), which indicate the position of some semiconductor die 12 on wafer 11 from which some sampled values ​​SV are measured, and processor 15 can input the input data to generator network 110. For example, coordinate values ​​(r1, θ1), (r2, θ2), and (r3, θ3) can be based on polar coordinates using the center of wafer 11 as the origin.

[0060] In some embodiments, the processor 15 can also input process parameters as input data to the reference. Figures 2 to 8 The generator network 110 of the described image generation models 100a to 100d. For example, process parameters may include parameters associated with the equipment for manufacturing wafer 11, parameters associated with the test equipment 13 for testing wafer 11, process conditions associated with wafer 11, etc. Process parameters may include the following information about wafer 11: temperature, pressure, and / or dimensions.

[0061] Figure 9 Showing a true image of the sample wafer and a reference Figures 5 to 8 The image generation model described generates pseudo-images. Wafer images of sample wafers "A", "B", and "C" are illustrated in... Figure 9 At a line of real image. The generator network 110 of image generation model 100b can receive some sampled values ​​measured from some semiconductor dies of sample wafers "A", "B" and "C", and can generate and output wafer images of sample wafers "A", "B" and "C". The wafer images generated by the generator network 110 of image generation model 100 are illustrated in Figure 9 The first pseudo-image in the first row. The generator network 110 of the image generation model 100c can receive some sampled values ​​from some semiconductor dies of sample wafers "A", "B" and "C", and can generate and output wafer images of sample wafers "A", "B" and "C". The wafer images generated by the generator network 110 of the image generation model 100 are illustrated in Figure 9 The second pseudo-image in the first row. The generator network 110 of the image generation model 100d can receive some sampled values ​​from some semiconductor dies of sample wafers "A", "B", and "C", and can generate and output wafer images of sample wafers "A", "B", and "C". The wafer images generated by the generator network 110 of the image generation model 100 are illustrated in... Figure 9 The third pseudo-image in the first line.

[0062] Figure 10 Show Figure 9The error between the real image and the pseudo image. The error can be the mean absolute error (MSE) or the root mean square error (RMSE), which is based on the difference between sampled pixel values ​​of the real image (e.g., the wafer pattern generated by test device 13) and sampled pixel values ​​of the pseudo image (e.g., the wafer pattern generated by generator network 110 of image generation model 100). Figure 10 In this context, "FI" is an abbreviation for pseudo-image. FI1 can indicate the wafer pattern generated by the generator network 110 of image generation model 100b. The MAE and RMSE between the wafer pattern of test device 13 and the wafer pattern generated by the generator network 110 of image generation model 100b can fall within the ranges from y3 to y4 and from y5 to y6, respectively. FI2 can indicate the wafer pattern generated by the generator network 110 of image generation model 100c, and FI3 can indicate the wafer pattern generated by the generator network 110 of image generation model 100d. Compared to the generator network 110 of image generation model 100b, coordinate information can be further input into the generator network 110 of each of image generation models 100c and 100d. Compared to the generator network 110 of image generation model 100b, the MAE and RMSE between the wafer pattern of test device 13 and the wafer pattern generated by the generator networks 110 of image generation models 100c / 100d can be further reduced. The MAE and RMSE between the wafer pattern of test device 13 and the wafer pattern generated by generator network 110 of image generation model 100c / 100d can belong to the range from y2 to y3 and from y3 to y4, respectively.

[0063] Figure 11 Detailed examples of embodiments based on the inventive concept are shown. Figure 1 The image generation model 100e can be any of the image generation models 100b to 100d described above. The image generation model 100e can include a generator network 110 and a discriminator network 120 learned by the processor 15 relative to the chip 11 of any product. Figure 11 The image generation model 100e can be in a state of learning relative to any product by the processor 15.

[0064] Processor 15 can generate input data about other products' chips 11 and can input the input data to generator network 110. The input data is an example of an input array in... Figure 11 As shown, processor 15 may depend on reference 15. Figures 2 to 8The described example embodiment generates input data for a wafer 11 of another product. Processor 15 can generate at least one of the following input vectors as input data: sampled values ​​measured from some semiconductor dies of the wafer 11 of the other product, an input array, and the coordinates of some semiconductor dies on the wafer 11. Generator network 110 can generate a wafer map of the wafer 11 of the other product from the input data.

[0065] Figure 12 Showing a real image of any other chip and by Figure 11 The pseudo-images generated by the image generation model. Wafer images of sample wafers "A", "B", "C", "D", and "E" are illustrated in... Figure 12 The image generation model 100e's generator network 110 can receive sampled values ​​measured from some semiconductor dies of sample wafers "A", "B", "C", "D", and "E", and can generate and output wafer images of sample wafers "A", "B", "C", "D", and "E". The wafer images generated by the generator network 110 of the image generation model 100 are illustrated in... Figure 12 At the location of the pseudo-image. (Reference) Figure 12 The wafer pattern of a pseudo image can resemble the wafer pattern of a real image.

[0066] Figure 13 It is a flowchart illustrating the operation, in which a processor according to an example embodiment of the inventive concept learns an image generation model stored in memory, executes the learned image generation model, and generates a wafer image. Figure 13 The flowchart will refer to Figure 1 and Figure 12 Described.

[0067] In operation S110, computing device 14 can receive a wafer pattern from test device 13. The wafer pattern received in operation S110 can indicate the characteristics of all semiconductor dies 12 of wafer 11 and can be generated by test device 13. In operation S120, processor 15 can input the wafer pattern from operation S110 into discriminator network 120 of image generation model 100.

[0068] In operation S130, processor 15 can learn the discriminator network 120 so that the discriminator network 120 will identify the wafer image received in operation S110 as genuine. Processor 15 can update or adjust the weights or biases of the nodes of discriminator network 120 based on the discrimination results of discriminator network 120.

[0069] In operation S140, the processor 15 can learn the discriminator network 120 so that the discriminator network 120 can identify the wafer image output from the generator network 110 as real. The processor 15 can update or adjust the weights or biases of the nodes of the discriminator network 120 based on the discrimination results of the discriminator network 120.

[0070] In operation S150, processor 15 can generate data that includes sampled values ​​of the wafer image received in operation S110. Processor 15 can input the generated data into the generator network 110 of the image generation model 100. In addition to the sampled values, processor 15 can also include coordinate values ​​in the data to be input to generator network 110, indicating the position of some semiconductor dies 12 on wafer 11 from which some sampled values ​​are measured. Furthermore, processor 15 can generate a one-dimensional input vector including the data to be input to generator network 110, or it can generate an input array (e.g., a two-dimensional input vector corresponding to the wafer) (see reference). Figures 5 to 8 ).

[0071] In operation S160, processor 15 can perform learning on discriminator network 120, so that discriminator network 120 will identify the wafer image output from generator network 110 in operation S150 as real. Processor 15 can update or adjust the weights or biases of nodes in generator network 110 based on the discrimination results of discriminator network 120.

[0072] In operation S170, processor 15 can receive sampled values ​​from any other chip 11. Other chips 11 can be distinguished from chip 11 in operation S110. The products of the plurality of semiconductor dies 12 on chip 11 in operation S170 can be the same as or different from the products of the plurality of semiconductor dies 12 on chip 11 in operation S110.

[0073] As in operation S150, in operation S180, processor 15 can generate data that includes the sampled values ​​received in operation S170. Processor 15 can input the generated data into generator network 110, and generator network 110 can generate and output wafer patterns for other wafers 11. Operations S170 and S180 can be repeated on one or more wafers 11.

[0074] In some embodiments, the processor 15 may perform operations S110 to S160 on the wafer 11 in which any one of the products is implemented. Then, the processor 15 may further perform operations S110 to S160 on the wafer 11 in which any other product is implemented. For example, the processor 15 may learn the generator network 110 and the discriminator network 120 of the image generation model 100 for both the one product and the other product.

[0075] According to an exemplary embodiment of the inventive concept, the test equipment can generate a wafer pattern of a sample wafer (or die) by testing a sample wafer (or die) instead of all wafers (or dies), and the computing device can execute an image generation model to generate wafer patterns of the remaining wafers. Therefore, compared to some embodiments in which the test equipment tests all wafers (or dies), time and / or cost can be reduced.

[0076] The computing device 14 may include processing circuitry, such as hardware including logic circuitry; hardware / software combinations, such as processors executing software; or combinations thereof. For example, the processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0077] In some embodiments, Figure 1 IGNs can utilize various artificial neural network organization and processing models, such as convolutional neural networks (CNNs), deconvolutional neural networks, recurrent neural networks (RNNs) (optionally including long short-term memory (LSTM) units and / or gated recurrent units (GRUs)), stacked neural networks (SNNs), state-space dynamic neural networks (SSDNNs), deep belief networks (DBNs), generative adversarial networks (GANs), and / or restricted Boltzmann machines (RBMs).

[0078] Alternatively or additionally, such machine learning systems may include other forms of machine learning models, such as, for example, linear and / or logistic regression, statistical clustering, Bayesian classification, decision trees, dimensionality reduction such as principal component analysis, and expert systems; and / or combinations thereof, including ensembles such as random forests.

[0079] Although the inventive concept has been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made therein without departing from the spirit and scope of the inventive concept as set forth in the appended claims.

Claims

1. A non-transitory computer-readable medium storing program code including an image generation model, which, when executed, causes a processor to: By inputting sampled data from some semiconductor dies among multiple semiconductor dies including a wafer into the generator network of the image generation model, the generator network of the image generation model is trained to generate wafer images. Output a wafer diagram generated during the training of the generator network, indicating the plurality of semiconductor dies; The wafer image output from the generator network is input into the discriminator network of the image generation model, such that the discriminator network discriminates the wafer image generated during the training period; and Based on the discrimination results of the discriminator network, which correctly distinguishes between the generated wafer image and the real wafer image, additional training is performed on the generator network.

2. The non-transitory computer-readable medium of claim 1, wherein the image generation model, when executed, causes the processor to: The sampling data is arranged on the input data depending on the location of some of the semiconductor dies in the wafer.

3. The non-transitory computer-readable medium of claim 1, wherein the image generation model, when executed, causes the processor to: Generate input data including sampled data and at least one of a predetermined first value and a second value based on the sampled data.

4. The non-transitory computer-readable medium of claim 3, wherein the image generation model, when executed, causes the processor to: The sampled value of the sampled data is set on the input data depending on the position of the first semiconductor die among the semiconductor dies; and Depending on the position of the second semiconductor die among the remaining semiconductor dies in the plurality of semiconductor dies, at least one of the first value and the second value is set on the input data.

5. The non-transitory computer-readable medium of claim 1, wherein the image generation model, when executed, causes the processor to: Reshape the dimensions of the input data to match the dimensions of the chip pattern.

6. The non-transitory computer-readable medium of claim 1, wherein the image generation model, when executed, causes the processor to: Reshape the size of the input data into a one-dimensional vector.

7. The non-transitory computer-readable medium of claim 1, wherein the image generation model, when executed, causes the processor to: Input data is generated that includes sampled data and coordinate values ​​indicating the location of some of the semiconductor dies on the wafer.

8. The non-transitory computer-readable medium of claim 7, wherein the coordinate values ​​are based on one of a Cartesian coordinate system and a polar coordinate system.

9. The non-transitory computer-readable medium of claim 1, wherein the plurality of semiconductor dies are a plurality of first semiconductor dies, and the wafer is a first wafer, and When the image generation model is executed, the processor: A generator network based on the discrimination results is executed to generate a wafer diagram of a second wafer including multiple second semiconductor dies.

10. The non-transitory computer-readable medium of claim 1, wherein the image generation model, when executed, causes the processor to: Generate input data including sampling data and wafer process parameters.

11. A non-transitory computer-readable medium storing program code including an image generation model, which, when executed, causes a processor to: The discriminator network of the image generation model is trained such that it identifies a first wafer image, comprising multiple sampled values ​​measured from multiple semiconductor dies of a wafer, as genuine, and identifies a second wafer image, output by the generator network of the image generation model from some of the multiple sampled values, as counterfeit; and The generator network is trained so that the discriminator network can identify the second chip image output by the generator network as real.

12. The non-transitory computer-readable medium of claim 11, wherein the image generation model, when executed, causes the processor to: Input data, including the sampled values ​​and the coordinate values ​​of some of the semiconductor dies from which the sampled values ​​were measured, is input to the generator network.

13. The non-transitory computer-readable medium of claim 11, wherein the plurality of semiconductor dies are a plurality of first semiconductor dies, the wafer is a first wafer, and the plurality of sample values ​​are a plurality of first sample values. When the image generation model is executed, the processor: The discriminator network is trained such that it identifies a third wafer image, comprising multiple second sample values ​​measured from multiple second semiconductor dies, as genuine, and a fourth wafer image, output from a generator network that inputs some of the multiple second sample values, as counterfeit; and The generator network is trained so that the discriminator network can identify the fourth chip image output by the generator network as real.

14. The non-transitory computer-readable medium of claim 11, wherein the image generation model, when executed, causes the processor to: Input data, including the sampled values ​​and wafer process parameters, is fed into the generator network.

15. The non-transitory computer-readable medium of claim 11, wherein the generator network outputs a second wafer pattern from input data including said sampled values ​​without upsampling.

16. A computing device comprising a processor configured to execute an image generation model stored in a memory, wherein the processor is configured to: The discriminator network of the image generation model is trained such that the discriminator network identifies a first wafer image of the first wafer, which includes multiple first sample values ​​measured from multiple first semiconductor dies of the first wafer, as genuine, and identifies a second wafer image of the first wafer output by the generator network of the image generation model, which is input to some of the multiple first sample values, as fake. The generator network is trained so that the discriminator network can identify the second wafer image output by the generator network as real; and Some of the second sampled values ​​measured from some of the multiple second semiconductor dies of the second wafer are input into the generator network to generate a third wafer pattern of the second wafer.

17. The computing device of claim 16, wherein the positions of some of the second sampled values ​​on the third wafer pattern respectively correspond to the positions of some of the first sampled values ​​on the second wafer pattern.

18. The computing device of claim 16, wherein the processor is configured to: Input data, including the first sampled values ​​and the coordinate values ​​of some of the semiconductor dies from which the first sampled values ​​were measured, is input to the generator network.

19. The computing device of claim 16, wherein the processor is configured to: Input data, including some of the first sampled values ​​and the process parameters of the first wafer, is input into the generator network.

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