Coding device and coding method

Abstract

The present disclosure can provide an encoder and an encoding method. The encoder can include a first stage and a second stage. The first stage can be configured to receive a first input, decode the first input, and generate a first output including the decoded first input. The second stage can be configured to receive a second input, receive the first output from the first stage, and convert the first input and the second input from a first coding system to a second coding system based on the second input and the first output. The second stage can generate a second output including the converted first input and the converted second input.

Description

Technical Field

[0001] The present disclosure relates to an encoding device and an encoding method. Background Art

[0002] Magnetoresistive Random Access Memory (MRAM) is a non-volatile memory in which data is stored in magnetic storage elements. In a simple configuration, each cell has two ferromagnetic plates separated by a thin insulating layer, and each of the two ferromagnetic plates can hold a magnetic field. One of the plates is a permanent magnet set to a selected polarity, and the magnetic field of the other plate can be changed to match the magnetic field of an external magnetic field to store a bit. Depending on the magnetic field, the cell is in a low (R L ) resistance state that can represent logic "1" or in a high (R H ) resistance state that can represent logic "0".

[0003] Due to process variations, individual MRAM cells in an array can have different RH values (when programmed at RH) and different RL values (when programmed at RL). Process variations can cause the resistance values of the high (RH) state and the low (RL) state to overlap, which can lead to read errors. This overlap is defined between RH min and RL max . Summary of the Invention

[0004] According to an embodiment of the present disclosure, an encoding device includes a first stage and a second stage. The first stage is configured to receive a first input, decode the first input, and generate a first output including the decoded first input. The second stage is configured to receive a second input, receive the first output from the first stage, convert the first input and the second input from a first coding system to a second coding system based on the second input and the first output, and generate a second output including the converted first input and the converted second input.

[0005] According to an embodiment of the present disclosure, an encoding device includes a first stage and a second stage. The first stage includes a 7:1 decoder. The first stage is configured to receive a first input including a 0th bit, a 1st bit, and a 2nd bit of an input code, decode the first input, and generate a first output including the decoded first input at seven output nodes of the 7:1 decoder. The second stage includes a second-stage input port, a first plurality of two-input port AND gates, and a 15-bit output. The second-stage input port is configured to receive a 3rd bit of the input code. Each of the first plurality of two-input port AND gates has a first input port respectively connected to one of the seven output nodes of the 7:1 decoder and a second input port connected to an inversion of the 3rd bit of the input code. Each of the second plurality of two-input port AND gates has a first input port respectively connected to one of the seven output nodes of the 7:1 decoder and a second input port connected to the 3rd bit of the input code. Bits 1 to 7 of the 15-bit output respectively correspond to the outputs of the first plurality of two-input port AND gates. Bits 9 to 15 of the 15-bit output respectively correspond to the outputs of the second plurality of two-input port AND gates. Bit 8 of the 15-bit output corresponds to the second-stage input port.

[0006] According to an embodiment of the present disclosure, an encoding method includes: receiving a 0th bit, a 1st bit, a 2nd bit, and a 3rd bit of an input code; decoding the 0th bit, the 1st bit, and the 2nd bit of the input code to create a first output; generating a first portion of a second output based on the 3rd bit of the input code and the first output; generating a second portion of the second output based on the 3rd bit of the input code and the first output; and generating a third portion of the second output including the 3rd bit of the input code. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of various features may be arbitrarily increased or decreased.

[0008] Figure 1 is a block diagram that may illustrate an encoding system according to some embodiments.

[0009] Figure 2A and Figure 2B illustrates a truth table according to some embodiments.

[0010] Figure 3 is a flowchart of a method for providing encoding according to some embodiments.

[0011] Figure 4A and Figure 4B illustrates swapping logic gate inputs using NOR2 gates according to some embodiments to reduce standby current for more frequently occurring cases.

[0012] Figure 5A and Figure 5B illustrates swapping logic gate inputs according to some embodiments to reduce standby current for more frequent cases using a 2 (AND2) gate.

[0013] Figure 6A and Figure 6B illustrates swapping logic gate inputs according to some embodiments to reduce standby current for more frequent trim codes used in a sense amplifier (SA) trimming function. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are set forth below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Additionally, the disclosure may repeat reference numerals and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0015] In addition, for ease of explanation, spatially relative terms such as "beneath", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the figures to another (other) element or feature. In addition to the orientation depicted in the figures, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative terms used herein may be interpreted accordingly.

[0016] MRAM is a non-volatile random access memory technology that uses magnetic storage elements to store data. MRAM stores data in memory cells that have two superimposed layers of magnetic material separated by a thin insulating film to define the magnetic tunnel junction (the "MTJ element") of the MRAM cell. These two layers include a magnetic layer that is permanently magnetized in a fixed magnetic field alignment direction (this layer is called the pinned layer) and a magnetic layer with variable magnetization (this layer is called the free layer). The magnetic layer with variable magnetization can be magnetized in one of two orientations relative to the permanently magnetized layer. These two orientations are characterized by significantly different series resistances through the superimposed layers of the MTJ. The magnetic field orientation of the variable layer can be aligned to be the same (parallel) as the magnetic field orientation of the permanent magnet layer, or the magnetic field of the variable layer can be aligned to be directly opposite (antiparallel) to the magnetic field orientation of the permanent magnet layer. The parallel alignment state has a relatively low resistance, while the antiparallel alignment state has a higher resistance.

[0017] These two states of the MRAM cell are sensed from its relatively high or low resistance (R H and R L ), which represents the different binary logic values of the bits stored in the memory. A reference voltage is applied to the MRAM cell, and the resulting cell current can be used to determine whether the cell is in the low-resistance state or the high-resistance state. For this purpose, a sense amplifier (SA) can be used to compare the cell current with a reference current.

[0018] In MRAM, a thermometer code encoder (i.e., a unary code encoder) can be used for the trimming function corresponding to the SA. The thermometer code encoder can be used in circuit design to achieve its advantage of glitch reduction. Traditional thermometer code encoders not only occupy a large part of the SA area, but also induce a large standby current. Compared with other coding types such as binary encoding and gray encoding, the area consumed by the thermometer code encoder in traditional systems is relatively large.

[0019] Embodiments of the present disclosure can reduce the implementation area of the encoder and also reduce the standby current. For example, compared with traditional systems, embodiments of the present disclosure can reduce the implementation area of the encoder by about 22%, and compared with traditional systems, can reduce the standby current of the encoder by about 15.3%. The encoder according to the embodiments of the present disclosure can be disposed in the MRAM and can be used in combination with the SA trimming function of the MRAM.

[0020] For example, embodiments of the present disclosure may utilize the symmetric property of unary codes to simplify the implementation logic of embodiments of the present disclosure. In addition, due to the simplified logic, embodiments of the present disclosure may reduce standby current. Further, by considering the input distribution, embodiments of the present disclosure may swap logic gate inputs to reduce the standby current of more frequently occurring trim codes used in the SA trimming function of MRAM.

[0021] Traditional SA trimming logic may account for 43% of the total SA area. In addition, the SA trimming logic may be highly symmetric. As will be elaborated in more detail below, embodiments of the present disclosure may use, for example, a 7:1 decoder (e.g., instead of a 15:1 decoder) and logic gates to achieve logical equivalence. Since embodiments of the present disclosure may use a smaller decoder, the total SA area may be reduced. In this way, embodiments of the present disclosure may reduce the SA trimming logic area by about 22% compared to traditional systems, without any trimming resolution penalty. Further, embodiments of the present disclosure may reduce the SA trimming logic standby current by about 15.3% compared to traditional systems, while maintaining, for example, "gray-to-thermal" characteristics. This reduction in standby current may be achieved because embodiments of the present disclosure may use a smaller decoder and may also swap logic gate inputs to support default trim codes, which will be elaborated in more detail below.

[0022] Figure 1 is a block diagram that may illustrate an encoding system 100 according to some embodiments of the present disclosure. As Figure 1 shown, the encoding system 100 may include a first stage 102 and a second stage 104. The first stage 102 may be configured to receive a first input 106, decode the first input 106, and produce a first output 108 including the decoded first input. The second stage 104 may be configured to receive a second input 110, receive the first output 108 from the first stage 102, and convert the first input 106 and the second input 110 from a first encoding system to a second encoding system based on the second input 110 and the first output 108. The second stage 104 may produce a second output 112 including the converted first input 106 and the converted second input 110. The second stage 104 may include a first plurality of two-input port AND gates 114 and a second plurality of two-input port AND gates 116. According to embodiments of the present disclosure, the encoding system 100 may be disposed, for example, in an MRAM 118. For example, the second output 112 may correspond to a trim code used in the sense amplifier (SA) trimming function 120 of the MRAM 118. The second output 112 may include a first portion 122, a second portion 124, and a third portion 126.

[0023] Figure 2AShows truth table 200 according to some embodiments of the present disclosure. For example, input code 202 may be provided as an input to encoding system 100, and output code 204 may be provided as an output by encoding system 100 in response to input code 202. In Figure 2A an example, input code 202 uses reflected binary (RB) or Gray code, which is an ordering of a binary number system such that two consecutive values differ by only one bit. Although input code 202 may include Gray code as shown in Figure 2A , embodiments of the present disclosure are not limited to Gray code, and other coding systems (such as binary) may be utilized as input code 202. In addition, although output code 204 may include unary code as shown in Figure 2A , embodiments of the present disclosure are not limited to unary code, and other coding systems (such as other coding systems with symmetric properties) may be utilized as output code 204. The symmetric property may include the quality of the truth table, where when a first block of the truth table is transposed onto a second block by rotating it around a vertical axis and a horizontal axis, the first block of the truth table may be the same as the second block of the truth table, and vice versa.

[0024] As Figure 2A shown, the unary code may have a symmetric property. For example, the block in truth table 200 that includes rows 0 to 7 and columns F to 9 includes all 0s. Similarly, the block in truth table 200 that includes rows 8 to 15 and columns 7 to 1 includes all 0s. In addition, the block in truth table 200 that includes rows 8 to 15 and columns F to 9 is the same as the block in truth table 200 that includes rows 0 to 7 and columns 7 to 1. In addition, column 3 of input code 202 is the same as column 8 of output code 204. Embodiments of the present disclosure may utilize Figure 2A such a symmetric property of the unary code shown to simplify the implementation logic of encoding system 100. Embodiments of the present disclosure may use other symmetric coding systems and are not limited to unary code.

[0025] Symmetric properties may exist in truth table 200. For example, by rotating first block 206 around the vertical axis including column 8, and then rotating first block 206 again around the horizontal axis between rows 7 and 8, first block 206 can be transposed onto second block 208. Similarly, by rotating second block 208 around the vertical axis including column 8, and then rotating second block 208 again around the horizontal axis between rows 7 and 8, second block 208 can be transposed onto first block 206. After such a transposition, the two blocks are the same. Therefore, truth table 200 may have symmetric properties.

[0026] Figure 2BIllustrates how a truth table 200 is obtained in the case of replacing a 15:1 one-hot encoder with an encoding system 100 according to some embodiments of the present disclosure. The 15:1 one-hot encoder may consume a large area and require a high standby current. At least due to the symmetry of the truth table 200, the encoding system 100 according to some embodiments of the present disclosure may provide simplified logic compared to the 15:1 one-hot encoder. For example, as shown in the truth table 210, outputs 8 to 15 may be removed. Next, outputs 7 to 1 may be copied to outputs 15 to 9, as shown in the truth table 212. Then, as shown in the truth table 214, output 8 may be connected to input 3 because, as can be seen in this example, output 8 is always the same as input 3. The encoding system 100 may use input 3 being tied low to obtain the truth table 216. The next output 9 may be swapped with F, output A may be swapped with E, and output B may be swapped with D to obtain the truth table 204. Thus, the encoding system 100 may provide a logic equivalent of a 15:1 encoder by using only a 7:1 encoder. As can be seen from Figure 2B this, such a reduction in encoder size can be achieved by leveraging the symmetric properties of the one-hot code to simplify the implementation logic of the embodiments of the present disclosure.

[0027] Returning to Figure 1 , embodiments of the present disclosure may include, for example, a 4-bit input to 15-bit output gray code-to-one-hot code encoder. In this example, the first stage 102 may include, but is not limited to, a 7:1 decoder. As Figure 1 shown, the first stage 102 may receive a first input 106 including the 0th, 1st, and 2nd bits of the input code 202. Then the first stage 102 may decode the first input 106. For example, for the values of the 0th, 1st, and 2nd bits of the input code 202 shown in the truth table 200, the first stage 102 may decode these values into the corresponding 7 outputs in columns 7 to 1 (for rows 0 to 7) or columns 9 to F (for rows 8 to 15) of the output code 204. The first stage 102 may then produce a first output 108 including the decoded first input 106 on seven output nodes on the first stage 102 (e.g., including a 7:1 decoder). Although Figure 1 shown producing the first output 108 on only one output interface, this is for simplicity, and the first stage 102 may have any number of output nodes, e.g., one node for each bit in the first output 108. In this example, the number of output nodes may include 7.

[0028] The second stage 104 may include a second stage input port that may receive the 3rd bit of the input code 202 as the second input 110. Accordingly, the second stage 104 may pass the value of column 3 of the input code 202 as the value of column 8 of the output code 204. As Figure 2A shown, these two columns may match in the truth table 200.

[0029] As Figure 1 shown, the second stage 104 may include a first plurality of two-input port AND gates 114. Each of the first plurality of two-input port AND gates 114 may have a first input port connected to one of the seven output nodes of a 7:1 decoder (i.e., the first stage 102) and a second input port connected to the inverse of the 3rd bit of the input code 202. Similarly, the second stage 104 may include a second plurality of two-input port AND gates 116. Each of the second plurality of two-input port AND gates 116 may have a first input port connected to one of the seven output nodes of the 7:1 decoder and a second input port connected to the 3rd bit of the input code 202. Accordingly, in the Figure 1 example shown, the first plurality of two-input port AND gates 114 may include seven two-input port AND gates (e.g., indicated by Figure 1 the "×7" in). Similarly, the second plurality of two-input port AND gates 116 may include seven two-input port AND gates (e.g., indicated by Figure 1 the "×7" in).

[0030] The second output 112 of the second stage 104 may include a 15-bit output corresponding to the Figure 1 example shown. For example, bits 1 to 7 of the 15-bit output (i.e., columns 1 to 7 of the output code 204) may respectively correspond to the outputs of the first plurality of two-input port AND gates 114, bits 9 to 15 of the 15-bit output (i.e., columns 9 to F of the output code 204) may respectively correspond to the outputs of the second plurality of two-input port AND gates 116, and bit 8 of the 15-bit output (i.e., column 8 of the output code 204) may correspond to the above-mentioned second stage input port. AND gates are shown in Figure 1 but according to embodiments of the present disclosure, other types of logic gates that may be used in combination with other circuit elements such as buffers and inverters may be used.

[0031] Figure 3 is a flowchart of the general stages involved in a method 300 according to an embodiment of the present disclosure for providing encoding. The manner of implementing each stage of the method 300 will be described in more detail below.

[0032] The method 300 shown begins and proceeds to operation 310, in which the encoding system 100 may receive the 0th, 1st, 2nd, and 3rd bits of the input code. For example, the first stage 102 may receive a first input 106 including the 0th, 1st, and 2nd bits of the input code 202.

[0033] The method 300 shown proceeds from operation 310, in which the encoding system 100 receives the 0th, 1st, 2nd, and 3rd bits of the input code, to operation 320, in which the first stage 102 may decode the 0th, 1st, and 2nd bits of the input code to create a first output 108. For example, for the values of the 0th, 1st, and 2nd bits of the input code 202 shown in the truth table 200, the first stage 102 may decode these values into the corresponding 7 outputs in columns 7 to 1 (for rows 0 to 7) or columns 9 to F (for rows 8 to 15) of the output code 204.

[0034] Once the first stage 102 decodes the 0th, 1st, and 2nd bits of the input code to create the first output 108 in operation 320, the method 300 may continue to operation 330, in which the second stage 104 may generate a first portion 122 of a second output 112 based on the 3rd bit of the input code and the first output 108. Then the method 300 may continue to operation 340, in which the second stage 104 may generate a second portion 122 of the second output 112 based on the 3rd bit of the input code and the first output 108. Next, the method 300 may continue to operation 350, in which the second stage 104 may generate a third portion 126 of the second output 112 including the 3rd bit of the input code. Operations 330, 340, and 350 may be implemented substantially simultaneously, as described in more detail below.

[0035] For example, the first stage 102 may generate a first output 108 including the decoded first input 106 on seven output nodes on the first stage 102 (e.g., including a 7:1 decoder). The second stage 104 may receive a second input 110. The second stage 104 may include a second-stage input port that may receive the 3rd bit of the input code 202 as the second input 110. Thus, the second stage 104 may pass the value of column 3 of the input code 202 as the value of column 8 of the output code 204 as the third portion 126 of the second output 112. As Figure 2A shown, these two columns may match.

[0036] The second stage 104 may receive a first output 108 from the first stage 102. For example, each of the first plurality of two-input port AND gates 114 may have a first input port connected to one of the seven output nodes of a 7:1 decoder (i.e., the first stage 102) and a second input port connected to the inverse of the 3rd bit of the input code 202. Similarly, the second stage 104 may further include a second plurality of two-input port AND gates 116. Each of the second plurality of two-input port AND gates 116 may have a first input port connected to one of the seven output nodes of the 7:1 decoder and a second input port connected to the 3rd bit of the input code 202.

[0037] The second stage 104 may convert the first input 106 and the second input 110 from the first coding system to the second coding system based on the second input 110 and the first output 108. For example, the second output 112 of the second stage 104 may include a 15-bit output corresponding to the Figure 1 illustrated example. For example, bits 1 to 7 of the 15-bit output (i.e., the first part 122) (i.e., columns 1 to 7 of the output code 204) may respectively correspond to the outputs of the first plurality of two-input port AND gates 114, bits 9 to 15 of the 15-bit output (i.e., the second part 124) (i.e., columns 9 to F of the output code 204) may respectively correspond to the outputs of the second plurality of two-input port AND gates 116, and bit 8 of the 15-bit output (i.e., the third part 126) (i.e., column 8 of the output code 204) may correspond to the above-mentioned second stage input port. Thus, the second stage 104 may generate a second output 112 including the converted first input 106 and the converted second input 110. Once the second stage 104 generates the second output 112 including the converted first input 106 and the converted second input 110, the method 300 may end.

[0038] Figure 4A and Figure 4B illustrate swapping logic gate inputs to reduce the standby current for more frequent cases. In Figure 4A and Figure 4B a NOR2 gate is shown, but according to embodiments of the present disclosure, other types of logic gates may be used. As Figure 4A and Figure 4B shown, the standby current of the NOR2 gate may depend on the input. If the top P-type metal-oxide-semiconductor (PMOS) transistor is turned off ( Figure 4A ), the leakage current through the parasitic capacitance between the two PMOS transistors to ground may be significantly smaller than when the top PMOS transistor is turned on ( Figure 4B ).

[0039] Figure 5A and Figure 5BThe switching of logic gate inputs is shown to reduce the standby current for more frequently occurring cases. In Figure 5A and Figure 5B an AND2 gate is shown, but according to embodiments of the present disclosure, other types of logic gates can be used. As Figure 5A and Figure 5B shown, the standby current of the AND2 gate can depend on the input. If the upper N-type metal-oxide-semiconductor (NMOS) transistor is turned off ( Figure 5A ), the leakage current through the parasitic capacitance can be significantly less than when the upper NMOS transistor is turned on ( Figure 5B ), and there can be two leakage current paths when the NMOS transistor is turned on.

[0040] Furthermore, by considering the input distribution (e.g., Gaussian trimmed code distribution), embodiments of the present disclosure can switch the logic gate inputs to reduce the standby current for more frequently occurring trimmed codes used in the SA trimming function of the MRAM. Embodiments of the present disclosure can also switch the logic gate inputs to support default trimmed codes (i.e., optimized to support trimmed codes close to the default value (e.g., 8)). In other words, embodiments of the present disclosure can map the most frequently used trimmed codes to the states of the coding system 100 with the lowest standby current. Therefore, embodiments of the present disclosure can reduce the SA trimming logic area by about 22% compared to traditional systems without any trimming resolution penalty. In addition, embodiments of the present disclosure can reduce the SA trimming logic standby current by about 15.3% compared to traditional systems while maintaining, for example, the "Gray to hot" characteristic.

[0041] Figure 6A and Figure 6B show, for example, the switching of logic gate inputs to reduce the standby current for more frequently occurring trimmed codes used in the SA trimming function. According to embodiments of the present disclosure, the trimmed codes "7" and "8" can include the most frequently occurring cases. Taking the trimmed code "8" as an example, according to the truth table 216, the trimmed code "8" corresponds to IN<3:0> = 1100. Since the trimmed code "8" occurs most frequently, embodiments of the present disclosure can accordingly rearrange the inputs to the logic gate to minimize the energy. According to embodiments of the present disclosure, whenever IN<3:0> is connected to the logic gate, the inputs corresponding to zero (e.g., IN<1:0>) can be connected, for example, in the manner shown in Figure 6A and Figure 6B . As Figure 6A shown, for a logic gate such as OR (e.g., OR, NOR), the inputs corresponding to zero can be connected to the PMOS transistor closer to the center node between the PMOS transistor and the NMOS transistor. As Figure 6BAs shown, for logic gates similar to (e.g., AND, NAND), the input corresponding to zero can be connected to the NMOS transistor closer to the center node between the PMOS transistor and the NMOS transistor. Thus, the logic gate inputs can be swapped to reduce the standby current of the more frequently occurring trim codes.

[0042] Embodiments of the present disclosure may include, for example, a 4-bit input to 15-bit output Gray code to one-hot encoder. Embodiments of the present disclosure may utilize the symmetric characteristics of the one-hot code to simplify the implementation logic of the embodiments of the present disclosure. In addition, due to the simplified logic, embodiments of the present disclosure may reduce the standby current. Further, by considering the input distribution, embodiments of the present disclosure may swap the logic gate inputs to reduce the standby current of the more frequently occurring trim codes used in the SA trimming function of the MRAM.

[0043] Embodiments of the present disclosure may include an encoding system. The encoding system may include a first stage and a second stage. The first stage may be configured to receive a first input, decode the first input, and produce a first output including the decoded first input. The second stage may be configured to receive a second input, receive the first output from the first stage, and convert the first input and the second input from a first encoding system to a second encoding system based on the second input and the first output. The second stage may produce a second output including the converted first input and the converted second input.

[0044] In some embodiments, the second stage includes a plurality of logic gates.

[0045] In some embodiments, the first stage includes a decoder that produces a first output smaller than the second output.

[0046] In some embodiments, the decoder includes a 7:1 decoder.

[0047] In some embodiments, the second stage includes a first plurality of two-input port AND gates. Each of the first plurality of two-input port AND gates has a first input port connected to one of the seven output nodes of the 7:1 decoder and a second input port connected to the inversion of the input bit.

[0048] In some embodiments, the second stage includes a second plurality of two-input port AND gates. Each of the second plurality of two-input port AND gates has a first input port connected to one of the seven output nodes of the 7:1 decoder and a second input port connected to the input bit.

[0049] In some embodiments, the inputs of the first plurality of two-input port AND gates and the second plurality of two-input port AND gates are arranged to reduce the standby current of the more frequently occurring trim codes used in the sense amplifier (SA) trimming function.

[0050] In some embodiments, the first coding system includes one of a binary code and a Gray code.

[0051] In some embodiments, the second coding system includes a unary code.

[0052] In some embodiments, the coding device is disposed in a magnetoresistive random access memory (MRAM).

[0053] In some embodiments, the second output corresponds to a trim code used in a sense amplifier (SA) trimming function of the magnetoresistive random access memory.

[0054] Another embodiment of the present disclosure may include a coding system. The coding system may include a first stage and a second stage. The first stage may include a 7:1 decoder configured to: i) receive a first input including a 0th bit, a 1st bit, and a 2nd bit of an input code, ii) decode the first input, and iii) generate a first output including the decoded first input on seven output nodes of the 7:1 decoder. The second stage may include a second stage input port configured to receive a 3rd bit of the input code. The second stage may further include a first plurality of two-input port AND gates. Each of the first plurality of two-input port AND gates may have a first input port respectively connected to one of the seven output nodes of the 7:1 decoder and a second input port connected to an inversion of the 3rd bit of the input code. The second stage may further include a second plurality of two-input port AND gates. Each of the second plurality of two-input port AND gates may have a first input port respectively connected to one of the seven output nodes of the 7:1 decoder and a second input port connected to the 3rd bit of the input code. The second stage may further include a 15-bit output, wherein bits 1 to 7 of the 15-bit output respectively correspond to outputs of the first plurality of two-input port AND gates, bits 9 to 15 of the 15-bit output respectively correspond to outputs of the second plurality of two-input port AND gates, and bit 8 of the 15-bit output corresponds to the second stage input port.

[0055] In some embodiments, the input code includes a Gray code.

[0056] In some embodiments, the input code includes a binary code.

[0057] In some embodiments, the 15-bit output includes a unary code.

[0058] In some embodiments, the coding device is disposed in a magnetoresistive random access memory (MRAM).

[0059] In some embodiments, the 15-bit output corresponds to a trim code used in a sense amplifier (SA) trimming function of the magnetoresistive random access memory.

[0060] Another embodiment of the present disclosure may include a method of providing an encoder. Embodiments of the present disclosure may include: receiving a first input at a first stage, decoding the first input at the first stage, and generating a first output including the decoded first input at the first stage. Embodiments of the present disclosure may further include: receiving a second input at a second stage, receiving the first output from the first stage at the second stage, and converting the first input and the second input from a first coding system to a second coding system based on the second input and the first output at the second stage. Embodiments of the present disclosure may further include generating a second output including the converted first input and the converted second input by the second stage.

[0061] An embodiment of the present disclosure may include a coding method. The coding method includes: receiving the 0th bit, the 1st bit, the 2nd bit, and the 3rd bit of an input code; decoding the 0th bit, the 1st bit, and the 2nd bit of the input code to create a first output; generating a first part of a second output based on the 3rd bit of the input code and the first output; generating a second part of the second output based on the 3rd bit of the input code and the first output; and generating a third part of the second output including the 3rd bit of the input code.

[0062] In some embodiments, generating the first part of the second output includes performing a logical AND operation on the inverse of the 3rd bit and the first output.

[0063] In some embodiments, generating the second part of the second output includes performing a logical AND operation on the 3rd bit and the first output.

[0064] The above content outlines the features of several embodiments to enable those skilled in the art to better understand various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or realize the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent structures do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions, and alterations without departing from the spirit and scope of the present disclosure.

[0065] [Description of Symbols]

[0066] 100: Coding system

[0067] 102: First stage

[0068] 104: Second stage

[0069] 106: First input

[0070] 108: First output

[0071] 110: Second input

[0072] 112: Second output

[0073] 114, 116: Two-input port AND gate

[0074] 118: MRAM

[0075] 120: Sense amplifier (SA) trimming function

[0076] 122: First part

[0077] 124: Second part

[0078] 126: Third part

[0079] 200, 210, 212, 214, 216: Truth tables

[0080] 202: Input code

[0081] 204: Output code / truth table

[0082] 206: First block

[0083] 208: Second block

[0084] 300: Method

[0085] 310, 320, 330, 340, 350: Operations.

Claims

1. A coding device, characterized in that: include: The first level is configured as: Receive a first input, decoding the first input, and generating a first output comprising the decoded first input; as well as The second level is configured as: Receive a second input, receiving the first output from the first stage, based on the second input and the first output, converting the first input and the second input from a first coding system to a second coding system, and generating a second output including the converted first input and the converted second input, Wherein the first stage comprises a decoder, the decoder generating the first output which is smaller than the second output.

2. The encoding device according to claim 1, characterized in that The second stage includes a plurality of logic gates.

3. The encoding device according to claim 1, characterized in that The decoder comprises a 7:1 decoder.

4. The encoding device according to claim 3, characterized in that The second stage includes a first plurality of two-input port AND gates, each of the first plurality of two-input port AND gates having a first input port connected to one of the seven output nodes of the 7:1 decoder respectively and a second input port connected to an inversion of an input bit.

5. The encoding device according to claim 4, characterized in that The second stage includes a second plurality of two-input port AND gates, each of the second plurality of two-input port AND gates having a first input port connected to one of the seven output nodes of the 7:1 decoder and a second input port connected to an input bit, respectively.

6. The encoding device according to claim 5, characterized in that The inputs of the first plurality of two-input port AND gates and the second plurality of two-input port AND gates are arranged to reduce standby current for more commonly occurring trim codes used in a sense amplifier trim function.

7. The encoding device according to claim 1, characterized in that The first encoding system includes one of a binary code and a Gray code.

8. The encoding device according to claim 1, characterized in that The second encoding system includes a unary code.

9. The encoding device according to claim 1, characterized in that The encoding device is arranged in a magnetoresistive random access memory.

10. The encoding device according to claim 9, characterized in that The second output corresponds to a trim code used in a sense amplifier trim function of the magnetoresistive random access memory.

11. A coding device, characterized in that: include: The first stage, including the 7:1 decoder, is configured as: receiving a first input including the 0th, 1st and 2nd bits of an input code, decoding the first input, and generating a first output comprising the decoded first input at seven output nodes of the 7:1 decoder; and The second level includes: The second input port is configured to receive the third bit of the input code, a first plurality of two-input port AND gates, each of the first plurality of two-input port AND gates having a first input port connected to one of the seven output nodes of the 7:1 decoder and a second input port connected to an inversion of the third bit of the input code, a second plurality of two-input port AND gates, each of the second plurality of two-input port AND gates having a first input port connected to one of the seven output nodes of the 7:1 decoder and a second input port connected to the third bit of the input code, and A 15-bit output, wherein bits 1 to 7 of the 15-bit output respectively correspond to outputs of the first plurality of two-input port AND gates, bits 9 to 15 of the 15-bit output respectively correspond to outputs of the second plurality of two-input port AND gates, and bit 8 of the 15-bit output corresponds to the second-level input port.

12. The encoding device according to claim 11, characterized in that The input code includes a Gray code.

13. The encoding device according to claim 11, characterized in that The input code comprises a binary code.

14. The encoding device according to claim 11, characterized in that The 15-bit output comprises a unary code.

15. The encoding device according to claim 11, characterized in that The device is arranged in a magnetoresistive random access memory.

16. The encoding device according to claim 15, characterized in that The 15-bit output corresponds to a trim code used in a sense amplifier trim function of the magnetoresistive random access memory.

17. A coding method, characterized in that: include: Receive the 0th, 1st, 2nd and 3rd digits of the input code; decoding the bit 0, the bit 1, and the bit 2 of the input code to create a first output; generating a first portion of a second output based on the third bit of the input code and the first output; generating a second portion of the second output based on the third bit of the input code and the first output; as well as A third portion of the second output is generated that includes the 3rd bit of the input code.

18. The encoding method according to claim 17, characterized in that: Generating the first portion of the second output includes ANDing an inversion of the third bit with the first output.

19. The encoding method according to claim 17, characterized in that: Generating the second portion of the second output includes performing an AND operation on the third bit and the first output.

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