Save-Restore in Integrated Circuits

Abstract

In the described example, the circuit for saving and restoring the design block state includes: a first memory 102 configured to receive different portions of first data and store them in different first memories in a first order; and a second memory 112 coupled to the first memory 102. The first memory 102 with the most memory cells 106 has N memory cells 106. The first memory 102 with fewer memory cells 106 has M memory cells 106. When saving the state, the first data from different first memories 102 are written to different corresponding areas of the second memory 112 in a second order as second data. The second order repeats the portion of the first data stored in the first N mod M cells 106 of the corresponding first memory 102 with fewer cells 106 determined using the first order. When restoring the state, the second data is read from the second memory 112 and stored in the corresponding first memory 102 in the first order; the repeated portion is repeatedly stored in the corresponding first memory 102 with fewer cells 106.

Description

Background Art

[0001] The present application relates generally to energy conservation in electronic circuits, and more particularly to save-restore functionality in integrated circuits.

[0002] An integrated circuit (IC) may include various functional blocks such as input / output, control, encoding, and decoding. The system directs power to the IC, and the IC directs power to the component functional blocks to keep the IC and the functional blocks (respectively) active and enable them to perform their respective functions on demand. (A "design block" refers to an IC or a functional block.) When the functions performed by a design block are not being used, the design block can be idle. However, even when idle, the active design block will continue to consume power to maintain the current state of the contents of the memory elements (such as flip-flops and registers) of the design block (also called the background or configuration of the design block). If an active design block is powered down to reduce power consumption, its current state is lost, which can result in errors or the need to reinitialize the design block, either of which will generally take power and time to resolve.

[0003] Save-Restore (SR) is a method that enables a design block in a specific operating state to be powered down and later powered up and returned to the same operating state to reduce power and time costs. To perform SR, the operating state of the design block is stored in an on-die memory before the design block is powered down. When the design block is powered up again, the operating state information is retrieved from the on-die memory and used to reconstruct the operating state in the design block.

[0004] Scan chains can be used in test designs. Scan chains typically include clocked, serially connected flip-flops that are connected to load data stored by memory elements in a design block when a scan enable signal is asserted. Scan chain lengths (the number of cells (e.g., flip-flops) in different scan chains) can be different due to, for example, clock domain mixing constraints, memory chains, physical design and floor plan requirements, and power domain merging. Scan elements (e.g., cells and control elements) typically need to be in the same clock domain (synchronous clocking). Moreover, separate power domains typically have separate, dedicated scan chains that are active in a power mode provided by the respective power domain when the respective power domain is "on" (active).

[0005] FIG. 1A shows an example block diagram 100 of a prior art circuit for saving the state of a design block using scan chains 102. (For convenience, the scan chains 102 are referred to as numbered from the top scan chain 102 (chain 1) to the bottom scan chain 102 (chain 4).) Bits 104 representing the state of the design block are first loaded from the design block memory elements into cells 106 of the plurality of scan chains 102. (The design blocks and the structures for loading the state information from the design blocks into the scan chains 102 are not shown.) The individual bits 104 correspond to the state of the respective memory elements in the design blocks. The scan chains 102 are connected to output to an SR control block 108. The SR control block 108 is connected to output control signals including a clock 130 to the scan chains 102. The SR control block 108 is also connected to store the bits 104 output from the end cells 110 of the respective scan chains 102 to a memory 112, where in FIG. 1A (and subsequent figures), the end cells 110 are intended to identify the rightmost cell in each respective chain. For example, chain 1 includes five cells 106, where the fifth cell from left to right is also the end cell 110 because it is connected to output its stored bit to the SR control block 108. As another example, chain 3 (which includes fewer cells 106 than chain 1) includes three cells, where the third cell from left to right is also the end cell 110, which is also connected to output its stored bit 104 to the SR control block 108. The memory 112 has multiple rows 114 and multiple columns 116 of memory cells 118. The SR control block 108 stores bits 104 to the rows 114 of memory cells 118 at a time by typically copying one bit 104 of the end cell 110 of each scan chain 102 to the corresponding row 114 and then writing. Thus, individual columns 116 of memory cells 118 correspond to individual respective scan chains 102; bits 104 read out from a scan chain 102 are stored in the memory cells 118 in the corresponding columns 116. The rows 114 are numbered one (1) to five (5) (five being the length of the longest of the scan chains 102), and the columns 116 are numbered one (1) to four (4) (four being the number of scan chains 102). In FIGS. 1B to 1F , the arrows from the SR control block 108 to the memory 112 indicate the row 114 of the memory 112 that has just been loaded with data from the scan chain 102.

[0006] FIG. 1B shows an example block diagram 120 of a prior art circuit for using a scan chain 102 to save the state of a design block after one clock 130 cycle has passed after FIG. 1A . The scan chain 102 is clocked by a clock signal 130 received from an SR control block 108. The clock 130 causes the scan chain 102 to continuously advance the bits 104 stored by the cells 106 of the scan chain 102 to the adjacent subsequent cells 106 of the respective scan chain 102 in the direction of the end cells 110 of the respective scan chains 102. The end cells 110 of the scan chains 102 output their stored bits 104 to the SR control block 108, which sequentially stores the bits 104 in a row of memory cells 118. Thus, in FIG. 1B , the bits 104 (i.e., 1100) from the previous end cells 110 of FIG. 1A have been written to row 114 number (1) of memory 112. Furthermore, the bit 104 in each scan chain 102 has been successively advanced one cell 106 per scan chain 102. The successive advancement of the bit 104 (also referred to herein as iterative advancement of the bit 104 or stepwise movement of the bit 104) means that if the bit 104 is stored in the serially connected cells 106 of the scan chain (which for reference are considered from left to right in the orientation of FIG. 1C and are referred to for connection as cells A, B, and C), then since the cells 106A, B, C are serially connected A→B→C such that C is the terminal cell 110, a single iterative advancement will output the bit 104 stored in cell 106C, cause the bit 104 stored in cell 106B to be stored in cell 106C, and cause the bit 104 stored in cell 106A to be stored in cell 106B. (Thus, the clock 130 is used as a propagation signal that causes the bit 104 to be successively advanced through the scan chain 102. In some embodiments, a propagation signal other than the clock 130 may be used.)

[0007] FIG1C shows an example block diagram 122 of a prior art circuit for saving the state of a design block using a scan chain 102 after two clock 130 cycles after FIG1A . As shown in FIG1C , the clock 130 cycles output by the SR control block 108 cause the scan chain 102 to iterate the successive advancement of bits 104 stored by the scan chain 102 and sequentially output the contents of the scan chain 102 to the SR control block 108. Thus, in FIG1C , the end cell bit (i.e., 0001) from the previous FIG1B has been written into row number (2) of the memory 112. As the bits 104 output from the end cell 110 of the scan chain 102 are stored in sequential rows of corresponding columns 116 of memory cells, the contents of the scan chain 102 are progressively reconstructed in the memory 112, transposed from the scan chain 102 to the memory columns 116.

[0008] Figure ID shows an example block diagram 124 of a prior art circuit for saving the state of a design block using scan chains 102 after three clock 130 cycles after Figure 1A. As shown in Figure IE, because chain 3 has only three cells 106, it has now output all three of its storage bits 104 and is empty.

[0009] FIG IE shows an example block diagram 126 of a prior art circuit for saving the state of a design block using scan chains 102 after four clock 130 cycles after FIG IA. As shown in FIG IE, because chain 2 has only four cells 106, it has now output all four of its stored bits 104. Also, because chain 3 is empty after FIG ID, the SR control block 108 has no bit 104 to store in the memory cell 118 located at row number (4), column (3) (also referred to as (4,3) in the (row, column) convention) of the memory 112.

[0010] FIG. 1F shows an example block diagram 128 of a prior art circuit for saving the state of a design block using scan chains 102 after five clock 130 cycles after FIG. 1A . As shown in FIG. 1F , all scan chains 102 have now output all of their storage bits 104. Also, because chains 2 and 3 are empty after FIG. 1D , the SR control block 108 has no bits 104 to store at memory cells 118 (5, 2) and (5, 3). Therefore, memory cells 118 (4, 3), (5, 2), and (5, 3) are not assigned by the SR control block 108.

[0011] FIG. 1G shows a prior art example block diagram 132 of a memory 112 for saving the state of a design block. The memory 112 may be viewed as a first-in, first-out (FIFO); this reflects the connections that have been used for the state save process. Moreover, as described with respect to the state save process, the scan chains 102 are clocked together. Thus, if the memory 112 state shown in FIG. 1F is used to reload state data into the scan chains 102 by reading row by row from the top of the memory 112, then data from the shorter scan chains 102 (i.e., in columns (2) and (3)) will iteratively advance through and out of the respective shorter scan chains 102, and unknown data (in the example shown in FIG. 1F, the contents of (4,3), (5,2), and (5,3)) will be written to and retained in the shorter scan chains 102, resulting in an inaccurate copy of the data stored during the save portion of the save-reset event. Thus, the memory 112 is rearranged in preparation for restoring the design block state. FIG. 1G shows the memory 112 before being rearranged 134 and after being rearranged 136. The memory cells 118 are rearranged so that the last few bits 104 written from the shorter scan chain 102 are aligned with the last row 114 (the fifth row 114, because the longest scan chain 102 in FIGS. 1A to 1F is five cells 106 long) of the memory cells 118 written by the SR control block 108. Also, the now unassigned memory cells 118 at (1,2), (1,3), and (2,3) are filled with zeros. These filler zeros are first loaded into the corresponding scan chains 102 (chains 2 and 3, as the scan chains 102 that are shorter than the longest scan chain 102) during the state recovery process (see FIGS. 2A to 2F), and are discarded during the state recovery process by moving over the end cells 110 of the shorter chains 102. This will result in proper alignment of the state recovery data within the cells 106 of the scan chains 102 when the recovery process is complete. The memory 112 rearrangement shown in FIG. 1G may require software execution or specialized hardware execution and add considerable time to the SR process.

[0012] Alternatively, in some prior art embodiments, additional flip-flops may be used to increase the length of the shorter scan chain 102 so that it is as long as the longest scan chain 102 so that each scan chain 102 has the same number of cells 106. This enables the state recovery data within the cells 106 of the scan chain 102 to be properly aligned when the recovery process is complete without requiring rearrangement of the memory 112. However, the additional flip-flops add a significant amount of additional device area usage and add additional leakage current when the design block is in a functional mode.

[0013] FIG. 2A shows an example block diagram 200 of a prior art circuit for restoring a saved state of a design block using a scan chain 102. The state restore process may begin when a non-active design block is powered up from a sleep state. As shown in FIG. 2A , at the start of the state restore process, the memory 112 contains the same data as the configuration at the end of the state save process shown in FIG. 1G after re-saving the data at step 136. The memory 112 is connected to output the data read out from the row 114 to the SR control block 108. The SR control block 108 is configured to output the data received from the memory 112 to the first unit 202 of the corresponding scan chain 102 and distribute the clock 130 to the scan chain 102. (In FIGS. 2A-2F , the first cell 202 wishes to identify the leftmost cell in each respective scan chain 102.) The clock 130 causes data received by each of the scan chains 102 from the SR control block 108 to be stored in the corresponding cell 106 of each receiving scan chain 102 and causes bits 104 (not shown in FIG. 2A ) to iteratively advance through the serially connected cells 106 of the respective scan chains 102. In FIGS. 2B-2F , the arrows from the memory 112 to the SR control block 108 indicate the rows 114 that have just been unloaded from the memory 112 to reload the respective cells 106 in each of the scan chains 102.

[0014] FIG. 2B shows an example block diagram 202 of a prior art circuit for restoring a saved state of a design block using a scan chain 102 after one clock 130 cycle has passed since FIG. 2A . The clock 130 cycle causes the data stored in the first row 114 (row 1) of the memory 112 to be read out of the memory 112 and stored in the cells 106 in the corresponding ones of the scan chains 102. Thus, the columns 116 in the memory 112 correspond to the respective scan chains 102, such that the data read out of the memory cells 118 in column 1 is stored in chain 1, the data read out of the memory cells 118 in column 2 is stored in chain 2, and so on. Thus, the data is transferred back to the scan chain 102 from which it was previously read in the save process described with respect to FIGS. 1A to 1G . Note that the zeros moved into the second and third scan chains 102 (chains 2 and 3) are fillers added during the memory 112 rearrangement shown in and described with respect to FIG. 1G . These zeros will later be discarded (ie, moved out of the corresponding scan chain 102) during the recovery process, as described below.

[0015] 2C shows an example block diagram 204 of a prior art circuit for restoring the state of a design block using scan chains 102 after two clock 130 cycles have passed since FIG 2A. The clock 130 cycles cause the bits 104 stored in each of the scan chains 102 to move through the serially connected cells 106 in the scan chains 102 and the data stored in each column of the second row 114 of memory cells 118 to be read out of the memory 112 and stored in the corresponding scan chain 102.

[0016] 2D shows an example block diagram 206 of a prior art circuit for restoring a saved state of a design block using a scan chain 102 after three clock 130 cycles have passed since FIG 2A. The clock 130 cycles cause the bits 104 stored in the scan chain 102 to move through the serially connected cells 106 in the scan chain 102 and the data stored in the third row 114 of the memory cells 118 to be read out of the memory 112 and stored in the corresponding scan chain 102.

[0017] 2E shows an example block diagram 208 of a prior art circuit for restoring a saved state of a design block using a scan chain 102 after the fourth clock 130 cycle has passed since FIG 2A. The clock 130 cycle causes the bits 104 stored in the scan chain 102 to move through the serially connected cells 106 in the scan chain 102 and the data stored in the fourth row 114 of memory cells 118 to be read out of the memory 112 and stored in the corresponding scan chain 102. Because the third scan chain 102 (Chain 3) is only three cells 106 long, one of the filler zeros is shifted out of Chain 3 and thereby discarded.

[0018] FIG. 2F shows an example block diagram 210 of a prior art circuit for restoring a saved state of a design block using a scan chain 102 after the fifth clock 130 cycle has passed since FIG. 2A . The clock 130 cycle causes the bits 104 stored in the scan chain 102 to move through the serially connected cells 106 in the scan chain 102 and the data stored in the fifth row 114 of the memory cells 118 to be read out of the memory 112 and stored in the corresponding scan chain 102 . Because the second and third scan chains 102 (chains 2 and 3) are less than five cells 106 long (the length of the longest scan chain 102 (the first and fourth scan chains 102)), filler zeros are shifted out of each of chains 2 and 3 and thereby discarded. As shown in FIG. 2F , the scan chain 102 now contains the bits 104 in the same configuration as when the save process in FIG. 1A was started. The data contained in the scan chain 102 can then be used to restore the saved state of the design block, reversing the process used to initially load the state data of the design block into the scan chain 102 . Summary of the invention

[0019] In the described example, a circuit for saving and restoring a design block state includes: a first memory configured to receive different portions of first data and store them in different first memories in a first order; and a second memory coupled to the first memory. The first memory with the most memory cells has N memory cells. The first memory with fewer memory cells has M memory cells. When saving the state, the first data from the different first memories are written to different corresponding areas of the second memories in a second order as second data. The second order repeats a portion of the first data stored in the first N mod M cells of the corresponding first memory with fewer cells in a sequence determined using the first order. When restoring the state, the second data is read from the second memory and stored in the corresponding first memory in the first order; the repeated portion is repeatedly stored in the corresponding first memory with fewer cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] FIG. 1A shows an example block diagram of a prior art circuit for preserving the state of a design block using a scan chain.

[0021] 1B shows an example block diagram of a prior art circuit for preserving the state of a design block using a scan chain after one clock cycle has passed following FIG. 1A .

[0022] 1C shows an example block diagram of a prior art circuit for preserving the state of a design block using a scan chain after two clock cycles following FIG. 1A .

[0023] 1D shows an example block diagram of a prior art circuit for preserving the state of a design block using a scan chain after three clock cycles following FIG. 1A .

[0024] IE shows an example block diagram of a prior art circuit for preserving the state of a design block using a scan chain after four clock cycles following FIG. 1A.

[0025] IF shows an example block diagram of a prior art circuit for preserving the state of a design block using a scan chain after five clock cycles following FIG. 1A.

[0026] FIG. 1G shows a block diagram of a prior art example of a memory for saving the state of a design block.

[0027] 2A shows an example block diagram of a prior art circuit for restoring a saved state of a design block using a scan chain.

[0028] 2B shows an example block diagram of a prior art circuit for restoring a saved state of a design block using a scan chain after one clock cycle has passed since FIG. 2A .

[0029] 2C shows an example block diagram of a prior art circuit for restoring the state of a design block using a scan chain after two clock cycles have passed since FIG. 2A .

[0030] 2D shows an example block diagram of a prior art circuit for restoring a saved state of a design block using a scan chain after three clock cycles have passed since FIG. 2A .

[0031] 2E shows an example block diagram of a prior art circuit for restoring a saved state of a design block using a scan chain after the fourth clock cycle has passed since FIG. 2A .

[0032] 2F shows an example block diagram of a prior art circuit for restoring a saved state of a design block using a scan chain after the fifth clock cycle has passed since FIG. 2A .

[0033] Figure 3A A block diagram showing an example of a circuit for saving the state of a design block using a scan chain.

[0034] Figure 3B Display for self Figure 3A Block diagram of an example circuit that uses a scan chain to save the state of a design block after one clock cycle.

[0035] Figure 3C Display for self Figure 3A Figure 2 is an example block diagram of a circuit that uses a scan chain to save the state of a design block after two clock cycles.

[0036] Figure 3D Display for self Figure 3A Figure 1 is an example block diagram of a circuit that uses a scan chain to save the state of a design block after three clock cycles.

[0037] Figure 3E Display for self Figure 3A Figure 2 is an example block diagram of a circuit that uses a scan chain to save the state of a design block after four clock cycles.

[0038] Figure 3F Display for self Figure 3A Figure 2 is an example block diagram of a circuit that uses a scan chain to save the state of a design block after five clock cycles.

[0039] Figure 4A A block diagram showing an example of a circuit for saving the state of a design block using a scan chain.

[0040] Figure 4B Display for self Figure 4A 2 is an example block diagram of a circuit that uses a scan chain to restore a saved state of a design block after one clock cycle.

[0041] Figure 4C Display for self Figure 4A 2 is a block diagram of an example circuit that uses a scan chain to restore the state of a design block after two clock cycles.

[0042] Figure 4D Display for self Figure 4A 2 is an example block diagram of a circuit that uses a scan chain to restore the saved state of a design block after three clock cycles.

[0043] Figure 4E Display for self Figure 4A 2 is an example block diagram of a circuit that uses a scan chain to restore the saved state of a design block after four clock cycles.

[0044] Figure 4F Display for self Figure 4A 4 is an example block diagram of a circuit that uses a scan chain to restore a saved state of a design block after the fifth clock cycle.

[0045] Figure 5A Shows an example procedure for saving the state of a design block using scan chains.

[0046] Figure 5B Shows an example procedure for saving the state of a design block using scan chains.

[0047] Fig. 6A An example block diagram of a clock circuit for clocking a scan chain used to save the state of a design block is shown.

[0048] Figure 6B A timing diagram showing an example of a clock circuit.

[0049] Figure 6C An example block diagram of a clock circuit for clocking a scan chain for saving the state of a design block and configured to suppress erroneous clock transitions upon SR mode transitions is shown.

[0050] Fig.6D A timing diagram showing an example of a clock circuit. DETAILED DESCRIPTION

[0051] Figure 3A An example block diagram 300 of a circuit for preserving the state of a design block using a scan chain 102 is shown. Figures 3A to 3F The circuits 300, 312, 314, 316, 318, 320 of FIG. 1A to 1F share various aspects with the circuits 100, 120, 122, 124, 126, 128 of FIG. 1A to 1F, respectively, and therefore, the same element numbers from FIG. 1A to 1F are carried over. Figures 3A to 3F For this type of item. Figures 3A to 3FThe shorter scan chain 102 in the circuits 300, 312, 314, 316, 318, 320 does not include a connection between the end cell 110 and the SR control block 108, and Figures 3A to 3F The longer scan chain 102 in the circuits 300, 312, 314, 316, 318, 320 includes a connection between the end cell 110 and the SR control block 108' ( Figures 3A to 4F Shown in and about Figures 3A to 4F The depicted SR control block 108' has some similarities to the SR control block 108 of prior art FIGS. 1A-1F and 2A-2F, but also introduces additional functionality described with respect to the inventive subject matter introduced herein).

[0052] When a design block receives a sleep command and is ready to power down, a state preservation process may be performed. The design block state data is initially loaded from the design block memory element (not shown) into the corresponding scan chain 102 using the state data input 302 (this process is not shown), resulting in Figure 3A The scan chain 102 loaded with status data is shown in FIG. Figure 3A The longest scan chain 102 shown in FIG. 1 is five cells 106 long. In the longest scan chain 102, the state data input 302 is directly connected to the first cell 304 of the scan chain 102 (farthest from the SR control block 108' in terms of the number of serially connected scan path cells 106). In the shorter scan chains 102, the state data input 302 is connected to the first input of a multiplexer 306. The multiplexer 306 also receives as a second input the output of the end cell 110 of the corresponding scan chain 102. The SR mode selector 308 provides a control signal to each multiplexer 306 to control which of the corresponding inputs of the multiplexer is output to the first cell 304 of the corresponding scan chain 102. When the scan chain 102 is executing Figures 3A to 3F During the storage process shown in FIG. 1 , the SR mode selector 308 will select the output of the terminal unit 110. When the scan chain 102 is executing Figures 4A to 4F (and below about Figures 4A to 4F When the recovery process of SR mode is further described, the SR mode selector 308 will select the data received from the status data input 302.

[0053] Each scan chain 102 also includes an SR output 310 that outputs data of the selected cells 106 from the corresponding scan chain 102 to the SR control block 108' for storage in the memory 112. In the longest scan chain 102, the selected cell 106 providing the SR output 310 is the end cell 110. In the shorter scan chains 102, the selected cell 106 providing the SR output 310 is a cell 106 other than the end cell 110 of the corresponding scan chain 102. For the longest scan chain 102 of length N and the shorter scan chains 102 of length M, where the first cell 106 of the shorter scan chain 102 is numbered one (1) and the subsequent cells 106 of the shorter scan chain 102 are consecutively numbered up to the end cell 110 numbered M: The SR output 310 is connected to the (N - M) cell such that when the bit 104 advances through the serially connected cells 106 of the scan chain 102 triggered by the clock 130, the bit 104 in the (N - M) cell 106 is output to the SR control block 108' for storage in the memory 112 and also advances to the next cell 106 (numbered N - M + 1). (For convenience, the scan chains 102 are referred to as being numbered from the top scan chain 102 (chain 1) to the bottom scan chain 102 (chain 4).) As Figure 3A shown, both chain 1 and 4 have the same maximum number of cells (where the length is five cells 106), while chain 2 is four cells 106 long and chain 3 is three cells 106 long. Thus, the SR output 310 of chain 2 is connected to the output of cell 106 one (N - M = 5 - 4 = 1), and the SR output 310 of chain 3 is connected to the output of cell 106 two (N - M = 5 - 3 = 2).

[0054] Consider the general case where N - M ≥ M leading to the generalization of this design. Thus, the SR output 310 should be connected to cell 106 N mod M to produce the results described herein. Note that when N - M < M, cell 106 N mod M is the same as cell 106 N - M.

[0055] In Figures 3A to 3E it, for clarity, the values of the bits 104 that will be output by the corresponding scan chain 102 due to the next clock 130 cycle are shown, where the corresponding SR output 310 is connected to the SR control block 108'. Chain 1 will output 1 from the end cell 110 of chain 1; chain 2 will output 1 from cell 106 one of chain 2; chain 3 will output 0 from cell 106 two of chain 3; and chain 4 will output 0 from the end cell 110 of chain 4.

[0056] Figure 3B Shown is an example block diagram 312 of a circuit for using the scan chain 102 to save the state of a design block after one clock 130 cycle has elapsed since Figure 3A In Figures 3B to 3F3, the arrow from the SR control block 108' to the memory 112 indicates in which row 114 of the memory 112 the SR control block 108' caused the data output from the scan chain 102 to be stored at the most recent clock 130 cycle. In FIG3, the data output from the scan chain 102 as a result of the most recent clock 130 cycle has been stored in row 1 of the memory 112. At the same time (preferably during the same clock 130 cycle), the SR control block 108' reads the bit 104 value from each respective scan chain 102 as follows. Chain 1 will output a 0 from the end cell 110 of chain 1; chain 2 will output a 1 from cell 106 one of chain 2; chain 3 will output a 1 from cell 106 two of chain 3; and chain 4 will output a 1 from the end cell 110 of chain 4.

[0057] like Figure 3B , the bits 104 have progressed successively through the cells 106 of each scan chain 102. Thus, the bits 104 previously stored in the end cells 110 of chains 1 and 4 (the longest scan chains 102) are no longer stored by the respective scan chains 102. However, in chains 2 and 3 (the shorter scan chains 102), the bits 104 stored in the respective end cells 110 are cycled back to the respective multiplexers 306 and passed by the multiplexers 306 (as selected by the SR mode selector 308) to and stored in the respective first cells 304. Thus, the data will cycle through the shorter scan chains 102 such that some of the bits stored in the shorter scan chains 102 will be output to the SR control block 108' and stored in the memory 112 more than once during the number of clock 130 cycles (i.e., N clock 130 cycles) required to fully output the data from the longest chain 102.

[0058] Figure 3C Display for self Figure 3A 1. An example block diagram 314 of a circuit that uses scan chains 102 to save the state of a design block after two clock 130 cycles have passed. The data output from the scan chains 102 as a result of the most recent clock 130 cycle has been stored in row 2 of the memory 112. At the same time, the values ​​of the bits 104 that will be output by the corresponding scan chains 102 as a result of the next clock 130 cycle are: chain 1 will output a 1 from the end cell 110 of chain 1; chain 2 will output a 0 from cell 106 one of chain 2; chain 3 will output a 0 from cell 106 two of chain 3; and chain 4 will output a 1 from the end cell 110 of chain 4. Also, the 0 stored in the end cell 110 of chain 2 from the previous cycle has been cycled back and stored in the first cell 304 of chain 2, and the 0 stored in the end cell 110 of chain 3 from the previous cycle has been cycled back and stored in the first cell 304 of chain 3 (via corresponding multiplexers 306).

[0059] Figure 3D Display for self Figure 3A130 cycles has passed. The data output from the scan chain 102 as a result of the most recent clock 130 cycle has been stored in row 3 of the memory 112. The values ​​of the bits 104 that will be output by the corresponding scan chains 102 as a result of the next clock 130 cycle are: chain 1 will output a 1 from the end cell 110 of chain 1; chain 2 will output a 1 from cell 106 one of chain 2; chain 3 will output a 0 from cell 106 two of chain 3; and chain 4 will output a 0 from the end cell 110 of chain 4. Furthermore, the 1 stored in the end cell 110 of chain 2 from the previous cycle has been looped back and stored in the first cell 304 of chain 2, and the 1 stored in the end cell 110 of chain 3 from the previous cycle has been looped back and stored in the first cell 304 of chain 3 (via the corresponding multiplexers 306). Note that in Figure 3D After three clock cycles 130, chain 3 has returned to the state stored in Figure 3A 106. This is because M (the length of the cells 106 of the scan chain 102) of chain 3 is equal to three (three cells 106, three clock 130 cycles). Therefore, the data sequence output by chain 3 and stored by memory 112 will begin to repeat for the remainder of the state preservation process.

[0060] Figure 3E Display for self Figure 3A 130 cycles has passed. The data output from the scan chain 102 as a result of the most recent clock 130 cycle has been stored in row 4 of the memory 112. The values ​​of the bits 104 that will be output by the corresponding scan chains 102 as a result of the next clock 130 cycle are: chain 1 will output a 0 from the end cell 110 of chain 1; chain 2 will output a 1 from cell 106 one of chain 2; chain 3 will output a 1 from cell 106 two of chain 3; and chain 4 will output a 0 from the end cell 110 of chain 4. Furthermore, the 1 stored in the end cell 110 of chain 2 from the previous cycle has been cycled back and stored in the first cell 304 of chain 2, and the 0 stored in the end cell 110 of chain 3 from the previous cycle has been cycled back and stored in the first cell 304 of chain 3 (via the corresponding multiplexers 306). Note that in Figure 3D Four clock cycles later, chain 2 has returned to the state stored in Figure 3A 106. This is because M (the length of the cells 106 of the scan chain 102) of chain 2 is equal to four (four cells 106, four clock 130 cycles). Therefore, the data sequence output by chain 2 and stored by memory 112 will begin to repeat for the remainder of the state preservation process.

[0061] Figure 3FDisplay for self Figure 3A 304. An example block diagram 320 of a circuit using scan chain 102 to save the state of a design block after five clock 130 cycles have passed. The data output from scan chain 102 as a result of the most recent clock 130 cycle has been stored in row 5 of memory 112. The 1 stored in the end cell 110 of chain 2 from the previous cycle has been cycled back and stored in the first cell 304 of chain 2, and the 0 stored in the end cell 110 of chain 3 from the previous cycle has been cycled back and stored in the first cell 304 of chain 3 (via respective multiplexers 306).

[0062] because Figures 3A to 3F In the state preservation process, if the memory cells 118 in column P (where P is the number from 1 to 4 corresponding to the scan chain P) of the memory 112 are read from row 5 to row 1, then the bits 104 stored in the memory cells 118 in column P will be the same as the bits 104 stored in the memory cells 118 in the left-to-right order. Figure 3A 104 in chain P (scan chain 102 numbered P). This is true for shorter scan chains 102, but with one caveat: the bit 104 stored in memory cell 118 is repeated after the Mth bit 104 (for a given M bits in the scan chain, reading upward in memory 112, the repetition begins at (NM) row 114). This repetition may include one or more copies of the bit 104 originally stored in the scan chain 102 or a partial copy of the bit 104 originally stored in the scan chain 102. For example, Figure 3A The initial content of chain 3, shown in , and having M=3 bits, read from the first cell 106 of chain 3 to the third cell 106 is (1,0,0). Figure 3F The content of column 3 of memory 112 shown in FIG. 1 is (1,0,0,1,0) read from row 5 to row 1 of memory 112. Therefore, reading from row 5 to row 1, Figure 3F Column 3 of memory 112 shown in FIG. 1 contains the initial contents of chain 3 plus (NM=5-3=2) additional bits of chain 3 that are read from the first cell 304 of chain 3 to the third cell 106 (the end cell 110). As a bit 104 progresses through the serially connected cells 106 before one clock 130 cycle, the shorter scan chain 102 cycles from its respective end cell 110 to its respective first cell 304. Thus, during the state recovery process, when data is loaded back from memory 112 into the respective scan chain 102, duplicate bit 104 values ​​(from the shorter scan chain 102) will be overwritten by the same, previously written bit 104 values ​​(as described with respect to FIG. 1 ) as those previously written bit values ​​are cycled from the end cell 110 of the scan chain 102 to the first cell 304 of the scan chain 102. Figures 4A to 4F further described).

[0063] Figure 4AAn example block diagram 400 of a circuit for restoring the state of a scan chain and, therefore, a design block using scan chain 102 is shown. The state restoration process may be performed when a non-active design block wakes up (powers up the design block). Figure 4A As shown in FIG. 1 , at the beginning of the state recovery process, the memory 112 contains the same Figure 3F 104. The memory 112 is connected to output data from its row 114 to the SR control block 108'. The SR control block 108' is configured to output data received from the memory 112 to the first cell 304 of the corresponding scan chain 102 and distribute the clock 130 to the scan chain 102. The clock 130 causes the data received by the scan chain 102 from the SR control block 108' to be stored in the corresponding cell 106 and causes the bit 104 ( Figure 4A 106 ) iteratively advances through the serially connected cells 106 of the corresponding scan chain 102. The shorter scan chain 102 (e.g. Figure 4A 3, chains 2 and 3) also loop the bit 104 advancing from the respective end cell 110 back to the respective multiplexer 306. Because the SR mode selector 308 is set to pass the most recently received data rather than the looped data (which during the state restore process means the data received from the memory 112), the particular data that was looped during the store operation is discarded during the restore operation, and the data received from the memory 112 via the SR control block 108' and the respective state data input 302 is passed by the respective multiplexer 306 for storage in the respective first cell 304 (of chains 2 and 3). However, because the data stored in the memory 112 repeats the data originally stored in the shorter scan chain 102, the repeated bit 104 matches the looped (and discarded) bit 104. In effect, Figures 3A to 3F The state preservation process of 112 fills the memory 112 with the state data stored in the shorter scan chain 102. This avoids zero padding, memory 112 rearrangement, or sacrificing device area to balance the scan chain 102 length with additional cells 106 (as described above with respect to Figures 1A-2F).

[0064] exist Figures 4B to 4F , the arrow from the memory 112 to the SR control block 108 ′ indicates the row 114 that has just been unloaded to reload the scan chain 102 .

[0065] Figure 4B Display for self Figure 4A1 is an example block diagram 402 of a circuit for restoring a saved state of a design block using scan chains 102 after a clock 130 cycle. The clock 130 cycle causes data stored in the first row 114 (row 1) of memory 112 to be read out of memory 112 and stored in cells 106 in corresponding scan chains 102. Thus, columns 116 in memory 112 correspond to respective scan chains 102 such that data read from memory cells 118 in column 1 is stored in chain 1, data read from memory cells 118 in column 2 is stored in chain 2, and so on. Thus, the data is transferred back to the state it was previously in with respect to the scan chain 102. Figures 3A to 3F The description saves the scan chain 102 from which it is read.

[0066] Figure 4C Display for self Figure 4A 4 is an example block diagram 404 of a circuit that uses a scan chain 102 to restore a state of a design block after two clock 130 cycles. The clock 130 cycles cause the bits 104 stored in the scan chain 102 to iteratively move (advance) through the serially connected cells 106 in the scan chain 102 and the data stored in the second row 114 of the memory cells 118 to be read out of the memory 112 and stored in the corresponding scan chain 102.

[0067] Figure 4D Display for self Figure 4A 406 of an example circuit for restoring a saved state of a design block using a scan chain 102 after three clock 130 cycles. The clock 130 cycles cause the bits 104 stored in the scan chain 102 to iteratively move through the serially connected cells 106 in the scan chain 102 and the data stored in the third row 114 of the memory cells 118 to be read out of the memory 112 and stored in the corresponding scan chain 102. At this point in the state restoration process, all cells 106 in chain 3 contain bits 104, but column 3 of the memory 112 is not yet empty. The data remaining in column 3 of the memory 112 will be stored in the cells 106 of chain 3, rather than the same data being looped back from the end cell 110 of chain 3 to the multiplexer 306 of chain 3 as was the case in the save operation. The multiplexer 306 will not pass the looped bit 104 because the SR mode selector 308 currently selects the new data to be input into the shorter scan chain 106.

[0068] Figure 4E Display for self Figure 4A4 is an example block diagram 408 of a circuit for restoring a saved state of a design block using a scan chain 102 after four clock 130 cycles. The clock cycles 130 cause the bits 104 stored in the scan chain 102 to iteratively move through the serially connected cells 106 in the scan chain 102 and the data stored in the fourth row 114 of the memory cells 118 are read out of the memory 112 and stored in the corresponding scan chain 102. Because the third scan chain 102 (Chain 3) is only three cells 106 long, the data stored in the fourth row 114 of the memory cells 118 is read out of the memory 112 and stored in the corresponding scan chain 102. Figure 4D The zero in the end cell 110 of mid-chain 3 is connected back to the input of the multiplexer 306 of chain 3, but it is actually discarded because the SR mode selector 308 controls the multiplexer 306 to output the data from the SR control block 108' rather than looping the data back in. Therefore, the chain 3 multiplexer 306 outputs the zero previously stored in column 3 (corresponding to chain 3), row 4 of the memory 112 (read out of chain 3 in the fourth clock 130 cycle of the state preservation process, and read out of column 3 of the memory 112 in the fourth clock 130 cycle of the state restoration process), whereby it is stored in the first cell 304 of chain 3.

[0069] exist Figure 4E , all cells 106 of chain 2 contain storage bits 104 read from memory 112 during the state recovery process. Figure 4F The behavior of chain 2 (discarding the cyclic bit 104, storing the same bit 104 read from the memory 112) will be similar to Figure 4E The behavior of chain 3.

[0070] Figure 4F Display for self Figure 4A 4. An example block diagram 410 of a circuit for restoring a saved state of a design block using a scan chain 102 after a fifth clock 130 cycle has passed. The clock 130 cycle causes the bits 104 stored in the scan chain 102 to iteratively move through the serially connected cells 106 in the scan chain 102 and the data stored in the fifth row 114 of the memory cells 118 are read out of the memory 112 and stored in the first cells 304 of the corresponding scan chain 102. The ones previously stored in the end cells 110 of chains 2 and 3 are cycled back as inputs to the respective multiplexers 306 and are discarded (due to the SR mode selector 308), and the same ones read out of row 5, columns 2 and 3 of the memory 112 are stored in the respective first cells 304 of chains 2 and 3. Figure 4F As shown in FIG. 1 , the scan chain 102 now contains the same Figure 4A The data contained in scan chain 102 can then be used to restore the saved state of the design block, thereby reversing the process used to initially load the state of the design block into scan chain 102.

[0071] Figure 5A An example process 500 for saving the state of a design block using a scan chain is shown. In step 502, a sleep command is received at a design block, causing the design block to prepare for power down, and then power down. Saving the state of the design block is part of the power down preparation. In step 504, different portions of the state data of the design block are loaded into different ones of a plurality of scan chains. Such chains are composed of a plurality of serially connected memory cells. The longest scan chain has N cells, and the shorter scan chains have M cells, where M may be different for different scan chains. In step 506, the state data stored in the scan chains is iteratively advanced through the scan chains. Bits are output from the end cells of the longest scan chain, and bits are output from the (NM)th cells of the shorter scan chains. Bits are circulated from the Mth cells in the shorter scan chains to be stored in the first cells of the corresponding shorter scan chains. In step 508, the bits output from different ones of the scan chains are sequentially stored in different regions of the memory, so that the different ones of the scan chains correspond to different ones of the memory regions. In step 510, the iterative progress and storage of steps 506 and 508 are repeated until all state data stored in the longer scan chain in step 504 are stored in memory. This will result in more than one copy (e.g., one copy plus a partial copy) of the state data stored in the shorter scan chain being stored in memory.

[0072] Figure 5B An example process 500 for saving the state of a design block using a scan chain is shown. In step 514, bits are sequentially read out from the memory regions corresponding to the scan chains (as described with respect to step 508), preferably one bit per region per iteration of step 514. In step 516, the bits read out from the memory are stored in the respective first cells of the scan chains. In step 518, if the longest scan chain has not been (re)filled with state data, the state data is iteratively advanced through the scan chains, and steps 514 and 516 are repeated. In step 520, the state data is repeatedly iteratively advanced through the scan chains, and the state data output from the scan chains is returned to the respective memory elements of the design block.

[0073] Fig. 6A An example block diagram of a clock circuit 600 for providing a clock for a scan chain used to save the state of a design block is shown. The clock circuit 600 includes a clock divider 608 that receives a reference clock 602 as an input and is connected to output a divided clock signal CLK DIV 604 as its own input (feedback) and as the input to multiplexer 606. Multiplexer 606 also receives the save-recovery clock CLK SR 610 as input. SR mode 612 selector selects multiplexer 606 output CLK DIV 604 or CLK SR610 as multiplexer output 614. During normal function of the design block, multiplexer 606 outputs CLK DIV 604 is used by the design block. During the state saving process or the state recovery process, the multiplexer 606 outputs CLK SR 610 is used for scan chain and related circuits.

[0074] Figure 6B An example timing diagram 611 of the clock circuit 600 is shown. Figure 6B , SR mode 612 is initially set to a high state to correspond to a design block idle state (e.g., a power-down state) in which SR (save-restore) functionality has been triggered. SR mode 612 later transitions to a low state to indicate a transition of the design block from an idle state to a functional (e.g., power-up) state and a corresponding transition from a save-restore mode to a functional mode. CLK DIV 604 starts low and transitions to high before SR mode 612 transitions to low (before the design block transitions from save-restore mode to functional mode). Figure 6B During the time period shown in SR 610 initially oscillates and stops oscillating before SR Mode 612 turns low when the state recovery process is complete. The multiplexer output 614 initially follows CLK SR 610, and turns high when SR mode 612 turns low to follow CLK DIV 604 (SR mode 612 change causes selected multiplexer output 614 to change). This transition of multiplexer output 614, producing rising clock edge 616, occurs simultaneously with the SR mode 612 transition. This can be problematic: rising clock edge 616 in multiplexer output 614 indicates a clock transition (rising clock edge) where no clock transition existed, which can cause the clocked circuit to exhibit undesirable (erroneous) behavior.

[0075] Figure 6C An example block diagram of a clock circuit 618 for providing a clock for a scan chain for saving the state of a design block and configured to suppress erroneous clock transitions when the SR mode 612 transitions is shown. The clock circuit 618 includes a control flip-flop 620 that receives a CLK SR 610 and reset signal 622 as input and connected to convert the clock CLK XN 624 outputs to an OR logic gate 626. OR logic gate 626 also receives CLK SR 610 as input. OR logic gate 626 gates the saved-recovered clock CLK SR_G 628 is output to the multiplexer 606. SR mode 620 selects the multiplexer 606 to output CLK DIV604 or CLK SR_G 628 as multiplexer output 614. During normal function of the design block, multiplexer 606 outputs CLK DIV 604 is used by the design block. During the state saving process or the state recovery process, the multiplexer 606 outputs CLK SR_G 628 is used for scan chain and related circuits.

[0076] Fig.6D An example timing diagram 630 of clock circuit 618 is shown. Fig.6D The signal timing shown in Figure 6B , only the reset signal 622 and its effect on the multiplexer output 614 are added. The reset signal 622 starts out low and goes high before the SR mode 612 goes high at the end of the state recovery process, and remains high until the transition from the idle state to the functional state is completed. The reset signal 622 causes CLK XN 624 (not shown) goes high, which causes CLK SR_G 628 (not shown) goes high, causing the multiplexer output 614 to remain high. This prevents the multiplexer output 614 from showing a false rising edge transition.

[0077] Fig. 6A , 6B , 6C and 6D address the transition from idle state to functional state in the design block. Figure 6C The clock circuit 618 of the embodiment can also be used to suppress erroneous clock transitions during the functional state to SR state transition in the design block by activating the reset signal 622 before the SR mode 612 goes high and remains high until the transition to the idle state is complete (e.g., when the state preservation process is ready to begin). It should be understood by one of ordinary skill in the art of save-restore functionality in integrated circuits that the clock circuit 618 can also be modified to prevent both erroneous rising edge transitions and erroneous falling edge transitions.

[0078] The described embodiments may be modified and other embodiments are possible within the scope of the claims.

[0079] In some embodiments, a memory cell can store more than one bit. In some embodiments, different memory cells can store different numbers of bits.

[0080] In some embodiments, different numbers of cells and memory sizes than those described herein may be used.

[0081] In some embodiments, a different number of clock cycles may be used to advance the bits through the scan chain.

[0082] In some embodiments, a propagation signal other than a clock signal may be used (a signal that causes bits to advance serially through the scan chain).

[0083] In some embodiments, the bits read from the scan chain are stored in memory non-contiguously. In some embodiments, the bits are stored in memory in a different order (e.g., written alternately). In some embodiments, the bits from the scan chain are stored in the same column of memory instead of on the same row. In some embodiments, the bits from the scan chain are stored in memory from the bottom up.

[0084] In some embodiments, additional copies of state data may be stored in memory during the save state process.

[0085] In some embodiments, the order in which the state data is stored in the memory is different from the order in which the state data is stored in the scan chain.

[0086] In some embodiments, the memory into which the state data is loaded from the scan chain is on the same die as the design block; in some embodiments, the memory into which the state data is loaded from the scan chain is on a different die than the design block.

[0087] In some embodiments, during the initialization action, data is initially loaded serially into the scan chain (e.g., via the first cell of the scan chain). In some embodiments, during the initialization action, data is initially loaded in parallel into the scan chain, such as by loading all data into corresponding cells of the scan chain during the same clock cycle or by loading multiple bits directly into corresponding cells of the scan chain during individual clock cycles.

[0088] In some embodiments, the circuit for saving and restoring the state of a design block includes a plurality of first memories (e.g., scan chain 102) and second memories (e.g., memory 112). The first memories are configured to receive first data (e.g., state data) from memory elements (e.g., registers and flip-flops) of the design block during an initialization action. The first memories store different portions of the first data in different ones of the first memories in a first order (e.g., scan chain 102 stores state data in a specific sequential order, such as Figure 3A106). Different ones of the first memories have different numbers of memory cells (e.g., different scan chains 102 have different numbers of cells 106), some of the first memories with the most memory cells have N memory cells, and some of the first memories with fewer memory cells have M memory cells. The second memory is coupled to the first memory. During the save state action, the first data (state data) is read from the first memory (scan chain 102) and stored in the second memory (memory 112), and the parts of the first data stored in the different ones of the first memories are written to different corresponding areas of the second memory in a second order as the second data (e.g., the state data in the scan chain 102 is written to the corresponding column 116 of the memory 112). The second order includes repeated portions of the first data stored in the sequential first N minus M memory cells of the counterpart of the first memory with fewer memory cells determined using the first order (e.g., bits 104 stored in the first N minus M cells 106 of the shorter scan chain 102 are repeated in the memory 112 due to the position of the cyclic input and output 310 in the shorter scan chain 102 and because N clock cycles are used to output M bits 104 different from the shorter scan chain 102, where N>M). During the restore state action, different portions of the second data are read from the second memory and stored in different counterparts of the first memory in the first order (the state data is output from the memory 112 back to the corresponding scan chain 102 so that the state data is stored by the scan chain 102 in the same order as when the state data was originally stored in the scan chain 102), and the repeated portions are stored in the first order in the counterpart of the first memory with fewer memory cells in which the same portion of the second data was stored (the repeated bits 104 in the memory 112 are stored in the scan chain 102 in the initial sequential order, e.g. Figure 4E and 4F (shown in the).

Claims

1. A circuit for saving and restoring the state of a design block, comprising: a first group of memory cells coupled in a first scan chain, wherein the first group of memory cells has a first number N of cells; a second group of memory cells coupled in a second scan chain, wherein the second group of memory cells has a second number M of cells less than the first number of cells, and wherein the first group of memory cells and the second group of memory cells are configured to receive a first set of data and store a first portion of the first set of data of the first group of memory cells and a second portion of the first set of data of the second group of memory cells in a first order during an initialization action; a second memory coupled to the first group of memory cells and the second group of memory cells and configured such that: During a save state action, a second set of data is read from the first set of memory cells and the second set of memory cells and stored in the second memory in a second sequence, wherein the second sequence includes a repeated portion of the second set of data stored in a sequential first subset of N mod M memory cells of the second set of memory cells; and During the restore state action, the second set of data is read from the second memory and stored in the first set of memory cells and the second set of memory cells in the first order, and the repeated portions are stored in corresponding ones of the second set of memory cells in the first order.

2. The circuit according to claim 1, further comprising: a memory controller coupled to the first and second sets of memory cells and to the second memory; as well as A multiplexer is coupled between the second group of memory cells and the memory controller.

3. The circuit of claim 2, wherein the multiplexer comprises: an output coupled to a first cell of the second group of memory cells that is arranged first in the second scan chain; a first input coupled to an output of the memory controller; as well as A second input is coupled to a second cell arranged in a last second group of memory cells in the second scan chain.

4. The circuit of claim 3, wherein the second group of memory cells includes a third cell that is a middle cell of the second scan chain and is coupled to an input of the memory controller.

5. The circuit of claim 2, wherein the first group of memory cells is coupled to the memory controller without involving an intermediate multiplexer.

6. A circuit comprising: a memory controller comprising a first and a second input and a first and a second output; A first group of memory cells coupled in a first scan chain, wherein: The first group of memory cells has a first number of cells; The first set of memory cells includes a first cell coupled to the first output of the memory controller and a second cell coupled to the first input of the memory controller; and The first set of memory cells is configured to receive a propagated signal; A second group of memory cells coupled in a second scan chain, wherein: the second group of memory cells having a second number of cells which is less than the first number of cells; The second set of memory cells includes a third cell coupled to the second output of the memory controller and a fourth cell coupled to the second input of the memory controller; and a memory coupled to the memory controller; The memory controller is configured to: During a save state action, the propagation signal is provided to the first group of memory cells and the second group of memory cells a number of times equal to the number of the first number of cells, and the memory is caused to store a set of data output from the first group of memory cells and the second group of memory cells in a receiving order so that the data stored in the second group of memory cells is repeated when stored in the memory; and During the recovery state action, the memory is caused to output the set of data in the receiving order, and the first group of memory cells and the second group of memory cells are caused to store the set of data output by the memory in the receiving order. The circuit of claim 6 , wherein the propagating signal is a clock.

8. The circuit of claim 6, further comprising a multiplexer coupled between the third cell of the second group of memory cells and the second output of the memory controller.

9. A circuit comprising: a controller comprising a first input, a second input, a first output, and a second output; a first scan chain comprising a first number of memory cells coupled in series, wherein the first scan chain comprises: a first unit, which is arranged first in the first scan chain, the first unit being coupled to the first output of the controller; and a second unit, which is arranged last in the first scan chain, the second unit being coupled to the first input of the controller; and a second scan chain comprising a second number of memory cells coupled in series, wherein the second number of memory cells is less than the first number of memory cells, and wherein the second scan chain comprises: a third unit, which is arranged first in the second scan chain, and the third unit is coupled to the second output of the controller; a fourth unit, which is arranged last in the second scan chain, and is coupled to the third unit; and A fifth cell, which is a middle cell in the second scan chain, is coupled to the second input of the controller.

10. The circuit of claim 9, further comprising a multiplexer coupled between the second output of the controller and the third cell of the second scan chain.

11. The circuit of claim 10, wherein the multiplexer comprises: a first input coupled to the fourth cell of the second scan chain; a second input coupled to the second output of the controller; and an output coupled to the third unit.

12. The circuit of claim 9, wherein the first cell of the first scan chain is coupled to the first output of the controller without involving an intermediate multiplexer.

13. The circuit of claim 9, further comprising a memory coupled to the controller, wherein the controller is operative to: Execute save state actions, which include: causing the first scan chain and the second scan chain to provide a set of scan data; and storing the set of scan data in the memory, wherein the set of scan data comprises a repeating portion of a subset of data stored in the second scan chain; and Perform the restore state action, which includes: retrieving the set of scan data from the memory; and The first scan chain and the second scan chain are caused to store the set of scan data.

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