Semiconductor device

Abstract

The present disclosure relates to a semiconductor device. The semiconductor device includes a base member, a multilayer wiring layer, and a first resistance element. The multilayer wiring layer is formed on the base member. The first resistance element is formed in the multilayer wiring layer. The first resistance element includes a first conductive portion, a second conductive portion, and a third conductive portion. The second conductive portion is formed on the first conductive portion. The third conductive portion electrically connects the first conductive portion and the second conductive portion to each other. A length of the third conductive portion in a first direction along a surface of the base member is greater than a length of the third conductive portion in a second direction along the surface of the base member, and the second direction is perpendicular to the first direction.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device, for example, a semiconductor device including a resistance element formed in a multilayer wiring layer. BACKGROUND

[0002] One disclosed technology is listed below.

[0003] [Patent Literature 1] Japanese Unexamined Patent Application Publication No. 2019-009345

[0004] A semiconductor device including a resistance element is known (see, for example, Patent Literature 1). The semiconductor device disclosed in Patent Literature 1 includes a semiconductor substrate and a wiring layer formed on the semiconductor substrate. The resistance element is formed on the wiring layer. The resistance element is composed of a repeating pattern of a first conductive portion, a second conductive portion, and an interlayer conductive portion that connects the first conductive portion and the second conductive portion. In a cross-sectional view along the semiconductor substrate, a cross-sectional shape (hereinafter also referred to as a “via hole”) of the interlayer conductive portion is substantially circular.

[0005] In the resistance element of the semiconductor device described in Patent Literature 1, if an amount of current flowing through the resistance element is too large, metal atoms constituting the via hole move, and a defect occurs in the via hole, that is, so-called electromigration occurs in some cases. Therefore, the characteristics of the resistance element deteriorate. As described above, in the conventional semiconductor device, there is room for improvement from the viewpoint of improving the reliability of the semiconductor device.

[0006] A problem of embodiments is to improve the reliability of a semiconductor device. Other problems and novel features will become apparent from the description of the specification and drawings. SUMMARY

[0007] The semiconductor device according to an embodiment includes a base member, a multilayer wiring layer, and a first resistance element. The first resistance element is formed in the multilayer wiring layer. The first resistance element includes a first conductive portion, a second conductive portion, and a third conductive portion. The second conductive portion is formed on the first conductive portion. The third conductive portion electrically connects the first conductive portion and the second conductive portion to each other. A length of the third conductive portion in a first direction along a surface of the base member is greater than a length of the third conductive portion in a second direction along the surface of the base member, and the second direction is perpendicular to the first direction.

[0008] According to the embodiment, it is possible to improve the characteristics of the semiconductor device. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a circuit diagram showing an exemplary circuit configuration of a semiconductor device according to an embodiment;

[0010] Figure 2 is a plan view showing an exemplary configuration of a semiconductor device according to an embodiment;

[0011] Figure 3 is a perspective view showing an exemplary configuration of a main part of a semiconductor device according to an embodiment;

[0012] Figure 4 is a cross-sectional view showing an exemplary configuration of a main part of a semiconductor device according to an embodiment;

[0013] Figure 5 is a cross-sectional view showing an exemplary step included in a manufacturing method of a semiconductor device according to an embodiment;

[0014] Figure 6 is a cross-sectional view showing an exemplary step included in a manufacturing method of a semiconductor device according to an embodiment;

[0015] Figure 7 is a cross-sectional view showing an exemplary step included in a manufacturing method of a semiconductor device according to an embodiment;

[0016] Figure 8 is a perspective view showing an exemplary configuration of a main part of a semiconductor device according to a first modification of the embodiment;

[0017] Figure 9 is a cross-sectional view showing an exemplary configuration of a main part of a semiconductor device according to the first modification of the embodiment;

[0018] Figure 10 is a perspective view showing an exemplary configuration of a main part of a semiconductor device according to a second modification of the embodiment; and

[0019] Figure 11 is a perspective view showing an exemplary configuration of a main part of a semiconductor device according to a third modification of the embodiment. DETAILED DESCRIPTION

[0020] Hereinafter, a semiconductor device according to an embodiment will be described in detail with reference to the accompanying drawings. In the specification and the drawings, the same or corresponding elements are denoted by the same reference numerals or hatching lines, and repetitive description thereof will be omitted. In the drawings, the configuration can be omitted or simplified for convenience of description. A cross-sectional view can be shown as an end view. At least some and each modification in the embodiments can be arbitrarily combined with each other.

[0021] (Circuit configuration of semiconductor device)

[0022] Figure 1 is a circuit diagram showing an exemplary circuit configuration of a semiconductor device SD according to the present embodiment.

[0023] AsFigure 1 As shown in FIG. 1, the semiconductor device SD includes a control circuit CTR, a high-voltage-side transistor HTr, a low-voltage-side transistor LTr, a resistive element RE, and a detection circuit DT. The semiconductor device SD is coupled with the load LD via a terminal T1 and a terminal T2.

[0024] The control circuit CTR is coupled with the high-voltage-side transistor HTr, the low-voltage-side transistor LTr, and the detection circuit DT. The control circuit CTR controls the operation of the high-voltage-side transistor HTr and the low-voltage-side transistor LTr. The control circuit CTR controls the operation of the high-voltage-side transistor HTr and the low-voltage-side transistor LTr based on a signal received from the detection circuit DT. The control circuit CTR includes, for example, a feedback circuit.

[0025] The high-voltage-side transistor HTr is coupled between a power supply line Vdd and a ground line GND. The high-voltage-side transistor HTr is coupled with the power supply line Vdd via a terminal T3. The high-voltage-side transistor HTr is electrically coupled to the power supply potential Vdd closer to the ground than the low-voltage-side transistor LTr. The high-voltage-side transistor HTr controls a connection state between the power supply line Vdd and the resistive element RE.

[0026] The low-voltage-side transistor LTr is coupled between the power supply line Vdd and the ground line GND. The low-voltage-side transistor LTr is coupled to the ground line GND via a terminal T4. The low-voltage-side transistor LTr is electrically coupled to the ground potential GND closer to the ground than the high-voltage-side transistor HTr. The high-voltage-side transistor HTr controls a connection state between the ground line GND and the resistive element RE.

[0027] The resistive element RE is generally coupled with the high-voltage-side transistor HTr and the low-voltage-side transistor LTr. The resistive element RE is coupled between the high-voltage-side transistor HTr and the load LD. The resistive element RE is coupled between the low-voltage-side transistor LTr and the load LD.

[0028] The detection circuit DT is coupled with one end of the resistive element RE and the other end of the resistive element RE. The detection circuit DT detects an amount of current flowing through the resistive element RE. For example, the detection circuit DT detects the amount of current based on a potential difference (voltage drop) between the one end of the resistive element RE and the other end of the resistive element RE. The configuration of the detection circuit DT is not particularly limited as long as the above-described function is exhibited. The detection circuit DT includes, for example, an amplification circuit and an A / D conversion circuit.

[0029] The load LD is coupled between the resistive element RE and the ground line GND. The load LD is not particularly limited. For example, the load LD is a coil that constitutes a solenoid coil. In the present embodiment, the load LD is a coil.

[0030] Here, an exemplary operation of the semiconductor device SD will be described.

[0031] First, the control circuit CTR controls the high-voltage-side transistor HTr to be in an on state and controls the low-voltage-side transistor LTr to be in an off state. Accordingly, the power supply potential is supplied from the power supply line Vdd to the resistance element RE and the load LD via the high-voltage-side transistor HTr. That is, a current in the forward direction flows through the resistance element RE and the load LD. At this time, a voltage drop occurs in the resistance element RE. The detection circuit DT detects the voltage drop and generates a feedback signal corresponding to the amount of current flowing through the resistance element RE. The feedback signal is transmitted to the control circuit CTR. The control circuit CTR controls the operation of the high-voltage-side transistor HTr and the low-voltage-side transistor LTr on the basis of the received feedback signal.

[0032] For example, the control circuit CTR controls the high-voltage-side transistor HTr to be in an off state and controls the low-voltage-side transistor LTr to be in an on state. Accordingly, the ground potential is supplied from the ground line GND to the resistance element RE and the load LD via the low-voltage-side transistor LTr. That is, a current in the forward direction flows through the resistance element RE and the load LD. Also in this case, a voltage drop occurs in the resistance element RE. As described above, the detection circuit DT detects the voltage drop and transmits a feedback signal to the control circuit CTR.

[0033] [Configuration of semiconductor device]

[0034] Figure 2 is a plan view showing an exemplary configuration of the semiconductor device SD according to the present embodiment. Figure 2 An exemplary layout of the configuration of the semiconductor device SD is shown, which is used to realize the circuit configuration of the semiconductor device SD.

[0035] As Figure 2 shown, the semiconductor device SD includes a high-voltage-side region HSR, a low-voltage-side region LSR, a resistance element region RER, a control circuit region CTRR, and a detection circuit region DTR.

[0036] The high-voltage-side region HSR is a region in which the high-voltage-side transistor HTr is formed. The type of the high-voltage-side transistor HTr is not particularly limited. For example, the high-voltage-side transistor HTr is a laterally diffused metal oxide semiconductor (LDMOS).

[0037] The low-voltage-side region LSR is a region in which the low-voltage-side transistor LTr is formed. The type of the low-voltage-side transistor LTr is not particularly limited. For example, the low-voltage-side transistor LTr is an LDMOS.

[0038] The resistance element region RER is a region in which the resistance element RE for current detection is formed. The position of the resistance element region RER is not particularly limited. In a plan view, the resistance element region RER is preferably located between the high-side region HSR and the low-side region LSR. Thus, the region between the high-side region HSR and the low-side region LSR is effectively utilized. Therefore, the semiconductor device SD can be downsized. In addition, since the resistance element RE is formed in the vicinity of the high-side transistor HTr and the low-side transistor LTr, the parasitic resistance is reduced, and the accuracy of the current detection by the resistance element RE is improved.

[0039] The control circuit region CTRR is a region in which the control circuit CTR is formed. The position of the control circuit region CTRR is not particularly limited. In the present embodiment, the control circuit region CTRR is formed so that the control circuit region CTRR is adjacent to a part of one side of the high-side region HSR and one side of the resistance element region RER in a plan view.

[0040] The detection circuit region DTR is a region in which the detection circuit DT is formed. The position of the detection circuit region DTR is not particularly limited. In the present embodiment, the detection circuit region DTR is formed so that the detection circuit region DTR is adjacent to another part of one side of the low-side region LSR and one side of the resistance element region RER in a plan view.

[0041] (Configuration of main part of semiconductor device)

[0042] Here, the configuration of the main part of the semiconductor device SD will be described in detail.

[0043] Figure 3 is a perspective view showing an exemplary configuration of the main part of the semiconductor device SD.

[0044] Figure 4 is a cross-sectional view showing an exemplary configuration of the main part of the semiconductor device SD. Figure 4 is a cross-sectional view taken along the line A-A in Figure 2 In Figure 3 , the base member BM and the multilayer wiring layer MWL are omitted from the perspective of easy observation.

[0045] The semiconductor device SD includes a base member BM, a multilayer wiring layer MWL, a heat dissipation portion HDP, a resistance element RE, and a thermal stress mitigation portion TSM.

[0046] The base member BM includes a semiconductor substrate SS and a semiconductor layer SL. The base member BM supports a multilayer wiring layer MWL. A portion of the heat dissipation portion HDP is formed in the base member BM. A recessed portion RP is formed in the base member BM. More specifically, the recessed portion RP penetrates the semiconductor layer SL such that the recessed portion RP reaches the semiconductor substrate SS in a thickness direction of the base member BM. A portion of the heat dissipation portion HDP is formed in the recessed portion RP. Thus, the shape, size, and position of the portion of the heat dissipation portion HDP are defined.

[0047] The semiconductor substrate SS is, for example, a p-type semiconductor substrate including a p-type impurity or an n-type semiconductor substrate including an n-type impurity. Examples of the p-type impurity include boron (B) and aluminum (Al). Examples of the n-type impurity include arsenic (As) and phosphorus (P).

[0048] The semiconductor layer SL includes a first p-type epitaxial layer PE1, an n-type buried layer NBL, a p-type buried layer PBL, and a second p-type epitaxial layer PE2. The first p-type epitaxial layer PE1, the n-type buried layer NBL, the p-type buried layer PBL, and the second p-type epitaxial layer PE2 are formed in this order from the semiconductor substrate SS side. The semiconductor layer SL is formed on the semiconductor substrate SS. The n-type buried layer NBL and the p-type buried layer PBL are not essential constituent elements. From the viewpoint of electrical insulation between the semiconductor substrate SS and a semiconductor element formed above the n-type buried layer NBL and the p-type buried layer PBL in the semiconductor layer SL, the semiconductor layer SL preferably includes the n-type buried layer NBL or the p-type buried layer PBL.

[0049] The first p-type epitaxial layer PE1 is an epitaxial layer formed on a surface of the semiconductor substrate SS. The first p-type epitaxial layer PE1 includes a p-type impurity. The impurity concentration of the first p-type epitaxial layer PE1 is, for example, 1 x 1018cm-3or more and 1 x 1020cm-3or less. 13 cm -3 The above and 1 x 1018cm-3or more and 1 x 1020cm-3or less. 19 cm -3 The above and 1 x 1018cm-3or more and 1 x 1020cm-3or less. 13 cm -3 The above and 1 x 1018cm-3or more and 1 x 1020cm-3or less. 16 cm -3 or less.

[0050] The n-type buried layer NBL is formed on a portion or all of the first p-type epitaxial layer PE1. Examples of the n-type impurity include phosphorus (P), arsenic (As), and antimony (Sb). The impurity concentration of the n-type buried layer NBL is, for example, 1 x 1018cm-3or more and 1 x 1020cm-3or less. 13 cm -3 The above and 1 x 1018cm-3or more and 1 x 1020cm-3or less. 20 cm -3 The above and 1 x 1018cm-3or more and 1 x 1020cm-3or less.

[0051] The p-type buried layer PBL is formed, for example, on a part or all of the n-type buried layer NBL. The impurity concentration of the p-type buried layer PBL is, for example, 1 x 1014cm-2or more and 1 x 1020cm-3or less, preferably 1 x 1015cm-2or more and 1 x 1019cm-3or less. 15 cm -3 The above and 1 x 1014cm-2or more and 1 x 1020cm-3or less, preferably 1 x 1015cm-2or more and 1 x 1019cm-3or less. 21 cm -3 The above and 1 x 1014cm-2or more and 1 x 1020cm-3or less, preferably 1 x 1015cm-2or more and 1 x 1019cm-3or less. 15 cm -3 The above and 1 x 1014cm-2or more and 1 x 1020cm-3or less, preferably 1 x 1015cm-2or more and 1 x 1019cm-3or less. 18 cm -3 The above and 1 x 1014cm-2or more and 1 x 1020cm-3or less, preferably 1 x 1015cm-2or more and 1 x 1019cm-3or less.

[0052] The second p-type epitaxial layer PE2 is an epitaxial layer formed on the p-type buried layer PBL. In a portion where the n-type buried layer NBL and the p-type buried layer PBL are not formed, the second p-type epitaxial layer PE2 is formed on the first p-type epitaxial layer PE1. The second p-type epitaxial layer PE2 contains a p-type impurity. The impurity concentration of the second p-type epitaxial layer PE2 is, for example, 1 x 1014cm-2or more and 1 x 1020cm-3or less, preferably 1 x 1015cm-2or more and 1 x 1019cm-3or less. 13 cm -3 The above and 1 x 1014cm-2or more and 1 x 1020cm-3or less, preferably 1 x 1015cm-2or more and 1 x 1019cm-3or less. 19 cm -3 The above and 1 x 1014cm-2or more and 1 x 1020cm-3or less, preferably 1 x 1015cm-2or more and 1 x 1019cm-3or less. 13 cm -3 The above and 1 x 1014cm-2or more and 1 x 1020cm-3or less, preferably 1 x 1015cm-2or more and 1 x 1019cm-3or less. 16 cm -3 The above and 1 x 1014cm-2or more and 1 x 1020cm-3or less, preferably 1 x 1015cm-2or more and 1 x 1019cm-3or less.

[0053] The multilayer wiring layer MWL is formed on the base member BM so that the multilayer wiring layer MWL covers the semiconductor element formed on the base member BM. The multilayer wiring layer MWL is constituted of two or more wiring layers. A wiring layer is a layer including an interlayer insulating layer and one or both of a wiring and a via formed in the interlayer insulating layer. A via is a conductive member that electrically connects two wirings formed in different layers from each other.

[0054] As Figure 4 illustrated, the multilayer wiring layer MWL includes a first interlayer insulating layer IIL1, a first wiring WR1, a second interlayer insulating layer IIL2, a first via V1, a second wiring WR2, a third interlayer insulating layer IIL3, a second via V2, a third wiring WR3, a fourth interlayer insulating layer IIL4, a fifth interlayer insulating layer IIL5, and a protective layer PL. As will be described in detail later, a part of the heat dissipation portion HDP, the resistance element RE, and the thermal stress mitigation portion TSM are formed in the multilayer wiring layer MWL.

[0055] The first interlayer insulating layer IL1, the second interlayer insulating layer IL2, the third interlayer insulating layer IL3, the fourth interlayer insulating layer IL4, and the fifth interlayer insulating layer IL5 are formed in this order on the base member BM. Examples of the material of each of the first interlayer insulating layer IL1, the second interlayer insulating layer IL2, the third interlayer insulating layer IL3, the fourth interlayer insulating layer IL4, and the fifth interlayer insulating layer IL5 include silicon oxide. The thickness of each of the first interlayer insulating layer IL1, the second interlayer insulating layer IL2, the third interlayer insulating layer IL3, the fourth interlayer insulating layer IL4, and the fifth interlayer insulating layer IL5 is not particularly limited.

[0056] The first wiring WR1 is formed on the first interlayer insulating layer IL1. For the first wiring WR1, a known configuration used as a wiring in semiconductor technology can be employed. The first wiring WR1 is, for example, a stacked film in which a barrier metal, a conductive film, and a barrier metal are stacked in this order. Examples of the material of the barrier metal include titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN). Examples of the material of the conductive film include aluminum, copper, and tungsten.

[0057] The first via V1 is formed in the second interlayer insulating layer IL2 so that the first via V1 reaches the first wiring WR1. In a cross section along the surface of the base member BM, the cross-sectional shape of the first via V1 is substantially circular. As the configuration of the first via V1, a known configuration used as a via in semiconductor technology can be employed. The first via V1 includes, for example, a barrier film and a conductive film formed on the barrier film. Examples of the material of the barrier film include titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN). The material of the conductive film is, for example, tungsten (W), aluminum (Al), or copper (Cu).

[0058] The second wiring WR2 and the third wiring WR3 are similar to the wiring WR1, except for the position formed in the multilayer wiring layer MWL. The second via V2 is also similar to the first via V1, except for the position formed in the multilayer wiring layer MWL.

[0059] The protective layer PL is a layer that protects the semiconductor device SD from external moisture and the like. The protective layer PL is formed on the fifth interlayer insulating layer IL5. Within the multilayer wiring layer MWL, the protective layer PL is formed in the uppermost layer of the multilayer wiring layer MWL. The protective layer PL can be a single-layer film or a stacked film of two or more layers. Examples of the protective layer PL include a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a phosphosilicate glass (PSG) film, and a stacked film of these films. The thickness of the protective layer PL is, for example, 1.0 μm or more and 2.0 μm or less, and is preferably about 1.5 μm.

[0060] In the multilayer wiring layer MWL, a portion of the heat dissipation portion HDP, the resistance element RE, and the thermal stress mitigation portion TSM are formed. In the base member BM, the remaining portion of the heat dissipation portion HDP is formed. Details of these elements will be described below.

[0061] The heat dissipation portion HDP has the insulating film ILF, the heat conduction portion HCP, and the coupling portion CP. The heat dissipation portion HDP is configured to transfer heat generated in the resistance element RE to the outside of the multilayer wiring layer MWL. For example, a portion of the heat dissipation portion HDP can be formed in the multilayer wiring layer MWL, and another portion of the heat dissipation portion HDP can be exposed from the multilayer wiring layer MWL. In the present embodiment, a portion of the heat dissipation portion HDP is formed in the multilayer wiring layer MWL, and the remaining portion of the heat dissipation portion HDP is formed in the base member BM. Thereby, heat generated in the resistance element RE is transferred to the base member BM via the heat dissipation portion HDP.

[0062] The insulating film ILF is formed on the bottom surface and the side surface of the recessed portion RP formed on the surface of the base member BM. The insulating film ILF suppresses short-circuiting of the heat conduction portion HCP and the base member BM to each other. The thickness of the insulating film ILF is not particularly limited as long as the above-described function can be obtained. The thickness of the insulating film ILF is, for example, about 0.1 μm. The material of the insulating film ILF is, for example, silicon oxide.

[0063] The heat conduction portion HCP is formed on the insulating film ILF so that the heat conduction portion HCP fills the inside of the recessed portion RP. The heat conduction portion HCP is made of a material having heat conductivity. From the viewpoint of improving heat conductivity, examples of the material of the heat conduction portion HCP preferably include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and tungsten (W).

[0064] From the viewpoint of improving heat dissipation, the size of the heat conduction portion HCP is preferably large. The heat conduction portion HCP preferably reaches the p-type buried layer PBL, more preferably reaches the n-type buried layer NBL, still more preferably reaches the first p-type epitaxial layer PE1, and still more preferably reaches the semiconductor substrate SS of the base member BM.

[0065] From the viewpoint of improving heat dissipation, the shape of the heat conduction portion HCP is preferably plate-like. That is, the length of the heat conduction portion HCP in the Y direction is preferably larger than the length of the heat conduction portion HCP in the X direction. The length of the heat conduction portion HCP in the Y direction is preferably larger than the length of the resistance element RE in the Y direction. In the present embodiment, the length of the heat conduction portion HCP in the Y direction is substantially the same as the length of the resistance element RE in the Y direction.

[0066] In the present specification, the "Y direction" is a first direction along a surface (upper surface, main surface) of the base member BM. The Y direction is also a direction in which a long side of a third conductive portion CL3a (described later) extends in a plan view. The "X direction" is a second direction perpendicular to the Y direction in the plan view. The Y direction is also a direction in which a short side of the third conductive portion CL3a (described later) extends in the plan view. The "Z direction" is a thickness direction of the multilayer wiring layer MWL. The X direction, the Y direction, and the Z direction are orthogonal to each other.

[0067] The coupling portion CP is formed in the first interlayer insulating layer IIL1 so that the coupling portion CP is in direct contact with the resistance element RE. From the viewpoint of improving the heat dissipation property of the heat dissipation portion HDP, it is preferable that the coupling portion CP be in direct contact with the resistance element RE. The coupling portion CP is made of a material having a heat conductivity. The coupling portion CP can have, for example, the same configuration as a via hole (not shown) formed in the first interlayer insulating layer IIL1, or can have a different configuration. The coupling portion CP includes, for example, a barrier film and a conductive film formed on the barrier film. Examples of the material of the barrier film include titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN). The material of the conductive film is, for example, tungsten (W), aluminum (Al), or copper (Cu).

[0068] From the viewpoint of improving the heat dissipation property, it is preferable that the coupling portion CP have a so-called slit shape. That is, the length of the coupling portion CP in the Y direction is preferably greater than the length of the coupling portion CP in the X direction. In the present embodiment, the length of the coupling portion CP in the Y direction is about the same as the length of the first conductive portion CL1b in the Y direction.

[0069] The resistance element RE is formed in the multilayer wiring layer MWL. The use of the resistance element RE is not particularly limited. In the present embodiment, the resistance element RE is a so-called sense resistor that is used to detect a current at a desired position in the semiconductor device SD.

[0070] The resistance element RE includes first conductive portions CL1a, CL1b, second conductive portions CL2a, CL2b, and third conductive portions CL3a, CL3b, CL3c. The first conductive portion CL1a, the third conductive portion CL3a, the second conductive portion CL2a, the third conductive portion CL3b, the first conductive portion CL1b, the third conductive portion CL3c, and the second conductive portion CL2b are connected to each other in this order.

[0071] The number of the first conductive portions, the second conductive portions, and the third conductive portions that constitute the resistance element RE is appropriately adjusted according to a desired resistance value. The first conductive portion CL1a and the first conductive portion CL1b are similar to each other except for a position and a size. The second conductive portion CL2a and the second conductive portion CL2b are also similar to each other except for a position. The third conductive portion CL3a, the third conductive portion CL3b, and the third conductive portion CL3c are also similar to each other except for a position. From the viewpoint of omitting repetitive description, only the first conductive portion CL1a, the second conductive portion CL2a, and the third conductive portion CL3a will be described below.

[0072] The first conductive portion CL1a is formed in the multilayer wiring layer MWL. The first conductive portion CL1a is formed in the same layer as a layer in which the first wiring WR1 is formed in the multilayer wiring layer MWL. In the present embodiment, the first conductive portion CL1a is formed on the first interlayer insulating layer IIL1.

[0073] The shape, the size, and the material of the first conductive portion CL1a are appropriately adjusted according to a desired resistance value and an occupied area. A length of the first conductive portion CL1a in the Y direction is preferably greater than a length of the first conductive portion CL1a in the X direction.

[0074] The first conductive portion CL1a can have, for example, the same configuration as the first wiring WR1 formed in the same layer, or can have a different configuration. The first conductive portion CL1a is, for example, a stacked film in which a barrier film, a conductive film, and a barrier film are stacked in this order. Examples of a material of the barrier film include titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN). Examples of a material of the conductive film include aluminum, copper, and tungsten. In the present embodiment, the first conductive portion CL1a is an aluminum wiring.

[0075] The second conductive portion CL2a is formed in the multilayer wiring layer MWL. The second conductive portion CL2a is formed in the same layer as a layer in which the third wiring WR3 is formed in the multilayer wiring layer MWL. In the present embodiment, the second conductive portion CL2a is formed on the third interlayer insulating layer IIL3.

[0076] In addition, the second conductive portion CL2a is formed on the first conductive portion CL1a. That is, a distance between the second conductive portion CL2a and the surface of the base member BM in the Z direction is greater than a distance between the first conductive portion CL1a and the surface of the base member BM in the Z direction. In a plan view, a part of the second conductive portion CL2a is formed so as to overlap with a part of the first conductive portion CL1a. Preferably, in a plan view, the second conductive portion CL2a is formed along the first conductive portion CL1a.

[0077] The shape, size, and material of the second conductive portion CL2a are appropriately adjusted depending on the desired resistance value and the occupied area. The shape, size, and material of the second conductive portion CL2a can be the same as or different from those of the first conductive portion CLla, respectively. In the present embodiment, the length of the second conductive portion CL2a in the X direction is greater than the length of the first conductive portion CLla in the X direction, and the length of the second conductive portion CL2a in the X direction is about the same as the length of the first conductive portion CLlb in the X direction.

[0078] The third conductive portion CL3a is formed between the first conductive portion CLla and the second conductive portion CL2a in the multilayer wiring layer MWL. The third conductive portion CL3a electrically connects the first conductive portion CLla and the second conductive portion CL2a to each other. The third conductive portion CL3a penetrates the interlayer insulating layer ILI2 and the interlayer insulating layer ILL3 sandwiched between the first conductive portion CLla and the second conductive portion CL2a.

[0079] The third conductive portion CL3a includes a first via Vla, a connection portion CNTa, and a second via V2a. The configuration of the first via Vla and the configuration of the second via V2a are similar to each other except for the position. The first via Vla will be described below from the viewpoint of omitting repetitive description. The third conductive portion CL3b includes a first via Vlb, a connection portion CNTb, and a second via V2b. The third conductive portion CL3c includes a first via Vic, a connection portion CNTc, and a second via V2c.

[0080] The first via Vla is formed in the multilayer wiring layer MWL. The first via Vla is formed on the first conductive portion CLla. The first via Vla is formed in the same layer as the layer in which the first via Vl is formed in the multilayer wiring layer MWL. In the present embodiment, the first via Vla is formed in the second interlayer insulating layer IIL2.

[0081] The length Ly of the first via Vla in the Y direction is greater than the length Lx of the first via Vla in the X direction. Therefore, compared with the first via Vl having a substantially circular cross-sectional shape, it is difficult for defects caused by electromigration to occur in the first via Vla even if a large current flows through the first via Vla. From this viewpoint, the ratio (Ly / Lx) of Ly to Lx is preferably 50 or greater, and more preferably 1000 or greater. The ratio (Ly / Lx) is not particularly limited, and can be appropriately adjusted depending on the size of the current.

[0082] On the other hand, from the viewpoint of miniaturizing the semiconductor device SD, Ly / Lx is preferably 5000 or less, and more preferably 2000 or less.

[0083] From the viewpoint of enhancing the resistance to electromigration, preferably, the length Lx (short width) of the first via V1a in the X direction is greater than the length (diameter) of the first via V1 in the X direction. The first via V1 is formed in one or both of the high-side region HSR and the low-side region LSR.

[0084] The size and material of the first via V1a are appropriately adjusted according to the desired resistance value. In addition, for example, the configuration of the first via V1a can be the same as or different from the first via V1 formed in the second interlayer insulating layer IIL2. The first via V1 includes, for example, a barrier film and a conductive film formed on the barrier film. Examples of the material of the barrier film include titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN). The material of the conductive film is, for example, tungsten (W), aluminum (Al), or copper (Cu).

[0085] The connection portion CNTa connects the first via V1a and the second via V2a in the multilayer wiring layer MWL to each other. In the present embodiment, the connection portion CNTa is formed on the second interlayer insulating layer IIL2. From the viewpoint of suppressing the variation in the resistance value of the resistance element RE, preferably, the connection portion CNTa is formed between the first via V1a and the second via V2a. More specifically, since the third conductive portion CL3a includes the connection portion CNTa, even if the positional deviation of the first via V1a and the second via V2a occurs, the variation in the resistance value of the resistance element RE can be suppressed.

[0086] The shape and size of the connection portion CNTa are appropriately adjusted according to the desired resistance value. For example, the configuration of the connection portion CNTa can be the same as or different from the wiring WR2 formed on the second interlayer insulating layer IIL2. Examples of the configuration of the connection portion CNTa are the same as examples of the configuration of the first conductive portion CL1a.

[0087] The thermal stress mitigation portion TSM is formed in the multilayer wiring layer MWL. The thermal stress mitigation portion TSM is formed between the resistance elements RE and the protective layer PL. The thermal stress mitigation portion TSM is configured to suppress stress caused by heat from outside the multilayer wiring layer MWL from being applied to the resistance elements RE. More specifically, the thermal stress mitigation portion TSM mitigates stress applied to the resistance elements RE due to a difference in the coefficient of thermal expansion of the resistance elements RE and the coefficient of thermal expansion of the interlayer insulating layer that constitutes the multilayer wiring layer MWL. The thermal stress mitigation portion TSM preferably overlaps at least a portion of the resistance elements RE in a plan view. From the viewpoint of improving thermal insulation, more preferably, the thermal stress mitigation portion TSM overlaps all of the resistance elements RE in a plan view. From the viewpoint of improving thermal insulation, preferably, the thermal stress mitigation portion TSM is formed so as to surround the resistance elements RE. For example, more preferably, the thermal stress mitigation portion TSM overlaps all of the resistance elements RE in a side view, more preferably, the thermal stress mitigation portion TSM overlaps all of the resistance elements RE in a front view, and more preferably, the thermal stress mitigation portion TSM overlaps all of the resistance elements RE in a back view. In the present embodiment, the thermal stress mitigation portion TSM overlaps all of the resistance elements RE in a plan view.

[0088] The configuration of the thermal stress mitigation portion TSM can be the same as or different from a wiring (not shown) formed on the fourth interlayer insulating layer IIL4, for example. The thermal stress mitigation portion TSM includes a barrier film and a conductive film formed on the barrier film. Examples of the material of the barrier film include titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN). The material of the conductive film is aluminum (Al) or copper (Cu), for example.

[0089] (Method for manufacturing semiconductor device)

[0090] Next, an exemplary method of manufacturing the semiconductor device SD according to the present embodiment will be described. Figures 5 to 7 are cross-sectional views showing exemplary steps included in the method of manufacturing the semiconductor device SD, respectively.

[0091] The method of manufacturing the semiconductor device SD includes, for example, a step (1) of providing the semiconductor wafer SW, a step (2) of forming a portion of the heat dissipation portion HDP, a step (3) of forming the multilayer wiring layer MWL, the remaining portion of the heat dissipation portion HDP, and the thermal stress mitigation portion TSM.

[0092] (1) Providing the semiconductor wafer SW

[0093] First, as Figure 5As shown, a semiconductor wafer SW is provided. The semiconductor wafer SW can be purchased as a commercial product or can be manufactured. The semiconductor wafer SW includes a semiconductor substrate SS and a semiconductor layer SL, the semiconductor layer SL being composed of a first p-type epitaxial layer PE1, an n-type buried layer NBL, a p-type buried layer PBL, and a second p-type epitaxial layer PE2. Each layer of the semiconductor wafer SW is formed, for example, by forming an epitaxial layer on the semiconductor substrate SS using an epitaxial growth method and implanting desired impurities into desired sites in the epitaxial layer.

[0094] (2) Forming part of the heat dissipation section of HDP

[0095] Next, as Figure 6 As shown, an insulating film ILF and a thermally conductive portion HCP are formed in a semiconductor wafer SW. First, a recessed portion RP is formed on the front (top) surface of the semiconductor wafer SW. Then, an insulating film ILF is formed on the bottom and side surfaces of the recessed portion RP and on the top surface of the semiconductor wafer SW. The recessed portion RP is formed, for example, by photolithography and etching. The method for forming the insulating film ILF is, for example, CVD. Next, the thermally conductive portion HCP is formed on the insulating film ILF to fill the recessed portion RP. The method for forming the thermally conductive portion HCP is, for example, CVD. Excess portions of the insulating film ILF and the thermally conductive portion HCP formed outside the recessed portion RP are removed, for example, by CMP.

[0096] (3) Forming a multilayer wiring layer (MWL), the remaining part of the heat dissipation section (HDP), and the thermal stress relief section (TSM).

[0097] Next, as Figure 7 As shown, a multilayer wiring layer (MWL), a coupling portion (CP), and a thermal stress relief portion (TSM) are formed on a semiconductor wafer (SW). The method for forming the multilayer wiring layer (MWL), the coupling portion (CP), and the thermal stress relief portion (TSM) can be a method known in semiconductor technology as the method for forming multilayer wiring layers.

[0098] The first interlayer insulating layer IIL1, the second interlayer insulating layer IIL2, the third interlayer insulating layer IIL3, the fourth interlayer insulating layer IIL4, and the fifth interlayer insulating layer IIL5 are formed, for example, by CVD. The coupling portion CP is formed, for example, by forming a through-hole in the first interlayer insulating layer IIL1 and then filling the through-hole with a conductive material. For example, the first through-holes V1, V1a, V1b, and V1c are formed, for example, by forming a through-hole in the second interlayer insulating layer IIL2 and then filling the through-hole with a conductive material. For example, the second through-holes V2, V2a, V2b, and V2c are formed, for example, by forming a through-hole in the third interlayer insulating layer IIL3 and then filling the through-hole with a conductive material.

[0099] The first conductive portions CL1a, CL1b and the first wiring WR1 are formed by forming a conductive film on the first interlayer insulating layer IIL1 using a sputtering method and then patterning the conductive film into a desired structure. The second conductive portions CL2a, CL2b and the third wiring WR3 are formed by forming a conductive film on the third interlayer insulating layer IIL3 using a sputtering method and then patterning the conductive film into a desired structure. The connection portions CNTa, CNTb, CNTc and the second wiring WR2 are formed by forming a conductive film on the second interlayer insulating layer IIL2 using a sputtering method and then patterning the conductive film into a desired structure. The protective layer PL is formed on the fifth interlayer insulating layer IIL5 by a sputtering method.

[0100] Then, the structure obtained through the above steps is detached from the electrostatic chuck and cut into small pieces, thereby obtaining a plurality of singulated semiconductor devices SD. Finally, the semiconductor devices SD are sealed with a sealing resin.

[0101] (EFFECTS)

[0102] The resistance element RE of the semiconductor device SD according to the present embodiment includes third conductive portions CL3a, CL3b, CL3c that electrically connect the first conductive portions CL1a, CL1b and the second conductive portions CL2a, CL2b to each other. The lengths of the third conductive portions CL3a, CL3b, CL3c in the Y direction (first direction) along the surface of the base member BM are greater than the lengths of the third conductive portions CL3a, CL3b, CL3c in the X direction (second direction) along the surface of the base member BM and perpendicular to the Y direction. In particular, the lengths Ly of the first vias V1a, V1b, V1c in the Y direction are greater than the lengths Lx of the first vias V1a, V1b, V1c in the X direction. The lengths Ly of the second vias V2a, V2b, V2c in the Y direction are also greater than the lengths Lx of the second vias V2a, V2b, V2c in the X direction. Therefore, the current density in the first vias V1a, V1b, V1c and the second vias V2a, V2b, V2c is reduced compared to vias whose cross-sectional shape is substantially circular. Thus, in the present embodiment, even if a large current flows through the resistance element RE, defects caused by electromigration are less likely to occur in the first vias V1a, V1b, V1c and the second vias V2a, V2b, V2c compared to resistance elements whose cross-sectional shape of the vias is substantially circular. Therefore, the reliability of the semiconductor device SD can be enhanced.

[0103] [First Modification]

[0104] Figure 8 is a perspective view illustrating an exemplary configuration of a main portion of a semiconductor device mSD1 according to a first modification of the present embodiment. Figure 9 is a cross-sectional view illustrating an exemplary configuration of a main portion of the semiconductor device mSD1.

[0105] The semiconductor device mSD1 according to the first modification includes the insulating film ILF, the heat conduction portion HCP, the coupling portion CP, and the heat conduction portion mHCP. The heat dissipation portion mHDP1 according to the first modification is not directly connected to the resistance element RE. That is, the heat dissipation portion mHDP1 is formed in the multilayer wiring layer MWL such that the heat dissipation portion mHDP1 is spaced apart from the resistance element RE and connected to the heat conduction portion mHCP.

[0106] The heat conduction portion mHCP is formed of a wiring and a via formed in the multilayer wiring layer MWL. The heat conduction portion mHCP is formed along the third conductive portions CL3a, CL3b, CL3c. The heat conduction portion mHCP includes a first wiring mWR1, a first via mV1, and a second wiring mWR2. The configuration of the first wiring mWR1 is the same as that of the first conductive portion CL1a. The configuration of the first via mV1 is the same as that of the first via V1a. The configuration of the second wiring mWR2 is the same as that of the connection portion CNTa.

[0107] One end portion of the heat conduction portion mHCP faces a portion of the resistance element RE in a direction along the surface of the base member BM. In the first modification, one end portion of the heat conduction portion mHCP faces the first conductive portions CL1a, CL1b and the third conductive portions CL3a, CL3b in the X direction. The other end portion of the heat conduction portion mHCP faces another portion of the resistance element RE in a direction perpendicular to the surface of the base member BM. In the first modification, the other end portion of the heat conduction portion mHCP faces the second conductive portion CL2a in the Z direction.

[0108] In the first modification, since the heat dissipation portion mHDP1 is spaced apart from the resistance element RE, it is possible to suppress the flow of the current from the resistance element RE to the heat dissipation portion mHDP1. This makes it possible to simultaneously achieve heat dissipation and detection accuracy of the current value.

[0109] [Second Modification]

[0110] Figure 10 is a perspective view showing an exemplary configuration of a main portion of a semiconductor device mSD2 according to a second modification of the present embodiment.

[0111] The semiconductor device mSD2 according to the second modification has a plurality of the resistive elements. The number of the resistive elements is not particularly limited. The semiconductor device mSD2 according to the second modification includes a first resistive element mREl and a second resistive element mRE2. The exemplary configuration of the first resistive element mREl and the exemplary configuration of the second resistive element mRE2 are the same as the exemplary configuration of the resistive element RE. In the second modification, the first conductive portion mCLla of the first resistive element mREl is disposed so that the first resistive element mREl is adjacent to the second conductive portion mCL2a of the second resistive element mRE2 in a plan view. Thus, the magnetic field generated by the current flowing in the first resistive element mREl and the magnetic field generated by the current flowing in the second resistive element mRE2 cancel each other out. Thus, the change in the characteristics of the peripheral semiconductor elements due to the magnetic field generated by the current flowing through the resistive elements can be suppressed. Thus, the performance of the semiconductor device can also be enhanced.

[0112] [Third Modification]

[0113] Figure 11 is a perspective view showing an exemplary configuration of a main portion of a semiconductor device mSD3 according to a third modification of the present embodiment.

[0114] The semiconductor device mSD3 according to the third modification includes a resistive element mRE3. The resistive element mRE3 also includes a first conductive portion CLId, a second conductive portion CL2d, and a third conductive portion CL3d. The length of the first conductive portion CLId in the Y direction is smaller than the length of the first conductive portion CLId in the X direction. The length of the second conductive portion CL2d in the Y direction is smaller than the length of the second conductive portion CL2d in the X direction. The length of the third conductive portion CL3d in the Y direction is smaller than the length of the third conductive portion CL3d in the X direction.

[0115] In the third modification, the resistive element mRE3 includes portions in which each component (the first conductive portions CLla, CLlb, the second conductive portions CL2a, CL2b, and the third conductive portions CL3a, CL3b, CL3c) extends in the Y direction and portions in which each component (the first conductive portion CLId, the second conductive portion CL2d, and the third conductive portion CL3d) extends in the X direction. Thus, when the semiconductor device mSD3 is sealed with a sealing resin, when there is a difference between the stress in the X direction and the stress in the Y direction, the sum of the stresses applied to the semiconductor device mSD3 can be reduced on average.

[0116] It should be noted that the present application is not limited to the above-described embodiments, and various modifications can be made without departing from the gist thereof. For example, the third conductive portion CL3 need only be capable of electrically connecting the first conductive portion CL1a and the second conductive portion CL2a to each other, and need not necessarily have the connecting portion CNTa.

[0117] In addition, even in the case where a specific numerical example is described, the numerical value can be a value exceeding the specific numerical value, or can be a value smaller than the specific numerical value, except for the case where it is theoretically obviously limited to the numerical value. In addition, the composition means "B contains A as a main component" and the like, and does not exclude a mode of containing other components.

[0118] Furthermore, at least a part of each of the embodiments and at least a part of each of the modifications can be arbitrarily combined with each other. For example, the structure, position, and material of the heat-conducting portion and the heat-dissipating portion can be appropriately designed.

Claims

1. A semiconductor device comprising: a base member; a multilayer wiring layer formed on the base member; a first resistance element formed in the multilayer wiring layer; and a heat dissipation portion, wherein the first resistance element includes: a first conductive portion; a second conductive portion formed on the first conductive portion; and a third conductive portion electrically connecting the first conductive portion and the second conductive portion to each other, wherein a length of the third conductive portion in a first direction along a surface of the base member is greater than a length of the third conductive portion in a second direction along the surface of the base member, and the second direction is perpendicular to the first direction, wherein a portion of the heat dissipation portion is formed in the multilayer wiring layer, wherein a remaining portion of the heat dissipation portion is formed in the base member, wherein the heat dissipation portion includes: a first insulating film formed on a bottom surface and a side surface of a recessed portion formed on the surface of the base member; and a first heat conduction portion formed on the first insulating film such that the first heat conduction portion buries the recessed portion, and wherein the heat dissipation portion includes a second heat conduction portion formed in the multilayer wiring layer such that the second heat conduction portion is spaced apart from the first resistance element and connected to the first heat conduction portion.

2. The semiconductor device according to claim 1, wherein the heat dissipation portion includes a first coupling portion formed in the multilayer wiring layer such that the first coupling portion connects the second heat conduction portion and the first heat conduction portion to each other.

3. The semiconductor device according to claim 1, wherein the second heat conduction portion extends along the third conductive portion in a direction perpendicular to a cross-sectional view in a thickness direction of the semiconductor device.

4. The semiconductor device according to claim 1, wherein one end portion of the second heat conduction portion faces a portion of the first resistance element in the second direction along the surface of the base member, and wherein the one end portion of the second heat conduction portion faces another portion of the first resistance element in a direction perpendicular to the surface of the base member.

5. The semiconductor device according to claim 1, wherein one end portion of the second heat conduction portion faces the first conductive portion and the third conductive portion in a direction along the surface of the base member, and wherein the one end portion of the second heat conduction portion faces the second conductive portion in a direction perpendicular to the surface of the base member.

6. The semiconductor device according to claim 1, wherein the multilayer wiring layer includes: a protective layer formed in an uppermost layer of the multilayer wiring layer; and a thermal stress relief portion formed between the first resistance element and the protective layer, and wherein the thermal stress relief portion overlaps the first resistance element in a plan view.

7. The semiconductor device according to claim 1, comprising: ​ ​ a first region in which the first transistor is formed; and a second region in which the second transistor is formed, wherein the first resistance element is formed between the first region and the second region in a plan view.

8. The semiconductor device according to claim 1, comprising a second resistance element formed in the multilayer wiring layer, wherein the second resistance element includes: a fourth conductive portion; a fifth conductive portion formed over the fourth conductive portion; and a sixth conductive portion electrically connecting the fourth conductive portion and the fifth conductive portion to each other, and wherein a length of the sixth conductive portion in the first direction is smaller than a length of the sixth conductive portion in the second direction.

9. The semiconductor device according to claim 1, comprising a third resistance element formed in the multilayer wiring layer, wherein the third resistance element includes: a fourth conductive portion; a fifth conductive portion formed over the fourth conductive portion; and a sixth conductive portion electrically connecting the fourth conductive portion and the fifth conductive portion to each other, wherein the fourth conductive portion, the fifth conductive portion, and the sixth conductive portion extend in the first direction in a plan view, and wherein the first conductive portion is adjacent to the fifth conductive portion in a plan view.

10. A semiconductor device comprising: a base member; a multilayer wiring layer formed over the base member; a first resistance element formed in the multilayer wiring layer; and a heat dissipation portion, wherein the first resistance element includes: a first conductive portion; a second conductive portion formed over the first conductive portion; and a third conductive portion electrically connecting the first conductive portion and the second conductive portion to each other, wherein a length of the third conductive portion in a first direction along a surface of the base member is larger than a length of the third conductive portion in a second direction along the surface of the base member, and the second direction is perpendicular to the first direction, wherein a portion of the heat dissipation portion is formed in the multilayer wiring layer, wherein a remaining portion of the heat dissipation portion is formed in the base member, wherein the base member includes: a semiconductor substrate; and a semiconductor layer formed on a surface of the semiconductor substrate, wherein the heat dissipation portion penetrates the semiconductor layer so that the heat dissipation portion reaches the semiconductor substrate, and wherein the semiconductor layer includes: a first epitaxial layer having a first conductivity type; a first buried layer formed on the first epitaxial layer and having a second conductivity type opposite to the first conductivity type; and a second epitaxial layer formed on the first buried layer and having the first conductivity type. ​ ​ ​

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