Semiconductor devices

Abstract

An embodiment of the present invention provides a semiconductor device capable of improving operational reliability. The semiconductor device of the embodiment has: a plurality of first input-output circuits for a first channel; a plurality of first input-output pads corresponding to the plurality of first input-output circuits, respectively; a plurality of second input-output circuits for the first channel; a plurality of second input-output pads corresponding to the plurality of second input-output circuits, respectively; and an input circuit arranged between a row of the plurality of first input-output pads and a row of the plurality of second input-output pads, and inputting data from the plurality of first input-output circuits and the plurality of second input-output circuits to a memory. In the memory, data input to the memory from the plurality of first input-output pads and the plurality of second input-output pads is obtained based on the rise and fall of an input clock signal.

Description

[0001] Information about divisional applications

[0002] This case is a divisional application. The parent case of this case is an invention patent application with application date of March 8, 2017, application number 201710134242.3, and invention name “Semiconductor Device”.

[0003] Related Applications

[0004] The present application claims priority based on Japanese Patent Application No. 2016-162762 (filing date: August 23, 2016) as a basic application, and the present application incorporates the entire contents of the basic application by reference. Technical Field

[0005] Embodiments of the present invention relate to a semiconductor device. Background Art

[0006] There is known a semiconductor device in which a core chip is stacked on an interface chip provided on a semiconductor substrate via a through-silicon via (TSV: Through-Silicon Via). Summary of the invention

[0007] Embodiments of the present invention provide a semiconductor device capable of improving operation reliability.

[0008] The semiconductor device of the embodiment includes: a plurality of first input-output circuits for a first channel; a plurality of first input-output pads corresponding to the plurality of first input-output circuits, respectively; a plurality of second input-output circuits for the first channel; a plurality of second input-output pads corresponding to the plurality of second input-output circuits, respectively; and an input circuit arranged between a row of the plurality of first input-output pads and a row of the plurality of second input-output pads, and inputting data from the plurality of first input-output circuits and the plurality of second input-output circuits to a memory. In the memory, data inputted to the memory from the plurality of first input-output pads and the plurality of second input-output pads is acquired based on the rising and falling of an input clock signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 This is a block diagram of the memory system according to this embodiment.

[0010] Figure 2 It is a diagram showing the structure of the I / F chip 400 according to the embodiment.

[0011] Figure 3 It is a diagram showing the arrangement structure of the pads Pa of the I / F chip 400 according to the first embodiment.

[0012] Figure 4 1 is a diagram showing wiring on the data input (data write) side of the I / F chip 400 according to the embodiment.

[0013] Figure 5 1 is a diagram showing wiring on the data output (data read) side of the I / F chip 400 according to the embodiment.

[0014] Figure 6 It is a cross-sectional view showing a method of mounting an I / F chip 400 and a NAND (Not And) type flash memory 100 according to an embodiment.

[0015] Figure 7 (a) to (e) are diagrams for explaining the relationship between the signal DQS and the signal BDQS and data when reading from the NAND flash memory 100 according to the embodiment.

[0016] Figure 8 It is a diagram showing the configuration of the arrangement of the pad of the comparative example.

[0017] Fig. 9 It is a diagram showing the arrangement structure of pads Pa of the I / F chip 400 according to the second embodiment.

[0018] Fig.10 It is a diagram showing the arrangement structure of pads Pa of the I / F chip 400 according to the third embodiment.

[0019] Fig.11 It is a diagram showing the arrangement structure of pads Pa of the I / F chip 400 according to the fourth embodiment.

[0020] Fig.12 It is a diagram showing the arrangement structure of the pads Pa of the I / F chip 400 according to the fifth embodiment. DETAILED DESCRIPTION

[0021] Hereinafter, embodiments will be described with reference to the drawings.

[0022] 1. First Implementation Aspect

[0023] The memory system of the first embodiment is described. A memory system having a NAND flash memory in which storage cells are arranged two-dimensionally on a semiconductor substrate is used as an example for description. In the embodiment, a high-speed memory system using a DDR (Double Data Rate) method is described, but the present invention is not limited thereto. The memory system of the embodiment is preferably a general memory system.

[0024] 1.1 About composition

[0025] The following describes a memory cell by taking a memory system including NAND flash memories arranged two-dimensionally on a semiconductor substrate as an example.

[0026] 1.1.1 Overall Structure of the Memory System

[0027] First, use Figure 1 A general overall configuration of the memory system according to the present embodiment will be described. Figure 1 This is a block diagram of the memory system according to this embodiment.

[0028] As shown in the figure, the memory system 1 includes a plurality of NAND flash memories 100-0 to 100-N, an interface (I / F) chip 400, and a controller 200. In the embodiment, when it is not necessary to distinguish between the NAND flash memories 100-0 to 100-N, the hyphen is omitted and described as "NAND flash memory 100". The same applies to other components.

[0029] The NAND flash memory 100 has a plurality of storage units for storing data in a non-volatile manner. In the present embodiment, the NAND flash memory 100 has two channels (channel 0 (ch0) and channel 1 (ch1)). The controller 200 is connected to the NAND flash memory 100 for each channel via the I / F chip 400 through the NAND bus, and is connected to the host machine 300 through the host bus. Furthermore, the controller 200 controls the NAND flash memory 100 for each channel via the I / F chip 400. Furthermore, the controller 200 responds to commands received by the host machine 300 and accesses the NAND flash memory 100 for each channel via the I / F chip 400. The host machine 300 is, for example, a digital camera or a personal computer, and the host bus is, for example, based on an SD card. TM (Secure Digital Memory Card: Secure Digital Card) interface bus.

[0030] The NAND bus performs transmission and reception of signals based on the NAND interface. Figure 1 As shown, the controller 200 and the I / F chip 400 are connected via a two-channel NAND interface. In addition, here, a case where a NAND interface is provided for each channel is shown, but the same NAND interface may be used using channel identification information or the like.

[0031] Specific examples of the signal are a chip enable signal CEn, an address latch enable signal ALE, a command latch enable signal CLE, a write enable signal WEn, a read enable signal REn, an input / output signal I / O, and a data select signal DQS.

[0032] Signal CEn is a signal for starting the NAND flash memory 100 and is asserted at a low level. Signals CLE and ALE are signals for notifying the NAND flash memory 100 that the signals input to the NAND flash memory 100 are instructions and addresses, respectively. Signal WEn is a signal for acquiring instructions or addresses at the transition timing from a low level to a high level. Signal REn is also asserted at a low level and is a signal for reading the output signal I / O from the NAND flash memory 100. Signal BREn is a complementary signal of signal REn and is a signal for reading the output signal I / O from the NAND flash memory 100.

[0033] The input / output signal I / O is, for example, an 8-bit signal and is the entity of data transmitted and received between the NAND flash memory 100 and the controller 200, such as a command, an address, write data, and read data.

[0034] The signal DQS and the complementary signal BDQS of the signal DQS are output from the transmission side together with the signal I / O (data). The data reception side receives the transmitted signal DQS and the signal BDQS and adjusts the timing of acquiring data.

[0035] 1.1.2 Configuration of NAND Flash Memory 100

[0036] Next, the structure of the NAND flash memory 100 is described. Figure 1 As shown, the NAND flash memory 100 includes a memory cell array 110 , a row counter 120 , a drive circuit 130 , a sense amplifier 140 , an address resistor 150 , a command resistor 160 , and a sequencer 170 .

[0037] The memory cell array 110 includes a plurality of nonvolatile memory cells corresponding to rows and columns, ie, for example, four blocks BLK ( BLK0 to BLK3 ), and stores data given by the controller 200 .

[0038] The row counter 120 selects any one of the blocks BLK0 ˜ BLK3 , and further selects the row direction of the selected block BLK.

[0039] The driving circuit 130 supplies a voltage to the selected block BLK via a row decoder.

[0040] When reading data, the sense amplifier 140 senses the data read from the memory cell array 110 and performs necessary operations, and outputs the data DAT to the controller 200 . When writing data, the write data DAT received from the controller 200 is transmitted to the memory cell array 110 .

[0041] The address resistor 150 holds the address ADD received from the controller 200 . The command resistor 160 holds the command CMD received from the controller 200 .

[0042] The sequencer 170 controls the overall operation of the NAND flash memory 100 based on the command CMD held in the command resistor 160 .

[0043] In addition, the memory cell array 110 may also be a structure in which memory cell transistors are three-dimensionally stacked on the upper side of the semiconductor substrate. Such a structure is described, for example, in U.S. Patent Application No. 12 / 407,403 filed on March 19, 2009, “Three-dimensional stacked non-volatile semiconductor memory”. Also, it is described in U.S. Patent Application No. 12 / 406,524 filed on March 18, 2009, “Three-dimensional stacked non-volatile semiconductor memory”, U.S. Patent Application No. 12 / 679,991 filed on March 25, 2010, “Non-volatile semiconductor memory device and method of manufacturing the same”, and U.S. Patent Application No. 12 / 532,030 filed on March 23, 2009, “Semiconductor memory and method of manufacturing the same”. These patent applications are incorporated herein by reference in their entirety.

[0044] 1.1.3 Configuration of I / F chip 400

[0045] Figure 2 It is a diagram showing the structure of the I / F chip 400 according to the embodiment.

[0046] The I / F chip 400 includes an I / F circuit 500 for each channel. In the embodiment, each of the plurality of NAND flash memories 100-0 to 100-N is connected to either channel 0 (ch0) or channel 1 (ch1).

[0047] Therefore, (N+1) NAND flash memories 100-0 to 100-N can be accessed simultaneously through two channels (channel 0 (ch0) and channel 1 (ch1)).

[0048] The I / F circuit 500-0 of channel 0 (ch0) has an input I / F 410-0 for inputting the signal I / O etc. from the controller 200 to the NAND flash memory 100 of channel 0 (ch0), and an output I / F 420-0 for outputting the signal I / O etc. from the NAND flash memory 100 of channel 0 (ch0) to the controller 200.

[0049] The I / F circuit 500-1 of channel 1 (ch1) has an input I / F 410-1 for inputting the signal I / O etc. from the controller 200 to the NAND flash memory 100 of channel 1 (ch1), and an output I / F 420-1 for outputting the signal I / O etc. from the NAND flash memory 100 of channel 1 (ch1) to the controller 200.

[0050] Input I / F 410 - 0 is an interface used to connect the signals (CEn, ALE, CLE, WEn, REn, BREn, I / O, DQS, BDQS) input from the controller 200 to channel 0 (ch0) to the corresponding NAND flash memory 100 of channel 0 (ch0).

[0051] The input I / F 410 - 1 is an interface for connecting the signals (CEn, ALE, CLE, WEn, REn, BREn, I / O, DQS, BDQS) input from the controller 200 to the channel 1 (ch1) to the corresponding NAND flash memory 100 of the channel 1 (ch1).

[0052] The output I / F 420 - 0 is an interface for connecting data (signal I / O) output from the NAND flash memory 100 of channel 0 (ch0) to channel 0 (ch0) of the controller 200 .

[0053] The output I / F 420 - 1 is an interface for connecting data (signal I / O) output from the NAND flash memory 100 of channel 1 (ch1) to channel 1 (ch1) of the controller 200 .

[0054] 1.1.4 Configuration of pad Pa of I / F chip 400

[0055] Figure 3 It is a diagram showing the arrangement structure of pads Pa of the I / F chip 400 having a two-channel structure according to the first embodiment.

[0056] As shown in the figure, the I / O circuits 10-0 to 10-7 on the channel 0 (ch0) side each have a pad Pa used for inputting and outputting the signal I / O of the channel 0 (ch0) of the controller 200 and an input receiver IR for receiving the signal input from the channel 0 of the controller 200 via the pad Pa.

[0057] The DQS circuit 11, BDQS circuit 12, REn circuit 13, and BREn circuit 14 each have a pad Pa used for inputting and outputting a signal of channel 0 (ch0) of the controller 200. The DQS circuit 11 and BDQS circuit 12 each independently have an input receiver IR. The REn circuit 13 and BREn circuit 14 have an input receiver IR in common.

[0058] The control circuits 21-1 to 21-4 respectively include a pad Pa for inputting and outputting signals on the channel 0 side of the controller 200 and an input receiver IR for receiving signals input from the channel 0 of the controller 200 via the pad Pa. The signals inputted and outputted to the control circuits 21-1 to 21-4 are signals (CEn, ALE, CLE, WEn) other than the signals (I / O, DQS, BDQS, REn, BREn).

[0059] A micro bump MBP is formed on the pad Pa, and the I / F chip 400 is electrically connected to the channel 0 (ch0) of the controller 200 via the micro bump MBP. In other words, the corresponding circuits (I / O circuit 10, DQS circuit 11, BDQS circuit 12, REn circuit 13, BREn circuit 14, and control circuit 21) of the I / F chip 400 communicate signals with the controller 200 via the pad Pa.

[0060] Furthermore, the communication between the corresponding circuit of the I / F chip 400 and the NAND flash memory 100 selected by the address selection is performed via the corresponding pads (not shown) of the micro-bump areas A-1 to A-3 and the micro-bumps MBP. Figure 6 Described below.

[0061] The pads Pa of the I / O circuits 10-0 to 10-3, the BDQS circuit 12, and the DQS circuit 11 on the channel 0 (ch0) side are arranged in a row from the inside to the outside of the I / F chip 400. Similarly, the pads Pa of the I / O circuits 10-7 to 10-4, the REn circuit 13, and the BREn circuit 14 on the channel 0 (ch0) side are arranged in a row from the inside to the outside of the I / F chip 400. The wiring distance between each input receiver IR of the I / O circuits 10-0 to 10-7 and each corresponding pad Pa of the I / O circuits 10-0 to 10-7 is fixed.

[0062] The pads Pa of the I / O circuits 10-0 to 10-3 are arranged inside the I / F chip 400 than the pads Pa of the DQS circuit 11 and the BDQS circuit 12. The pads Pa of the I / O circuits 10-4 to 10-7 are arranged inside the I / F chip 400 than the pads Pa of the REn circuit 13 and the BREn circuit 14.

[0063] The data input latch DIN of channel 0 (ch0) is connected to the input receivers IR of the I / O circuits 10-0 to 10-7, the DQS circuit 11, and the BDQS circuit 12 through wiring.

[0064] The data input latch DIN is arranged between the row of pads Pa of the I / O circuits 10-0 to 10-3, the DQS circuit 11, and the BDQS circuit 12, and the row of pads Pa of the I / O circuits 10-4 to 10-7, the REn circuit 13, and the BREn circuit 14. By configuring the data input latch DIN in this way, the length of the wiring of each input receiver IR of the I / O circuits 10-0 to 10-7 and the data input latch DIN can be made substantially uniform.

[0065] Each control circuit 21-1 to 21-4 on the channel 0 (ch0) side has an input receiver IR and a pad Pa. The pads Pa of each control circuit 21-1 to 21-4 are arranged in a row. The row of the pads Pa of the control circuits 21-1 to 21-4 is a row in a direction orthogonal to the row of the pads Pa of the I / O circuits 10-0 to 10-3, the DQS circuit 11 and the BDQS circuit 12 and the row of the pads Pa of the I / O circuits 10-4 to 10-7, the REn circuit 13 and the BREn circuit 14.

[0066] Next, the channel 1 (ch1) side is described. The configuration of the channel 1 (ch1) side is the same as that of the channel 0 (ch0) side, but the configuration is different. That is, the I / O circuits 10-0 to 10-7, the DQS circuit 11, the BDQS circuit 12, the REn circuit 13, and the BREn circuit 14 on the channel 1 (ch1) side are configured to be point-symmetrical with respect to the center of the circuits on the channel 0 (ch0) side (I / O circuits 10-0 to 10-7, the DQS circuit 11, the BDQS circuit 12, the REn circuit 13, and the BREn circuit 14) and the circuits on the channel 1 (ch1) side (I / O circuits 10-0 to 10-7, the DQS circuit 11, the BDQS circuit 12, the REn circuit 13, and the BREn circuit 14).

[0067] Furthermore, the control circuits 21 - 1 to 21 - 4 on the channel 1 (ch1) side are arranged point-symmetrically with respect to the centers of the control circuits 21 - 1 to 21 - 4 on the channel 0 (ch0) side and the control circuits 21 - 1 to 21 - 4 on the channel 1 (ch1) side.

[0068] A micro-protrusion area A-1 is formed in the area between the area where IO circuits 10-4 to 10-7, REn circuit 13, and BREn circuit 14 are formed on the channel 0 (ch0) side and the area where IO circuits 10-0 to 10-3, DQS circuit 11, and BDQS circuit 12 are formed on the channel 1 (ch1) side.

[0069] A micro-protrusion area A-2 is formed in the area between the area where IO circuits 10-0 to 10-3, DQS circuit 11 and BDQS circuit 12 are formed on the channel 0 (ch0) side and the area where IO circuits 10-4 to 10-7, REn circuit 13 and BREn circuit 14 are formed on the channel 1 (ch1) side.

[0070] A micro bump region A-3 is formed in the region where the control circuits 21-1 to 21-4 are formed on the channel 0 (ch0) side and the region where the control circuits 21-1 to 21-4 are formed on the channel 1 (ch1) side. In addition, there is a region where a voltage generating circuit is formed. Pads (not shown) are formed in the micro bump regions A-1, A-2, and A-3, and micro bumps MBP for connecting to the core chip CC-8 are formed on the pads.

[0071] 1.1.5 Circuit Configuration for Inputting and Outputting Data of IF Chip 400

[0072] Figure 4 The figure shows the wiring of the input receiver IR and the data input latch DIN of each I / O circuit 10 on the data input (data writing) side of the I / F chip 400 of the embodiment. These input receiver IR and the data input latch DIN show the wiring relationship of each channel.

[0073] As shown in the figure, the pads Pa of the I / O circuits 10-0 to 10-7 and the input receivers IR of the I / O circuits 10-0 to 10-7 are connected by pad wiring.

[0074] The input receivers IR (for example, Figure 3 The input receiver IR of the I / O circuits 10-0 to 10-7 on the channel 0 (ch0) side and the data input latch DIN (for example, Figure 3 In the I / F chip 400, the distances between the pads Pa of each I / O circuit 10-0 to 10-7 and the input receiver IR corresponding to the pads Pa are fixed. In the embodiment, the length of the wiring between the input receiver IR of each I / O circuit 10-0 to 10-7 and the data input latch DIN is designed to be shorter than that of the previous I / F chip 400.

[0075] The data input latch DIN receives as trigger signals the signal DQS transmitted from the controller 200 and input to the input receiver IR via the pad 11Pa of the DQS circuit 11 and the signal BDQS input to the input receiver IR via the pad Pa of the BDQS circuit 12. The data input latch DIN is connected to the pad Pa' of the corresponding micro bump MBP of the micro bump areas A-1 and A-2, and latches the signal I / O (8 bits) received by the input receiver IR of each I / O circuit 10-0 to 10-7 based on the input trigger signal (signal DQS, signal BDQS).

[0076] The data latched by the data input latch DIN is output to the NAND flash memory 100 selected by the address selection via the pad Pa' and the micro bump MBP of the corresponding micro bump areas A-1 and A-2. The data is output to the NAND flash memory 100 in 8×m bits (m is an arbitrary integer), for example.

[0077] Figure 5 The figure shows the wiring of the input receiver IR of the REn circuit 13 on the data output (data read) side of the I / F chip 400 according to the embodiment and the MUX (Multiplexer) 620 of each I / O circuit 10. These input receiver IR and MUX 620 show the wiring relationship of each channel.

[0078] As shown in the figure, the pad Pa of the REn circuit 13 and the input receiver IR of the REn circuit 13 are connected by pad wiring. Also, the input receiver IR of the REn circuit 13 and the MUX 620 of each I / O circuit 10 are connected by internal wiring of the I / F chip 400.

[0079] The MUX 620 of each I / O circuit 10 is connected to the pad Pa' of the corresponding micro bump MBP of the micro bump area A-1, A-2. And, the MUX 620 of each I / O circuit 10 is connected to the pad Pa of each I / O circuit 10 through the pad wiring (8 bits). The MUX 620 selects the corresponding read data stored in the buffer from the NAND flash memory 100 based on the signal REn of the input receiver IR from the REn circuit 13. Data is output from the NAND flash memory 100 in, for example, 8×n bits (n is an arbitrary integer).

[0080] Furthermore, based on the signal REn of the input receiver IR from the REn circuit 13, the signal DQS and the signal BDQS are generated in the MUX circuits in the DQS circuit 11 and the BDQS circuit 12. The generated signal DQS and the signal BDQS are output to the channel 0 (ch0) of the controller 200 through the pad Pa of the DQS circuit 11 and the BDQS circuit 12.

[0081] The read data selected by MUX620 of I / O circuits 10-0 to 10-7 is output to controller 200 via pad Pa of each I / O circuit 10 at a double data rate via an output driver driven by a front driver and using the falling edges of signal DQS and signal BDQS generated in I / F chip 400.

[0082] In the embodiment, the length of the wiring between the input receiver IR610 of the REn circuit 13 and the MUX 620 of the I / O circuits 10 - 0 to 10 - 7 is designed to be shorter than that of the conventional I / F chip 400 .

[0083] In addition, in the embodiment, the MUX 620 of the I / O circuits 10 - 0 to 10 - 7 is described, but it may be another component of the output circuit (for example, a pre-driver, etc.).

[0084] 1.1.6 Installation of I / F chip 400 and NAND flash memory 100

[0085] Figure 6 4 is a cross-sectional view showing a method of mounting the I / F chip 400 and the NAND flash memory 100 according to the embodiment. Figure 1 The figure shows the case of (N+1) NAND flash memories 100, but Figure 6 , a semiconductor device having a two-channel structure (N=7) is shown in which one NAND flash memory 100 is mounted on each of eight core chips CC-1 to CC-8.

[0086] As shown in the figure, an I / F chip 400 is mounted on a mounting substrate S. A plurality of large bumps LBP (LBP-1 to LBP-4) are formed on the upper surface of the semiconductor substrate S. Also, a plurality of micro bumps MBP (MBP-1 to MBP-3) are formed on the upper surface of the I / F chip 400. In order to stack a plurality of core chips CC (CC-1 to CC-8), the large bumps LBP and the micro bumps MBP are formed at the same height from the upper surface of the substrate S.

[0087] A plurality of bumps BP (BP-1 to BP-9) are formed on the lower surface of the substrate S. The bump BP is electrically connected to the large bump LBP via wiring formed in the substrate S. The bump BP is used for input / output signals to the outside of the substrate S. In the embodiment, the bump BP-1 is used, for example, for supplying power to each core chip CC-1 to CC-8. The bumps BP-2 to BP-9 are used for input / output signals I / O transmitted between the controller 200 and the I / F chip 400.

[0088] Multiple core chips CC (CC-1 to CC-8) are stacked on the large bump LBP and micro bump MBP. Each core chip CC-1 to CC-8 is stacked using through-chip electrodes (TSV) and bumps BP-A. This structure is called BGA (Ball Grid Array), which is one of the packaging methods with more input and output pins.

[0089] In addition, Figure 6 In the figure, only bumps BP-1 to BP-9, large bumps LBP-1 to LBP-4 and micro bumps MBP-1 to MBP-4 are shown, but bumps BP, large bumps LBP and micro bumps MBP not shown are provided on the mounting substrate S for other input and output signals.

[0090] If Figure 6 For example, core chips CC-2 to CC-8 are mounted face up on the mounting substrate, and the top core chip CC-1 is mounted face down on the core chip CC-2. Figure 1 The NAND flash memory 100 described in . Alternatively, the core chips CC-2 to CC-8 may be mounted face down on the mounting substrate.

[0091] A redistribution layer RDL (RDL-1 to RDL-4 and a redistribution layer RDL not shown) is formed on the lower surface of the bottom core chip CC-8 (opposite to the upper surface of the substrate S on which the NAND flash memory 100 is formed). The large bumps LBP formed on the substrate S are electrically connected to the redistribution layer RDL via the pads P. Furthermore, the redistribution layer RDL electrically connects the large bumps LBP formed on the substrate S to the micro bumps MBP.

[0092] Specifically, bump BP-1 is electrically connected to TSV via wiring, large bump LBP-1, redistribution layer RDL-1, and bump P-1 in substrate S. Bumps BP-2 to BP-9 and BP (not shown) are electrically connected to I / F chip 400 via wiring, large bump LBP, redistribution layer RDL, micro bump MBP, and pad Pa (not shown) in substrate S. I / F chip 400 is electrically connected to each core chip CC via micro bump MBP, redistribution layer RDL, pad Pa', and TSV.

[0093] TSVs are formed in a manner that penetrates each core chip CC-2 to CC-8. The TSVs of each core chip CC-2 to CC-8 are used to electrically connect to another core chip CC in the upper and / or lower layers. Since the core chip CC-1 is mounted face down, TSVs are not formed. The NAND flash memory 100 formed on the core chip CC-1 is electrically connected to the TSVs of the core chip CC-2 via the bumps BP-A and pads (not shown). Each TSV of the core chips CC-2 to CC-8 is electrically connected to the TSVs of another core chip CC in the upper and / or lower layers via the bumps BP-A.

[0094] 1.2 About Action

[0095] Below, refer to Figure 7 The read operation of channel 0 (ch0) of the I / F chip 400 of the first embodiment will be described with reference to the timing chart of FIG. 1. In addition, although channel 0 (ch0) is described here, the operation of channel 1 (ch1) is also described in the same manner.

[0096] In the memory system of the embodiment, the DDR method is adopted, and the signal DQS and the signal BDQS are used to perform reading and writing with respect to the NAND flash memory 100.

[0097] In terms of reading, the controller 200 inputs a data output command to the I / F chip 400 for channel 0 (ch0), and then selects the corresponding NAND flash memory 100 according to the chip address signal. Specifically, the data output command and the chip address signal are transmitted to the large bump LBP mounted on the upper surface of the substrate S via the bump BP mounted on the lower surface of the substrate S and the wiring formed inside the substrate S. The data output command and the chip address signal transmitted to the large bump LBP are output to the pad Pa of the IO circuit 10-0 to 10-7 on the channel 0 (ch0) side, the input receiver IR, the data input latch DIN, and the corresponding micro bump MBP of the micro bump area A-1 and A-2 through the redistribution layer RDL mounted on the lower surface of the core chip CC-8 and the micro bump MBP formed on the upper surface of the I / F chip 400. Thus, the corresponding NAND flash memory 100 is selected.

[0098] Next, a readout enable signal REn is issued for channel 0 (ch0) from the controller 200. The signal REn is transmitted to the large bump LBP mounted on the upper surface of the substrate S via the bump BP mounted on the lower surface of the substrate S and the wiring formed inside the substrate S. The signal REn transmitted to the large bump LBP passes through the redistribution layer RDL mounted on the lower surface of the core chip CC-8 and the micro bump MBP formed on the upper surface of the I / F chip 400, and reaches the pad Pa of the REn circuit 13 on the channel 0 (ch0) side.

[0099] The signal REn reaching the pad Pa is output as an internal signal REn to the corresponding micro bump MBP in the micro bump areas A-1 and A-2 via the input receiver IR of the REn circuit 13. The internal signal REn is transmitted to the NAND flash memory 100 (selected by the address selection signal) via the micro bump MBP, the redistribution layer RDL, the pad P of the TSV of the core chip CC-8, the TSV of the core chips CC-1 to CC-7, and BP-A. Figure 7 (a): CNT→I / F→NAND).

[0100] Signals (CEn, ALE, CLE, WEn) other than the signals (I / O, DQS, BDQS, REn, and BREn) are transmitted and received with the controller 200 and the NAND flash memory 100 via the pads Pa and Pa′ of the control circuits 21 - 1 to 21 - 4 .

[0101] When the NAND flash memory 100 corresponding to channel 0 (ch0) receives the signal REn, data of the designated address is read in accordance with the falling edge of the signal REn ( Figure 7 (b): NAND→I / F). The read data is input as signal I / O to MUX620 of I / O circuits 10-0 to 10-7 of I / F chip 400 on the channel 0 (ch0) side via pad Pa' through TSV of core chip CC, bump BP-1, redistribution layer RDL of core chip CC-8, and corresponding micro bumps MBP of micro bump areas A-1 and A-2.

[0102] The MUX 620 is provided in the I / O circuits 10 - 0 to 10 - 7 on the channel 0 (ch0) side, and selects corresponding read data stored in the buffer area from the NAND flash memory 100 .

[0103] The I / F chip 400 outputs the signal DQS and the signal BDQS generated based on the REn signal from the pad Pa of the DQS circuit 11 and the pad Pa of the BDQS circuit. Furthermore, the corresponding read data selected by the MUX 620 is output at a double data rate from the pad Pa of the I / O circuits 10-0 to 10-7 of the corresponding channel 0 (ch0) at a timing synchronized with the DQS and the signal BDQS generated based on the REn signal in the I / F chip 400. The signal I / O, the signal DQS, and the signal BDQS output from the pad Pa are output to the controller 200 (via the micro bumps MBP, the redistribution RDL, the large bumps LBP, the wiring inside the substrate S, and the bumps BP. Figure 7 (c)~(e):I / F→CNT).

[0104] In terms of the write action, the controller 200 outputs the signal I / O, the signal DQS, and the signal BDQS for channel 0 (ch0). The signal I / O, the signal DQS, and the signal BDQS are transmitted to the large bump LBP mounted on the upper surface of the substrate S via the bump BP mounted on the lower surface of the substrate S and the wiring formed inside the substrate S. The signal I / O, the signal DQS, and the signal BDQS transmitted to the large bump LBP pass through the redistribution layer RDL mounted on the lower surface of the core chip CC-8 and the micro bump MBP formed on the upper surface of the I / F chip 400, and reach the pad Pa of the I / O circuit 10-0 to 10-7, the DQS circuit 11, and the BDQS circuit 12 on the channel 0 (ch0) side.

[0105] The signal I / O, signal DQS and signal BDQS reaching pad Pa are output to the corresponding micro bump MBP in micro bump areas A-1 and A-2 via the input receivers IR of I / O circuits 10-0 to 10-7, DQS circuits 11 and BDQS circuits 12, and data input latches DIN. The signal I / O, signal DQS and signal BDQS are transmitted to the NAND flash memory 100 selected by the address selection signal via the micro bump MBP, the redistribution layer RDL, the pad P of the TSV of the core chip CC-8, the TSV of the core chips CC-1 to CC-7, and BP-A, and are written via the sense amplifier.

[0106] In the above embodiment, the case where the number of pads Pa of the I / O circuits 10-0 to 10-7 is equally distributed for each channel ch (I / O circuits 10-0 to 10-3, I / O circuits 10-4 to 10-7) is described, but the number does not necessarily need to be the same.

[0107] Furthermore, in the embodiment, the I / F chip 400 is shown as having two channels, but the I / F chip 400 may also have a single channel. Furthermore, the I / F chip 400 may also have three or more channels.

[0108] 1.3 About the effect

[0109] 1.3.1 Comparative Example

[0110] Figure 8 It is a diagram showing the configuration of the arrangement of the pads of the comparative example.

[0111] Channel 0 (ch0) is described. As shown in the figure, the configuration of the pad Pa of the comparative example is that the pad Pa of the I / O circuit 10-0 to 10-3, the BDQS circuit 12, and the DQS circuit 11 are arranged in a row on the channel 0 (ch0) side. In addition, the pad Pa of the I / O circuit 10-4 to 10-7, the REn circuit 13, and the BREn circuit 14 are arranged in a row. Furthermore, the pad Pa of the control circuit 21-1 to 21-4 is arranged in a row. These three rows are arranged in the same direction.

[0112] The data input latch DIN is arranged in a region between a row other than the pad Pa of the I / O circuits 10 - 0 to 10 - 3 , the BDQS circuit 12 and the DQS circuit 11 and a row of the pad Pa of the I / O circuits 10 - 4 to 10 - 7 , the REn circuit 13 and the BREn circuit 14 .

[0113] When pad Pa is configured in this way, the structure of I / O circuits 10-0 to 10-7 is the same (in other words, the position of pad Pa of each I / O circuit 10-0 to 10-7 is the same), and the distance between pad Pa of each I / O circuit 10-0 to 10-7 and input receiver IR is roughly the same, so the distance between input receiver IR of each I / O circuit 10-0 to 10-7 and data input latch DIN affects the length of the input data line.

[0114] For configuration Figure 8 In the case of the pad Pa shown, the input / output data line is extended to the pad Pa of each I / O circuit 10-0 to 10-7. Therefore, regarding the input data line, the distance from the data input latch DIN to the pad Pa of the farthest I / O circuit 10-0, 10-7 and the distance from the closest I / O circuit 10-3, 10-4 are the largest.

[0115] This results in waveform changes and I / O timing deviations caused by differences in data line lengths. In order to minimize I / O timing deviations, the I / O circuit farthest from the data input latch DIN is connected to the I / O circuit ( Figure 8 The length of the data line 10-0, 10-7) is matched to the ground, and the other I / O circuits ( Figure 8 In this case, the parasitic capacitance increases due to the extension of the data line, resulting in an increase in current consumption.

[0116] Regarding the output data line, since the signal I / O is output based on the common signal REn, the distance between the REn circuit 13 and the output circuit (e.g., MUX 620) becomes an issue. According to the comparative example, the distance between the nearest I / O circuit 10-4 and the farthest I / O circuit 10-0 is the largest.

[0117] 1.3.2 Effects of the First Implementation

[0118] According to the I / F chip 400 of the semiconductor device of the first embodiment, Figure 3 As shown, the pads Pa of the I / O circuits 10-0 to 10-7 of the same channel are arranged in two rows, and the two are arranged in a manner that they are opposite to each other. Moreover, there is a data input latch DIN between the two opposite rows of pads Pa. With such a configuration, the distance between each I / O circuit 10-0 to 10-7 and the data input latch DIN can be shortened compared to the comparative example. As a result, the signal I / O timing from each I / O circuit 10 is made consistent, so that the I / O circuit 10 ( Figure 8 The length of the data line of the I / O circuits 10-0 and 10-7 of the other I / O circuits 10 ( Figure 8 As a result, the increase in current consumption can be minimized.

[0119] Moreover, by adopting such a configuration, the distances of the output clocks supplied to the I / O circuits 10-1 to 10-7, the DQS circuit 11, and the BDQS circuit 12 can be made uniform compared to the comparative example. As a result, the deviation of the output timings between the I / O signal, the DQS signal, and the BDQS signal can be suppressed. In order to minimize the deviation of the output timing, sometimes, the circuit farthest from the REn circuit 13 and the BREn circuit 14 (at Figure 8 In the case of the I / O circuit 10-0), the output clock signal to other circuits (I / O circuits 10-1 to 10-7, DQS circuit 11 and BDQS circuit 12) is extended to match the length. In this case, the increase in parasitic capacitance can be suppressed compared to the comparative example, so the increase in current consumption can be minimized.

[0120] Therefore, according to the first embodiment, the change of waveform caused by the difference in length of a plurality of input / output data lines and the timing deviation between I / Os can be suppressed. In particular, even for a memory system operating at high speed, the timing margin can be improved. Furthermore, since the parasitic capacitance of the input / output data lines is reduced, the power consumption can be reduced.

[0121] 2. Second Implementation Method

[0122] Next, a memory system according to the second embodiment will be described. The second embodiment and subsequent embodiments have the same configuration as the first embodiment except for the configuration of the I / F chip 400, so only the different parts will be described here.

[0123] Fig. 9 This is a diagram showing the arrangement of pads Pa of the I / F chip 400 of the second embodiment. As shown in the figure, the arrangement of I / O circuits 10-0 to 10-7, DQS circuit 11, BDQS circuit 12, REn circuit 13, and BREn circuit 14 is different from that of the first embodiment.

[0124] Specifically, the pads Pa of the I / O circuits 10-0, 10-1, the BDQS circuit 12, the DQS circuit 11, and the I / O circuits 10-2, 10-3 on the channel 0 (ch0) side are arranged in a row from the inside to the outside of the I / F chip 400. Similarly, the pads Pa of the I / O circuits 10-6, 10-7, the REn circuit 13, the BREn circuit 14, and the IO circuits 10-4, 10-5 on the channel 0 (ch0) side are arranged in a row from the inside to the outside of the I / F chip 400.

[0125] That is, in the second embodiment, the pads Pa of the BDQS circuit 12 and the DQS circuit 11 are arranged between the pads Pa of the I / O circuits 10-0 and 10-1 and the pads Pa of the I / O circuits 10-2 and 10-3. Furthermore, the pads Pa of the BREn circuit 14 and the REn circuit 13 are arranged between the pads Pa of the I / O circuits 10-4 and 10-5 and the pads Pa of the I / O circuits 10-6 and 10-7.

[0126] Next, the channel 1 (ch1) side is described. The configuration of the channel 1 (ch1) side is the same as that of the channel 0 (ch0) side, but the arrangement is different. That is, the circuits on the channel 1 (ch1) side (I / O circuits 10-0 to 10-7, DQS circuits 11, BDQS circuits 12, REn circuits 13, and BREn circuits 14) are arranged to be point-symmetrical with respect to the center point of the circuits on the channel 0 (ch0) side (I / O circuits 10-0 to 10-7, DQS circuits 11, BDQS circuits 12, REn circuits 13, and BREn circuits 14) and the circuits on the channel 1 (ch1) side (I / O circuits 10-0 to 10-7, DQS circuits 11, BDQS circuits 12, REn circuits 13, and BREn circuits 14).

[0127] According to the second embodiment, in addition to the effects of the first embodiment, the wiring of the output clock signal generated by the input buffer of the REn circuit 13 and the BREn circuit 14 can be further shortened.

[0128] 3. Third Implementation Method

[0129] Fig.10 It is a diagram showing the arrangement structure of pads Pa of the I / F chip 400 according to the third embodiment.

[0130] In the third embodiment, Figure 3 Compared with the arrangement of the pads Pa of the I / O circuits 10-0 to 10-7, the BDQS circuit 12, the DQS circuit 11, the REn circuit 13, and the BREn circuit 14 in the first embodiment shown, the pads Pa of the I / O circuits 10-0 to 10-3, the BDQS circuit 12, and the DQS circuit 11 on the channel 0 (ch0) side are arranged in a row in an oblique direction from the inside to the outside of the I / F chip 400. Similarly, the pads Pa of the I / O circuits 10-4 to 10-7, the REn circuit 13, and the BREn circuit 14 on the channel 0 (ch0) side are arranged in a row in an oblique direction from the inside to the outside of the I / F chip 400.

[0131] The data input latch DIN is arranged between the row of the pads Pa of the I / O circuits 10 - 0 to 10 - 3 and the row of the pads Pa of the I / O circuits 10 - 4 to 10 - 7 .

[0132] Next, the channel 1 (ch1) side is described. The configuration of the channel 1 (ch1) side is the same as that of the channel 0 (ch0) side, but the configuration is different. That is, the circuits on the channel 1 (ch1) side (I / O circuits 10-0 to 10-7, DQS circuits 11, BDQS circuits 12, REn circuits 13, and BREn circuits 14) are configured to be point-symmetrical with respect to the center point of the circuits on the channel 0 (ch0) side (I / O circuits 10-0 to 10-7, DQS circuits 11, BDQS circuits 12, REn circuits 13, and BREn circuits 14) and the circuits on the channel 1 (ch1) side (I / O circuits 10-0 to 10-7, DQS circuits 11, BDQS circuits 12, REn circuits 13, and BREn circuits 14).

[0133] According to the third embodiment, in addition to the effects of the first embodiment, evaluation by the I / F chip 400 alone becomes easy. That is, since there is no RDL wiring when evaluating the I / F chip 400 alone, it is necessary to connect it to the pad of the I / F chip 400 through a lead. In the third embodiment, by displacing each pad Pa obliquely, the lead can be easily set.

[0134] 4. Fourth Implementation Method

[0135] Fig.11 This is a diagram showing the arrangement of pads Pa of the I / F chip 400 of the fourth embodiment. As shown in the figure, the arrangement of I / O circuits 10-0 to 10-7, DQS circuit 11, BDQS circuit 12, REn circuit 13, and BREn circuit 14 is different from that of the first embodiment.

[0136] Specifically, the pads Pa of the I / O circuits 10-0, 10-1, the BDQS circuit 12, the DQS circuit 11, and the I / O circuits 10-2 and 10-3 on the channel 0 (ch0) side are arranged in a row in an oblique direction from the inside to the outside of the I / F chip 400. Similarly, the pads Pa of the I / O circuits 10-6, 10-7, the REn circuit 13, the BEREn circuit 14, and the I / O circuits 10-4 and 10-5 on the channel 0 (ch0) side are arranged in a row in an oblique direction from the inside to the outside of the I / F chip 400.

[0137] That is, in the fourth embodiment, the pads Pa of the BDQS circuit 12 and the DQS circuit 11 are arranged between the pads Pa of the I / O circuits 10-0 and 10-1 and the pads Pa of the I / O circuits 10-2 and 10-3. Furthermore, the pads Pa of the BREn circuit 14 and the REn circuit 13 are arranged between the pads Pa of the I / O circuits 10-4 and 10-5 and the pads Pa of the I / O circuits 10-6 and 10-7.

[0138] Next, the channel 1 (ch1) side is described. The configuration of the channel 1 (ch1) side is the same as that of the channel 0 (ch0) side, but the configuration is different. That is, the circuits on the channel 1 (ch1) side (I / O circuits 10-0 to 10-7, DQS circuits 11, BDQS circuits 12, REn circuits 13, and BREn circuits 14) are configured to be point-symmetrical with respect to the center point of the circuits on the channel 0 (ch0) side (I / O circuits 10-0 to 10-7, DQS circuits 11, BDQS circuits 12, REn circuits 13, and BREn circuits 14) and the circuits on the channel 1 (ch1) side (I / O circuits 10-0 to 10-7, DQS circuits 11, BDQS circuits 12, REn circuits 13, and BREn circuits 14).

[0139] According to the fourth embodiment, in addition to the effects of the third embodiment, the wiring of the output clock signal generated by the input buffer of the REn circuit 13 and the BREn circuit 14 can be further shortened.

[0140] 5. Fifth Implementation Method

[0141] Fig.12 1 is a diagram showing the arrangement of pads Pa of an I / F chip 400 according to the fifth embodiment. In the same figure, the arrangement of an I / F chip 400 having a two-channel configuration is shown.

[0142] The channel 0 (ch0) side is described below. The arrangement of the row of pads Pa of the control circuits 21-1 to 21-4, the I / O circuits 10-0 to 10-3, the DQS circuit 11, and the BDQS circuit 12 is similar to Fig. 9The pads Pa of the I / O circuits 10 - 4 to 10 - 7 are arranged in a row from the inside to the outside of the I / F chip 400 .

[0143] The row of pads Pa of the REn circuits 13 and BREn circuits 14 is arranged in a direction orthogonal to the row of pads Pa of the I / O circuits 10-0 to 10-3, the DQS circuit 11 and the BDQS circuit 12, and the row of pads Pa of the I / O circuits 10-4 to 10-7.

[0144] Furthermore, the data input latch DIN is arranged between the row of pads Pa of the I / O circuits 10-0 to 10-3, the DQS circuit 11, and the BDQS circuit 12, and the row of pads Pa of the I / O circuits 10-4 to 10-7.

[0145] Next, the channel 1 (ch1) side is described. The configuration of the channel 1 (ch1) side is the same as that of the channel 0 (ch0) side, but the arrangement is different. That is, the circuits on the channel 1 (ch1) side (I / O circuits 10-0 to 10-7, DQS circuits 11, BDQS circuits 12, REn circuits 13, and BREn circuits 14) are arranged to be point-symmetrical with respect to the center point of the circuits on the channel 0 (ch0) side (I / O circuits 10-0 to 10-7, DQS circuits 11, BDQS circuits 12, REn circuits 13, and BREn circuits 14) and the circuits on the channel 1 (ch1) side (I / O circuits 10-0 to 10-7, DQS circuits 11, BDQS circuits 12, REn circuits 13, and BREn circuits 14).

[0146] According to the fifth embodiment, in addition to the effects of the first embodiment, the wiring of the output clock signal generated by the input buffer of the REn circuit 13 and the BREn circuit 14 can be further shortened.

[0147] Although several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and can be omitted, replaced, and changed in various ways without departing from the scope of the invention. These embodiments or their variations are included in the scope or spirit of the invention, and are included in the invention described in the claims and their equivalents.

[0148] Explanation of symbols

[0149] 1 Memory System

[0150] 100 NAND flash memory

[0151] 200 Controller

[0152] 300 host machines

[0153] 400 I / F Chip

[0154] Pad

[0155] P pad

[0156] IR Input Receiver

[0157] RDL redistribution layer

Claims

1. A semiconductor device capable of transmitting and receiving signals with a memory device, and comprising: a controller capable of controlling the memory device; at least two pads of a first I / O circuit, associated with a first channel between the memory devices and arranged in at least one row; at least two pads of the second I / O circuit, associated with the first channel and arranged in at least one row; an input circuit for inputting data received by the pads of the first and second I / O circuits into the memory device; as well as A pad for inputting a clock signal is arranged in a row of pads of the at least two second I / O circuits, wherein the clock signal can be used to adjust the timing of the input circuit inputting data into the memory device. The wiring distances between the pads of the at least two first I / O circuits and the pads of the at least two second I / O circuits and the input circuit are uniform.

2. The semiconductor device according to claim 1, wherein The pad for inputting a clock signal is arranged between pads of the at least two second I / O circuits.

3. The semiconductor device according to claim 1, wherein The pad rows of the at least two first I / O circuits, the pad rows of the at least two second I / O circuits, and the pad rows for inputting clock signals are arranged in an oblique direction from the inside to the outside of the substrate of the semiconductor device.

4. The semiconductor device according to claim 1, further comprising: The pads of the 1st I / O circuit, the pads of the 2nd I / O circuit, and the input-output circuits are used for other channels.

5. The semiconductor device according to claim 1, further comprising: A pad is used to input a clock signal that can be used to adjust the timing of outputting data from the memory device to the controller.

6. A semiconductor device capable of transmitting and receiving signals with a memory device, and comprising: a controller capable of controlling the memory device; at least two pads of a first I / O circuit, associated with a first channel between the memory devices and arranged in at least one row; at least two pads of the second I / O circuit, associated with the first channel and arranged in at least one row; an input circuit for inputting data received by the pads of the first and second I / O circuits into the memory device; as well as pads for inputting a clock signal, arranged in a row of pads of the at least two second I / O circuits, the clock signal being capable of adjusting a timing of outputting data from the memory device to the controller, The wiring distances between the pads of the at least two first I / O circuits and the pads of the at least two second I / O circuits and the input circuit are uniform.

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