Very high rate coding method for next generation WLAN system

Abstract

A method for very high coding rates for next generation wireless local area network (WLAN) systems involves coding input data at a first coding rate to provide coded data, the coding input data at a first coding rate being based on a second coding rate, wherein the second coding rate is lower than the first coding rate and the second coding rate coding uses low density parity check codes. The method also involves wirelessly transmitting the coded data.

Description

[0001] Related references

[0002] This disclosure is a part of a non-provisional patent application that claims priority to U.S. Provisional Patent Application No. 62 / 951,189, filed on December 20, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to wireless communications, and more particularly, to an extremely high rate encoding and decoding method for a next-generation wireless local area network (WLAN) system. Background Art

[0004] Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims listed below and are not admitted to be prior art by inclusion in this section.

[0005] For extremely high-throughput (EHT) systems, such as WLAN systems compliant with the upcoming Institute of Electrical and Electronics Engineers (IEEE) 802.11be standard, 4096-quadrature amplitude modulation (4096-QAM) has been selected as one of the technologies to achieve the extremely high throughput goal. In current WLAN systems based on one or more IEEE 802.11 standards, the highest codec rate is 5 / 6. Considering that up to eight or even sixteen transmit antennas can be used in EHT WLANs based on the IEEE 802.11be standard, it is reasonable to assume that higher codec rates can be used in conjunction with transmit beamforming to achieve beamforming gain. Therefore, a solution is needed to provide higher codec rates to achieve extremely high throughput in next-generation WLAN systems. Summary of the Invention

[0006] The following summary is illustrative only and is not intended to be limiting in any way. That is, the following summary is provided to introduce the concepts, key points, benefits, and advantages of the novel and non-obvious technologies described herein. Selected implementations are further described in the detailed description below. Accordingly, the following summary is not intended to identify essential features of the claimed subject matter, nor is it intended to be used to determine the scope of the claimed subject matter.

[0007] One of the purposes of the present disclosure is to provide schemes, concepts, designs, techniques, methods and devices related to extremely high codec rates for next-generation WLAN systems. Specifically, under the various schemes proposed in accordance with the present disclosure, new codec rates higher than 5 / 6, such as 7 / 8 and 11 / 12, can be achieved. With this new higher codec rate, the overall system throughput can be improved (for example, by approximately 5% and 10%, respectively, compared to the existing codec rate). In addition, in order to reduce the complexity of implementation, by using several new parameters introduced in this article, the encoding and decoding process of the new codec rates according to the various schemes proposed in the present disclosure can be based on existing low-density parity check (LDPC) codes as defined in the IEEE 802.11n / ac / ax standards. Advantageously, the LDPC encoders and decoders used in WLANs based on the IEEE 802.11n / ac / ax standards are redesigned for these new codec rates.

[0008] In one aspect, a method may include encoding and decoding input data at a first codec rate to provide encoded data, wherein encoding and decoding the input data at the first codec rate is based on a second codec rate, wherein the second codec rate is lower than the first codec rate and the second codec rate codec uses a low-density parity-check code. The method may also include wirelessly transmitting the encoded data.

[0009] It is worth noting that although the description provided herein may be in the context of a particular radio access technology, network, and network topology (e.g., Wi-Fi), the concepts, solutions, and any variant(s) / derivatives thereof may be implemented in and with other types of radio access technologies, networks, and network topologies, such as, but not limited to, Bluetooth, ZigBee, 5th Generation (5G) / New Radio (NR), Long-Term Evolution (LTE), LTE-Advanced, LTE-Advanced Pro, Internet of Things (IoT), Industrial IoT (IIoT), and Narrowband IoT (NB-IoT). Therefore, the scope of the present disclosure is not limited to the examples described herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The following figures are provided to provide a further understanding of the present disclosure and are incorporated into and constitute a part of the present disclosure. These figures illustrate embodiments of the present disclosure and, together with the description, are used to explain the principles of the present disclosure. To clearly illustrate the concepts of the present disclosure, some elements may be shown out of scale compared to the dimensions in the actual embodiments, and these figures are not necessarily drawn to scale.

[0011] Figure 1 A diagram illustrating an example network environment in which various solutions and aspects according to the present disclosure may be implemented.

[0012] Figure 2 Diagram showing an example design according to the present disclosure.

[0013] Figure 3 Diagram showing an example design according to the present disclosure.

[0014] Figure 4 Diagram showing an example design according to the present disclosure.

[0015] Figure 5 A diagram illustrating an example scenario according to the present disclosure.

[0016] Figure 6 Diagram showing an example design according to the present disclosure.

[0017] Figure 7 Diagram showing an example design according to the present disclosure.

[0018] Figure 8 Diagram showing an example design according to the present disclosure.

[0019] Figure 9 Diagram showing an example design according to the present disclosure.

[0020] Figure 10 A diagram illustrating an example scenario according to the present disclosure.

[0021] Figure 11 A diagram illustrating an example scenario according to the present disclosure.

[0022] Figure 12 A block diagram illustrating an example communication system according to an embodiment of the present disclosure is shown.

[0023] Figure 13 A flowchart illustrating an example process according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] Detailed embodiments and implementations of the subject matter claimed in the present disclosure are described below. However, it should be understood that the disclosed embodiments and implementations are merely illustrations of the subject matter claimed, which can be embodied in various forms. However, the present disclosure can be implemented in many different forms and should not be interpreted as being limited to the exemplary embodiments and implementations set forth in the present disclosure. Rather, the provision of these exemplary embodiments and implementations makes the description of the present disclosure thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. In the following description, details of well-known features and technologies may be omitted to avoid unnecessarily obscuring the presented embodiments and implementations.

[0025] Overview

[0026] Embodiments of the present disclosure relate to various technologies, methods, schemes, and / or solutions related to extremely high codec rates in next-generation WLAN systems. According to the present disclosure, multiple possible solutions can be implemented individually or in combination. That is, while the possible solutions may be described separately below, two or more of the possible solutions may be implemented in one or more combinations.

[0027] Figure 1 An example network environment 100 is shown in which various solutions and approaches according to the present disclosure may be implemented. Figure 2-Figure 11 1 shows an example of implementation of various proposed solutions in a network environment 100 according to the present disclosure. Figures 1-11 ,The following provides a description of various proposed schemes.

[0028] Reference Figure 1 , network environment 100 may include at least one STA 110 that wirelessly communicates with a wireless access point (AP). In some cases, STA 110 and access point AP 120 are associated with a basic service set (BSS) 130 in accordance with one or more IEEE 802.11 standards (e.g., IEEE 802.11be and future standards). According to various proposed solutions described below, STA 110 and AP 120 may be configured to communicate with each other using very high codec rates.

[0029] Figure 2 An example design 200 according to the present disclosure is shown. Figure 2, design 200 introduces new LDPC parameters associated with a new codec rate R of 7 / 8. For example, for R=7 / 8, the length of the LDPC information block (i.e., the length of the bit stream of data at the input of the LDPC encoder) can be 539 bits, 1078 bits, or 1617 bits, and the length of the corresponding LDPC codeword block (i.e., the length of the coded stream of data at the output of the LDPC encoder) can be 616 bits, 1232 bits, or 1848 bits, respectively. In addition, in design 200, there may be multiple available bit numbers (N avbits ), each range corresponding to a corresponding LDPC parameter, including the number of multiple LDPC codewords (N CW ) and the length of the LDPC codeword (L LDPC ).

[0030] exist Figure 2 In part (A) of , various example sets of input lengths and output lengths corresponding to a codec rate R=7 / 8 are shown. Figure 2 In part (B), various example LDPC parameters N corresponding to the codec rate R = 7 / 8 CW and L LDPC Specifically, depending on the length of the input data (eg, in terms of the number of available bits N avbits For example), a set of corresponding N CW and L LDPC Can be used when encoding or decoding data. For example, for N avbits ≤616 range, N CW Can be 1, L LDPC Can be 1232 (if N avbits ≥Number of bits in the Physical Layer Convergence Protocol (PLCP) service data unit (PSDU) and SERVICE field (N pld )+864x(1–R)) or 616 (if not true). For 616 <N avbits Range ≤1232, N CW Can be 1, L LDPC Can be 1848 (if N avbits ≥N pld +1392x(1–R)) or 1232 (if not true). For 1232 <N avbits ≤1848 range, N CW It can be 1, L LDPC It can be 1848. For 1848 <N avbits ≤2464 range, N CW It can be 2, LLDPC Can be 1848 (if N avbits ≥N pld +2776x(1–R)) or 1232 (if not true). For 2464 <N avbits Range, N CW Can be [N pld / (1848 x R)],L LDPC It could be 1848.

[0031] Figure 3 An example design 300 according to the present disclosure is shown. Figure 3 , design 300 introduces new LDPC parameters associated with the new codec rate R = 11 / 12. For example, for R = 11 / 12, the LDPC information block length can be 539 bits, 1078 bits, or 1617 bits, and the corresponding LDPC codeword block length can be 588 bits, 1176 bits, or 1764 bits, respectively. In addition, in design 300, there may be multiple ranges of N avbits , each range corresponds to the corresponding N CW and L LDPC .

[0032] exist Figure 3 In part (A) of , various example sets of input lengths and output lengths corresponding to a codec rate R=11 / 12 are shown. Figure 3 In part (B), various exemplary LDPC parameters N corresponding to the codec rate R = 11 / 12 CW and L LDPC Specifically, depending on the length of the input data (eg, in terms of the number of available bits N avbits For example), a set of corresponding N CW and L LDPC Can be used when encoding or decoding data. For example, for N avbits ≤588 range, N CW It can be 1, and L LDPC Can be 1176 (if N avbits ≥N pld +828x(1-R)) or 588 (if not true). For 588 <N avbits Range ≤1176, N CW It can be 1, L LDPC Can be 1764 (if N avbits ≥N pld +1320x(1–R)) or 1176 (if not true). For 1176 <N avbits Range ≤1764, N CW It can be 1, L LDPCIt can be 1764. For 1764 <N avbits Range ≤2352, N CW It can be 2, L LDPC Can be 1764 (if N avbits ≥N pld +2652x(1–R)) or 1176 (if not true). For 2352 <N avbits Range, N CW Can be [N pld / (1764 x R)],L LDPC It could be 1764.

[0033] Figure 4 An example design 400 according to the present disclosure is shown. Figure 4 Design 400 introduces new codec parameters associated with the higher codec rates of the present disclosure, including the number of total shortened bits (N shrt ), the default number of total shortened bits (N shrt_default ), the total number of puncture bits (N punc ) and the default number of total puncture bits (N punc_default In design 400, there may be several combinations of parameters associated with the new codec rates 7 / 8 and 11 / 12. For example, for R=7 / 8, the length of the information block (K0) may be 539 bits, the length of the codeword block (L) may be 616 bits, the length of the parity bits (P) may be 77 bits, and N may be 11 / 12. shrt_default Can be 1, N punc_default It can be 31, and the parameters for selecting the LDPC parity check matrix can be Z=27, R=5 / 6 and n=648. Alternatively, for R=7 / 8, K0 can be 1078 bits, L can be 1232 bits, P can be 154 bits, and N can be 154 bits. shrt_default It can be 2, N punc_default It can be 62, and the parameters for selecting the LDPC parity check matrix can be Z=54, R=5 / 6 and n=1296. For R=7 / 8, K0 can be 1617 bits, L can be 1848 bits, P can be 231 bits, and N shrt_default It can be 3, N punc_default It can be 93, and the parameters for selecting the LDPC parity check matrix can be Z=81, R=5 / 6 and n=1944. For R=11 / 12, K0 can be 539 bits, L can be 588 bits, P can be 49 bits, and N shrt_default Can be 1, N punc_defaultIt can be 59, and the parameters for selecting the LDPC parity check matrix can be Z=27, R=5 / 6 and n=648. Alternatively, for R=11 / 12, K0 can be 1078 bits, L can be 1176 bits, P can be 98 bits, and N can be 1176 bits. shrt_default It can be 2, N punc_default It can be 118, and the parameters for selecting the LDPC parity check matrix can be Z=54, R=5 / 6 and n=1296. In addition, for R=11 / 12, K0 can be 1617 bits, L can be 1764 bits, P can be 147 bits, and N can be 118. shrt_default It can be 3, N punc_default It may be 177, and the parameters for selecting the LDPC parity check matrix may be Z=81, R=5 / 6, and n=1944.

[0034] Figure 5 An example scenario 500 according to the proposed solution of the present disclosure is shown. Scenario 500 illustrates an example of the entire LDPC encoding process for new codec rates (e.g., R=7 / 8 and 11 / 12) under the proposed solution of the present disclosure. It is noteworthy that, except for the fixed R=5 / 6 used in the functional block for LDPC parity bit generation, the other functional blocks in scenario 500 also apply to the new codec rates (e.g., R=7 / 8 and 11 / 12).

[0035] refer to Figure 5 , when encoding the data bits of the input data, a shortening procedure is performed on the input data to provide a bit string. The bit string may include multiple data bits of the input data, one or more default shortened bits (for example, from zero to three "0" bits), and multiple shortened bits calculated according to the shortening procedure. In addition, based on the bit string, multiple parity check bits are generated. In addition, the parity check bits are appended to the bit string to provide a concatenated bit string. In addition, one or more default shortened bits and multiple shortened bits may be discarded from the concatenated bit string to provide a shortened bit string. Then, a puncture procedure or a repetition procedure is performed on the shortened bit string.

[0036] Under the proposed scheme, the total number of shortened bits (N shrt ) can be calculated as follows: N shrt =max(0,(N CW XL LDPC x R)–Npld). In addition, the default shortening value (N shrt_default) may correspond to the first codec rate (R), the corresponding information block length (K0), the corresponding codeword block length (L), the corresponding length of the parity check bits (P) such that: (a) for R = 7 / 8, K0 = 539, L = 616 and P = 77, N shrt_default =1; (b) for R=7 / 8, K0=1078, L=1232 and P=154, N shrt_default =2; (c) for R=7 / 8, K0=1617, L=1848 and P=231, N shrt_default =3; (d) for R=11 / 12, K0=539, L=588 and P=49, N shrt_default =1; (e) for R=11 / 12, K0=1078, L=1176 and P=98, N shrt_default =2; (f) for R=11 / 12, K0=1617, L=1764 and P=147, N shrt_default =3.

[0037] Under the proposed scheme, during the execution of the puncturing procedure, specific operations are performed. For example, the total number of punctured bits is calculated. Furthermore, in response to the total number of punctured bits being determined to be greater than zero, a first number of parity bits are punctured. Alternatively, in response to the total number of punctured bits being determined to be equal to zero and the number of repeated bits per codeword being greater than a default number of punctured bits, a second number of parity bits are punctured. In this case, the first number may be equal to the default number of punctured bits plus the number of punctured bits per codeword. Alternatively, the second number may be equal to the default number of punctured bits minus the number of repeated bits per codeword.

[0038] Under the proposed scheme, the default value of the number of puncturing bits (N punc_default ) may correspond to a first codec rate (R), a corresponding information block length (K0), a corresponding codeword block length (L), and a corresponding length of parity bits (P), such that: (a) for R = 7 / 8, K0 = 539, L = 616, and P = 77, N punc_default =31; (b) for R=7 / 8, K0=1078, L=1232 and P=154, N punc_default =62; (c) for R=7 / 8, K0=1617, L=1848 and P=231, N punc_default =93; (d) for R=11 / 12, K0=539, L=588 and P=49, N punc_default =59; (e) for R=11 / 12, K0=1078, L=1176 and P=98, N punc_default=118; (f) for R=11 / 12, K0=1617, L=1764 and P=147, N punc_default =177.

[0039] Under the proposed scheme, additional operations are performed in performing the puncturing procedure. For example, based on the total number of punctured bits, the number of punctured bits per codeword (N ppcw ) is determined. In this case, when calculating the total number of punctured bits, the total number of punctured bits (N punc ) can be calculated as follows: N punc =max(0,(N CW x L LDPC )–N avbits –N shrt ).

[0040] Under the proposed scheme, specific operations are performed during the repetition process. For example, the total number of repeated bits is calculated. Furthermore, in response to the total number of punctured bits being equal to zero and the default number of punctured bits being less than the number of repeated bits per codeword, the total number of repeated bits is added to the parity bits.

[0041] Under the proposed scheme, when calculating the total number of repeated bits, the total number of repeated bits (N rep ) can be calculated as follows: N rep =max(0, N avbits –N CW XL LDPC x(1–R)–N pld ).

[0042] Under the proposed scheme, in performing the puncturing procedure, in response to the number of total puncturing bits (N punc ) is greater than or equal to zero, by discarding the last N parity bits punc_default +N ppcw bits to perform continuous puncturing on the shortened bit string.

[0043] Under the proposed scheme, in performing the puncturing procedure, in response to the number of total puncturing bits (N punc ) is greater than zero, by first discarding N of the parity bits in an interleaved manner punc_default bits and then discard the last N remaining parity bits ppcw bits to perform interleaving puncturing on the punctured bit string.

[0044] Under the proposed scheme, when N parity bits are dropped in an interleaved manner, punc_defaultWhen the first coding rate is 7 / 8, one of every three parity check bits is discarded. Alternatively, when the first coding rate is 11 / 12, one of every two parity check bits is discarded.

[0045] Figure 6 An example design 600 according to the present disclosure is shown. Figure 6 Design 600 introduces new codec parameters for other high codec rates, such as but not limited to 6 / 7, 8 / 9, 9 / 10, and 10 / 11. For example, for R=6 / 7, K0 can be 540 bits, L can be 630 bits, P can be 90 bits, and N shrt_default Can be 0, N punc_default It can be 18, and the parameters for selecting the LDPC parity check matrix can be Z=27, R=5 / 6 and n=648. Alternatively, for R=6 / 7, K0 can be 1080 bits, L can be 1260 bits, P can be 180 bits, and N can be 1260 bits. shrt_default Can be 0, N punc_default It can be 36, and the parameters for selecting the LDPC parity check matrix can be Z=54, R=5 / 6 and n=1296. In addition, for R=6 / 7, K0 can be 1620 bits, L can be 1890 bits, P can be 270 bits, and N can be 1620 bits. shrt_default Can be 0, N punc_default It can be 54, and the parameters for selecting the LDPC parity check matrix can be Z=81, R=5 / 6 and n=1944. For R=8 / 9, K0 can be 536 bits, L can be 603 bits, P can be 67 bits, and N shrt_default It can be 4, N punc_default It can be 41, and the parameters for selecting the LDPC parity check matrix can be Z=27, R=5 / 6 and n=648. Alternatively, for R=8 / 9, K0 can be 1080 bits, L can be 1215 bits, P can be 135 bits, and N can be 135 bits. shrt_default Can be 0, N punc_default It can be 81, and the parameters for selecting the LDPC parity check matrix can be Z=54, R=5 / 6 and n=1296. Alternatively, for R=8 / 9, K0 can be 1616 bits, L can be 1818 bits, P can be 202 bits, and N can be 1616 bits. shrt_default It can be 4, N punc_default It can be 122, and the parameters for selecting the LDPC parity check matrix can be Z=81, R=5 / 6, n=1944. For R=9 / 10, K0 can be 540 bits, L can be 600 bits, P can be 60 bits, and N shrt_default Can be 0, N punc_defaultIt can be 48, and the parameters for selecting the LDPC parity check matrix can be Z=27, R=5 / 6 and n=648. Alternatively, for R=9 / 10, K0 can be 1080 bits, L can be 1200 bits, P can be 120 bits, and N can be 120 bits. shrt_default Can be 0, N punc_default It can be 96, and the parameters for selecting the LDPC parity check matrix can be Z=54, R=5 / 6 and n=1296. In addition, for R=9 / 10, K0 can be 1620 bits, L can be 1800 bits, P can be 180 bits, and N can be 1620 bits. shrt_default Can be 0, N punc_default It can be 144, and the parameters for selecting the LDPC parity check matrix can be Z=81, R=5 / 6 and n=1944. For R=10 / 11, K0 can be 540 bits, L can be 594 bits, P can be 54 bits, and N shrt_default Can be 0, N punc_default It can be 54, and the parameters for selecting the LDPC parity check matrix can be Z=27, R=5 / 6 and n=648. Alternatively, for R=10 / 11, K0 can be 1080 bits, L can be 1188 bits, P can be 108 bits, and N can be 1188 bits. shrt_default Can be 0, N punc_default It can be 108, and the parameters for selecting the LDPC parity check matrix can be Z=54, R=5 / 6, n=1296. For R=10 / 11, K0 can be 1620 bits, L can be 1782 bits, P can be 162 bits, and N shrt_default Can be 0, N punc_default It may be 162, and the parameters for selecting the LDPC parity check matrix may be Z=81, R=5 / 6, and n=1944.

[0046] Under the proposed parity bit puncturing scheme according to the present disclosure, an option of continuous puncturing or another option of interleaved puncturing is utilized. By continuous puncturing, the last N punc_default Add the number of punctured bits per codeword (N ppcw )(Herein, it is represented by N punc_default +N ppcw ), the parity bits can be discarded: P n–k–Nppcw–Npunc_default–1 ,…P n–k-1 Under the proposed scheme, the option of continuous puncturing can be applied to the total number of punctured bits N punc >0 and N punc =0.

[0047] By staggered puncture, the first N punc_defaultThe parity bits can be punctured in an interleaved manner as follows. punc_default Bits can be discarded such as: P 0：3：3 *N punc_default–1 That is, in the case of R=7 / 8, one parity bit out of every three parity bits is discarded. For the remaining parity bits, the last N ppcw Can be discarded. For R = 11 / 12, N punc_default Bits can be discarded such as: P 0：2：2 *(n–k–Npunc_default)P2*(n–k–Npunc_default)+1:n–k-1. That is, in the case of R=11 / 12, one parity bit is discarded for every two parity bits. For the remaining parity bits, the last N ppcw bits can be discarded. Under the proposed scheme, for N punc >0, the option of staggered puncture can be applied.

[0048] Figure 7 An example design 700 according to the present disclosure is shown. Figure 7 , Design 700 introduces a new modulation and coding scheme (MCS) index for the proposed new codec rate with 4096-QAM. For example, Figure 7 The new MCS shown in [1] can be appended to the existing high-efficiency (HE)-MCS in the IEEE 802.11ax standard for different resource units (RUs) and RU combinations. Therefore, the signaling MCS defined in the IEEE 802.11 standard can be reused along with the new MCS index to signal the new codec rates proposed here.

[0049] Figure 8 An example design 800 according to the present disclosure is shown. Figure 8 , Design 800 introduces a new MCS index for the proposed new codec rate with 4096-QAM. For example, Figure 8 The new MCS shown in can be added to the existing HE-MCS and EHT-MCS in the IEEE 802.11ax / be standards for different RUs and RU combinations. Therefore, the signaling MCS defined in the IEEE 802.11 standard can be reused together with the new MCS index to send the new codec rate proposed here. Under the proposed scheme according to the present disclosure, Figure 8 As shown, one reserved bit is used together with the existing MCS bits to indicate the newly defined MCS.

[0050] Figure 9 An example design 900 according to the present disclosure is shown. Under the proposed scheme, support for 4096-QAM in EHT WLAN is optional. Under the proposed scheme, indications of support for 4096-QAM and different codec rates may be included in the capability field and may be exchanged between STAs (including APs and non-AP STAs). For example, Figure 9 As shown, two bits are used as an indication of a new codec rate with 4096-QAM or a new MCS.

[0051] Figure 10 An example scenario 1000 according to the present disclosure is shown. For illustrative purposes and without limiting the scope of the present disclosure, scenario 1000 illustrates the proposed sensitivity signal-to-noise ratio (SNR) requirements for higher codec rates (eg, R=7 / 8 and 11 / 12). Figure 11 An example scenario 1100 according to the present disclosure is shown. For illustrative purposes and without limiting the scope of the present disclosure, scenario 1100 shows sensitivity SNR requirements for higher codec rates (eg, R=7 / 8 and 11 / 12) proposed herein.

[0052] Illustrative Implementation

[0053] Figure 12 An example system 1200 is shown having at least an example device 1210 and an example device 1220 according to an embodiment of the present disclosure. Each of device 1210 and device 1220 can perform various functions to implement the schemes, techniques, processes, and methods described herein related to extremely high codec rates for next-generation WLAN systems, including the various schemes described above regarding various proposed designs, concepts, schemes, systems, and methods, as well as the various schemes described below. For example, device 1210 can be implemented in STA 110, while device 1220 can be implemented in AP 120, or vice versa.

[0054] Each of apparatus 1210 and apparatus 1220 may be part of an electronic device, such as a STA or AP, such as a portable or mobile device, a wearable device, a wireless communication device, or a computing device. When implemented in a STA, each of apparatus 1210 and apparatus 1220 may be implemented in a smartphone, a smartwatch, a personal digital assistant, a digital camera, or a computing device such as a tablet, laptop, or notebook computer. Each of apparatus 1210 and apparatus 1220 may also be part of a machine-type device, such as an IoT device, such as a stationary or fixed device, a household appliance, a wired communication device, or a computing device. For example, each of apparatus 1210 and apparatus 1220 may be implemented in a smart thermostat, a smart refrigerator, a smart door lock, a wireless speaker, or a home control center. When implemented in or as a network device, apparatus 1210 and / or apparatus 1220 may be implemented in a network node, such as an AP in a WLAN.

[0055] In some embodiments, each of the apparatus 1210 and the apparatus 1220 may be implemented in the form of one or more integrated circuit (IC) chips, such as, but not limited to, one or more single-core processors, one or more multi-core processors, one or more reduced-instruction set computing (RISC) processors, or one or more complex instruction set computing (CISC) processors. In the various schemes described above, each of the apparatus 1210 and the apparatus 1220 may be implemented as a STA or an AP or as a STA or an AP. Each of the apparatus 1210 and the apparatus 1220 may include Figure 12 At least some of the components shown in the figure, such as processor 1212 and processor 1222. Each of device 1210 and device 1220 may further include one or more other components not related to the proposed solution of the present disclosure (e.g., an internal power supply, a display device and / or a user interface device), and therefore, for the sake of simplicity and brevity, these components of device 1210 and device 1220 are not shown in the figure. Figure 12 It is not shown in the figure and is not described below.

[0056] In one aspect, each of the processors 1212 and 1222 may be implemented in the form of one or more single-core processors, one or more multi-core processors, one or more RISC processors, or one or more CISC processors. That is, even though the singular term "processor" is used herein to refer to the processors 1212 and 1222, according to the present disclosure, each of the processors 1212 and 1222 may include multiple processors in some embodiments and a single processor in other embodiments. On the other hand, each of the processors 1212 and 1222 may be implemented in the form of hardware (and optionally, firmware) having electronic components, including, for example, but not limited to, one or more transistors, one or more diodes, one or more capacitors, one or more resistors, one or more inductors, one or more memristors, and / or one or more varactors, which are configured and arranged to achieve specific purposes according to the present disclosure. In other words, in at least some embodiments, each of the processors 1212 and 1222 is a dedicated machine specifically designed, arranged, and configured to perform specific tasks, including tasks related to extremely high codec rates for next-generation WLAN systems according to various embodiments of the present disclosure.

[0057] In some embodiments, the device 1210 may further include a transceiver 1216 coupled to the processor 1212. The transceiver 1216 may include a transmitter capable of wireless transmission and a receiver capable of wireless reception of data. In some embodiments, the device 1220 may further include a transceiver 1226 coupled to the processor 1222. The transceiver 1226 may include a transmitter capable of wireless transmission and a receiver capable of wireless reception of data. It is worth noting that although the transceiver 1216 and the transceiver 1226 are illustrated as being external to and separate from the processor 1212 and the processor 1222, respectively, in some embodiments, the transceiver 1216 may be an integral part of the processor 1212 as a system on chip (SoC). The transceiver 1226 and / or the transceiver 1226 may be an integral part of the processor 1222 as an SoC.

[0058] In some embodiments, the device 1210 may further include a memory 1214, which is coupled to the processor 1212 and can be accessed by the processor 1212 and stores data therein. In some embodiments, the device 1220 may further include a memory 1224, which is coupled to the processor 1222 and can be accessed by the processor 1222 and stores data therein. Each of the memory 1214 and the memory 1224 may include a random-access memory (RAM), such as dynamic random-access memory (DRAM), static random-access memory (SRAM), thyristor RAM (T-RAM), and / or zero-capacitor RAM (Z-RAM). Alternatively or additionally, each of memory 1214 and memory 1224 may include a type of read-only memory (ROM), such as mask ROM, programmable ROM (PROM), erasable programmable ROM (EPROM), and / or electrically erasable programmable ROM (EEPROM). Alternatively or additionally, each of memory 1314 and memory 1324 may include a type of non-volatile random-access memory (NVRAM), such as flash memory, solid-state memory, ferroelectric RAM (FeRAM), magnetoresistive RAM (MRAM), and / or phase change memory.

[0059] Each of device 1210 and device 1220 may be a communication entity capable of communicating with each other using various proposed schemes according to the present disclosure. For illustrative purposes and not limitation, the following provides a description of the capabilities of device 1210 as STA 110 and device 1220 as AP 120. It is worth noting that although a detailed description of the functions, features, and / or technical characteristics of device 1210 is provided below, it can also be applied to device 1220, although a detailed description thereof is not provided for the sake of brevity. It is also worth noting that although the example implementations described below are provided in the context of a WLAN, they can also be implemented in other types of networks.

[0060] In a proposed scheme related to extremely high codec rates for next-generation WLAN systems according to the present disclosure, in a network environment 100, a device 1210 is implemented in or as a STA 110, and a device 1220 is implemented in or as an AP 120. A processor 1212 of the device 1210 encodes and decodes input data at a first codec rate to provide encoded data, wherein the encoding and decoding of the input data at the first codec rate is based on a second codec rate that is lower than the first codec rate. Furthermore, the processor 1212 may wirelessly transmit the encoded data via a transceiver 1216 (e.g., to the device 1220 implemented as the AP 120).

[0061] In some embodiments, when encoding and decoding input data at a first codec rate, wherein the second codec rate uses an LDPC code defined in one of the IEEE 802.11n / ac / ax standards, the processor 1212 may use 4096-QAM to encode and decode the input data at a rate higher than 5 / 6. Furthermore, when wirelessly transmitting the encoded and decoded data, the processor 1212 may utilize transmit beamforming to wirelessly transmit the encoded and decoded data.

[0062] In some embodiments, the second codec rate may be 5 / 6, and the first codec rate may be a rate higher than 5 / 6. For example, the first codec rate may be 6 / 7, 7 / 8, 8 / 9, 9 / 10, 10 / 11, or 11 / 12.

[0063] In some embodiments, in encoding and decoding input data, the processor 1212 may perform specific operations. For example, the processor 1212 may perform a shortening procedure on the input data to provide a bit string, which includes multiple data bits of the input data, one or more default shortening bits, and multiple shortening bits calculated according to the shortening procedure. In addition, the processor 1212 may generate multiple parity bits based on the bit string. In addition, the processor 1212 may append parity bits to the bit string to provide a concatenated bit string. In addition, the processor 1212 may discard one or more default shortening bits and multiple shortened bits from the concatenated bit string to provide a shortened bit string. The processor 1212 may then: (a) perform a puncture procedure on the shortened bit string; or (b) perform a repetition procedure on the shortened bit string.

[0064] In some embodiments, when executing the shortening procedure, the processor 1212 may calculate the total number of shortened bits (N) in the plurality of shortened bits as follows: shrt ):N shrt =max(0,(N CW XL LDPCx R)–N pld ). Here, N CW It can represent the number of LDPC code words, L LDPC It can represent the length of the LDPC codeword, R can represent the first encoding and decoding rate, that is, 7 / 8 or 11 / 12, N pld It can indicate the number of bits in the PSDU and SERVICE fields.

[0065] In some embodiments, the value of the number of default shortening bits (N shrt_default ) may correspond to a first codec rate (R), a corresponding information block length (K0), a corresponding codeword block length (L), and a corresponding length of parity bits (P), such that: (a) for R = 7 / 8, K0 = 539, L = 616, and P = 77, N shrt_default =1; (b) for R=7 / 8, K0=1078, L=1232 and P=154, N shrt_default =2; (c) for R=7 / 8, K0=1617, L=1848 and P=231, N shrt_default =3; (d) for R=11 / 12, K0=539, L=588 and P=49, N shrt_default =1; (e) for R=11 / 12, K0=1078, L=1176 and P=98, N shrt_default =2; (f) for R=11 / 12, K0=1617, L=1764 and P=147, N shrt_default =3.

[0066] In some embodiments, when executing the puncturing procedure, processor 1212 may perform specific operations. For example, processor 1212 may calculate the total number of punctured bits. Furthermore, processor 1212 may: (a) puncture a first number of parity bits in response to the total number of punctured bits being determined to be greater than zero; or (b) puncture a second number of parity bits in response to the total number of punctured bits being determined to be equal to zero and the number of repeated bits per codeword being greater than a default number of punctured bits. In this case, the first number may be equal to the default number of punctured bits plus the number of punctured bits per codeword. Alternatively, the second number may be equal to the default number of punctured bits minus the number of repeated bits per codeword.

[0067] In some embodiments, the value of the default number of puncturing bits (N punc_default ) may correspond to a first codec rate (R), a corresponding information block length (K0), a corresponding codeword block length (L), and a corresponding length of parity bits (P), such that: (a) for R = 7 / 8, K0 = 539, L = 616, and P = 77, N punc_default=31; (b) for R=7 / 8, K0=1078, L=1232 and P=154, N punc_default =62; (c) for R=7 / 8, K0=1617, L=1848 and P=231, N punc_default =93; (d) for R=11 / 12, K0=539, L=588 and P=49, N punc_default =59; (e) for R=11 / 12, K0=1078, L=1176 and P=98, N punc_default =118; (f) for R=11 / 12, K0=1617, L=1764 and P=147, N punc_default =177.

[0068] In some implementations, the processor 1212 may perform additional operations in executing the puncturing procedure. For example, the processor 1212 may determine the number of punctured bits per codeword (N) based on the total number of punctured bits. ppcw In this case, when calculating the total number of punctured bits, the processor 1212 may calculate the total number of punctured bits (N) as follows: punc ):N punc =max(0,(N CW ×L LDPC )-N avbits -N shrt ). Here, N CW It can represent the number of LDPC code words, L LDPC Can represent the length of the LDPC codeword, N avbits can represent the number of available bits, and N shrt The total number of shortened bits can be expressed.

[0069] In some embodiments, during the execution of the repetition procedure, the processor 1212 may perform specific operations. For example, the processor 1212 may calculate the total number of repeated bits. In addition, in response to the total number of punctured bits being equal to zero and the number of default punctured bits being less than the number of repeated bits per codeword, the processor 1212 may add the total number of repeated bits to the parity bits.

[0070] In some embodiments, when calculating the total number of repetition bits, the processor 1212 may calculate the total number of repetition bits (N) as follows: rep ):N rep =max(0, N avbits –N CW XL LDPC x(1–R)–N pld ). Here, N avbit It can represent the number of available bits, N CWIt can represent the number of LDPC code words, L LDPC It can represent the length of the LDPC codeword, R can represent the first encoding and decoding rate of 7 / 8 or 11 / 12, N pld It can indicate the number of bits in the PSDU and SERVICE fields.

[0071] In some implementations, in performing the puncturing procedure, in response to the total number of punctured bits (N punc ) is greater than or equal to zero, the processor 1212 can discard the last N parity bits punc_default +N ppcw bits to perform continuous puncturing on the shortened bit string. punc_default It can represent the number of default puncture bits, and N ppcw It can represent the number of punctured bits per codeword.

[0072] In some embodiments, in performing the puncturing procedure, in response to the number of total puncturing bits (N punc ) is greater than zero, by first discarding N of the parity bits in an interleaved manner punc_default bits and then discard the last N remaining parity bits ppcw bits, the processor 1212 can perform interleaving puncturing on the shortened bit string. punc_default It can represent the number of default puncture bits, and N ppcw It can represent the number of punctured bits per codeword.

[0073] In some embodiments, the N parity bits are dropped in an interleaved manner. punc_default When the parity bits are equal, the processor 1212 may drop one bit for every three parity bits in response to the first codec rate (7 / 8). Alternatively, the processor 1212 may drop one bit for every two parity bits in response to the first codec rate (11 / 12).

[0074] In some implementations, when encoding and decoding the input data at the first codec rate, the processor 1212 may use 4096-QAM to encode and decode the input data at a codec rate (7 / 8) with an MCS index of 14.

[0075] In some embodiments, when encoding and decoding the input data at the first codec rate, the processor 1212 may use 4096-QAM to encode and decode the input data at a codec rate (11 / 12) with an MCS index of 14 or 15.

[0076] In some embodiments, when encoding and decoding input data at a first codec rate, based on the existing MCS bits and the bits having a predetermined value (e.g., Figure 8 The processor 1212 may use 4096-QAM to encode and decode the input data at the codec rate (7 / 8) with an MCS index of 16. In addition, the corresponding EHT-MCS bits may include 0000.

[0077] In some embodiments, when encoding and decoding input data at a first codec rate, based on the existing MCS bits and the bits having a predetermined value (e.g., Figure 8 The processor 1212 may use 4096-QAM to encode and decode the input data at the codec rate (11 / 12) with an MCS index of 17. In addition, the corresponding EHT-MCS bits may include 0001.

[0078] In some embodiments, the processor 1212 may further signal a station in the WLAN (e.g., the device 1220 serving as the AP 120) via the transceiver 1216 to indicate support for the first codec rate by indicating the physical layer (PHY) capability in the capability field. Figure 9 As shown, the processor 1212 may indicate support for codec rates of 7 / 8 (or 11 / 12) by indicating "11" in the capability field.

[0079] Illustrative Process

[0080] Figure 13 An example process 1300 is shown according to an embodiment of the present disclosure. Process 1300 may represent one aspect of implementing the various proposed designs, concepts, schemes, systems, and methods described above. More specifically, process 1300 may represent one aspect of the proposed concepts and schemes related to very high codec rates in next generation WLAN systems according to the present disclosure. Process 1300 may include one or more operations, actions, or functions shown in one or more of blocks 1310 and 1320. Although shown as discrete blocks, the various blocks of process 1300 may be divided into additional blocks, combined into fewer blocks, or eliminated, depending on the desired implementation. In addition, the blocks / sub-blocks of process 1300 may be arranged as follows: Figure 13110 or an AP 120. The process 1300 may be performed in the order shown or in other orders. Furthermore, one or more blocks / sub-blocks of process 1300 may be performed repeatedly or iteratively. Process 1300 may be implemented by or in apparatus 1210 and apparatus 1220, or any variation thereof. For illustrative purposes only and without limiting the scope, process 1300 is described below in the context of apparatus 1210 implemented in or as STA 110 and apparatus 1220 implemented in or as AP 120 in a wireless network environment 100 according to one or more IEEE 802.11 standards (e.g., a WLAN). Process 1300 may begin at block 1310.

[0081] At 1310, processing 1300 may involve a processor 1212 including device 1210 encoding and decoding input data at a first codec rate to provide encoded data, wherein encoding and decoding the input data at the first codec rate is based on a second codec rate, the second codec rate is lower than the first codec rate, and the second codec rate encoding uses a low-density parity-check code, and processing 1300 may proceed from 1310 to 1320.

[0082] At 1320 , process 1300 may involve processor 1212 wirelessly transmitting the encoded data via transceiver 1216 (eg, to device 1220 acting as AP 120 ).

[0083] In some embodiments, when encoding and decoding input data at a first codec rate, process 1300 may include processor 1212 encoding and decoding the input data at a rate greater than 5 / 6 using 4096-QAM, wherein the second codec rate codec uses an LDPC code defined in one of the IEEE 802.11n / ac / ax standards. Furthermore, when wirelessly transmitting the encoded and decoded data, process 1300 may include processor 1212 utilizing transmit beamforming to wirelessly transmit the encoded and decoded data.

[0084] In some embodiments, the second codec rate may be 5 / 6, and the first codec rate may be a rate higher than 5 / 6. For example, the first codec rate may be 6 / 7, 7 / 8, 8 / 9, 9 / 10, 10 / 11, or 11 / 12.

[0085] In some embodiments, when encoding or decoding input data, process 1300 may involve processor 1212 performing specific operations. For example, process 1300 may involve processor 1212 performing a shortening process on the input data to provide a bit string, the bit string comprising a plurality of data bits of the input data, one or more default shortening bits, and a plurality of shortening bits calculated from the shortening process. Additionally, process 1300 may involve processor 1212 generating a plurality of parity bits based on the bit string. Furthermore, process 1300 may involve processor 1212 appending the parity bits to the bit string to provide a concatenated bit string. Furthermore, process 1300 may involve processor 1212 discarding one or more default shortening bits and a plurality of shortened bits from the concatenated bit string to provide a shortened bit string. Process 1300 may then involve processor 1212: (a) performing a puncturing process on the shortened bit string; or (b) performing a repetition process on the shortened bit string.

[0086] In some embodiments, in performing the shortening procedure, the process 1300 involves the processor 1212 calculating the total number of shortened bits (N) in the plurality of shortened bits as follows: shrt ):N shrt =max(0,(N CW XL LDPC x R)–N pld ). Here, N CW It can represent the number of LDPC code words, L LDPC It can represent the length of the LDPC codeword, R can represent the first encoding and decoding rate, that is, 7 / 8 or 11 / 12, N pld It can indicate the number of bits in the PSDU and SERVICE fields.

[0087] In some embodiments, the value of the number of default shortening bits (N shrt_default ) may correspond to a first codec rate (R), a corresponding information block length (K0), a corresponding codeword block length (L), and a corresponding length of parity bits (P), such that: (a) for R = 7 / 8, K0 = 539, L = 616, and P = 77, N shrt_default =1; (b) for R=7 / 8, K0=1078, L=1232 and P=154, N shrt_default =2; (c) for R=7 / 8, K0=1617, L=1848 and P=231, N shrt_default =3; (d) for R=11 / 12, K0=539, L=588 and P=49, N shrt_default =1; (e) for R=11 / 12, K0=1078, L=1176 and P=98, N shrt_default=2; (f) for R=11 / 12, K0=1617, L=1764 and P=147, N shrt_default =3.

[0088] In some embodiments, during execution of the puncturing procedure, process 1300 may involve processor 1212 performing specific operations. For example, process 1300 may involve processor 1212 calculating the total number of punctured bits. Furthermore, process 1300 may involve processor 1212: (a) puncturing a first number of parity bits in response to the total number of punctured bits being determined to be greater than zero; or (b) puncturing a second number of parity bits in response to the total number of punctured bits being determined to be zero and the number of repeated bits per codeword being greater than a default number of punctured bits. In this case, the first number may be equal to the default number of punctured bits plus the number of punctured bits per codeword. Alternatively, the second number may be equal to the default number of punctured bits minus the number of repeated bits per codeword.

[0089] In some embodiments, the value of the default number of puncturing bits (N punc_default ) may correspond to a first codec rate (R), a corresponding information block length (K0), a corresponding codeword block length (L), and a corresponding length of parity bits (P), such that: (a) for R = 7 / 8, K0 = 539, L = 616, and P = 77, N punc_default =31; (b) for R=7 / 8, K0=1078, L=1232 and P=154, N punc_default =62; (c) for R=7 / 8, K0=1617, L=1848 and P=231, N punc_default =93; (d) for R=11 / 12, K0=539, L=588 and P=49, N punc_default =59; (e) for R=11 / 12, K0=1078, L=1176 and P=98, N punc_default =118; (f) for R=11 / 12, K0=1617, L=1764 and P=147, N punc_default =177.

[0090] In some implementations, process 1300 may involve processor 1212 performing additional operations in performing the puncturing procedure. For example, process 1300 may involve processor 1212 determining the number of punctured bits per codeword (N) based on the total number of punctured bits. ppcw In this case, when calculating the total number of punctured bits, process 1300 may involve processor 1212 calculating the total number of punctured bits (N) as follows: punc ):N punc =max(0,(N CW×L LDPC )-N avbits -N shrt ). Here, N CW It can represent the number of LDPC code words, L LDPC Can represent the length of the LDPC codeword, N avbits can represent the number of available bits, and N shrt The total number of shortened bits can be expressed.

[0091] In some embodiments, during the execution of the repetition procedure, process 1300 may involve processor 1212 performing specific operations. For example, process 1300 may involve processor 1212 calculating the total number of repetition bits. Additionally, in response to the total number of punctured bits being equal to zero and the default number of punctured bits being less than the number of repetition bits per codeword, process 1300 may involve processor 1212 adding the total repetition bits to the parity bits.

[0092] In some embodiments, when calculating the total number of repetition bits, process 1300 may involve processor 1212 calculating the total number of repetition bits (N) as follows: rep ):N rep =max(0, N avbits –N CW XL LDPC x(1–R)–N pld ). Here, N avbit It can represent the number of available bits, N CW It can represent the number of LDPC code words, L LDPC It can represent the length of the LDPC codeword, R can represent the first encoding and decoding rate of 7 / 8 or 11 / 12, N pld It can indicate the number of bits in the PSDU and SERVICE fields.

[0093] In some implementations, in performing the puncturing procedure, in response to the number of total puncturing bits (N punc ) is greater than or equal to zero, the process 1300 may involve the processor 1212 discarding the last N parity bits punc_default +N ppcw bits to perform continuous puncturing on the shortened bit string. punc_default It can represent the number of default puncture bits, and N ppcw It can represent the number of punctured bits per codeword.

[0094] In some embodiments, in performing the puncturing procedure, in response to the number of total puncturing bits (N punc ) is greater than zero, by first discarding N of the parity bits in an interleaved manner punc_defaultbits and then discard the last N remaining parity bits ppcw bits, the process 1300 may involve the processor 1212 performing interleaving puncture on the shortened bit string. punc_default It can represent the number of default puncture bits, and N ppcw It can represent the number of punctured bits per codeword.

[0095] In some embodiments, the N parity bits are dropped in an interleaved manner. punc_default When the parity bits are equal, the process 1300 may involve the processor 1212 dropping one bit for every three parity bits in response to the first codec rate (7 / 8). Alternatively, the process 1300 may involve the processor 1212 dropping one bit for every two parity bits in response to the first codec rate (11 / 12).

[0096] In some embodiments, when encoding and decoding the input data at the first codec rate, the process 1300 may involve the processor 1212 encoding and decoding the input data using 4096-QAM at a codec rate (7 / 8) with an MCS index of 14.

[0097] In some embodiments, when encoding and decoding the input data at the first codec rate, the process 1300 may involve the processor 1212 encoding and decoding the input data using 4096-QAM at a codec rate (11 / 12) with an MCS index of 14 or 15.

[0098] In some embodiments, when encoding and decoding input data at a first codec rate, based on the existing MCS bits and the bits having a predetermined value (e.g., Figure 8 The process 1300 may involve the processor 1212 encoding and decoding the input data using 4096-QAM at the codec rate (7 / 8) with an MCS index of 16. In addition, the corresponding EHT-MCS bits may include 0000.

[0099] In some embodiments, when encoding and decoding input data at a first codec rate, based on the existing MCS bits and the bits having a predetermined value (e.g., Figure 8 The process 1300 may involve the processor 1212 encoding and decoding the input data using 4096-QAM at the codec rate (11 / 12) with an MCS index of 17. In addition, the corresponding EHT-MCS bits may include 0001.

[0100] In some embodiments, process 1300 may involve processor 1212 signaling, via transceiver 1216, to a station in the WLAN (e.g., device 1220 acting as AP 120) to indicate support for a first codec rate by indicating physical layer (PHY) capabilities in a capability field. For example, Figure 9 As shown, process 1300 may involve processor 1212 indicating support for codec rates of 7 / 8 (or 11 / 12) by indicating "11" in the capability field.

[0101] Additional Notes

[0102] The subject matter described herein sometimes represents different components that are contained in or connected to other different components. It will be understood that the described structures are merely examples and that many other structures can actually be implemented to achieve the same function. Conceptually, any arrangement of components that achieve the same function is actually "associated" to achieve the desired function. Therefore, regardless of the structure or intermediate components, any two components combined to achieve a specific function are considered to be "interrelated" to achieve the desired function. Similarly, any two associated components are considered to be "operably connected" or "operably coupled" to each other to achieve the specific function. Any two components that can be associated with each other are also considered to be "operably coupled" to each other to achieve the specific function. Any two components that can be associated with each other are also considered to be "operably coupled" to each other to achieve the specific function. Specific examples of operable connections include, but are not limited to, components that can be physically paired and / or physically interact with each other, and / or components that can interact wirelessly and / or interact wirelessly, and / or components that can interact logically and / or interact logically.

[0103] Furthermore, with respect to the use of substantially any plural and / or singular terms, those skilled in the art can translate from the plural to the singular and / or from the singular to the plural as appropriate to the context and / or application. For clarity, the various singular / plural permutations are expressly set forth herein.

[0104] Furthermore, those skilled in the art will appreciate that, generally, terminology used in this disclosure, particularly in the claims, and in the subject matter of the claims, is often used as "open" terms. For example, "including" should be interpreted as "including but not limited to," "having" should be interpreted as "at least having," and "comprising" should be interpreted as "including but not limited to," etc. Those skilled in the art will further appreciate that if a specific number of claim elements is intended to be introduced, this will be explicitly indicated within the claim, and in the absence of such reference, it will not be displayed. For example, to aid understanding, the following claims may include the phrases "at least one" and "one or more" to introduce claim elements. However, the use of these phrases should not be construed to imply that the use of "a" or "an" to introduce claim elements limits any particular claim. Even when the same claim includes the introductory phrases "one or more" or "at least one," the indefinite article, such as "a" or "an," should be interpreted to mean at least one or more, as is the case with the explicit use of the term to introduce the claim. Furthermore, even when an introductory clause explicitly refers to a specific number, those skilled in the art will recognize that such reference should be interpreted to refer to the referenced number. For example, "two references" without other modifications means at least two references, or two or more references. In addition, when expressions similar to "at least one of A, B, and C" are used, they are generally expressed so that those skilled in the art can understand the expression. For example, "a system includes at least one of A, B, and C" will include but is not limited to a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B, and C, etc. Those skilled in the art will further understand that any separated words and / or phrases represented by two or more alternative terms, whether in the specification, claims, or drawings, should be understood to include the possibility of one, one, or both of these terms. For example, "A or B" should be understood as the possibility of "A", or "B", or "A and B".

[0105] As can be seen from the foregoing, various embodiments have been described for illustrative purposes, and various modifications may be made without departing from the scope and spirit of the present disclosure. Therefore, the various embodiments disclosed herein are not intended to be limiting, with the true scope being indicated by the claims.

Claims

1. A very high rate encoding and decoding method for a next generation wireless local area network system, comprising: encoding and decoding input data at a first codec rate to provide encoded data, wherein encoding and decoding the input data at the first codec rate is based on a second codec rate, the second codec rate is lower than the first codec rate, and the second codec rate codec uses a low-density parity-check code; as well as wirelessly transmitting the encoded and decoded data, The step of encoding and decoding the input data includes: performing a shortening procedure on the input data to provide a bit string, the bit string comprising a plurality of data bits of the input data, one or more default shortening bits, and a plurality of shortening bits calculated from the shortening procedure; generating a plurality of parity check bits based on the bit string; appending the plurality of parity bits to the bit string to provide a concatenated bit string; discarding the one or more default shortening bits and the plurality of shortening bits from the concatenated bit string to provide a shortened bit string; and Either: performing a puncturing procedure on the shortened bit string; or performing a repetitive procedure on said shortened bit string, The step of performing the shortening procedure includes calculating the total number N of shortened bits in the plurality of shortened bits as follows shrt : N shrt =max(0,(N CW x L LDPC x R)–N pld ), in: N CW represents the number of codewords of the low-density parity-check code, L LDPC represents the length of the low-density parity-check codeword, R indicates that the first codec rate is 7 / 8 or 11 / 12, and N pld Indicates the number of bits in the physical layer convergence protocol service data unit and the SERVICE field.

2. The extremely high rate encoding and decoding method for the next generation wireless local area network system according to claim 1, wherein: The step of encoding and decoding the input data at a first codec rate to provide encoded data, wherein the encoding and decoding of the input data at the first codec rate is based on a second codec rate, the second codec rate is lower than the first codec rate, and the second codec rate encoding and decoding uses a low-density parity-check code, includes: using the low-density parity-check code to encode and decode the input data at a rate higher than 5 / 6, the low-density parity-check code is defined in one of the Institute of Electrical and Electronics Engineers 802.11n / ac / ax standards and uses 4096 orthogonal amplitude modulation, wherein wirelessly transmitting the encoded data includes wirelessly transmitting the encoded data through transmit beamforming.

3. The extremely high rate encoding and decoding method for the next generation wireless local area network system according to claim 1, wherein: The second codec rate is 5 / 6, and wherein the first codec rate comprises a rate higher than 5 / 6.

4. The extremely high rate encoding and decoding method for the next generation wireless local area network system according to claim 3, wherein: The first codec rate is 6 / 7, 7 / 8, 8 / 9, 9 / 10, 10 / 11 or 11 / 12.

5. The extremely high rate encoding and decoding method for the next generation wireless local area network system according to claim 1, wherein: The value N of the default number of shortening bits shrt_default Corresponding to the first coding rate R, the corresponding information block length K0, the corresponding codeword block length L, and the corresponding length P of the plurality of parity check bits are such that: For R=7 / 8, K0=539, L=616 and P=77, N shrt_default =1; For R=7 / 8, K0=1078, L=1232 and P=154, N shrt_default =2; For R=7 / 8, K0=1617, L=1848 and P=231, N shrt_default =3; For R=11 / 12, K0=539, L=588 and P=49, N shrt_default =1; For R=11 / 12, K0=1078, L=1176 and P=98, N shrt_default =2; and For R=11 / 12, K0=1617, L=1764 and P=147, N shrt_default =3.

6. The extremely high rate encoding and decoding method for the next generation wireless local area network system according to claim 1, wherein: The steps of performing the puncture procedure include: Calculating the total number of punctured bits; and Either: In response to a total number of punctured bits being determined to be greater than zero, puncturing a first number of the plurality of parity bits; or In response to determining that the total number of punctured bits is equal to zero and the number of repeated bits per codeword is greater than a default number of punctured bits, puncturing a second number of the plurality of parity bits, wherein the first number is equal to the default number of punctured bits plus the number of punctured bits per codeword, and The second number is equal to the default puncturing bit number minus the repeated bit number of each codeword.

7. The extremely high rate encoding and decoding method for the next generation wireless local area network system according to claim 6, wherein: The value N of the default number of puncture bits punc_default Corresponding to the first coding rate R, the corresponding information block length K0, the corresponding codeword block length L, and the corresponding length P of the plurality of parity check bits are such that: For R=7 / 8, K0=539, L=616 and P=77, N punc_default =31; For R=7 / 8, K0=1078, L=1232 and P=154, N punc_default =62; For R=7 / 8, K0=1617, L=1848 and P=231, N punc_default =93; For R=11 / 12, K0=539, L=588 and P=49, N punc_default =59; For R=11 / 12, K0=1078, L=1176 and P=98, N punc_default =118; and For R=11 / 12, K0=1617, L=1764 and P=147, N punc_default =177.

8. The extremely high rate encoding and decoding method for the next generation wireless local area network system according to claim 6, wherein: The steps of performing the puncture procedure also include: Determine the number of punctured bits N for each codeword based on the total number of punctured bits ppcw , Calculating the total number of puncture bits includes: calculating the total number of puncture bits N punc ,as follows: N punc =max(0,(N CW x L LDPC )–N avbits –N shrt ), in: N CW represents the number of codewords of the low-density parity-check code, L LDPC represents the length of the low-density parity-check codeword, N avbits represents the number of available bits, and N shrt Indicates the total number of shortened bits.

9. The extremely high rate encoding and decoding method for the next generation wireless local area network system according to claim 1, It is characterized by: The steps of performing the repetition procedure include: calculating the number of total repetition bits; and In response to the number of total punctured bits being equal to zero and the number of default punctured bits being less than the number of repetition bits per codeword, the total repetition bits are added to the plurality of parity bits.

10. The extremely high rate encoding and decoding method for the next generation wireless local area network system according to claim 9, wherein: Calculating the total number of repetition bits includes calculating the total number N of repetition bits as follows: rep : N rep =max(0,N avbits –N CW x L LDPC x(1–R)–N pld ), in: N avbits Indicates the number of available bits. N CW represents the number of codewords of the low-density parity-check code, L LDPC represents the length of the low-density parity-check codeword, R indicates that the first codec rate is 7 / 8 or 11 / 12, and N pld Indicates the number of bits in the physical layer convergence protocol service data unit and the SERVICE field.

11. The very high rate encoding and decoding method for the next generation wireless local area network system according to claim 1, wherein: The steps of executing the puncturing procedure include: responding to the total number of puncturing bits N punc greater than or equal to zero, by discarding the last N of the multiple parity bits punc_default +N ppcw bits, performing continuous puncturing on the shortened bit string; and in: N punc_default represents the number of default puncture bits, and N ppcw Indicates the number of punctured bits per codeword.

12. The very high rate encoding and decoding method for the next generation wireless local area network system according to claim 1, wherein: The steps of executing the puncturing procedure include: responding to the total number of puncturing bits N punc greater than zero, by first discarding N of the plurality of parity bits in an interleaved manner punc_default bits, and then discard the remaining N parity bits ppcw bits to perform interleaving puncturing on the shortened bit string, and in: N punc_default represents the number of default puncture bits, and N ppcw Indicates the number of punctured bits per codeword.

13. The very high rate encoding and decoding method for the next generation wireless local area network system according to claim 12, wherein: Discard N of the plurality of parity bits in an interleaved manner punc_default The bits include: In response to the first coding rate being 7 / 8, discarding one bit for every three bits of the plurality of parity check bits; or In response to the first coding rate being 11 / 12, one bit is dropped for every two bits of the plurality of parity bits.

14. The very high rate encoding and decoding method for the next generation wireless local area network system according to claim 1, wherein: The step of encoding and decoding the input data at the first codec rate includes encoding and decoding the input data at the first codec rate of 7 / 8, wherein the modulation codec index is 14, and 4096 orthogonal amplitude modulation is used.

15. The extremely high rate encoding and decoding method for the next generation wireless local area network system according to claim 1, wherein: The step of encoding and decoding the input data at the first codec rate includes encoding and decoding the input data at the first codec rate of 11 / 12, wherein the modulation codec index is 14 or 15, and 4096 quadrature amplitude modulation is used.

16. The extremely high rate encoding and decoding method for the next generation wireless local area network system according to claim 1, wherein: The step of encoding and decoding the input data at the first codec rate includes: based on the first codec rate of 7 / 8 indicated by the existing modulation and decoding scheme bits and a reserved bit with a predetermined value, encoding and decoding the input data at the first codec rate of 7 / 8 using a modulation and decoding scheme index of 16 and 4096 orthogonal amplitude modulation, and wherein the corresponding very high throughput-modulation and decoding scheme bits include 0000.

17. The very high rate encoding and decoding method for the next generation wireless local area network system according to claim 1, wherein: The step of encoding and decoding the input data at the first codec rate includes: based on the first codec rate of 11 / 12 indicated by the existing modulation and decoding scheme bits and a reserved bit with a predetermined value, encoding and decoding the input data at the first codec rate of 11 / 12 using a modulation and decoding scheme index of 17 and 4096 orthogonal amplitude modulation, and wherein the corresponding very high throughput-modulation and decoding scheme bits include 0001.

18. The very high rate encoding and decoding method for the next generation wireless local area network system according to claim 1, wherein: Also includes: By indicating the physical layer capability in the capability field, a signal is sent to a station in the wireless local area network to indicate support for the first codec rate of 4096 quadrature amplitude modulation.

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