Microelectronic device with vertical means of stacking

Abstract

Embodiments can include a microelectronic device. The microelectronic device can include a first pair of transistors that are vertically stacked and connected in series. Each transistor of the first pair of transistors is of the same type. The microelectronic device can include a second pair of transistors that are connected in parallel. The second pair of transistors is of a different type than the first pair of transistors. The first pair of transistors and the second pair of transistors are arranged substantially perpendicular to a plurality of layers.

Description

Background Technology

[0001] This disclosure relates to an integrated circuit and a method for manufacturing the same.

[0002] Most integrated circuits consist of multiple adjacent layers deposited and structured sequentially. Power rails are provided to power the integrated circuit's battery. Cells of an integrated circuit may contain static random access memory (SRAM) cells for storing data and logic cells for performing combinational logic functions (e.g., using NAND and NOR gates). Signal lines are provided for transmitting data, such as the result of Boolean operations or data to be stored in the cell (e.g., SRAM cell). Cells of an integrated circuit include field-effect transistors (FETs), each FET including a drain region, a source region, a channel region, and a gate region. Typically, FETs are formed in the lowest layer of the integrated circuit. Layers including signal lines and power rails are disposed in layers above the FETs.

[0003] Vertical interconnect access contacts (VIAs) are provided to connect the drain, source, and gate regions of the FET to signal lines and power rails. Each VIA results in contact capacitance and resistance at the interface to the corresponding region of the FET, signal line, and power rail. Furthermore, each VIA increases the surface area required to fabricate the integrated circuit. Therefore, it may be necessary to reduce the number of VIAs required to fabricate the integrated circuit.

[0004] Furthermore, a separate VIA may need to be aligned with the source and gate regions of the FET, as well as signal lines and power rails. A vertical structure that facilitates the fabrication of conductors extending across different layers of the integrated circuit may also be required. Summary of the Invention

[0005] By providing the integrated circuit and method according to the independent claims, the disadvantages of the prior art are overcome, and additional advantages are provided. Advantageous embodiments are described in the dependent claims.

[0006] According to an embodiment, an integrated circuit is provided, comprising a plurality of adjacent layers, wherein the integrated circuit includes a plurality of vertical structures, wherein the vertical structures extend in a vertical direction substantially perpendicular to the layers of the integrated circuit, wherein the vertical structure includes at least one vertical connection element and at least one vertical channel region, and wherein the vertical structures are arranged above nodes of a virtual two-dimensional regular grid. Nodes of the grid may exist, with no vertical structures provided on the nodes. The regularity of the grid facilitates the fabrication of the integrated circuit.

[0007] According to an embodiment, an integrated circuit is provided. The integrated circuit includes a plurality of adjacent layers, each adjacent layer including a stack of one or more field-effect transistors (FETs) (e.g., a first FET and a second FET). Each FET includes a channel region. The channel regions of the stacked FETs are electrically connected in series. The stack extends in a vertical direction substantially perpendicular to the layers (e.g., layers of the integrated circuit). The first FET and the second FET are of the same type.

[0008] According to an embodiment, the two opposite ends of the stack correspond to a power support terminal and a signal terminal. The power support terminal is connected to the power rail of the integrated circuit. The signal terminal is connected to the signal line of the integrated circuit.

[0009] According to an embodiment, the FETs of the stack are of the same type, wherein the channel regions of the field-effect transistors of the stack are connected in series, wherein the two opposite ends of the stack correspond to a power support terminal and a signal terminal, and wherein the power support terminal is connected to the power rail of the integrated circuit.

[0010] According to an embodiment, several cell types within an integrated circuit (i.e., cells that perform Boolean operations or store data) require two FETs of the same type connected in series. A stack of two FETs extending vertically can facilitate wiring and routing within and between functional cells. This allows for higher cell density within the integrated circuit.

[0011] According to an embodiment, the power rail can be provided as a buried conductive layer in the substrate of an integrated circuit. Specifically, the power rail can be formed as a heavily doped semiconductor region. The heavily doped semiconductor region can be formed by an ion implantation process. Alternatively, the heavily doped semiconductor region can be formed by a diffusion process. The low-resistance power rail can be formed by different process options (e.g., a recombination method).

[0012] According to an embodiment, the channel region of the FET of the stack is provided in a layer between the layer including the power rail of the integrated circuit and the layer including the signal line of the integrated circuit.

[0013] Separating the layer containing signal lines from the layer containing power rails can significantly reduce the routing complexity of integrated circuits. In particular, it can reduce the number of VIA contacts and wire lengths. This allows for higher device density and / or lower power consumption of integrated circuits.

[0014] According to an embodiment, a stack can be formed on a heavily doped semiconductor region forming a power rail via epitaxy. The dopant concentration can be varied during epitaxy.

[0015] According to an embodiment, the channel region of the stacked FETs is a horizontal channel region, wherein, in the conductive state of the FET, charge carriers move in a direction parallel to the layers of the integrated circuit. The stack may include two classical planar FETs, one on top of the other, with the source region of one classical planar FET electrically connected to the drain region of the other classical planar FET. Alternatively, the stack may include two finned FETs connected in series with a source-drain connection. The fins of the finned FETs may be configured to be parallel or orthogonal to each other.

[0016] According to embodiments, the first FET and / or the second FET includes more than one vertical channel region. Providing more than one vertical channel allows the FET to more easily adapt to different electrical requirements. The vertical channel regions can have substantially the same size to improve process stability for manufacturing integrated circuits. "Substantially the same size" can refer to a size that fluctuates only during the processing of the integrated circuit due to unavoidable variations. The characteristics of the FET in the integrated circuit can be tuned by selecting the number of vertical channel regions. For example, if the FET must provide twice the current of another FET, the FET can include twice the amount of the vertical channel region of the other FET. Therefore, the size of the FET can be quantified.

[0017] According to an embodiment, the vertical channel region has a cross-section having a longitudinal axis and a transverse axis, wherein the longitudinal axis and the transverse axis have substantially the same length. For example, the vertical channel region can have a circular cross-section. The circular cross-section can be produced by exposing a mask with quadratic characteristics due to exposure artifacts at quadratic corners. In an embodiment, the vertical channel region can have a hexagonal cross-section. For example, a semiconductor with a hexagonal crystal structure can be used to form the vertical channel region. Furthermore, in an embodiment, the vertical channel region can have a triangular cross-section. The triangle can be an equilateral triangle. Using a vertical channel region with a cross-section having a longitudinal axis and a transverse axis of substantially the same length can result in a FET with a particularly narrow channel.

[0018] According to an embodiment, the vertical channel region can be formed by epitaxial growth in a direction perpendicular to the layer. Epitaxial growth allows for precise definition of the length (e.g., vertical length) of the vertical channel region. Specifically, the lengths of the vertical channel regions of several FETs disposed in the same layer of an integrated circuit can be formed to be substantially the same. This avoids channel length deviations caused by patterning processes (e.g., using extreme ultraviolet (EUV) lithography).

[0019] According to embodiments, the longitudinal axis is longer than the transverse axis. For example, the vertical channel region can have a rectangular or elliptical cross-section. A vertical channel region with an elongated cross-section (an elongated cross-section with a longer longitudinal axis and a shorter transverse axis, or vice versa) can allow for a wider channel for a given cross-sectional area.

[0020] According to one embodiment, the longitudinal axis of the elongated cross-section is substantially perpendicular to the longitudinal direction of the power rail. This arrangement optimizes the use of space above the power supply rail while providing a narrow, quantized channel.

[0021] According to an embodiment, the stack includes a common nanowire. The common nanowire includes channel regions of multiple FETs. The region located between the channel region of the first FET and the channel region of the second FET can simultaneously form the source / drain region of the first FET and the drain / source region of the second FET.

[0022] According to an embodiment, the first FET and / or the second FET is a full-to-the-loop FET. The full-to-the-loop configuration providing the channel region for the first / second FET can improve the electrical characteristics of the FET. Boundary effects at the boundary of the gate extending parallel to the channel region can be avoided.

[0023] According to one embodiment, the integrated circuit includes a second stack of two FETs. The two FETs in the second stack are of the same type. Alternatively, the two FETs in the second stack may have a different type than the first and second FETs. The power supply terminal of the second stack is connected to another power rail.

[0024] According to an embodiment, the integrated circuit includes an SRAM cell. The SRAM cell includes a memory element and an access FET. The memory element includes a first inverter, which includes a first inverter FET connected to a power rail. The first inverter FET is a first FET on the stack. The access FET is a second FET on the stack. The access FET is electrically connected to a bit line.

[0025] According to the embodiments, the proposed SRAM cell may require fewer VIAs than a classic SRAM cell. Therefore, the proposed SRAM cell can have a smaller footprint and increase the SRAM cell density of the integrated circuit. Furthermore, the wires connecting the components of the proposed SRAM cell can be shorter, thus reducing the power consumption of the integrated circuit due to wire capacitance. Bit lines can be considered as signal lines of the integrated circuit.

[0026] According to one embodiment, the integrated circuit includes two mirror-symmetric SRAM cells. Providing mirror-symmetric SRAM cells allows for an increase in the density of SRAM cells in the integrated circuit.

[0027] According to one embodiment, mirror-symmetric SRAM cells share a power rail. Mirror-symmetric SRAM cells sharing a power rail allow for a wider power rail. Therefore, voltage fluctuations along the power rail can be better mitigated.

[0028] According to an embodiment, the integrated circuit includes a logic unit. The logic unit includes a stack and a second pair of FETs. The second pair of FETs is of a different type than the first and second FETs. The two FETs of the second pair are arranged in electrical parallel. The two FETs of the second pair form a vertical structure different from the stack.

[0029] According to an embodiment, the gate of one FET in the stack and the gate of one FET in the second pair are connected to each other and correspond to the first input of the logic cell. The gates of the FETs in the stack and the gates of one FET in the second pair extend in the same layer within the hierarchical structure of the integrated circuit. In an embodiment, the gates of one FET in the stack and the gates of one FET in the second pair may be formed as a single unit.

[0030] According to an embodiment, the gate of one FET in the stack and the gate of one FET in the second pair are connected to each other and correspond to the second input of the logic cell. The gate of one FET in the stack and the gate of one FET in the second pair extend in different layers of the integrated circuit's layer structure.

[0031] According to an embodiment, these power rails extend in at least one layer located at a first end of a stack and / or vertical structure. Signal interconnect conductors extend in a layer located at the opposite second end of the stack or vertical structure.

[0032] According to the embodiment, the logic unit is a NAND gate or a NOR gate.

[0033] According to an embodiment, the integrated circuit includes more than one cell selected from the group of SRAM cells and logic cells described herein, wherein the selected cells share at least one power rail.

[0034] According to the embodiment, the selected unit shares one of the VDD power rail and the ground power rail, and uses a different power rail for other potentials.

[0035] According to the embodiment, the selected units share two power rails.

[0036] According to an embodiment, a grid of nodes may exist, with no vertical structure provided on the nodes. The regularity of the grid facilitates the fabrication of integrated circuits.

[0037] According to an embodiment, the longitudinal spacing between two nodes of the grid in the vertical direction is equal to the transverse spacing between two nodes of the grid in the horizontal direction, wherein the vertical direction is perpendicular to the horizontal direction. Specifically, the grid can correspond to a chessboard.

[0038] According to an embodiment, the longitudinal spacing between two nodes of the grid in the longitudinal direction is different from the lateral spacing between two nodes of the grid in the transverse direction, wherein the longitudinal direction is perpendicular to the transverse direction. If these power rails extend along either the transverse or longitudinal direction of the grid, this allows for better insulation between two power rails providing different voltages. In particular, the different longitudinal and transverse spacings can reduce the amount of leakage current and / or unintentional capacitance.

[0039] According to an embodiment, the grid has a hexagonal pattern. The hexagonal pattern allows for a specific dense arrangement of vertical structures.

[0040] The embodiments may include microelectronic devices. The microelectronic devices may include a first pair of transistors vertically stacked and connected in series. Each transistor in the first pair is of the same type. The microelectronic devices may include a second pair of transistors connected in parallel. The second pair of transistors is of a different type from the first pair. The first and second pairs of transistors are arranged substantially perpendicular to multiple layers.

[0041] Embodiments may include a microelectronic device. The microelectronic device may include a first pair of transistors vertically stacked and connected in series. Each transistor in the first pair is of the same type. The microelectronic device may include a second pair of transistors connected in parallel. The second pair of transistors is of a different type from the first pair. The first and second pairs of transistors are arranged substantially perpendicular to multiple layers. The gate of one transistor in the first pair and the gate of one transistor in the second pair are connected to each other and correspond to a first input of the microelectronic device. The gates of one transistor in the first pair and the second pair are arranged in the same layer of the microelectronic device. The gates of one transistor in the first pair and the second pair are connected to each other and correspond to a second input of the microelectronic device. The gates of one transistor in the first pair and the second pair are arranged in different layers of the microelectronic device.

[0042] Embodiments may include a method of forming a microelectronic device. The method may include forming a first pair of transistors that are vertically stacked and connected in series. Each transistor in the first pair is of the same type. The method may include forming a second pair of transistors that are connected in parallel. The second pair of transistors is of a different type from the first pair. The first and second pairs of transistors are formed substantially perpendicular to multiple layers.

[0043] Embodiments may include a method of forming a microelectronic device. The method may include forming a first pair of transistors that are vertically stacked and connected in series. Each transistor in the first pair is of the same type. The method may include forming a second pair of transistors that are connected in parallel. The second pair of transistors is of a different type from the first pair. The first and second pairs of transistors are formed substantially perpendicular to multiple layers. The gate of one transistor in the first pair and the gate of one transistor in the second pair are connected to each other and correspond to a first input of the microelectronic device. The gates of one transistor in the first pair and the second pair are arranged in the same layer of the microelectronic device. The gates of one transistor in the first pair and the second pair are connected to each other and correspond to a second input of the microelectronic device. The gates of one transistor in the first pair and the second pair are arranged in different layers of the microelectronic device.

[0044] Specifically, a method for manufacturing an integrated circuit is provided, the integrated circuit comprising a plurality of adjacent layers having any of the aforementioned features. Regarding the advantageous effects of the proposed method, reference is made to the description of embodiments of the integrated circuit described in this disclosure.

[0045] Additional features and advantages are achieved through the techniques disclosed herein. Other embodiments and aspects of the invention are described in detail herein and are considered part of the claimed aspects. Attached Figure Description

[0046] In the conclusion of this specification, one or more aspects of the invention are specifically pointed out and clearly claimed as examples in the claims. The above and other objects, features, and advantages of the invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings, wherein:

[0047] Figures 1a-6a The circuit diagram of the NAND gate components is shown;

[0048] Figures 1b-6b It shows Figures 1a-6a The physical structure of the components shown;

[0049] Figure 7a The circuit diagram of a balanced NAND gate is shown;

[0050] Figure 7b It shows Figure 7a The physical structure of the equilibrium NAND gate;

[0051] Figure 7c The vertical structure on the nodes of the grid is shown;

[0052] Figure 7d Further shown Figure 7c The grid;

[0053] Figures 8a-13a A circuit diagram with NOR gates is shown;

[0054] Figure 8b-13b It shows Figures 8a-13a The physical structure of the components shown;

[0055] Figures 14a-20a A circuit diagram of a component with SRAM cells is shown;

[0056] Figure 14b-20b It shows Figures 14a-20a The physical structure of the components shown;

[0057] Figure 21-22 The physical structure of the first array of SRAM cells is shown;

[0058] Figure 23 The physical structure of the second array of SRAM cells is shown;

[0059] Figure 24 The physical structure of the third array of SRAM cells is shown;

[0060] Figure 25 The vertical structure on the nodes of the mesh is shown; and

[0061] Figure 26 A node from another grid is shown. Detailed Implementation

[0062] This document discloses detailed embodiments of the claimed structures and methods; however, it is to be understood that the disclosed embodiments are merely illustrative of the claimed structures and methods that may be implemented in different forms. The invention can be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be comprehensive and complete, and will fully convey the scope of the invention to those skilled in the art. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments of the invention.

[0063] References to "an embodiment," "embodiment," "example embodiment," etc., in the specification indicate that the described embodiment may include a particular feature, structure, or characteristic, but each embodiment may not necessarily include that particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is believed that incorporating other embodiments, whether explicitly described or not, to affect such a feature, structure, or characteristic is within the knowledge of those skilled in the art.

[0064] For the purposes described below, the terms “upper,” “lower,” “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” and their derivatives shall refer to the disclosed structures and methods oriented as shown in the accompanying drawings. The terms “cover,” “on top,” “on top of,” “positioned on,” or “positioned on top of” mean that a first element (such as a first structure) is present on a second element (such as a second structure), wherein an intermediate element (such as an interface structure) may be present between the first and second elements. The term “direct contact” means that the first element (such as a first structure) and the second element (such as a second structure) are connected without any intermediate conductive, insulating, or semiconductor layer at the interface between the two elements.

[0065] To avoid obscuring the presentation of embodiments of the invention, some processing steps or operations known in the art may have been combined for presentation and illustrative purposes in the following detailed description, and in some cases may not have been described in detail. In other instances, some processing steps or operations known in the art may not be described at all. It should be understood that the following description focuses primarily on the distinguishing features or elements of the various embodiments of the invention. Furthermore, it should be noted that while this specification may refer to some components of the structure in the singular tense, more than one component may be depicted throughout the drawings.

[0066] The terms substantially, substantially similar, approximately, or any other term indicating functional equivalence refer to the following: where differences in length, height, or orientation do not express an actual difference between a clearly stated description (e.g., a phrase that does not contain substantially similar terms) and substantially similar variations. In one embodiment, substantial (and its derivatives) means a difference in engineering or manufacturing tolerances generally accepted for similar devices, up to, for example, a 10% deviation in value or a 10% deviation in angle.

[0067] In the semiconductor industry, lithography limitations can be problematic when shrinking integrated circuits. Potential issues include the resistive impact of the current supply system on performance, lower levels of electromigration reliability, reduced wiring due to wiring resources applied to power and ground, and lithographic effects due to non-uniform track patterns.

[0068] One solution to lithographic limitations can include scaling down the circuitry and building the device in a vertical dimension (i.e., in the third dimension). The scaled-down circuitry can include supplying power and ground using buried contact layers beneath the active regions (i.e., opposite the wiring stack). For example, ground (GND) is below the n-channel FET (nFET) region, and the voltage source (VSS) is below the p-channel FET (pFET) region. Advantages are provided by supplying power and ground from opposite ends of the wiring stack. These advantages can also include optimized density, no electromigration, more space for signal lines, accessibility to signal pins, uniform spacing on lower metal and vertical interconnect access (VIA) layers, and fewer VIAs.

[0069] Additional advantages may include avoiding interference between signal lines and the power rails of the integrated circuit. This allows for greater flexibility in placing the logic cells of the integrated circuit.

[0070] Figures 1a-6a The circuit diagram of a NAND gate is shown, and Figures 1b-6b The physical structure of integrated circuit 100 is shown, including corresponding elements on multiple adjacent layers. For better understanding, integrated circuit 100 is shown as having an increasing number of elements, and in some figures, some elements are hidden behind other elements (i.e., can be seen from different angles not necessarily shown in every figure). Figures 1a-6a In terms of circuit diagrams, corresponding to Figures 1b-6b In the following description, the main references are as follows: Figures 1b to 6b The physical structure shown.

[0071] See Figure 1a / b, Integrated circuit 100 includes a stack 110 of a first field-effect transistor (FET) 110a and a second FET 110b. Each of FETs 110a and 110b includes a channel region. The channel region of the first FET 110a is covered by a gate dielectric 112 and a gate 113. The channel regions of FETs 110a and 110b in stack 110 are electrically connected in series. Stack 110 extends in a direction V substantially perpendicular to the layers of integrated circuit 100. The two FETs 110a and 110b in stack 110 are of the same type. For example, the two FETs in stack 110 can be n-channel FETs (nFETs) or the two FETs in stack 110 can be p-channel FETs (pFETs). The two opposite ends of stack 110 of FETs 110a and 110b correspond to a power support terminal 111 and a signal terminal 114.

[0072] The terms substantially, substantially similar, approximately, or any other term indicating functional equivalence refer to the following: where differences in length, height, or orientation do not express an actual difference between a clearly stated description (e.g., a phrase that does not contain substantially similar terms) and substantially similar variations. In one embodiment, substantial (and its derivatives) means a difference in engineering or manufacturing tolerances generally accepted for similar devices, up to, for example, a 10% deviation in value or a 10% deviation in angle.

[0073] The channel region of stack 110 (i.e., the channel region of the first FET 110a and the second FET 110b) may be a vertical channel region. A vertical channel region may refer to a channel region in which charge carriers can move in a direction substantially orthogonal to the layers of integrated circuit 100 when the first FET 110a and / or the second FET 110b are in a conductive state.

[0074] The first FET 110a and the second FET 110b may include more than one vertical channel region. Figure 1b In the illustrated embodiment, stack 110 is shown as a single pillar with a circular cross-section. However, stack 110 may also include a bundle of vertical columns, wherein each channel region is covered by a gate dielectric, and the gate dielectric is surrounded by a common gate.

[0075] The cross-section of the vertical channel region can have a longitudinal axis C. L and the transverse axis C T .like Figure 1b As shown, the longitudinal axis C L and the transverse axis C T They can have essentially the same length. Figure 1b In the embodiment shown, the cross-section is approximately circular. The longitudinal axes C have approximately the same length. L and the transverse axis C T Other cross sections can be square, hexagonal, and / or triangular.

[0076] Alternatively, the vertical channel region can have a slender cross-section, wherein the longitudinal axis C L Compared to the transverse axis C T Length. For example, the cross-section can have a rectangular or elliptical shape.

[0077] Stack 110 may include common nanowires, wherein the common nanowires include the channel regions of FETs 110a and 110b of stack 110. However, stack 110 may also have a shape different from that of nanowires.

[0078] exist Figure 1bIn the illustrated embodiment, both the first FET 110a and the second FET 110b are full-to-the-loop FETs. The gates of FETs 110a and 110b completely surround the channel regions of FETs 110a and 110b. This improves the electrical characteristics of FETs 110a and 110b.

[0079] Furthermore, integrated circuit 100 includes a second pair of FETs 115 and 116, which can be formed in a vertical structure different from that of stack 110. FET 115 can also be formed in a different vertical structure than FET 116. Therefore, stack 110, FET 115, and FET 116 can be formed in three different columns extending in direction V. The lower ends of FETs 115 and 116 can be considered as power support terminals.

[0080] like Figures 1a-1b As shown, the gate 113 of the first FET 110a and the gate of the FET 116 can be disposed in the same layer of the integrated circuit 100.

[0081] See now Figure 2a / 2b, the gates 113 and 116 of the first FET can be electrically connected to the conductive element 153. The conductive element 153 can be disposed in the same layer as the gates 113 and 116 of the first FET 110a. Specifically, the gate 113 of the first FET 110a, the conductive element 153, and the gate of the FET 116 can be formed as a single piece of material. Alternatively, the gates 113 of the first FET 110a and 116 can be formed of different materials. For example, the materials of the gates of the first FET 110a and 116 can be selected to obtain a certain threshold voltage for the first FET 110a and FET 116. The material of the conductive element 153 can be selected to have a particularly low resistivity.

[0082] See now Figure 3a / 3b, the gate of FET 115 can be electrically connected to the gate of the second FET 110b via conductive elements 151 and 152. Therefore, the integrated circuit 100 may include a conductive element 151 extending in the same layer as the gate of the second FET 110b. The conductive element 151 and the gate of the second FET 110b can be formed integrally. This facilitates the fabrication of the integrated circuit 100. They can also be formed of different materials, as explained above regarding gate 113 and conductive element 153. Another conductive element 152 may be disposed in the same layer as the gate of FET 115. This layer may correspond to the layer forming the gate 113 of the first FET 110a, the gate of FET 116, and the conductive element 153. The gate of FET 115 and conductive element 152 can be formed integrally. They can also be formed of different materials, as explained above regarding gate 113 and conductive element 153. A vertical conductive element 142 can electrically connect conductive elements 151 and 152.

[0083] The vertical conductive elements of the integrated circuits disclosed in this specification can be formed of metal. Metals can have particularly high conductivity. Furthermore, metals can promote heat distribution within the integrated circuit, avoiding hot spots. Alternatively, the vertical conductive elements of the integrated circuit can be formed of semiconductor material. The vertical conductive elements can be formed of the same semiconductor material as the source, channel, or drain regions of the FET in the integrated circuit. Using the same semiconductor material for both the vertical conductive elements and the FET avoids contamination of the FET by materials that could degrade its electrical characteristics. Furthermore, the same process can be used to form the vertical conductive elements and vertical channel regions of the FET. The physical dimensions (e.g., cross-section, width, length, or height) of the vertical conductive elements and the FET can be identical. If the number of features with different dimensions is reduced, patterning during the fabrication of the integrated circuit may be easier.

[0084] See now Figure 4a / b, Integrated circuit 100 may include an internal connection element 160 connecting FET 115 and FET 116. The internal connection element 160 may extend within a single layer of integrated circuit 100. Charge carriers may move substantially parallel to the layer of integrated circuit 100 within the internal connection element 160. The internal connection element 160 is electrically connected to the upper ends of FETs 115 and 116.

[0085] The internal interconnect elements of the integrated circuits disclosed in this specification may be formed of metal. Alternatively, the internal interconnect elements of the integrated circuits may be formed of semiconductor material. Specifically, the internal interconnect elements of the integrated circuits may be formed of the same semiconductor material as the source and / or drain regions of the FETs of the integrated circuit. This avoids contact resistance between the source and / or drain regions of the FETs of the integrated circuits and the internal interconnect elements.

[0086] The integrated circuit 100 may further include a vertical conductive element 143 and a vertical conductive element 144. The vertical conductive element 143 may be electrically connected to the conductive element 153. The vertical conductive element 143 may extend upward from the conductive element 153. The vertical conductive element 144 may be electrically connected to the internal connection element 160. The vertical conductive element 144 may extend upward from the internal connection element 160.

[0087] See now Figure 5a / 5b, the vertical conductive element 143 can be electrically connected to the first input terminal 171 of the integrated circuit 100. Therefore, the gates of FET 110a (FIG. 1-2) and FET 116 (FIG. 1-3) of the stack 110 (FIG. 1-2) are connected to each other and can correspond to the first input 171 of the integrated circuit 100.

[0088] Furthermore, the gates of FET 110b (FIG. 1-2) and FET 115 (FIG. 1-2) extend in different layers of integrated circuit 100. The gates of the second FET 110b and FET 115 are interconnected via conductive element 151, vertical conductive element 142, and further connected to the second input 172 of integrated circuit 100 via an additional vertical conductive element 141 (FIG. 4). One end of stack 110 may correspond to signal terminal 114. Signal terminal 114 of stack 110 may be connected to output terminal 181 of integrated circuit 100. Vertical conductive element 144 (FIG. 4) provides an electrical connection from internal connection element 160 (FIG. 4) to output 181 of integrated circuit 100.

[0089] See now Figure 6a / 6b, the power support terminal 111 of stack 110 can be connected to the power rail 191 of integrated circuit 100. The power support terminals of FET 115 (Figure 1-2) and FET 116 (Figure 1-2) can both be connected to another power rail 192. Power rails 191 and 192 can be arranged parallel to each other.

[0090] The electrical connection elements of integrated circuit 100 can be considered as logic units 100, specifically NAND gates 100 having inputs 171 and 172 and output 181. Inputs 171 and 172 and output 181 can be considered as signal lines of the integrated circuit. Additional local and global signal routing layers may exist above the input and output layers shown.

[0091] Such as integrated circuit 100 (i.e., Figures 1b to 6bAs shown in the diagram, the channel regions of the FETs 110a, 110b, 115, and 116 of the integrated circuit 100 can be disposed between the layer including signal lines 171, 172, and 181 and the layer including power rails 191 and 192. This avoids interference between the signal lines and the power rails of the integrated circuit. This allows for greater flexibility in placing the logic cells of the integrated circuit.

[0092] Using a FET with a vertical channel region to form the integrated circuit of Figure 1-6 can reduce the need for additional vertical interconnect components, because the vertical channel region already provides some electrical connections between different layers of the integrated circuit.

[0093] Power rail 191 can provide a ground voltage GND, and power rail 192 can provide a high potential voltage VDD for driving integrated circuit 100. FETs 110a and 110b of stack 110 can be nFETs, and FETs 115 and 116 can be pFETs.

[0094] The FETs of the disclosed integrated circuit can be provided at regular intervals along the extension direction of the power rail. The distance between FETs in the extension direction of the power rail and the distance between FETs in the direction perpendicular to the extension direction of the power rail can be equal. This regular arrangement of FETs can help reliably manufacture the integrated circuit. Furthermore, the regular arrangement of FETs can allow for optimization of the FET density of the integrated circuit.

[0095] Figures 7a-7d An integrated circuit 200 corresponding to the integrated circuit 100 described above is shown. Figure 7a The circuit diagram for a balanced NAND gate. Figure 7b The physical structure of a balanced NAND gate is shown. Figure 7c The vertical structure on the nodes of the mesh is shown, and Figure 7d Further explanation Figure 7c .

[0096] See now Figure 7a , Figure 7b According to an embodiment of the present invention, an integrated circuit 200 includes multiple adjacent layers. The integrated circuit 200 corresponds to the integrated circuit 100 described above. In addition to the stack 210 including a first FET 210a and a second FET 210b corresponding to the first stack 110 of the integrated circuit 100, the integrated circuit 200 also includes an additional stack 217 including a third FET 217a and a fourth FET 217b.

[0097] The power support terminals 211 and 218 of both stacks 210 and 217 can be connected to power rail 291. The signal terminals 214 and 219 of both stacks 210 and 217 can be connected to output 281 of integrated circuit 200. Furthermore, the gate of the first FET 210a, the gate of the third FET 217a, and the connection element 253 can extend in the same layer of the integrated circuit. Specifically, the gate of the first FET 210a, the gate of the third FET 217a, and the connection element 253 can be formed as a single unit. The gates of the second FET 210b and the fourth FET 217b can also extend in a single layer together with the connection element 251.

[0098] The resistance of a stack of two FETs can be greater than the resistance of a vertical structure that may consist of only one FET. Therefore, providing an additional stack 217 in parallel with stack 211 results in integrated circuit 200 having more balanced characteristics compared to integrated circuit 100. Specifically, the impedance at output terminal 281 of integrated circuit 200 can depend less on the voltage supplied at output terminal 281 of integrated circuit 200.

[0099] Figure 7c and 7d The vertical structures of integrated circuit 200 (specifically, vertical structures 241, 210, and 217 of integrated circuit 200) are arranged above nodes N of a virtual two-dimensional regular grid G. Grid G ​​exhibits translational symmetry. Furthermore, grid G ​​also exhibits rotational symmetry, as rotating the grid by 90° results in identical grids. The longitudinal spacing G between two nodes of the grid in the longitudinal direction is shown. L Equal to the lateral spacing G between two nodes of the mesh in the lateral direction T , where the longitudinal direction is perpendicular to the transverse direction.

[0100] Figures 8a-13a The circuit diagram elements of a logic NOR gate are shown, and Figure 8b-13b The physical structure of an integrated circuit 300 comprising multiple adjacent layers is shown, along with corresponding elements. The integrated circuit 300 is shown with an increasing number of elements. Figures 8a-13a In terms of circuit diagrams, corresponding to Figure 8b-13b The following description primarily references... Figure 8b-13b The physical structure shown.

[0101] See now Figure 8bIntegrated circuit 300 includes a stack 310. Stack 310 includes a first field-effect transistor (FET) 310a and a second FET 310b. The first FET 310a includes a channel region covered by a gate dielectric 312 and a gate 313. The channel region of the second FET 310b is electrically connected in series with the channel region of the first FET 310a. The first FET 310a and the second FET 310b are stacked in a direction V substantially perpendicular to the layers of integrated circuit 300. The two FETs 310a and 310b are of the same type. For example, the two FETs in stack 310 can be p-channel FETs or pFETs, or the two FETs 310a and 310b in stack 310 can be n-channel FETs or nFETs. A first end of stack 310 can be considered a power support terminal 311, and the other end on the opposite side can be considered a signal terminal 314.

[0102] Charge carriers can move in one direction within the channel regions of the first FET 310a and the second FET 310b (i.e., within the channel regions of the stack 310). If the channel is open (i.e., in the conducting state of the first FET 310a and the second FET 310b), the channel is substantially perpendicular to the layers of the integrated circuit 300. Therefore, the channel region can be considered a vertical channel region.

[0103] according to Figure 8b Stack 310 is shown as a pillar. The cross-section of the pillar corresponds to a circle. In an alternative embodiment, stack 310 may include several pillars, each having a vertical channel region. The vertical channel regions may each be covered by a gate dielectric (e.g., gate oxide), and the gate dielectric may be surrounded by a common gate. Typically, the pillars will have the same cross-section to facilitate the fabrication of the integrated circuit. It is also conceivable that the pillars have different cross-sections to allow for better fine-tuning of the electrical characteristics of the FET.

[0104] The vertical channel region may have a cross-section having a longitudinal axis C. L and the transverse axis C T .like Figure 8b-13b As shown, the longitudinal axis C L Can be used with the transverse axis C T They are the same length. They have approximately equal longitudinal axes C. L and the transverse axis C T The cross-section can be, for example, circular, square, triangular, and hexagonal.

[0105] In the embodiment, the longitudinal axis C of the cross-section of the vertical channel region is... L It can be compared to the horizontal axis C T Longer. This type of cross-section can be called an elongated cross-section. Rectangular or elliptical cross-sections can be examples of elongated cross-sections.

[0106] Stack 310 may be formed of common nanowires, wherein the common nanowires include the channel regions of FETs 310a and 310b of stack 310. In other embodiments, the shape of stack 310 may differ from that of nanowires.

[0107] Figure 8b-13b The gates of the FETs shown (specifically, the first FET 310a and the second FET 310b) can be full-to-the-loop FETs. The gate of the FET completely surrounds the channel region of the FET.

[0108] according to Figure 8b A second pair of FETs 315 and 316 are provided in integrated circuit 300. FETs 315 and 316 can be formed as different vertical structures of integrated circuit 310. FETs 315 and 316 can also each be formed as a vertical structure different from that of stack 310. A single layer of integrated circuit 300 includes both the gate 313 of the first FET 310a and the gate of the FET 316.

[0109] like Figure 9b As shown, a first FET 310a is provided (in...) Figure 8a , 8b Gate 313 (shown in) Figures 8a-13a The conductive element 351 in the same layer as the gate of FET 310a (shown in Figure 8b) and FET 316 can be electrically connected to the gate 313 of the first FET 310a and the gate of FET 316. The gate 313 of the first FET 310a, the conductive element 351 and the gate of FET 316 can be formed as a single unit.

[0110] The gate of the second FET 310b (in) Figure 8a , 8b (As shown in the diagram) is provided in a layer of integrated circuit 300 that is different from the gate of FET 315. Figure 10b As shown, the gate of FET 310b is electrically connected to the gate of FET 315. The electrical connection can be established through the depicted conductive element 353, vertical conductive element 344, and conductive element 352. Conductive element 353 and the gate of FET 315 can be formed as a single unit. Alternatively or additionally, the gate of FET 310b and conductive element 352 can also be formed as a single unit.

[0111] like Figure 11bAs shown, internal connection element 360 provides an electrical connection between FET 315 and FET 316. Internal connection element 360 is disposed within a single layer of integrated circuit 300. Current can flow substantially parallel to the layer of integrated circuit 300 within internal connection element 360. Internal connection element 360 can specifically connect the upper ends of FETs 315 and 316. The lower ends of FETs 315 and 316 can be considered as power support terminals.

[0112] Figure 12b A vertical conductive element 343 is shown that electrically connects internal connection element 360 to output terminal 381 of integrated circuit 300. Output 381 is also electrically connected to signal terminal 314 of stack 310.

[0113] Vertical conductive element 341 electrically connects conductive element 351 to input 372 of integrated circuit 300. Another vertical conductive element 342 provides an electrical connection between conductive element 352 and another input 371 of integrated circuit 300.

[0114] according to Figure 13b The power support terminal of stack 310 is connected to power rail 392, and the power support terminals of FETs 315 and 316 are connected to another power rail 391.

[0115] Power rail 391 can provide ground voltage GND and power rail 392 can provide a high potential voltage VDD for driving integrated circuit 300. FETs 310a and 310b of stack 310 (in...) Figure 8a , 8b (As shown in the diagram) can be a pFET, and FETs 315 and 316 can be nFETs.

[0116] The electrical connection elements of integrated circuit 300 correspond to logic units, specifically NOR gates.

[0117] The physical structure of NOR gate 300 can be mirror-symmetric to the physical structure of NAND gate 100, wherein power rail 191 (in Figure 6a , 6b (as shown in the diagram) and 391 both provide the ground voltage GND, where power rail 192 (in) Figure 6a , Figure 6b As shown in Figures 1-2a and 1-2b, FETs 110a, 110b (as shown in Figures 1-2a and 1-2b), and 115 (in...) both provide a high potential voltage VDD, and where FETs 110a, 110b (as shown in Figures 1-2a and 1-2b), and 115 (in...) provide a high potential voltage VDD. Figures 1a-6a (shown in 1b-2b) and 116 (in Figures 1a-5a The types shown in 1b-5b are the opposite of those of FETs 310a, 310b and 315, 316, respectively.

[0118] The integrated circuit may include sub-circuits corresponding to integrated circuit 100 and sub-circuits corresponding to integrated circuit 300, which share power rails 191 / 391 and 192 / 392. This may be an example of an integrated circuit comprising multiple adjacent layers, wherein the integrated circuit includes a (first) stack 110 of two FETs of the same type and a second stack 310 of two FETs of the same type, the type of which is different from that of the FETs in the (first) stack 110, the power supply terminal of the (first) stack 110 being connected to power rail 191 / 391, and the power supply terminal of the second stack 310 being connected to another power rail 192 / 392.

[0119] Extending from NAND and NOR, as illustrated in the examples of logic cells, p-channel stacks and n-channel stacks, as well as multiple combinations of individual p-channel and n-channel devices, can be fabricated with p-channels located above or below the VDD rail and n-channels located above or below the GND rail. Using p-channel and n-channel stacks and various variations of devices, devices can be connected to appropriately form the desired functionality using the connection elements shown in the NAND and NOR examples.

[0120] Figures 14a-20a The circuit diagram of the SRAM cell is shown, and Figure 14b-20b The corresponding elements of the physical structure of an integrated circuit 400 comprising multiple adjacent layers are shown. For better understanding, the integrated circuit 300 is shown as having an increasing number of elements. Figures 14a-20a In terms of circuit diagrams, corresponding to Figure 14b-20b In the following description, the main references are as follows: Figure 14b-20b The physical structure shown.

[0121] See now Figure 14b-20b The physical structure of an integrated circuit 400 with a layered structure. Specifically, Figures 14b to 20b The components of SRAM cell 400 are disclosed. Integrated circuit 400 is shown as having components from... Figures 14b to 20b An increasing number of components. Figures 14a-20a In terms of circuit diagrams, corresponding to Figure 14b-20b The following description focuses on the physical structure of integrated circuit 400 and primarily provides circuit diagrams to better understand the function of each component.

[0122] like Figure 14bAs shown, integrated circuit 400 includes a (first) stack 410 of a first field-effect transistor (FET) 410a and a second FET 410b. Both the first FET 410a and the second FET 410b include a channel region. The channel regions of the first FET 410a and the second FET 410b are connected in series. The (first) stack 410 extends in a vertical direction V, substantially perpendicular to the layers. The first FET 410a and the second FET 410b of the stack 410 are of the same type. The two opposite ends of the stack 410 correspond to a power support terminal 411 and a signal terminal 414.

[0123] Integrated circuit 400 may correspond to SRAM cell 400. SRAM cell 400 includes memory element 470, such as... Figure 20a As shown. Storage element 470 ( Figure 20a (As shown) includes a first inverter 471 having a first inverter FET 410a. Figure 20a (As shown). The first inverter FET 410a is in Figure 14b The first FET 410a, shown as (first) stack 410, is connected to power rail 491. Figure 20a , 20b As shown in the diagram). SRAM cell 400 further includes electrical connections to bit line 481 ( Figure 20a , 20b The access FET 410b is shown in the diagram. The access FET 410b is in... Figure 14b The second FET 410b is shown as (first) stack 410.

[0124] like Figure 14b As shown, the integrated circuit / SRAM cell 400 includes a second stack 415, which may include two FETs 415a and 415b. The channel regions of the two FETs 415a and 415b are connected in series. Specifically, the source region of one of the two FETs 415a and 415b may correspond to the drain region of the other two FETs 415a and 415b. The lower end of the stack 415 may be referred to as the power support terminal, and the upper end of the stack 415 may be referred to as the signal terminal of the stack 415.

[0125] Including power rail 491 (in Figure 20a , 20b The layer shown in the figure includes signal lines (specifically, such as...). Figure 20bThe integrated circuit 400 shown provides channel regions for a (first) stack 410 and a second stack 415 in two layers between the layers of bit lines 481 and 482. Bit line 482 can also be considered a complementary bit line 482, as bit lines 481 and 482 are configured to transmit complementary data. Separating the layer containing the gates of FETs 410a and 415a and the layer containing the gates of FETs 410b and 415b from the layer containing power rails 491 and 492 and the layer containing bit lines 481 and 482 can significantly reduce the wiring complexity of the integrated circuit 400. In particular, fewer VIA contacts may be required, and shorter wires may be sufficient for fabricating the integrated circuit. This can increase the device density of the integrated circuit. Furthermore, it can reduce power consumption caused by line capacitance.

[0126] Figure 14b The channel regions of stacks 410 and 415 shown are vertical channel regions. In the vertical channel region, charge carriers can move in a direction substantially perpendicular to the layers of integrated circuit 400 during the conduction states of each FET.

[0127] Figure 20a The first inverter 471 shown further includes a second inverter FET 417, which includes a gate. The second inverter FET 417 is of a different type from the first inverter FET 410a (shown in Figures 14-17a and 14-20b) which includes a gate. One end of the second inverter FET 417 is connected to another power rail 492. The second inverter 472 also includes two FETs, namely FET 415a (shown in Figures 14-17a and 14-20b) and FET 416. Figure 14b In this configuration, FET 416 is hidden behind stack 410. When viewed from above, stacks 410, 415, FET 417, and FET 416 can be arranged in the corners of a rectangle. Specifically, stacks 410, 415, FET 417, and FET 416 can be positioned in the corners of a quadrilateral.

[0128] like Figure 15b As shown, the gate 413 of the first inverter FET 410a and the gate of the second inverter FET 417 are electrically connected to each other via a conductive element 451 extending within a single layer of the integrated circuit 400. Specifically, the gate of the first inverter FET 410a, the gate of the second inverter FET 417, and the conductive element 451 may be formed as a single unit to facilitate the fabrication of the integrated circuit 400.

[0129] Accordingly, a conductive element 452 is provided, which connects the gate of FET 415a and the gate of FET 416. The conductive element 452 extends within a single layer of integrated circuit 400. The gate of FET 415a, the gate of FET 416, and the conductive element 452 may also be formed as a single unit.

[0130] exist Figure 14b-20b In the illustrated embodiment, the first inverter FET 410a and access FET 410b are n-channel FETs (nFETs), and the second inverter FET 417 is a p-channel FET (pFET). Accordingly, FETs 415a and FET 415b are nFETs and FET 416 is a pFET. For a given physical size, an nFET can have higher conductivity. Using a type of FET with higher conductivity can be particularly useful when FETs are connected in series to reduce the power consumption of an integrated circuit. However, embodiments in which the first inverter FET and access FET are pFETs and the second inverter FET is an nFET are conceivable. This can be useful for integrated circuits with inverting logic.

[0131] like Figure 16b and 17b As shown, integrated circuit 400 includes an intermediate layer. The intermediate layer is disposed between a first gate layer including the gate 413 of a first inverter FET 410a and a second gate layer including the gate of an access FET 410b. Storage element 470 ( Figure 20a (As shown) includes a second inverter 472 ( Figure 20a (As shown). The second inverter 472 is formed by FET 415a and FET 416.

[0132] The second inverter 472 is connected to the first inertial converter 471 by means of two cross-coupled conductors. Figure 20a (As shown in the diagram) cross-coupling. (As illustrated in the diagram) Figure 17b As shown, one cross-coupled conductor includes a conductive element 462 (shown in Figure 16-20a) and a vertical conductive element 441 (shown in Figure 16-20a). The vertical conductive element 441 provides a connection between the upper end of the FET 415a and the conductive element 451 (shown in Figures 15-17a, 20a, and 15-20b). Another cross-coupled conductor includes a conductive element 461 and another vertical conductive element 442 (in... Figure 17b (Hidden behind conductive element 461), the vertical conductive element 442 connects conductive element 461 and conductive element 452. Thus, both cross-coupled conductors are included in the segments 461, 462 extending within the intermediate layer.

[0133] according to Figure 18bThe access FET 410b includes a gate, which is connected to a word line 453. The gate of the FET 415b may also be connected to the word line 453. The word line 453 may extend in the same layer as the gate of the access FET 410b. Specifically, the word line 453 and the access FET 410b of the SRAM cell 400 may be formed as a single unit. This can further reduce the manufacturing complexity of the integrated circuit 400.

[0134] like Figure 19b As shown, the signal terminals of stacks 410 and 415 are connected to the corresponding bit lines 482 and 481.

[0135] The power support terminals of stacks 410 and 415 are connected to power rail 491, and the power support terminals of FETs 416 and 417 are connected to power rail 492, as shown. Figure 20b As shown.

[0136] exist Figure 13b-20b In the embodiment shown, the word line 453 extends in direction P perpendicular to the extension direction of the power rail 491. T The width of the word line 453 is only slightly larger than the gate of the access FET 410b. In other embodiments, a wider word line 453 may also be provided, extending above FETs 416 and 417. The word line 453 may be electrically connected in the direction P along the power rails 491 and 492. L The upper part provides access FETs for multiple SRAM cells. Therefore, word line 453 can allow data to be read from or written to multiple SRAM cells in parallel. Furthermore, word line 453 can extend parallel to power rail 491. More SRAM cells can be addressed through a wider word line 453.

[0137] Bit line 481 extends perpendicular to power rail 491. Bit line 481 can be connected in a direction P that extends laterally to power rail 391. L Direction P T Multiple SRAM cells are provided on the top. Another line 482 may be provided parallel to bit line 481.

[0138] Word lines 453, bit lines 481 / 482, and power rails 491 / 492 can be located in different layers of integrated circuit 400. This allows for a large two-dimensional array of SRAM cells without the need for special bridging structures to insulate the intersecting word lines / bit lines.

[0139] according to Figure 21 and 22The embodiment shown may provide an integrated circuit 500 comprising multiple adjacent layers, the integrated circuit including mirror-symmetric SRAM cells 501 and 502. SRAM cells 501 and 502 may correspond to SRAM cells of integrated circuit 300. The plane of symmetry of the two mirror-symmetric SRAM cells 501 and 502 may extend perpendicular to the layers of integrated circuit 500 and parallel to power rails 591, 592, and 593. The two mirror-symmetric SRAM cells 501 and 502 may share power rail 591.

[0140] For example, two mirror-symmetric SRAM cells 501 and 502 can share a power rail 591 connected to the stack of SRAM cells 501 and 502.

[0141] In addition, there are two mirror-symmetric SRAM cells 501 and 503 (SRAM cell 503 is in...) Figure 21 (Only partially depicted in the image) can share a power rail 593 connected to the second inverter FET of SRAM cells 501 and 503.

[0142] Therefore, wider power rails 591, 592, and 593 can be used to drive SRAM cells. This can mitigate voltage fluctuations when reading / writing SRAM cells connected to a common word line. Furthermore, the extension direction P transverse to power rails 591 and 592 can be reduced. L Direction P T The distance between SRAM cells on the device.

[0143] Integrated circuit 500 includes a pair of two additional SRAM cells 504 and 505. The two additional SRAM cells 504 and 505 are shifted versions of the SRAM cells 501 and 502. The array of SRAM cells can be formed by providing SRAM cells that are shifted even further along power rails 591, 592, and 593 and by continuing to provide mirror-symmetric SRAM cells in a direction perpendicular to power rails 591, 592, and 593.

[0144] like Figure 22 As shown, word line 553 can be used to address SRAM cells 501 and 504. Correspondingly, word line 554 can be used to address SRAM cells 502 and 505. Word line 553 can extend only along a vertical structure including two FETs, and not over a vertical structure including only one FET. SRAM cells can be read / written using bit line 581, complementary bit line 582, bit line 583, and complementary bit line 584. Thus, an integrated circuit with alternating bit lines and complementary bit lines can be provided.

[0145] Figure 23 It shows the relationship with Figure 21 and 22The integrated circuit 500 shown is very similar to another integrated circuit 600. Features 684, 683, 682, 681, 603, 693, 604, 605, 601, 691, 602, and 692 correspond to features 584, 583, 582, 581, 503, 593, 504, 505, 501, 591, 502, and 592 (…). Figure 22 (As shown). However, word lines 653 and 654 are different from word lines 553 and 554 (as shown). Figure 22 (As shown in the diagram). In particular, word lines 653 and 654 also extend above the vertical structure that includes only one FET. The wider word lines 653 and 654 can allow more SRAM cells to be addressed.

[0146] Figure 24 Another integrated circuit 700 is shown. Integrated circuits with features 703, 793, 704, 705, 701, 791, 702, and 792 essentially correspond to... Figure 21 The integrated circuit 500 is shown. However, SRAM cells 704 and 705 are mirror-symmetric versions of SRAM cells 701 and 702, not just shifted versions. This allows for a configuration where two bit lines are followed by two complementary bit lines, and these complementary bit lines are followed by two more bit lines.

[0147] Figure 25 Another integrated circuit 800 comprising multiple adjacent layers is shown. The integrated circuit includes a vertical structure extending in a vertical direction V substantially perpendicular to the layers of the integrated circuit. The vertical structure includes a vertical connection element 841, a stack 810 of two FETs each including a vertical channel region, and a FET 817 also including a vertical channel region.

[0148] Vertical structures 841, 810, and 817 are arranged above node N of the virtual two-dimensional regular mesh G. Mesh G exhibits translational symmetry. The longitudinal spacing G between two nodes of the mesh is [missing information]. L Unlike the lateral spacing G between two nodes in the grid, T In this context, the longitudinal direction is perpendicular to the transverse direction. However, other implementations may specify the longitudinal spacing G between two nodes of the mesh. L The lateral spacing G between two nodes of the grid in the lateral direction T same.

[0149] Figure 26 Another virtual two-dimensional regular grid G ​​with nodes N is shown, above which vertical structures can be arranged. Grid G ​​has a hexagonal structure.

[0150] Different components of an integrated circuit can be embedded in an electrically insulating material. For example, the "open" space can be filled with semiconductor oxide.

[0151] In the embodiment depicted in the accompanying drawings of this application, the power rails have been shown below the channel region of the FET and above the signal lines. However, a mirrored arrangement is also conceivable, in which the signal lines are positioned below the channel region of the FET and the power rails are positioned above the channel region of the FET.

[0152] Integrated circuits can include a stack of two FETs of the same type and a stack of two FETs of the same type but a different type from the first stack. Specifically, one stack can belong to a NAND cell, while the other stack can belong to a NOR cell. The two stacks can be provided as a vertical structure on different power rails.

[0153] Various embodiments of the invention have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or technical improvements found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A microelectronic device comprising a plurality of layers, the microelectronic device comprising: a first pair of transistors stacked vertically and connected in series, each of the first pair of transistors being of a same type; and a second pair of transistors connected in parallel and arranged in a same layer of the plurality of layers, the second pair of transistors being of a different type than the first pair of transistors, wherein the second pair of transistors are connected in series with the first pair of transistors, and wherein the second pair of transistors are connected together by an internal connection element arranged in the same layer, wherein the first pair of transistors and the second pair of transistors are arranged perpendicular to the plurality of layers, wherein a gate of a first transistor of the first pair of transistors and a gate of a first transistor of the second pair of transistors are connected to each other and correspond to a first input of the microelectronic device, wherein the gate of the first transistor of the first pair of transistors and the gate of the first transistor of the second pair of transistors are arranged in the same layer of the microelectronic device, wherein a gate of a second transistor of the first pair of transistors and a gate of a second transistor of the second pair of transistors are connected to each other and correspond to a second input of the microelectronic device, wherein the gate of the second transistor of the first pair of transistors and the gate of the second transistor of the second pair of transistors are arranged in different layers of the plurality of layers of the microelectronic device, and wherein channel regions of the first and second pairs of transistors are disposed in layers between layers comprising a VDD power rail and a ground power rail of the microelectronic device and layers comprising signal interconnect conductors of the microelectronic device.

2. The microelectronic device of claim 1, wherein, the VDD power rail is connected to one end of the first pair of transistors stacked vertically, the ground power rail is connected to the second pair of transistors, and the signal interconnect conductors are connected to opposite ends of the first pair of transistors stacked vertically.

3. The microelectronic device of claim 1, wherein the microelectronic device is a NAND gate or a NOR gate.

4. A method of forming a microelectronic device comprising a plurality of layers, the method comprising: forming a first pair of transistors stacked vertically and connected in series, each of the first pair of transistors being of a same type; forming a second pair of transistors connected in parallel and arranged in a same layer of the plurality of layers, the second pair of transistors being of a different type than the first pair of transistors, wherein the second pair of transistors are connected in series with the first pair of transistors; and forming an internal connection element arranged in the same layer and connecting the second pair of transistors together, wherein the first pair of transistors and the second pair of transistors are formed perpendicular to the plurality of layers, wherein a gate of one of the first pair of transistors and a gate of one of the second pair of transistors are connected to each other and correspond to a first input of the microelectronic device, wherein the gate of the one of the first pair of transistors and the gate of the one of the second pair of transistors are arranged in a same layer of the microelectronic device, wherein a gate of one of the first pair of transistors and a gate of one of the second pair of transistors are connected to each other and correspond to a second input of the microelectronic device, wherein the gate of the one of the first pair of transistors and the gate of the one of the second pair of transistors are arranged in different layers of the microelectronic device, and wherein channel regions of the first and second pairs of transistors are disposed in a layer between a layer comprising a VDD power rail and a ground power rail of the microelectronic device and a layer comprising a signal interconnect conductor of the microelectronic device.

5. The method of claim 4, wherein, the VDD power rail is connected to one end of the first pair of transistors in the vertical stack, the ground power rail is connected to the second pair of transistors, and the signal interconnect conductor is connected to an opposite end of the first pair of transistors in the vertical stack.

6. The method of claim 4, wherein the microelectronic device is a NAND gate or a NOR gate.

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