Semiconductor package structure and method of forming the same

Abstract

This invention provides a semiconductor package structure, comprising: a package including a chip located within the package; a thermoelectric cooler located on the upper surface of the package and having a plurality of through-holes; and a plurality of connectors connecting the package and the thermoelectric cooler, wherein the thermoelectric cooler has a first portion located at a position corresponding to the chip, the first portion having a greater thickness or a higher density of through-holes than other portions. The purpose of this invention is to provide a semiconductor package structure and a method for forming the same, to improve the heat dissipation of the semiconductor package structure.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor packaging structure and a method for forming the same. Background Art

[0002] In traditional packaging structures, the high temperatures generated by chip operation can cause temperature differences between the center and the edges of the packaging structure. These temperature differences can lead to problems such as warping, deformation, or poor bonding of the packaging structure. In severe cases, it can even cause open circuits in the entire electronic device. The larger the size of the packaging structure or the higher the load, the more serious this problem will be. Summary of the Invention

[0003] In view of the problems existing in related technologies, the purpose of this invention is to provide a semiconductor packaging structure and a method for forming the same, so as to improve the heat dissipation of the semiconductor packaging structure.

[0004] To achieve the above objectives, the present invention provides a semiconductor packaging structure, comprising: a package including a chip located within the package; a thermoelectric cooler located on the upper surface of the package and having a plurality of through holes; and a plurality of connectors connecting the package and the thermoelectric cooler, wherein the thermoelectric cooler has a first portion located at a position corresponding to the chip, the first portion having a greater thickness or a higher density of through holes than other portions.

[0005] In some embodiments, the diameter of the through-hole in the thermoelectric cooler gradually decreases toward the package.

[0006] In some embodiments, the thermoelectric cooler is formed by alternating stacks of dielectric layers and redistribution lines, with vias disposed between the stacked redistribution lines to electrically connect the multiple redistribution lines, and the vias comprising N-type material / P-type material.

[0007] In some embodiments, the number of dielectric layers and redistribution lines in the first portion is greater than the number of dielectric layers and redistribution lines in the other portions.

[0008] In some embodiments, the line width / spacing of the redistribution lines in the first part is smaller than the line width / spacing of the redistribution lines in other parts, and the diameter of the through-hole in the first part is smaller than the diameter of the through-hole in other parts.

[0009] In some embodiments, the thermoelectric cooling element includes a cold end face and a hot end face disposed opposite to the cold end face, the cold end face being connected to the upper surface of the package via a plurality of connectors.

[0010] In some embodiments, a plurality of connectors are formed as solder or bumps.

[0011] In some embodiments, a capillary bottom filler adhesive covering a plurality of connectors is further provided between the package and the thermoelectric cooling element.

[0012] In some embodiments, an adhesive material covering a plurality of connectors is further provided between the package and the thermoelectric cooling element.

[0013] In some embodiments, the first portion of the thermoelectric cooler is located directly above the chip.

[0014] In some embodiments, the package further includes: leads that electrically connect pads on the upper surface of the package that are not covered by the thermoelectric cooler to the upper surface of the thermoelectric cooler.

[0015] In some embodiments, the package encapsulates multiple chips, with a first portion covering the multiple chips and other portions located on both sides of the first portion.

[0016] In some embodiments, the thermoelectric cooler includes a first thermoelectric cooler covering the upper surface of the package and a second thermoelectric cooler located on the first thermoelectric cooler, the second thermoelectric cooler being located directly above the chip in the height direction, and the first portion including the second thermoelectric cooler.

[0017] In some embodiments, the thermoelectric cooling chip includes a third thermoelectric cooling chip and a fourth thermoelectric cooling chip arranged side by side covering the upper surface of the package, and a second thermoelectric cooling chip located on the third thermoelectric cooling chip and the fourth thermoelectric cooling chip, the first part including the second thermoelectric cooling chip.

[0018] In some embodiments, a method for forming a semiconductor package structure is provided, comprising: providing a package and encapsulating a chip within the package; forming a thermoelectric cooler having a plurality of connectors disposed on its lower surface; and connecting the plurality of connectors to an upper surface of the package, wherein the thermoelectric cooler has a first portion located at a position corresponding to the chip, the first portion having a greater thickness or a higher density of vias than other portions.

[0019] In some embodiments, the diameter of the through-hole in the thermoelectric cooler is formed to gradually decrease from top to bottom.

[0020] In some embodiments, the diameter of the through hole is formed to gradually decrease in the direction toward the cold end face of the thermoelectric cooler and gradually increase in the direction toward the hot end face of the thermoelectric cooler.

[0021] In some embodiments, the cold end face is connected to the upper surface of the package via a plurality of connectors.

[0022] In some embodiments, the step of forming a thermoelectric cooler with through holes includes: forming redistribution lines on a carrier; forming a dielectric layer on the redistribution lines; forming a first opening in the dielectric layer to expose the redistribution lines; filling the first opening with an N-type material; forming a second opening in the dielectric layer to expose the redistribution lines; and filling the second opening with a P-type material.

[0023] In some embodiments, the step of forming the redistribution line includes: forming a mask layer on a carrier; removing a portion of the mask layer to form a third opening; forming a metallic material at the bottom of the third opening; and removing the remaining portion of the mask layer to form a redistribution line comprising the metallic material. Attached Figure Description

[0024] Figures 1 to 30 The sequential formation process of a semiconductor package structure according to an embodiment of this application is illustrated.

[0025] Figures 31 to 41 A schematic diagram of a semiconductor package structure according to different embodiments of this application is shown. Detailed Implementation

[0026] To better understand the spirit of the embodiments of this application, the following description is based on some preferred embodiments of this application.

[0027] Embodiments of this application will be described in detail below. Throughout this specification, identical or similar components and components having identical or similar functions are indicated by similar reference numerals. The embodiments described herein with reference to the accompanying drawings are illustrative and diagrammatic in nature and are intended to provide a basic understanding of this application. The embodiments of this application should not be construed as limiting this application.

[0028] As used herein, the terms “approximately,” “generally,” “substantially,” and “about” are used to describe and indicate small variations. When used in conjunction with an event or situation, the terms may refer to examples in which the event or situation occurred precisely and examples in which the event or situation occurred very approximately. For example, when used in conjunction with numerical values, the terms may refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two values ​​is less than or equal to ±10% of the average of the values ​​(e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%), then the two values ​​can be considered "substantially" the same.

[0029] In this specification, unless otherwise specified or limited, relative terms such as “central,” “longitudinal,” “lateral,” “front,” “rear,” “right,” “left,” “inner,” “outer,” “lower,” “higher,” “horizontal,” “vertical,” “above,” “below,” “above,” “below,” “top,” “bottom,” and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.) should be interpreted as referring to the directions described in the discussion or depicted in the accompanying drawings. These relative terms are used for descriptive convenience only and do not require that this application be constructed or operated in a particular orientation.

[0030] Additionally, quantities, ratios, and other numerical values ​​are sometimes presented in range format in this document. It should be understood that such range format is for convenience and brevity and should be interpreted flexibly to include not only the numerical values ​​explicitly specified as range limits, but also all individual numerical values ​​or subranges covered within the range, as if each numerical value and subrange were explicitly specified.

[0031] Furthermore, for ease of description, "first," "second," "third," etc., can be used in this article to distinguish different components of a figure or a series of figures. "First," "second," "third," etc., are not intended to describe the corresponding components.

[0032] Because the temperature of the heat source is higher than that of other locations, a temperature difference will inevitably occur between the heat source and other locations when the system is under load. Even using a uniformly thick TEG (Transformer Electrode Gas) on the surface of the package for heat dissipation can still cause warping, deformation, and even poor connection of connectors, ultimately leading to open circuits and other problems. This problem becomes more pronounced with larger package sizes and / or higher loads. TEG is typically made of flexible circuit board materials, which have relatively low strength and limited stress balancing capabilities, therefore it can only be used to encapsulate cooling materials.

[0033] The semiconductor packaging structure and its formation method of this application will be explained in detail below with reference to the accompanying drawings.

[0034] Reference Figure 1 A first seed layer 12 is formed on the carrier 10. In this embodiment, the first seed layer 12 can be formed by a physical vapor deposition (PVD) process.

[0035] Reference Figure 2 A first mask layer 20 is formed on the first seed layer 12. The first mask layer 20 may include a photoresist (PR) material, and an exposure process 21 is performed to cure the first mask layer 20.

[0036] Reference Figure 3The first mask layer 20 is patterned and a first metal layer 30 is formed in the patterned first mask layer 20.

[0037] Reference Figure 4 Remove the patterned first mask layer 20, and use the first metal layer 30 as a mask to etch the first seed layer 20 so that the first seed layer 20 has the same pattern as the first metal layer 30.

[0038] See Figure 5 The semiconductor device 52 is placed on the adjacent first metal layer 30 using a clamp 50. During the clamping process, the clamp 50 and the semiconductor device 52 are in a vacuum state.

[0039] Reference Figure 6 A first dielectric layer 60 is formed covering the first metal layer 30 and the first seed layer 20. In an embodiment, the first dielectric layer 60 may include a polyamide (PA) material, and the first dielectric layer 60 is subjected to an exposure process 61 for curing.

[0040] See Figure 7 A first opening 71 and a second opening 72 are formed in the first dielectric layer 60 in succession to expose the first metal layer 30.

[0041] See Figure 8 The first thermoelectric material 84 is filled into the first opening 71 using a first mask 80 and an extrusion tool 82, wherein the first mask 80 covers the second opening 72 and the opening of the first mask 80 is aligned with the first opening 71.

[0042] See Figure 9The second thermoelectric material 94 is filled into the second opening 72 using a second mask 90 and an extrusion tool 92, wherein the second mask 90 covers the first thermoelectric material 84, and the opening of the second mask 90 is aligned with the second opening 72. In an embodiment, the first thermoelectric material 124 is a P-type material, and the second thermoelectric material 125 is an N-type material to form N-type electrodes and P-type electrodes, respectively. In an embodiment, the N-type electrode and the P-type electrode are regular polygons (e.g., squares or equilateral triangles), circles, or irregular shapes in a top view. In an embodiment, the N-type electrode and the P-type electrode are connected in series or in parallel. In other embodiments, the first thermoelectric material 124 is an N-type material, and the second thermoelectric material 125 is a P-type material. When two conductors or semiconductors of different states (N-type or P-type) have a temperature difference (ΔT) at their junctions, a current will be generated if the circuit is closed, and a potential difference (V) will be generated if the circuit is open. This is the Seebeck effect in thermoelectric effects. When a voltage is applied to a closed circuit formed by two conductors or semiconductors of different states (N-type or P-type), a current will be generated, resulting in heat absorption at one end and heat release at the other end at the junctions. This is the Peltier effect in thermoelectric effects. This effect can occur at the interface between two different materials, between different phase boundaries of a multiphase material, or within different concentration gradients of heterogeneous materials. When current flows through a single conductor or semiconductor with non-uniform temperature, in addition to irreversible Joule heating, it will also absorb or release a certain amount of heat (called Thomson heating). Conversely, when the two ends of a single conductor or semiconductor have different temperatures, a potential difference (Emf) will be formed between the two ends of the material. This is the Thomson effect. (Effect). In the embodiments, the p-type material may be SiGe, SiGe / GaP, CeFe. 3.5 Co 0.5 Sb 12 Zn4Sb3, Bi 0.25 Sb 0.75 Te3, etc. N-type materials can be PbTe, SiGe, Bi2Te, etc. 2.7 Se 0.3 CoSb3, Zn4Sb3, etc.

[0043] See Figure 10 A second seed layer 100 is formed on the first dielectric layer 60. In an embodiment, the second seed layer 100 can be formed by a physical vapor deposition (PVD) process. In an embodiment, the second seed layer 100 comprises copper and titanium.

[0044] See Figure 11A third mask layer 110 is formed on the second seed layer 100. The third mask layer 110 may include a photoresist (PR) material, and an exposure process 111 is performed to cure the third mask layer 110.

[0045] Reference Figure 12 The third mask layer 110 is patterned to expose the second seed layer 100. A second metal layer 120 is then formed on the exposed second seed layer 100.

[0046] See Figure 13 Remove the patterned third mask layer 110, and use the second metal layer 120 as a mask to etch the second seed layer 100 so that the second seed layer 100 has the same pattern as the second metal layer 120.

[0047] See Figure 14 A second dielectric layer 140 is formed covering the second seed layer 100 and the second metal layer 120. In an embodiment, the second dielectric layer 140 may include a polyamide (PA) material, and the second dielectric layer 140 is subjected to a heating process 141.

[0048] See Figure 15 A third seed layer 150 is formed on the second dielectric layer 140. In this embodiment, the third seed layer 150 can be formed by a physical vapor deposition (PVD) process.

[0049] See Figure 16 A fourth mask layer 160 is formed on the third seed layer 150. The fourth mask layer 160 may include a photoresist (PR) material, and an exposure process 161 is performed to cure the fourth mask layer 160.

[0050] See Figure 17 The fourth mask layer 160 is patterned to expose the third seed layer 150. A third metal layer 170 is then formed on the exposed third seed layer 150.

[0051] See Figure 18 Remove the patterned fourth mask layer 160, and use the third metal layer 170 as a mask to etch the third seed layer 150 so that the third seed layer 150 has the same pattern as the third metal layer 170.

[0052] See Figure 19 A third dielectric layer 190 is formed covering the third metal layer 170. In an embodiment, the third dielectric layer 190 may include a polyamide (PA) material, and an exposure process 191 is performed on the third dielectric layer 190 to cure it.

[0053] See Figure 20A third opening 201 and a fourth opening 202 are formed in the third dielectric layer 190 in succession to expose the third metal layer 170.

[0054] See Figure 21 The first thermoelectric material 84 is filled into the third opening 201 using the fifth mask 210 and the extrusion tool 212, wherein the fifth mask 210 covers the fourth opening 202 and the opening of the fifth mask 210 is aligned with the third opening 201.

[0055] See Figure 22 The second thermoelectric material 94 is filled into the fourth opening 202 using a sixth mask 220 and an extrusion tool 222, wherein the sixth mask 220 covers the first thermoelectric material 84, and the opening of the sixth mask 220 is aligned with the fourth opening 202. In one embodiment, the first thermoelectric material 124 is a P-type material, and the second thermoelectric material 125 is an N-type material. In other embodiments, the first thermoelectric material 124 is an N-type material, and the second thermoelectric material 125 is a P-type material.

[0056] See Figure 23 The etching process passes through the openings of the third dielectric layer 190 and the second dielectric layer 140, forming a fourth seed layer 230 in the openings and on the third dielectric layer 190. In an embodiment, the fourth seed layer 230 can be formed by a physical vapor deposition (PVD) process.

[0057] See Figure 24 A seventh mask layer 240 is formed on the fourth seed layer 230. The seventh mask layer 240 may include a photoresist (PR) material, and an exposure process 241 is performed to cure the seventh mask layer 240.

[0058] See Figure 25 The seventh mask layer 240 is patterned to expose the fourth seed layer 230. A fourth metal layer 250 is then formed on the exposed fourth seed layer 230.

[0059] See Figure 26 Remove the patterned seventh mask layer 240, and use the fourth metal layer 250 as a mask to etch the fourth seed layer 230 so that the fourth seed layer 230 has the same pattern as the fourth metal layer 250.

[0060] See Figure 27 A fourth dielectric layer 270 is formed covering the fourth metal layer 250. In an embodiment, the fourth dielectric layer 270 may include a polyamide (PA) material, and an exposure process 271 is performed on the fourth dielectric layer 270 to cure it.

[0061] refer to Figures 28 to 29The carrier 10 is removed to form a first thermoelectric cooler 280, and a plurality of connectors 290 are formed on the exposed first seed layer 12 of the first thermoelectric cooler 280. In an embodiment, the connectors 290 are formed as solder balls.

[0062] refer to Figure 30 A first thermoelectric cooler 280 is placed on a package 312, and a second thermoelectric cooler 314 is placed on the first thermoelectric cooler 280. The second thermoelectric cooler 314 is aligned with the chip 316 of the package 312 to form the semiconductor package structure 300 of this application.

[0063] refer to Figure 31 ,and Figure 29 In contrast, in this embodiment, the connector 290 is formed as a micro-bump.

[0064] refer to Figure 32 Fibers 320 are also formed in the first dielectric layer 60 and the second dielectric layer 140. In embodiments including and / or excluding fibers 320, the first dielectric layer 60 and the second dielectric layer 140 may be organic dielectrics, such as polyimide (PI), epoxy resin, polybenzoxazole (PBO), flame retardant grade 4 material (FR4), prepreg resin (PP), Ajinomoto build-up film (ABF), bismaleimide triazine resin (BT), photosensitive and / or non-photosensitive liquids. In embodiments excluding fibers 320, the first dielectric layer 60 and the second dielectric layer 140 may be inorganic electrolytes, such as silicon, glass, ceramics, oxides (e.g., SiOx, TaOx), and nitrides (e.g., SiNx).

[0065] refer to Figure 33 The connector 290 is also filled with capillary bottom filler (CUF) 330.

[0066] refer to Figure 34 Additionally, the first thermoelectric cooler 280 and the package 312 are connected via lead wire 340.

[0067] refer to Figure 35 The first thermoelectric cooling element 280 includes multiple units.

[0068] refer to Figure 36 ,and Figure 29 Compared to the connector 290, which includes connectors for input and output, Figure 36 Connector 290 is for input only.

[0069] refer to Figure 37 ,and Figure 29 Compared to the connector 290, which includes connectors for input and output, Figure 37 Connector 290 is for output only.

[0070] refer to Figure 38 Chip 316 comprises multiple chips arranged side-by-side. (Reference) Figure 39 The chip 316 is formed to occupy a larger area in the package 312.

[0071] refer to Figure 40 The thermoelectric cooling element includes a third thermoelectric cooling element 390 and a fourth thermoelectric cooling element 392 arranged side by side on the upper surface of the package 31, and a second thermoelectric cooling element 314 located on the third thermoelectric cooling element 390 and the fourth thermoelectric cooling element 392.

[0072] refer to Figure 41 A balancing film 400 is also formed on the first thermoelectric cooler 280 to further reduce the possibility of warping. The balancing film 400 may include one or more of copper, nickel, titanium, tungsten or platinum alloys and / or non-metals (e.g., PI, ABF, epoxy resin or solder resist ink).

[0073] This invention discloses a packaging structure and its manufacturing method that utilizes a thermoelectric cooler for heat dissipation. The main feature is a thermoelectric generator (TEG), fabricated using the principle of direct current to generate a temperature difference and encapsulated by a flexible circuit board, placed externally to the heat source (e.g., a power management chip) of the packaging structure. This effectively dissipates the high temperatures generated during packaging structure operation to the outside, effectively preventing warping, deformation, and poor bonding caused by high temperatures. It also prevents delamination caused by thermal expansion of the flexible circuit board material. Therefore, the through-holes for placing the cooling material are trapezoidal in shape, with the larger opening located at a location of high stress (generally the surface of the packaging structure) to effectively resist the tensile stress generated by thermal stress. The TEG made of flexible circuit board can be attached to any curved surface. When the flexible circuit board is attached to the surface of the packaging structure, the surface thin film effect effectively resists the tensile stress of the packaging structure, reducing warping. In the embodiments, the thermal dissipation efficiency of the test chip was measured when the temperature rose from room temperature to 400°C. The thermal dissipation efficiency of the package structure with thermoelectric cooling chip in this application is 1.6 to 4 times that of a general package and 5 times that of a simple IC chip.

[0074] This invention provides a semiconductor package structure 300, comprising: a package 312 including a chip 316 located within the package 312; thermoelectric coolers (280, 314, etc.) located on the upper surface of the package 312 and having a plurality of vias (parts of a fourth seed layer 230 and a fourth metal layer 250 extending into a third dielectric layer 190 and a second dielectric layer 140); and a plurality of connectors 290 connecting the package 312 and the thermoelectric coolers, wherein the thermoelectric coolers have a first portion located at a position corresponding to the chip 312 (e.g., a portion of all thermoelectric coolers projected upward from the chip 312), the first portion having a greater thickness or a higher density of vias than other portions. In some embodiments, the diameter of the vias in the thermoelectric coolers gradually decreases toward the package 312. In some embodiments, the thermoelectric cooler 312 is formed by alternating stacks of dielectric layers (60, 140, 190) and redistribution lines (lateral extensions of seed layers and metal layers in the dielectric layers), with vias disposed between the stacked redistribution lines to electrically connect the multiple redistribution lines. The vias include N-type / P-type materials. In some embodiments, the number of dielectric layers and redistribution lines in the first portion is greater than the number of dielectric layers and redistribution lines in the other portions. In some embodiments, the linewidth / spacing of the redistribution lines in the first portion is smaller than the linewidth / spacing of the redistribution lines in the other portions, and the diameter of the vias in the first portion is smaller than the diameter of the vias in the other portions. In some embodiments, the thermoelectric cooler includes a cold end face and a hot end face disposed opposite to the cold end face, the cold end face being connected to the upper surface of the package 312 via a plurality of connectors 290. In some embodiments, the plurality of connectors 290 are formed as solder or bumps. In some embodiments, a capillary bottom filler 330 covering a plurality of connectors 290 is further disposed between the package 312 and the thermoelectric cooler. In some embodiments, an adhesive material covering a plurality of connectors is further disposed between the package 312 and the thermoelectric cooler. In some embodiments, a first portion of the thermoelectric cooler is located directly above the chip. In some embodiments, it further includes: a lead 340 electrically connecting pads not covered by the thermoelectric cooler on the upper surface of the package 312 to the upper surface of the thermoelectric cooler 280. In some embodiments, the package 312 encapsulates a plurality of chips 316, a first portion covering the plurality of chips, and other portions located on both sides of the first portion. In some embodiments, the thermoelectric cooler includes a first thermoelectric cooler 280 covering the upper surface of the package 312 and a second thermoelectric cooler 314 located on the first thermoelectric cooler, the second thermoelectric cooler 314 being located directly above the chip 316 in the height direction, and the first portion including the second thermoelectric cooler 314.In some embodiments, the thermoelectric cooler includes a third thermoelectric cooler 390 and a fourth thermoelectric cooler 392 arranged side by side covering the upper surface of the package, and a second thermoelectric cooler 280 located on the third thermoelectric cooler 390 and the fourth thermoelectric cooler 392, the first part including the second thermoelectric cooler 280.

[0075] In some embodiments, a method for forming a semiconductor package structure is provided, comprising: providing a package 312 and encapsulating a chip 316 within the package 312; forming a thermoelectric cooler with a plurality of connectors 290 disposed on its lower surface; and connecting the plurality of connectors 290 to the upper surface of the package 312, wherein the thermoelectric cooler has a first portion located at a position corresponding to the chip 316, the first portion having a greater thickness or a higher density of vias than other portions. In some embodiments, the diameter of the vias in the thermoelectric cooler 316 is formed to gradually decrease from top to bottom. In some embodiments, the diameter of the vias is formed to gradually decrease in the direction toward the cold end face of the thermoelectric cooler and gradually increase in the direction toward the hot end face of the thermoelectric cooler. In some embodiments, the cold end face is connected to the upper surface of the package via the plurality of connectors. In some embodiments, the step of forming a thermoelectric cooler with through-holes includes: forming redistribution lines on a carrier 10; forming a dielectric layer on the redistribution lines; forming a first opening in the dielectric layer to expose the redistribution lines; filling the first opening with an N-type material; forming a second opening in the dielectric layer to expose the redistribution lines; and filling the second opening with a P-type material. In some embodiments, the step of forming the redistribution lines includes: forming a mask layer on a carrier; removing a portion of the mask layer to form a third opening; forming a metallic material at the bottom of the third opening; and removing the remaining portion of the mask layer to form redistribution lines comprising the metallic material.

[0076] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A semiconductor packaging structure, characterized in that, include: A package, including a chip located within the package; A thermoelectric cooling element is located on the upper surface of the package and has a plurality of through holes; as well as A plurality of connectors connect the package to the thermoelectric cooling element. The thermoelectric cooling element has a first portion located at a position corresponding to the chip, and this first portion has a greater thickness or a higher density of through-holes than other portions. The thermoelectric cooling chip is composed of alternating stacked dielectric layers and redistribution lines, and the through-holes are disposed between the stacked redistribution lines to electrically connect the multiple layers of redistribution lines.

2. The semiconductor packaging structure according to claim 1, characterized in that, The diameter of the through hole in the thermoelectric cooling element gradually decreases towards the package.

3. The semiconductor packaging structure according to claim 1, characterized in that, The through-hole includes N-type material / P-type material.

4. The semiconductor packaging structure according to claim 1, characterized in that, The first part has more dielectric layers and redistribution lines than the other parts.

5. The semiconductor packaging structure according to claim 1, characterized in that, The line width / spacing of the redistribution lines in the first part is smaller than the line width / spacing of the redistribution lines in the other parts, and the diameter of the through hole in the first part is smaller than the diameter of the through hole in the other parts.

6. The semiconductor packaging structure according to claim 1, characterized in that, The thermoelectric cooling element includes a cold end face and a hot end face opposite to the cold end face, and the cold end face is connected to the upper surface of the package through the plurality of connectors.

7. The semiconductor packaging structure according to claim 1, characterized in that, A capillary bottom filler adhesive covering the plurality of connectors is also provided between the encapsulation component and the thermoelectric cooling chip.

8. The semiconductor packaging structure according to claim 1, characterized in that, An adhesive material covering the plurality of connectors is also provided between the package and the thermoelectric cooling element.

9. The semiconductor packaging structure according to claim 1, characterized in that, Also includes: Leads are used to electrically connect the pads on the upper surface of the package that are not covered by the thermoelectric cooler to the upper surface of the thermoelectric cooler.

10. The semiconductor packaging structure according to claim 1, characterized in that, The package encapsulates multiple chips, the first portion covers the multiple chips, and the other portions are located on both sides of the first portion.

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