Semiconductor package device and method of manufacturing the same

Abstract

The present disclosure provides a semiconductor packaging device and a manufacturing method thereof. By embedding a functional chip at least partially in a wide-to-narrow accommodation cavity on a bridge layer, and by arranging a protrusion and a recess on both sides of the functional chip to correspond to a recess and a protrusion on both sides of the bridge chip, and by making the side surfaces of the recess and the protrusion on both sides of the bridge chip be inclined surfaces, the bonding offset of the functional chip can be effectively controlled by the inclined surfaces of the recess and the protrusion on both sides of the bridge chip, so as to achieve accurate alignment in a fine-pitch semiconductor packaging device, thereby improving the electrical yield.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor packaging technology, and more particularly to a semiconductor packaging device and a manufacturing method thereof. Background Art

[0002] With the development of electronic products, the demand for multifunctionality and thinner and lighter products is increasing dramatically. This is forcing a dramatic increase in the number of I / O (input / output) within products, coupled with an increasing adoption of fine pitch designs. However, to accommodate more circuit patterns within a unit area or volume, the line / space dimensions of the product's conductors and conductive vias must also be reduced accordingly.

[0003] However, the accuracy of traditional die attach is affected by machine systems (e.g., the transmission system, nozzle size and structure, imaging system, or actuation principle). The minimum variation is approximately 1 to 2 microns. This accuracy can lead to significant bonding shift for dies with a bonding pitch less than 10 microns, ultimately resulting in a low electrical functional yield, typically below 70% in practice. Summary of the Invention

[0004] The present disclosure provides a semiconductor packaging device and a method for manufacturing the same.

[0005] In a first aspect, the present disclosure provides a semiconductor packaging device, comprising: a bridge layer including at least two horizontally spaced bridge chips, the bridge chips comprising a chip and a dielectric layer covering the chip, the bridge chips having convex and concave portions spaced apart on both sides, the convex and concave portions of the bridge chips having inclined side surfaces, and a cavities wide at the top and narrow at the bottom formed between two adjacent bridge chips;

[0006] A functional chip is at least partially embedded in the accommodating cavity, the functional chip comprising an insulating isolation layer and a chip disposed within the insulating isolation layer, the functional chip having convex and concave portions spaced apart on both sides, the convex and concave portions of the functional chip having inclined side surfaces, the convex and concave portions of the functional chip respectively correspondingly engaging with the concave and convex portions of the bridging chip on both sides of the accommodating cavity in which the functional chip is embedded;

[0007] The protection layer is disposed on the functional chip and covers the functional chip.

[0008] In some optional embodiments, the longitudinal cross-section of the convex portion and the concave portion of the bridge chip, excluding the dielectric layer portion, is a trapezoid with an upper side length smaller than a lower side length.

[0009] In some optional embodiments, two inner angles of the trapezoidal bottom of the longitudinal interface between the convex portion and the concave portion of the bridge chip, excluding the dielectric layer portion, are respectively between 30° and 80°.

[0010] In some optional embodiments, the difference between the lower side length and the upper side length of the trapezoid excluding the dielectric layer portion in the longitudinal interface between the convex portion and the concave portion of the bridge chip is between 7 and 160 microns.

[0011] In some optional embodiments, the vertical height of the bridge chip excluding the dielectric layer portion is 10 to 50 microns.

[0012] In some optional embodiments, the bottom horizontal width of the longitudinal cross-section of the accommodating cavity, the bottom horizontal width of the longitudinal cross-section of the functional chip, and the top horizontal width of the longitudinal cross-section of the functional chip are arranged from small to large.

[0013] In some optional implementations, the vertical height of the functional chip embedded in the accommodating cavity portion is less than the minimum height of each of the bridge chips.

[0014] In some optional embodiments, the semiconductor packaging device includes at least two functional chips disposed in the accommodating cavity.

[0015] In some optional embodiments, the at least two function chips include a first function chip and a second function chip respectively arranged on both sides of the bridge chip, and the first function chip and the second function chip are electrically connected through the bridge chip.

[0016] In some optional embodiments, the outer surfaces of the insulating isolation layers of the first function chip and the second function chip are respectively provided with first and second wires electrically connecting the chip in the first function chip and the chip in the second function chip, and the outer surface of the dielectric layer of the bridge chip is provided with a bridge wire electrically connecting the chips in the bridge chip, and the bridge wires respectively contact the first wire and the second wire to realize the electrical connection of the first function chip to the second function chip.

[0017] In some optional embodiments, the first wire includes a seed layer contacting the insulating isolation layer of the first functional chip and a metal layer contacting the seed layer, the second wire includes a seed layer contacting the insulating isolation layer of the second functional chip and a metal layer contacting the seed layer, and the bridge wire includes a seed layer contacting the dielectric layer of the bridge chip and a metal layer contacting the seed layer.

[0018] In some optional embodiments, the line width / line spacing of the first conductive line, the second conductive line, and the bridge conductive line is less than 2 / 2 microns.

[0019] In some optional implementations, a bottom filler is filled between the accommodating cavity and the bottom of the functional chip.

[0020] In some optional embodiments, the semiconductor packaging device further includes:

[0021] The substrate is disposed below the bridge layer.

[0022] In some optional embodiments, the first function chip and the second function chip are electrically connected via solder balls and conductive holes provided at the bottom of the first function chip and the second function chip, and wires provided in the substrate.

[0023] In some optional embodiments, the semiconductor packaging device further includes a flexible circuit board, which is disposed on the protective layer. A first electronic component is further disposed on the bridging layer, and the protective layer covers the first electronic component.

[0024] In some optional embodiments, the semiconductor packaging device further includes a shell and an insulated wire covered with an insulating layer, the first functional chip and the bridge chip are arranged inside the shell, the second functional chip is arranged outside the shell, and the insulated wire passes through the shell to electrically connect the first functional chip.

[0025] In some optional embodiments, a second electronic component is further provided on the bridging layer, and the bridging layer further includes a third electronic component, the second electronic component is electrically connected to the first functional chip, and the third electronic component is electrically connected to the second functional chip.

[0026] In some optional embodiments, the semiconductor packaging device further includes a functional chip component layer disposed on the protective layer, and the functional chip component layer includes at least one of the following: a chip, a fourth electronic component.

[0027] In a second aspect, the present disclosure provides a method for manufacturing a semiconductor package device, the method comprising:

[0028] Providing a substrate, on which a bridging layer is provided, wherein the bridging layer includes at least two horizontally spaced bridging chips;

[0029] A dielectric layer is provided on the substrate, and the provided dielectric layer is photolithographically processed to obtain a bridge chip, wherein two sides of the bridge chip are provided with convex portions and concave portions spaced apart from each other, and the side surfaces of the convex portions and concave portions of the bridge chip are inclined surfaces, so that an accommodating cavity with a width at the top and a narrowness at the bottom is formed between two adjacent bridge chips;

[0030] The functional chip is placed in the corresponding accommodation cavity on the substrate, wherein the functional chip includes an insulating isolation layer and a chip placed in the insulating isolation layer, and the two sides of the functional chip are spaced apart by convex and concave portions, and the side surfaces of the convex and concave portions of the functional chip are inclined surfaces, and the convex and concave portions of the functional chip respectively engage with the concave and convex portions of the bridge chip on both sides of the accommodation cavity in which the functional chip is embedded;

[0031] electrically connecting the function chip to the substrate, and electrically connecting the function chip to the bridge chip;

[0032] Molding is performed to form a protection layer covering the functional chip.

[0033] In some optional embodiments, the functional chip is obtained by the following method:

[0034] providing a release layer on the carrier board;

[0035] Place the chip on the carrier;

[0036] Disposing a dielectric layer above the chip;

[0037] Performing photolithography on the laminated dielectric layer to obtain an insulating isolation layer corresponding to the chip, wherein two sides of the insulating isolation layer are formed with convex portions and concave portions spaced apart;

[0038] forming a seed layer on the insulating isolation layer of the chip;

[0039] After laminating the photoresist, photolithography is performed to form a circuit pattern and then the photoresist is removed;

[0040] etching away the surface seed layer;

[0041] Making solder balls on the circuit pattern to form various functional chips;

[0042] Inverting the structure including the carrier, chip, dielectric layer, circuit pattern and solder balls and bonding them to the frame;

[0043] Remove the carrier board and release layer, and take the fabricated functional chip off the frame.

[0044] In some optional embodiments, the functional chip is obtained by the following method:

[0045] cutting a groove on a wafer or a substrate, wherein a bonding pad is provided on the wafer or the substrate;

[0046] Disposing a dielectric layer above the wafer or substrate;

[0047] The dielectric layer after lamination is photoetched to obtain the insulating isolation layer corresponding to the chip, the two side parts of the insulating isolation layer are convex parts and concave parts arranged in intervals;

[0048] A seed layer is formed on the insulating isolation layer of the chip;

[0049] The photoresist after lamination is photoetched, and then the photoresist is removed after forming the circuit pattern;

[0050] The surface seed layer is etched away;

[0051] Solder balls are made on the circuit pattern;

[0052] The structure including the wafer or substrate, the chip, the dielectric layer, the circuit pattern and the solder balls is inverted and adhered to the frame;

[0053] The upper surface of the structure is ground to form the functional chip;

[0054] The functional chip obtained is taken away from the frame.

[0055] In some optional embodiments, before the cutting to form the semiconductor packaging device, the method further comprises:

[0056] The solder balls are mounted at the bottom of the substrate.

[0057] In order to maintain the high I / O number and fine pitch of the product, reduce the bonding deviation to improve the electrical yield, the semiconductor packaging device and the manufacturing method thereof provided by the embodiments of the present disclosure embed the functional chip at least partially in the wide-to-narrow accommodation cavity on the bridge layer, and the two side parts of the functional chip are convex parts and concave parts arranged in intervals, which correspond to the concave parts and convex parts of the side parts of the bridge chip on the two sides of the accommodation cavity, respectively, and since the side surfaces of the concave parts and convex parts of the side parts of the bridge chip on the two sides of the accommodation cavity are all inclined surfaces, the bonding deviation of the functional chip can be effectively controlled by the inclined surfaces of the concave parts and convex parts of the side parts of the bridge chip on the two sides of the accommodation cavity, so that the precise alignment in the fine-pitch semiconductor packaging device is achieved, and the electrical yield is improved. BRIEF DESCRIPTION OF DRAWINGS

[0058] Other features, objects and advantages of the present disclosure will become more apparent from the following detailed description of non-limiting embodiments made with reference to the accompanying drawings:

[0059] Figure 1A is a structural schematic diagram of one embodiment of a semiconductor packaging device according to the present disclosure;

[0060] Figure 1B is a partial enlarged schematic diagram of the longitudinal section of the convex part and the concave part of the bridge chip in one embodiment of the semiconductor packaging device according to the present disclosure, excluding the dielectric layer part;

[0061] Figure 1C is a partially enlarged schematic diagram of a longitudinal cross-section of an accommodating cavity and a functional chip in one embodiment of a semiconductor packaging device according to the present disclosure;

[0062] Figure 1D 、 1E 1F, 1G, 1H, 1I, and 1J are schematic structural diagrams of different embodiments of semiconductor packaging devices according to the present disclosure;

[0063] Figures 2A-2N are cross-sectional views of a semiconductor package device at various stages of fabrication according to one embodiment of the present disclosure.

[0064] Explanation of symbols:

[0065] 1 substrate; 30 functional chips;

[0066] 11 Conductors within the substrate; 301 Chips within the functional chip;

[0067] 2 bridge layer; 302 insulation isolation layer in the functional chip;

[0068] 21 bridge chip; 303 functional chip convex part;

[0069] 211 Chip in the bridge chip; 303a Side surface of the convex portion of the functional chip;

[0070] 212 dielectric layer in the bridge chip; 304 functional chip recess;

[0071] 213 bridge chip protrusion; 304a side surface of the functional chip concave portion;

[0072] 213a: side surface of the bridge chip protrusion; h: part of the cavity where the functional chip is embedded

[0073] vertical height;

[0074] 214 bridge chip recess; 31 first function chip;

[0075] 215 bridging conductor; 311 first conductor;

[0076] 2151 bridging conductor seed layer; 3111 first conductor seed layer;

[0077] 2152 bridge conductor metal layer; 3112 first conductor metal layer;

[0078] 214a bridge chip concave portion side surface; 312 first function chip bottom solder ball;

[0079] θ bridge chip convex and concave longitudinal 313 first functional chip bottom conductive hole;

[0080] The gradient of the interface except the dielectric layer

[0081] inner angle of the bottom of the shape;

[0082] t bridge chip excluding the dielectric layer portion 32 second function chip;

[0083] vertical height;

[0084] Wbt is a second longitudinal wire 321 bridging the convex and concave portions of the chip;

[0085] The gradient of the interface except the dielectric layer

[0086] The length of the side of the shape;

[0087] Wbb bridge chip convex and concave longitudinal 3211 second wire seed layer;

[0088] The gradient of the interface except the dielectric layer

[0089] The length of the lower side of the shape;

[0090] 22 accommodating cavity; 3212 second wire metal layer;

[0091] Wcb is the bottom water filling agent of the longitudinal cross section of the accommodating cavity;

[0092] Flat width;

[0093] Wfb is the bottom water 5 protection layer of the longitudinal cross section of the functional chip;

[0094] Flat width;

[0095] Wft functional chip longitudinal cross section top water 6 flexible circuit board;

[0096] Flat width;

[0097] 23 first electronic component; 7 housing;

[0098] 24 third electronic components; 8 insulated wires;

[0099] 10 functional chip component layer; 9 second electronic component.

[0100] 101 chips in the functional chip component layer;

[0101] 102 fourth electronic component; DETAILED DESCRIPTION

[0102] The following describes the specific embodiments of the present invention in conjunction with the accompanying drawings and examples. Those skilled in the art will readily understand the technical problems solved by the present invention and the technical effects produced by the present invention through the contents of this specification. It should be understood that the specific embodiments described herein are merely for the purpose of explaining the relevant invention and are not intended to limit the invention. Furthermore, for ease of description, only portions relevant to the relevant invention are shown in the accompanying drawings.

[0103] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of the specification are only used to match the contents recorded in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions for the implementation of the present invention. Therefore, they have no substantial technical significance. Any modification of the structure, change in the proportional relationship or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the efficacy and purpose that can be achieved by the present invention. At the same time, terms such as "on", "first", "second" and "one" quoted in this specification are only for the convenience of description and are not used to limit the scope of the implementation of the present invention. Changes or adjustments in their relative relationships should also be regarded as the scope of the implementation of the present invention without substantially changing the technical content.

[0104] It should also be noted that the longitudinal section corresponding to the embodiment of the present disclosure may be a section corresponding to the front view direction, the transverse section may be a section corresponding to the right view direction, and the horizontal section may be a section corresponding to the top view direction.

[0105] In addition, the embodiments and features of the embodiments of the present disclosure may be combined with each other without conflict. The present disclosure will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0106] refer to Figure 1A , Figure 1A A cross-sectional view of one embodiment of a semiconductor package device 1 a according to the present disclosure is shown.

[0107] like Figure 1A As shown, the semiconductor package device 1a may include a bridge layer 2, a functional chip 30 and a protective layer 5.

[0108] The bridge layer 2 includes at least two horizontally spaced bridge chips 21, each of which includes a chip 211 and a dielectric layer 212 covering the chip 211. The two sides of the bridge chip 21 are spaced apart by convex and concave portions, and the convex and concave side surfaces of the bridge chip are inclined surfaces. A accommodating cavity 22 with a width at the top and a narrowness at the bottom is formed between two adjacent bridge chips. The accommodating cavity 22 is as shown in FIG. Figure 1A As shown in the dotted box 22.

[0109] It should be noted that the chip 211 in the bridge chip 21 can be a semiconductor chip with circuits, or a semiconductor material without chip circuits, or a semiconductor material with circuits but without semiconductor materials. The dielectric layer 212 covering the chip 211 can be various insulating materials, which can be organic insulating materials or inorganic insulating materials. Organic insulating materials can be, for example, polyamide fiber (PA), polyimide (PI), epoxy resin (Epoxy), poly-p-phenylene benzobisoxazole (PBO) fiber, FR-4 epoxy glass cloth laminate, PP (PrePreg, prepreg material or semi-cured resin, semi-cured sheet), ABF (Ajinomoto Build-up Film), etc., while inorganic insulating materials can be, for example, glass, ceramic, silicon oxide, silicon nitride, tantalum oxide, etc.

[0110] The functional chip 30 is at least partially embedded within the accommodating cavity 22. The functional chip 30 includes an insulating isolation layer 302 and a chip 301 disposed within the insulating isolation layer 302. The functional chip 30 has two sides formed with spaced-apart convex and concave portions, each with inclined side surfaces. The convex and concave portions of the functional chip 30 correspond to the concave and convex portions of the bridge chip 21 on either side of the accommodating cavity 22 in which the functional chip 30 is embedded.

[0111] The chip 301 in the functional chip 30 can be a chip that implements various functions, such as a logic chip, a memory chip, or a radio frequency chip. The insulating isolation layer 302 in the functional chip 30 is used to protect and isolate the chip 301. The insulating isolation layer 302 can be made of various insulating materials, such as various organic or inorganic insulating materials.

[0112] The protective layer 5 is disposed on and covers the functional chip 30. The protective layer 5 is used to provide protection for the bridging layer 2 and the functional chip 30. The protective layer 5 can be composed of various insulating materials. For example, the protective layer 5 can be various molding compounds. For example, the molding compound may include epoxy resin, filler, catalyst, pigment, release agent, flame retardant, coupling agent, hardener, low stress absorber, adhesion promoter, ion trapping agent, etc.

[0113] In the semiconductor packaging device 1a, since the functional chip 30 is at least partially embedded in the accommodating cavity 22 which is wide at the top and narrow at the bottom of the bridge layer 2, and the convex and concave portions on both sides of the functional chip 30 are spaced apart and correspond to the concave and convex portions on the sides of the bridge chip 21 on both sides of the accommodating cavity 22 respectively, and since the side surfaces of the concave and convex portions on the sides of the bridge chip 21 on both sides of the accommodating cavity 22 are both inclined surfaces, the functional chip 30 can be guided by the inclined side surfaces of the concave and convex portions on the sides of the bridge chip 21 on both sides of the accommodating cavity 22, and the bonding offset of the functional chip 30 can be effectively controlled, thereby achieving precise alignment in the fine-pitch semiconductor packaging device 1a, thereby improving the electrical yield.

[0114] Please refer to Figure 1B , please refer to Figure 1B , Figure 1B FIG. 1 is a partial enlarged schematic diagram of a longitudinal cross section of the convex and concave portions of the bridge chip 21 excluding the dielectric layer 212 in an embodiment 1a of the semiconductor package device according to the present disclosure. Figure 1B As shown in FIG, the longitudinal cross section of the convex and concave portions of the bridge chip 21, excluding the dielectric layer portion, may be a trapezoidal shape with the upper side being shorter than the lower side. Figure 1BThe trapezoidal shape shown in the dotted box is a trapezoidal shape. Except for the portion of the dielectric layer 212 in the longitudinal cross-section of the convex and concave portions of the bridge chip 21, the upper side is shorter than the lower side. Thus, the accommodating cavity 22 formed between two adjacent bridge chips 21 in the bridging layer will be wide at the top and narrow at the bottom. During the placement of the functional chip 30 into the accommodating cavity 22, the functional chip 30 can move downward under the action of gravity. Because the accommodating cavity is wide at the top and narrow at the bottom, the functional chip 30 can move between the convex and concave portions on both sides of the accommodating cavity 22, where the convex and concave portions fit neatly into the accommodating cavity 22. The functional chip 30 will no longer move downward and will be fixed there. The bridge chip 21 then contacts the functional chip 30 in the horizontal, transverse, and longitudinal directions, allowing the accommodating cavity 22 to guide and position the functional chip 30. Moreover, since the accommodating cavity 22 is wide at the top and narrow at the bottom, even if there is a certain bonding offset when placing the functional chip 30 into the accommodating cavity 22, as long as the functional chip 30 is in the upper space of the accommodating cavity 22, the concave and convex parts on both sides of the accommodating cavity 22 can guide and position the functional chip 30.

[0115] In some optional embodiments, the two inner angles θ of the bottom of the trapezoid in the longitudinal interface between the convex and concave parts of the bridge chip 21, excluding the dielectric layer 212 part, can be between 30° and 80°. Figure 1B As shown in the figure, according to the setting of the inner angle of the bottom of the trapezoid, the angles of the side surface slopes of the concave and convex parts of the accommodating cavity 22 formed between two adjacent bridge chips 21 in the bridge layer 2 are more suitable for guiding the functional chip 30 downward, so that when the functional chip 30 is placed in the accommodating cavity 22, the bonding offset is too large due to the slope being too steep and sliding downward too fast, or the slope being too gentle and difficult to slide.

[0116] In some optional embodiments, the difference between the lower side length Wbb and the upper side length Wbt of the trapezoidal shape (excluding the dielectric layer portion) at the longitudinal interface between the convex and concave portions of the bridge chip 21 can be between 7 and 160 microns. In other words, the allowable horizontal bonding offset of the functional chip 30 placed in the accommodating cavity 22 is 7 to 160 microns. Within the precision range of current chip processes, a good electrical connection can be achieved within a bonding offset of 7 to 160 microns, thereby improving the electrical yield of the product.

[0117] In some optional embodiments, the vertical height t of the bridge chip 21, excluding the dielectric layer 212, is between 10 and 50 microns. Thus, the depth of the cavity formed by two adjacent bridge chips 21 is also between 10 and 50 microns. If t is less than 10 microns, the cavity 22 may be too small to accommodate the functional chip 30. Conversely, if t is greater than 50 microns, the cavity 22 may be too high, resulting in an excessively thick semiconductor package, hindering the trend toward product miniaturization.

[0118] Reference below Figure 1C , Figure 1C FIG. 1 is a partially enlarged schematic diagram of a longitudinal cross section of the accommodating cavity 22 and the functional chip 30 in the semiconductor packaging device 1a according to an embodiment of the present disclosure. Figure 1C As shown, the horizontal width Wcb of the bottom longitudinal section of the accommodating cavity 22, the horizontal width Wfb of the bottom longitudinal section of the functional chip 30, and the horizontal width Wft of the top longitudinal section of the functional chip 30 are arranged from small to large. Because the horizontal width Wfb of the bottom longitudinal section of the functional chip 30 is greater than the horizontal width Wcb of the bottom longitudinal section of the accommodating cavity 22, the functional chip 30 does not contact the bottom of the accommodating cavity 22. That is, there is a gap between the functional chip 30 and the bottom of the accommodating cavity 22, which can be used to set a solder ball at the bottom of the functional chip 30 to achieve electrical connection between the functional chip 30 and, for example, a substrate set at the bottom of the accommodating cavity 22 through the solder ball set at the bottom.

[0119] In some optional embodiments, the vertical height h of the portion of the functional chip 30 embedded in the accommodating cavity 22 may be less than the minimum height of each bridge chip 21. This is because there may be a gap between the functional chip 30 and the bottom of the accommodating cavity 22, which can be used to place a solder ball at the bottom of the functional chip 30 to achieve electrical connection between the functional chip 30 and, for example, a substrate disposed at the bottom of the accommodating cavity 22 via the solder ball.

[0120] Continue to refer Figure 1D and Figure 1E , Figure 1D and Figure 1E The semiconductor package devices 1d and 1e shown are similar to Figure 1A The semiconductor package device 1 a shown in FIG. 1 is different in that the semiconductor package devices 1 d and 1 e may include at least two functional chips 30 disposed in the accommodating cavity 22 .

[0121] In some optional embodiments, the semiconductor package devices 1d and 1e may include a first function chip 31 and a second function chip 32 respectively disposed on both sides of the bridge chip 21 , and the first function chip 31 and the second function chip 32 are electrically connected through the bridge chip 21 .

[0122] In some optional embodiments, the outer surfaces of the insulating isolation layers of the first function chip 31 and the second function chip 32 are respectively provided with first and second wires 311, 321 that electrically connect the first function chip 31 and the second function chip 32. The outer surface of the dielectric layer 212 of the bridge chip 21 is provided with a bridge wire 215 that electrically connects the chip 211 in the bridge chip 21. The bridge wire 215 contacts the first and second wires 311, 321, respectively, to electrically connect the first function chip 31 to the second function chip 32. This connection method can shorten the electrical connection path between the first function chip 31 and the second function chip 32.

[0123] In some optional embodiments, the first conductive line 311 may include a seed layer 3111 contacting the insulating isolation layer of the first functional chip 31 and a metal layer 3112 contacting the seed layer 3111; the second conductive line 32 may include a seed layer 3211 contacting the insulating isolation layer of the second functional chip 32 and a metal layer 3212 contacting the seed layer 3211; and the bridge conductive line 215 may include a seed layer 2151 contacting the dielectric layer 212 of the bridge chip 21 and a metal layer 2152 contacting the seed layer 2151. Here, by providing a seed layer and a metal layer on the first conductive line 31, the second conductive line 32, and the bridge conductive line 215, respectively, the seed layer can be used to improve the bonding strength between the metal layers of the first conductive line 31, the second conductive line 32, and the bridge conductive line 215 and the insulating isolation layer of the first functional chip 31, the insulating isolation layer of the second functional chip 32, and the dielectric layer 212 of the bridge chip 21. Here, the seed layer may be a metal such as titanium (Ti), tungsten (W), or nickel (Ni). The metal layer may be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu) or an alloy thereof.

[0124] In some optional embodiments, the line width / space ratio of the first conductive line 311, the second conductive line 321, and the bridge conductive line 215 is less than 2 / 2 microns. This line width / space ratio can balance the electrical performance of the circuit, the occupied area, and the process capability of the conductive line manufacturing process, such as the process capability of optical exposure, electroplating, and yellow light processing.

[0125] Solder balls (such as Figure 1D As shown), the first function chip 31 and the second function chip 32 may also have no solder balls at the bottom (as shown Figure 1E shown).

[0126] In some optional embodiments, the space between the accommodating cavity 22 and the bottom of the functional chip 30 may be filled with an underfill. Figure 1A 、 1C, 1D, 1E or 1F, the semiconductor package devices 1a, 1c, 1d, 1e, and 1f are shown in FIG. In this way, the bottom of the functional chip 30, the first functional chip 31 or the second functional chip 32 can be protected.

[0127] In some optional embodiments, the semiconductor package device may further include a substrate 1 disposed below the bridge layer 2. Figure 1A 、 1D , 1E or 1F as shown in the semiconductor package device 1a, 1d, 1e, 1f. In this way, the substrate 1 can support and protect the bottom of the bridge layer 2.

[0128] Continue to refer Figure 1F , Figure 1F The semiconductor package device 1f shown in FIG. Figure 1D 、 1E The difference between the semiconductor package devices 1d and 1e shown in FIG is that the first function chip 31 and the second function chip 32 can be electrically connected through solder balls, conductive vias, and wires provided in the substrate 1 provided at the bottom of the first function chip 31 and the second function chip 32. Figure 1F The semiconductor package device 1f in the embodiment of the present invention. Here, the guide hole can be a through hole, a buried via or a blind via, and the through hole, buried via or blind via can be filled with a conductive material such as a metal or a metal alloy. Here, the metal can be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu) or an alloy thereof.

[0129] Continue to refer Figure 1G , Figure 1G The semiconductor package device 1g shown in FIG. 1 is similar to Figure 1D 、 1E The semiconductor packaging devices 1d and 1e shown in FIG. 1 differ in that semiconductor packaging device 1g may further include a flexible circuit board 6 disposed on a protective layer 5. A first electronic component 23 may also be disposed on the bridging layer 2, with the protective layer 5 covering the first electronic component 23. This semiconductor packaging device 1g may be used to implement a flexible wearable device, such as the flexible circuit board portion of a watch.

[0130] Continue to refer Figure 1H , Figure 1H The semiconductor package device 1h shown in FIG is similar to Figure 1D 、 1EThe semiconductor package devices 1d and 1e shown in FIG 1 differ in that the semiconductor package device 1h may further include a housing 7 and an insulated wire 8 coated with an insulating layer. The first function chip 31 and the bridge chip 21 are disposed within the housing 7, and the second function chip 32 is disposed outside the housing 7. The insulated wire 8 passes through the housing 7 and is electrically connected to the first function chip 31. This semiconductor package device 1h can be used to implement various charging cable connectors, network cable connectors, and the like.

[0131] Continue to refer Figure 1I , Figure 1I The semiconductor package device 1i shown in FIG is similar to Figure 1D 、 1E The semiconductor packaging devices 1d and 1e shown in the figure are different in that: in the semiconductor packaging device 1i, a second electronic component 9 can also be provided on the bridging layer 2, and the bridging layer 2 can also include a third electronic component 24. The second electronic component 9 is electrically connected to the first functional chip 31, and the third electronic component 24 is electrically connected to the second functional chip 32.

[0132] Continue to refer Figure 1J , Figure 1J The semiconductor package device 1j shown in FIG. 1 is similar to Figure 1A 、 1D The semiconductor packaging devices 1a, 1d, 1d, and 1f shown in 1E and 1F differ in that: the semiconductor packaging device 1j may also include a functional chip component layer 10, which is provided on the protective layer 5, and the functional chip component layer 10 includes at least one of the following: a chip 101, a fourth electronic component 102.

[0133] Figure 2A-Figure 2N , are schematic longitudinal cross-sectional views of antenna semiconductor package devices 2a-2n manufactured at various stages according to some embodiments of the present disclosure. The figures have been simplified for better understanding of various aspects of the present disclosure.

[0134] refer to Figure 2A , providing a substrate 1.

[0135] A bridge layer 2 may be provided on the substrate 1 , and the bridge layer 2 includes at least two horizontally spaced bridge chips 21 . A cavity may be provided between two adjacent bridge chips 21 . The bridge chip 21 may include a chip 211 .

[0136] refer to Figure 2B , a dielectric layer 212 is disposed on the substrate 1 .

[0137] For example, the dielectric layer 212 may be provided on the substrate 1 by printing, lamination, potting, coating or similar techniques.

[0138] refer to Figure 2C , photolithography is performed on the provided dielectric layer 212 to obtain the bridge chip 21 .

[0139] in, Figure 2C The upper portion is a partially enlarged top view of the bridge chip 21 . Figure 1C The middle part is a top view of the structure. Figure 1C The lower part is a schematic diagram of the longitudinal cross-section of the structure.

[0140] from Figure 1C As can be seen, the bridge chip 21 includes a chip 211 and a dielectric layer 212 covering the chip 211. The bridge chip 21 has two sides formed with spaced-apart convex portions 213 and concave portions 214. Both the side surfaces 213a of the convex portion 213 and the side surfaces 214a of the concave portion 214 of the bridge chip 21 are inclined. A accommodating cavity 22, wider at the top and narrower at the bottom, is formed between two adjacent bridge chips 21.

[0141] refer to Figure 2D , a seed layer 2151 is formed on the bridge layer 2.

[0142] For example, the seed layer may be formed by sputtering, plating, electroless plating, physical vapor deposition (PVD), chemical vapor deposition (CVD), or similar techniques.

[0143] refer to Figure 2E , laminating photoresist followed by photolithography.

[0144] refer to Figure 2F A metal layer 2152 of a bridge wire 215 is formed on the bridge chip 21. Then, a seed layer 2151 and a metal layer 2152 of the bridge wire 215 are formed.

[0145] refer to Figure 2G , remove the photoresist, and etch away the surface seed layer.

[0146] Figure 2G The upper part is a schematic diagram of the longitudinal cross-section of the structure, while the lower part is a top view of the structure.

[0147] refer to Figure 2H , place the first functional chip 31 in the corresponding accommodating cavity 22 on the substrate 1 .

[0148] Here, the functional chip 31 includes an insulating isolation layer and a chip placed in the insulating isolation layer. The two sides of the first functional chip 31 are spaced apart convex and concave portions. The side surfaces of the convex and concave portions of the first functional chip are inclined surfaces. After the first functional chip 31 is placed in the accommodating cavity 22 on the substrate 1, the convex and concave portions of the first functional chip 31 respectively correspond to the concave and convex portions of the side portions of the bridge chip 21 on both sides of the accommodating cavity 22 where the first functional chip 31 is embedded. Specifically, Figure 2H A partially enlarged top view of the upper first functional chip 31 is shown.

[0149] refer to Figure 2I , place the second functional chip 32 into other corresponding accommodating cavities 22 on the substrate 1 .

[0150] Figure 2I The upper portion is a schematic longitudinal cross-section of the structure. The lower portion is a top view. This bottom view shows that the convex and concave portions on either side of the first function chip 31 have engaged with the concave and convex portions on the sides of the bridge chip 21 on either side of the accommodating cavity 22, while the second function chip 32 has not yet been placed in the accommodating cavity and is therefore not yet engaged.

[0151] refer to Figure 2J , the first function chip 31 and the second function chip 32 are electrically connected to the substrate 1 , and the first function chip 31 and the second function chip 32 are electrically connected to the bridge chip 21 .

[0152] For example, reflow soldering or flip chip bonding may be used to electrically connect the first function chip 3131 and the second function chip 32 to the substrate 1 , and to electrically connect the first function chip 3131 and the second function chip 32 to the bridge chip 21 .

[0153] The first function chip 31 may be provided with a first wire 311 electrically connected to the other chips, and the bridge chip 21 may be provided with a bridge wire 215 electrically connected to the other chips. The first function chip 31 may be electrically connected to the bridge chip 21 by electrically connecting the bridge wire 215 to the first wire 311. The first wire 311 may include a seed layer 3111 and a metal layer 3112. The bridge wire 215 may include a seed layer 2151 and a metal layer 2152.

[0154] The second function chip 32 may be provided with a second wire 321 electrically connected to the other chip, and the bridge chip 21 may be provided with a bridge wire 215 electrically connected to the other chip. The second function chip 32 may be electrically connected to the bridge chip 21 by electrically connecting the bridge wire 215 to the second wire 321. The second wire 321 may include a seed layer 3211 and a metal layer 3212.

[0155] refer to Figure 2K The bottom filler 4 is filled between the accommodating cavity 22 and the bottom of the first function chip 31 , and between the accommodating cavity 22 and the bottom of the second function chip 32 . This protects the bottom of the first function chip 31 and the bottom of the second function chip 32 .

[0156] refer to Figure 2L , molded to form a protection layer 5 covering the first function chip 31 and the second function chip 32.

[0157] refer to Figure 2M , flip the structure over, and install solder balls on substrate 1.

[0158] refer to Figure 2N , cutting to form packaged devices.

[0159] In some optional implementations, the function chip 30, the first function chip 31, and the second function chip 32 may be obtained by the following method:

[0160] The first step is to set a release layer on the carrier.

[0161] The second step is to place the chip on the carrier board.

[0162] The third step is to place a dielectric layer on top of the chip;

[0163] In the fourth step, the dielectric layer is photolithographically processed to obtain an insulating isolation layer corresponding to the chip, wherein both sides of the insulating isolation layer are provided with convex portions and concave portions spaced apart from each other.

[0164] The fifth step is to form a seed layer on the insulating isolation layer of the chip.

[0165] Step 6: After laminating the photoresist, the circuit pattern is formed by photolithography and then the photoresist is removed.

[0166] Step 7: Etch away the surface seed layer.

[0167] The eighth step is to make solder balls on the circuit pattern to form various functional chips.

[0168] In the ninth step, the structure including the carrier, chip, dielectric layer, circuit pattern and solder balls is inverted and bonded to the frame.

[0169] Step 10: Remove the carrier board and release layer, and take the manufactured functional chip off the frame.

[0170] In some optional implementations, the function chip 30, the first function chip 31, and the second function chip 32 may also be obtained by the following method:

[0171] The first step is to cut grooves on the wafer or substrate.

[0172] Wherein, a bonding pad is provided on the wafer or substrate.

[0173] The second step is to place a dielectric layer on the wafer or substrate.

[0174] The third step is to perform photolithography on the set dielectric layer to obtain an insulating isolation layer corresponding to the chip.

[0175] Here, both sides of the insulating isolation layer are formed with convex portions and concave portions arranged at intervals.

[0176] The fourth step is to form a seed layer on the insulating isolation layer of the chip.

[0177] The fifth step is to laminate the photoresist, form the circuit pattern by photolithography, and then remove the photoresist.

[0178] Step 6: Etch away the surface seed layer.

[0179] Step 7: Make solder balls on the circuit pattern.

[0180] In the eighth step, the structure including the wafer or substrate, chip, dielectric layer, circuit pattern and solder balls is turned upside down and bonded to the frame.

[0181] The ninth step is to grind the upper surface of the structure to form various functional chips.

[0182] Step 10: Remove the manufactured functional chip from the frame.

[0183] Although the present disclosure has been described and illustrated with reference to specific embodiments of the present disclosure, these descriptions and illustrations do not limit the present disclosure. It will be clearly understood by those skilled in the art that various changes may be made and equivalent elements may be substituted within the embodiments without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. Due to variables in the manufacturing process, etc., there may be differences between the technical reproduction in the present disclosure and the actual implementation. There may be other embodiments of the present disclosure that are not specifically described. The description and illustrations should be regarded as illustrative, not restrictive. Modifications may be made to adapt specific circumstances, materials, compositions of matter, methods or processes to the objectives, spirit and scope of the present disclosure. All such modifications fall within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a specific order, it should be understood that these operations may be combined, subdivided or reordered to form equivalent methods without departing from the teachings of the present disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit the present disclosure.

Claims

1. A semiconductor packaging device, comprising: The bridge layer includes at least two horizontally spaced bridge chips, each of which includes a chip and a dielectric layer covering the chip. The bridge chips have convex and concave portions spaced apart on both sides, and the convex and concave portions of the bridge chips have inclined side surfaces, forming a accommodating cavity that is wide at the top and narrow at the bottom between two adjacent bridge chips. At least two functional chips are at least partially embedded in the accommodating cavity, the functional chips include an insulating isolation layer and a chip placed in the insulating isolation layer, two sides of the functional chips are formed with convex and concave portions spaced apart, the side surfaces of the convex and concave portions of the functional chips are inclined surfaces, and the convex and concave portions of the functional chips respectively correspond to the concave and convex portions of the side portions of the bridge chip on both sides of the accommodating cavity in which the functional chip is embedded; the at least two functional chips include a first functional chip and a second functional chip respectively arranged on both sides of the bridge chip, and the first functional chip and the second functional chip are electrically connected via the bridge chip; The protection layer is disposed on the functional chip and covers the functional chip.

2. The semiconductor package device according to claim 1, wherein The longitudinal cross-section of the convex portion and the concave portion of the bridge chip, excluding the dielectric layer portion, is a trapezoid with an upper side having a smaller length than a lower side.

3. The semiconductor package device according to claim 1, wherein The vertical height of the portion of the functional chip embedded in the accommodating cavity is smaller than the minimum height of each of the bridge chips.

4. The semiconductor package device according to claim 1, wherein The outer surfaces of the insulating isolation layers of the first function chip and the second function chip are respectively provided with a first wire and a second wire electrically connecting the chip in the first function chip and the chip in the second function chip, and the outer surface of the dielectric layer of the bridge chip is provided with a bridge wire electrically connecting the chips in the bridge chip, and the bridge wire respectively contacts the first wire and the second wire to realize the electrical connection of the first function chip to the second function chip.

5. The semiconductor package device according to claim 4, wherein The first conductive line includes a seed layer contacting the insulating isolation layer of the first functional chip and a metal layer contacting the seed layer; the second conductive line includes a seed layer contacting the insulating isolation layer of the second functional chip and a metal layer contacting the seed layer; the bridge conductive line includes a seed layer contacting the dielectric layer of the bridge chip and a metal layer contacting the seed layer. The semiconductor package device according to claim 1 , wherein: A bottom filler is filled between the accommodating cavity and the bottom of the functional chip.

7. The semiconductor package device according to claim 1, wherein The semiconductor packaging device further includes: The substrate is disposed below the bridge layer.

8. The semiconductor package device according to claim 7, wherein The first function chip and the second function chip are electrically connected via solder balls and conductive holes provided at the bottom of the first function chip and the second function chip, and wires provided in the substrate.

9. The semiconductor package device according to claim 1, wherein A second electronic component is further provided on the bridging layer, and the bridging layer further includes a third electronic component. The second electronic component is electrically connected to the first functional chip, and the third electronic component is electrically connected to the second functional chip.

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