System for implementing shared lock-free memory that implements compound assignments

Abstract

The purpose of the disclosed technology is to provide a novel method and system for sharing concurrent access to storage units. According to the disclosed technology, a system for sharing concurrent access to storage units is provided, the system comprising at least one shared storage unit, an estimator and a plurality of processing agents coupled to an input of the estimator. The estimator is also coupled to the at least one storage unit. The estimator is configured to estimate an expression for performing a plurality of concurrent compound assignments on the at least one shared storage unit. The estimator also allows each of the plurality of processing agents to perform a concurrent compound assignment on the at least one shared storage unit. The compound assignment does not include a read operation of the plurality of processing agents on the at least one shared storage unit.

Description

Technical Field

[0001] The present invention relates generally to flexible computing, and in particular, to systems and methods for implementing concurrent flexible computing. Background Art

[0002] Implementing the fundamental principles of flexible computing requires well-defined results. With well-defined flexible execution, the final value is not affected by the order in which any one program instruction is executed, allowing instructions to be executed in serial, parallel, or various combinations thereof. Flexible execution can be achieved by adjusting the rules that control variable scope, such as affecting address definition, variable initialization, and reading and writing. Variables updated using this specialized instruction set are guaranteed to produce consistent, well-defined results for any allowed execution sequence. Examples of instructions that can adhere to these restrictions are: only once assignment, logical "OR" operation, and addition "+". These instructions are commutative and combinable; and can be combined in any way to produce consistent, well-defined outputs.

[0003] Given an operator f, a compound assignment is of the form xf=y, or x=(xfy). The unordered sequential compound assignment execution (USCAE) condition is necessary to achieve well-defined execution of compound assignments of the form xf=y when the compound assignments are executed sequentially in any order. The USCAE operator condition requires that ((afb)fc)=((afc)fb), for example, the exact addition operator satisfies this condition, and such a compound assignment is written as: x+=y, which is an abbreviation of x=x+y. Although the first parameter and value of f must be of the same type, no restrictions are placed on the second parameter of f. These operators are referred to as USCAE operators in this article. Examples of functions that satisfy this condition are logical "AND" and "OR" operators, exact arithmetic operations +, -, *, / , **, addition and subtraction with respect to fixed moduli, etc. As will be seen in the present disclosure, by exploiting the electrical properties of capacitors and semiconductors, certain compound assignments, such as OR= and AND=, can also be executed in parallel.

[0004] The USCAE condition can be extended to multiple different operators. For example, given operators f1, f2 (which can be the same or different), the USCAE function condition can be expressed as follows: ((a, f1, b) f2, c) = ((a, f2, c) f1, b). And, this is easily generalized to n operators, whether they are the same or different. Complying with these conditions allows considerable execution flexibility while ensuring uniquely defined deterministic outputs. For more details, please refer to the first publication.

[0005] publication

[0006] 4th Eastern European Regional Conference on Engineering Design of Computer-Based Systems (ECBS-EERC, 2015), publication “Flexible Algorithms: Enabling Well-defined Order-Independent Execution with an Imperative Programming Style.” IEEE Press, 75-82 (DOI: 10.1 109 / ECBS-EERC.2015.20), RB Yehezkael, M. Goldstein, D. Dayan, S. Mizrahi.

[0007] In Proceedings of the 4th Eastern European Regional Conference on Engineering Design of Computer-Based Systems (ECBS-EERC, 2015), publication “EFL: Implementing and Testing an Embedded Language Which Provides Safe and Efficient Parallel Execution”, IEEE Press, 83-90 (DOI: 10.1109 / ECBS-EERC.2015.21), D. Dayan, M. Goldstein, M. Popovic, M. Rabin, D. Berlovitz, O. Berlovitz, E. Bosni-Levy, M. Neeman, M. Nagar, D. Soudry, R.B. Yehezkael, 2015.

[0008] 5th European Conference on Engineering Design of Computer-Based Systems (ECBS2017), publication “Design Principles of an Embedded Language (EFL) Enabling Well Defined Order-Independent Execution”, ACM (DOI: 10.1145 / 3123779.3123789), M. Goldstein, D. Dayan, M. Rabin, D. Berlovitz, R.B. Yehezkael. Summary of the invention

[0009] The disclosed technology aims to provide a novel method and system for sharing concurrent access to storage units. According to the disclosed technology, a system for sharing concurrent access to storage units is provided, the system comprising at least one shared storage unit, an estimator, and a plurality of processing agents coupled to an input of the estimator. The estimator is also coupled to the at least one storage unit. The estimator is configured to estimate an expression for performing a plurality of concurrent compound assignments on the at least one shared storage unit. The estimator also allows each of the plurality of processing agents to perform a concurrent compound assignment on the at least one shared storage unit. The compound assignment does not include a read operation of the plurality of processing agents on the at least one shared storage unit.

[0010] According to another aspect of the disclosed technology, a system for sharing concurrent access to a storage unit is provided, the system comprising at least one shared storage unit, a logic circuit, and a plurality of processing agents coupled to an input of the logic circuit. The logic circuit is also coupled to the at least one storage unit. The logic circuit is configured to perform one of a plurality of concurrent compound assignments of OR= and AND= on the at least one shared storage unit. The logic circuit allows each of the plurality of processing agents to perform concurrent compound assignments on the at least one shared storage unit. The compound assignment does not include a read operation of the at least one shared storage unit by the plurality of processing agents.

[0011] According to another aspect of the disclosed technology, there is thus provided a one-bit memory cell that receives a write signal corresponding to a logical AND of data to be written using a corresponding write enable signal.

[0012] According to another aspect of the disclosed technology, there is thus provided a one-bit memory cell comprising circuitry associated with each processing agent for enabling reading from the memory cell and for writing to the memory cell.

[0013] According to another aspect of the disclosed technology, there is thus provided a processor for executing machine executable instructions relating to a plurality of concurrent compound assignments of OR=, wherein for a first bit x and a second bit y, the compound assignment is implemented by a statement selected from the group consisting of:

[0014] If y == 1, then x = 1;

[0015] If y == 1, then x = 1, otherwise x = x;

[0016] If y == 1, then x = y; and

[0017] If y == 1, then x = y, otherwise x = x.

[0018] According to another aspect of the disclosed technology, there is thus provided a processor for executing machine executable instructions relating to a plurality of concurrent compound assignments of AND=, wherein for a first bit x and a second bit y, the compound assignment is implemented by a statement selected from the group consisting of:

[0019] If y == 0, then x = 0;

[0020] If y == 0, then x = 0, otherwise x = x;

[0021] If y == 0, then x = y; and

[0022] If y == 0, then x = y, otherwise x = x. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The disclosed technology will be more fully understood and appreciated through the following detailed description in conjunction with the accompanying drawings, in which:

[0024] Figure 1A is a schematic diagram of a system for implementing concurrent OR= instructions on a shared one-bit DRAM storage cell, constructed and operative in accordance with an embodiment of the disclosed technology;

[0025] Figure 1B is a schematic diagram of a system for implementing concurrent OR= instructions on a shared one-bit DRAM storage unit constructed and operative in accordance with another embodiment of the disclosed technology;

[0026] Figure 1C is a schematic diagram of a system for implementing concurrent OR= instructions on a shared one-bit SRAM storage cell constructed and operative in accordance with another embodiment of the disclosed technology;

[0027] Figure 1D is a schematic diagram of a system for implementing compound assignment on a shared one-bit SRAM memory cell constructed and operative in accordance with another embodiment of the disclosed technology;

[0028] Figure 2 is a schematic diagram of an OR-memory DRAM accessed by a single processing core running multiple threads, constructed and operated in accordance with another embodiment of the disclosed technology; and

[0029] Figures 3A to 3G Together are schematic diagrams of a system for implementing concurrent OR= instructions on DRAM storage cells concurrently accessed by multiple core processors, the system being constructed and operative in accordance with another embodiment of the disclosed technology. DETAILED DESCRIPTION

[0030] The disclosed technology overcomes the shortcomings of the prior art by providing a novel technique for implementing well-defined computations by multiple parallel processors. A shared memory architecture is proposed to enable multiple processors to concurrently access a memory cell. Multiple concurrent compound assignments are performed on the shared memory cell without the need to lock the memory cell to prevent any of the multiple processors from accessing the memory cell. This is useful for a variety of scenarios, such as setting one or more flags. Often, it is sufficient to know that at least one processor has set a flag, without knowing which processor set the flag.

[0031] The instruction set for implementing the parallel memory access technology disclosed herein involves performing a logical OR= operation and complying with the flexible execution criteria described above. Storing well-defined calculation results requires retaining previous values. The memory hardware architecture disclosed herein is configured to implement the OR= instruction on a shared memory unit so that the new result does not replace the previously stored data. Instead, the data written to the memory is logically "OR" with the current value stored in the memory. Since the OR= instruction is well defined, the result is independent of the execution order. In addition, the storage unit does not have to be read before the result of the OR is written. Therefore, multiple processors can read and / or write to the shared memory concurrently, avoiding conflicts typically found in parallel computing.

[0032] The disclosed architecture can be implemented on a system with multiple processing cores operating in parallel, or on a single processing core running multiple parallel processing threads. For clarity, the technology disclosed herein will refer to a multi-core (e.g., hardware) processor; however, it should be understood that the technology is equally related to virtual processors, processing threads, etc. The disclosed technology can be software-implemented, hardware-implemented, or programmable hardware-implemented. The storage unit and any control logic can be implemented using suitable hardware components. For example, the storage unit can be implemented using one or more capacitors or triggers, and the control logic can include one or more diodes, OR gates, AND gates, etc.

[0033] In one embodiment, shared memory is implemented by limiting the instruction sets of multiple processors to OR= operations, however this is not intended to be limiting and the technique can be modified to accommodate addition operations, such as logical AND. For a one-bit variable, the x OR=y operation can be implemented with any of the following statements, where the symbol '==' indicates equality and the symbol '=' indicates assignment:

[0034] a) If y == 1 then x = 1

[0035] b) If y == 1 then x = 1, otherwise x = x

[0036] c) If y == 1, then x = y

[0037] d) If y == 1, then x = y, otherwise x = x.

[0038] As can be seen from the above rules, the OR= instruction complies with the requirement of well-defined calculations. The processor does not need to read the current value of the storage unit before using the current value to generate a new value through OR=. Since the result of the calculation is independent of the execution order, multiple processors can concurrently perform separate OR= operations on shared storage units without locking the shared memory, thereby allowing concurrent updates. The x AND=y statement can also be implemented by replacing 1 with 0, similar to statements a), b), c), and d) above, as shown below:

[0039] a) If y == 0, then x = 0

[0040] b) If y == 0, then x = 0, otherwise x = x

[0041] c) If y == 0, then x = y

[0042] d) If y == 0 then x = y, otherwise x = x

[0043] It should also be noted that the disclosed techniques may be implemented by machine-executable instructions (eg, software using the above-described rules or using an emulator).

[0044] In the following description, zero voltage is interpreted as false, also referred to as "0" or "low". Non-zero voltage is interpreted as true, and is referred to as "1" or "high". The disclosed technology is first presented using an OR= operation. The disclosed technology is also applied to an AND= operation by interpreting a zero voltage value as true and a non-zero voltage as false, without changing the circuit used. By changing the circuit, it is also applicable to any USCAE operator. It should also be noted that the OR= and AND= assignments do not include internal feedback in the storage cell. In addition, the storage cell implementing OR= may include a circuit associated with each processing agent that enables reading from and writing to the storage cell.

[0045] Reference now Figure 1A, which is a schematic diagram of a system for implementing concurrent OR=compound assignments on a shared one-bit DRAM storage cell, which is generally represented by reference symbol 100 and is constructed and operated according to an embodiment of the disclosed technology. System 100 enables one or more OR=compound assignments to be performed on a DRAM storage cell and initializes the DRAM memory to zero or one. System 100 includes a DRAM storage cell (represented by dashed line 116) for implementing concurrent OR=compound assignments, an initialization OR gate 102, an OR gate 104, an OR gate 106, a multiplexer 108, AND gates 110 and 112, and a capacitor 114. Initialization OR gate 102 has two input terminals 102A and 102B and an output terminal 102C. OR gate 104 has two input terminals 104A and 104B and an output terminal 104C. OR gate 106 has two input terminals 106A and 106B and an output terminal 106C. Multiplexer 108 has an input terminal 108A labeled "0" and an input terminal 108B labeled "1". Input terminal 108C and output terminal 108D are initialized. AND gate 110 has two input terminals 110A, 110B and an output terminal 110C. AND gate 112 has two input terminals 112A, 112B and an output terminal 112C.

[0046] The initialization OR gate 102 receives “Init0” from a first processor (not shown) via input 102A and receives “Init1” from a second processor (not shown) via input 102B. The initialization OR gate 102 allows the first processor and / or the second processor to send values ​​(i.e., Init0 from the first processor and Init1 from the second processor) directly to a memory cell without performing an OR= operation, for example, for initialization purposes. The output 102C of the initialization OR gate 102 is electrically coupled to the input 108D of the multiplexer 108, which receives the initialization signal and, when the initialization signal is “1”, it writes the output of the OR gate 106 to the memory cell accordingly. The OR gate 106 receives the logical AND of data (labeled DataW_Wen0) from the first processor at input 106A and writes the logical AND of the data to the memory cell 116 using a write enable signal. OR gate 106 receives the logical AND of data labeled DataW_Wen1 from the second processor at input 106B, and writes the logical AND of the data to memory cell 116 using the write enable signal. OR gate 106 performs a logical OR on the DataW_Wen0 signal and the DataW_Wen1 signal. Output 106C of OR gate 106 is electrically coupled to input 104B of OR gate 104, and is further electrically coupled to input 108B labeled “1” of multiplexer 108. Input 104A of OR gate 104 is electrically coupled to output 108D of multiplexer 108, i.e., the current value of capacitor 114, in a feedback loop. OR gate 104 performs a logical OR on the output from OR gate 106 (i.e., the logical OR of the input signals from the first processor and the second processor) and the contents of the memory cell, thereby implementing an OR= operation. Output 104C of OR gate 104 is electrically coupled to input 108A labeled “0” of multiplexer 108. Output 108D of multiplexer 108 is electrically coupled to capacitor 114 and input 104A of OR gate 104. In this manner, the values ​​received from the first and second processors are ORed with the contents of the memory cell to implement an OR=write operation.

[0047] To implement an OR= read operation, capacitor 114 is electrically coupled to input 110B of AND gate 110 and input 112B of AND gate 112. AND gate 110 receives a read enable signal Ren1 from the second processor at input 110A. AND gate 112 receives a read enable signal Ren0 from the first processor at input 112A. AND gate 112 performs a logical AND operation on the contents of the storage cell and the value of Ren0, allowing the first processor to read the contents of the storage cell when Ren0 is turned on (i.e., when Ren0=1). The first processor is electrically coupled to output 112C and receives DataR0 to read the contents of the storage cell. AND gate 112 performs a logical AND operation on the contents of the storage cell and the value of Ren0, allowing the first processor to read the contents of the storage cell when Ren0 is turned on (i.e., when Ren0=1). The second processor is electrically coupled to output 110C and receives DataR1 to read the contents of the storage cell. The OR= operation is implemented by logic integrated in the shared memory cell 116 and external to the processor. This logic is implemented using a feedback loop that couples the current value of capacitor 114 to OR gate 104 to feed multiplexer 108. The read enable line receives input from outside of shared memory cell 116.

[0048] Reference now Figure 1B , which is a schematic diagram of a system generally designated 120 constructed and operated in accordance with another embodiment of the disclosed technology, for implementing concurrent OR=compound assignments on a shared one-bit storage unit. System 120 enables one or more OR=compound assignments to be performed on a DRAM memory, and enables the DRAM memory to be initialized to 0. System 120 includes a storage unit (represented by dashed line 134) for implementing concurrent OR=compound assignments, a multiplexer 122, an OR gate 124, an initialization OR gate 126, AND gates 128 and 130, and a capacitor 132. Multiplexer 122 has an initialization input 122A, an input 122B corresponding to 0, an input 122C corresponding to 1, and an output 122D. OR gate 124 has inputs 124A, 124B, 124C, and an output 124D. Initialization OR gate 126 has inputs 126A, 126B, and an output 126C. AND gate 128 has input terminals 128A, 128B and an output terminal 128C. AND gate 130 has input terminals 130A, 130B and an output terminal 130C.

[0049] Initialization OR gate 126 receives a Zero0 signal from a first processor (not shown) via input 124A and a Zero1 signal from a second processor (not shown) at input 124B. Initialization OR gate 126 allows the first and second processors to zero a memory cell without performing an OR= operation, for example, for initialization purposes. Output 126C of initialization OR gate 126 is electrically coupled to input 122A of multiplexer 122, which receives the initialization signal and writes a zero to the memory cell in response. OR gate 124 receives a logical AND of data (labeled DataW_Wen0) from the first processor at input 124B, which is written to memory cell 134 from the first processor using a write enable signal. OR gate 124 receives a logical AND of data (labeled DataW_Wen1) from the second processor at input 124C, which is written to memory cell 134 from the second processor via a write enable signal. OR gate 124 performs a logical OR on the DataW_Wen0 signal and the DataW_Wen1 signal. The input terminal 124A of the OR gate 124 is electrically coupled to the output terminal 122D of the multiplexer 122, i.e., the value of the capacitor 132, in a feedback loop, thereby performing an OR= operation between the input signal and the contents of the memory cell. The output terminal 124D of the OR gate 124 is electrically coupled to the input terminal 122B of the multiplexer 122 corresponding to 0. The input terminal 122C of the multiplexer corresponding to 1 is grounded. The output terminal 122D of the multiplexer is electrically coupled to the capacitor 132 and the input terminal 124A of the OR gate 124. In this way, the values ​​received from the first processor and the second processor are ORed with the contents of the memory cell to implement an OR=write operation.

[0050] To implement an OR= read operation, capacitor 132 is electrically coupled to input 128B of AND gate 128 and input 130B of AND gate 130. AND gate 128 receives a read enable signal Ren1 from the second processor at input 128A. AND gate 130 receives a read enable signal Ren0 from the first processor at input 130A. AND gate 130 performs a logical AND operation on the contents of the storage cell and the value of Ren0, allowing the first processor to read the contents of the storage cell when Ren0 is turned on (i.e., when Ren0=1). The first processor is electrically coupled to output 130C and receives DataR0 to read the contents of the storage cell. AND gate 128 performs a logical AND operation on the contents of the storage cell and the value of Ren1, allowing the second processor to read the contents of the storage cell when Ren1 is turned on (i.e., when Ren1=1). The second processor is electrically coupled to output 128C and receives DataR1 to read the contents of the storage cell. The OR= operation is implemented by logic integrated in the shared memory cell 134 and external to the processor. The logic is implemented using a feedback loop that couples the current value of capacitor 132 to OR gate 124 to feed multiplexer 122. The read enable line receives input from outside of shared memory cell 134.

[0051] Reference now Figure 1C , which is a schematic diagram of a system generally designated 140 constructed and operative in accordance with another embodiment of the disclosed technology for implementing concurrent OR=compound assignments on a shared one-bit SRAM storage cell. System 140 is significantly similar in function to Figure 1A and Figure 1B The present invention relates to systems 100 and 120, which differ significantly in that a flip-flop 142 (static bit) replaces capacitors 114 and 132 (dynamic bit). System 140 enables one or more OR=compound assignments to be performed on a shared SRAM memory, and enables the SRAM memory to be initialized to zero. System 140 includes a shared storage unit (indicated by dashed line 148) for implementing an OR=compound assignment, a flip-flop 142, an OR gate 144, an OR gate 146, and AND gates 148 and 150. The flip-flop has inputs 142A, 142B, 142C and an output 142D. The OR gate has inputs 144A, 144B, 144C and an output 144D. The OR gate 146 has inputs 146A and 146B and an output 146C. The AND gate 148 has inputs 148A, 148B and an output 148C. AND gate 150 has input terminals 150A, 150B and an output terminal 150C.

[0052] Reset OR gate 146 receives a Zero0 signal from a first processor (not shown) via input 146A and / or receives a Zero1 signal from a second processor (not shown) at input 146B. Reset OR gate 146 allows the first processor and / or the second processor to reset the memory cell to 0 only. Reset OR gate 146 performs a logical OR on the Zero0 and Zero1 values. Output 146C of reset OR gate 146 is electrically coupled to input 142C of flip-flop 142, which corresponds to a reset signal (Rst) for the memory cell. Input 142A of flip-flop 142 may receive a clock signal (Clk) for synchronization.

[0053] OR gate 144 receives a logical AND of data (labeled as DataW_Wen0) from the first processor at input 144B, which is written to memory cell 148 from the first processor via a write enable signal. OR gate 144 receives a logical AND of data (labeled as DataW_Wen1) from the second processor at input 144C, which is written to memory cell 148 from the second processor via a write enable signal. Input 144A of OR gate 144 is electrically coupled to output 142D of flip-flop 142 in a feedback loop, thereby performing a logical OR on the contents of the memory cell and the input signal to implement an OR= operation. Output 144D of OR gate 144 is electrically coupled to input 142B of flip-flop 142. In this manner, the values ​​received from the first processor and the second processor are ORed with the contents of the memory cell to implement an OR=write operation.

[0054] To implement an OR=read operation, the output terminal 142D of the flip-flop 142 is electrically coupled to the input terminal 148B of the AND gate 148 and the input terminal 150B of the AND gate 150. The AND gate 148 receives the read enable signal Ren1 from the second processor at the input terminal 148A. The AND gate 150 receives the read enable signal Ren0 from the first processor at the input terminal 150A. The AND gate 150 performs a logical AND operation on the content of the storage cell and the value of Ren0, allowing the first processor to read the content of the storage cell when Ren0 is turned on (i.e., when Ren0=1). The first processor is electrically coupled to the output terminal 150C and receives DataR0 to read the content of the storage cell. The AND gate 148 performs a logical AND operation on the content of the storage cell and the value of Ren1, allowing the second processor to read the content of the storage cell when Ren1 is turned on (i.e., when Ren1=1). The second processor is electrically coupled to the output terminal 148C and receives DataR1 to read the content of the storage cell. The OR= operation is implemented by logic that is integrated with the shared memory cell 148 and is external to the processor. The logic is implemented using a feedback loop that couples the current value of the memory cell with the input values ​​DataW_Wen0 and DataW_Wen1, i.e., the output terminal 142D of the flip-flop 142 is coupled to the OR gate 144, which is fed to the input terminal 142B of the flip-flop 142. The read enable line receives input from outside the shared memory cell 148.

[0055] Reference now Figure 1D , which is a schematic diagram of a system generally designated 200 constructed and operative in accordance with another embodiment of the disclosed technology for implementing compound assignments on a shared one-bit SRAM memory cell. The system 200 is functionally similar to Figures 1A to 1C The systems 100, 120, and 140 are significantly similar, with a significant difference in that the system 200 implements a compound assignment f=, where f is a USCAE operator with a right unitary element (e.g., an exclusive OR XOR operation with a right unitary element of 0). The system 200 enables one or more Boolean operations to be performed on a shared SRAM memory, and enables the SRAM memory to be initialized to zero. The system 200 includes a shared memory unit 202 for implementing the compound assignment. The shared memory unit 202 includes an estimator 204, a flip-flop 206, a write enable OR gate 208, a clock AND gate 210, a clear OR gate 212, a first read AND gate 214, and a second read AND gate 216.

[0056] An input terminal 206A of the flip-flop 206 is coupled to an output terminal 204D of the estimator 204. An input terminal 206B of the flip-flop 206 is coupled to an output terminal 210C of the clock AND gate 210. An input terminal 206C of the flip-flop 206 is coupled to an output terminal 212C of the clear OR gate 212. An output terminal 206D of the flip-flop 206 is coupled to an input terminal 204A of the estimator 204, to an input terminal 214A of a first read AND gate 214, and to an input terminal 216A of a second read AND gate 216. An output terminal 208C of the write enable OR gate 208 is coupled to an input terminal 210A of the clock AND gate 210.

[0057] The input terminal 204B of the estimator 204 is configured to receive a first data signal ( Figure 1D , and the input terminal 204C of the estimator 204 is configured to receive the second data signal ( Figure 1D The input terminal 208A of the write enable OR gate 208 is configured to receive a first write enable signal ( Figure 1D ), and the input terminal 208B of the write enable OR gate 208 is configured to receive a second write enable signal ( Figure 1D The input terminal 210B of the clock OR gate receives the clock signal ( Figure 1D The input terminal 212A of the clear OR gate 212 is configured to receive a first clear memory signal ( Figure 1D 0), and the input terminal 212B of the clear OR gate 212 is configured to receive the second clear memory signal ( Figure 1D The input terminal 214B of the read enable AND gate 214 is configured to receive a first read enable signal ( Figure 1D ), and the input terminal 216B of the read enable AND gate 216 is configured to receive the second read enable signal ( Figure 1D marked as “REN 1” in the

[0058] The estimator 204 receives the current value of DATA_W0, DATA_W1, and the output terminal 206D of the flip-flop 206, and estimates ((206D f DATA_W0) f DATA_W1), and produces the result on the output line 204D. In order to write a value to the shared memory cell 202, the write enable OR gate 208 performs an OR operation on the inputs of its input terminals 208A and 208B. The clock OR gate 210 performs an AND operation on the output of CLK_SIG and the output terminal 208C of the write enable OR gate 208. Therefore, when WEN0 or WEN1 is high, and CLK_SIG is high, the input received by the input terminal 206A of the flip-flop 206 from the output terminal 204D of the estimator 204 is propagated through the flip-flop 206 to its output terminal 206D. The output terminal 206D of the flip-flop 206 is cleared when ZERO 0 or ZERO 1 is high.

[0059] When the first processor needs to read a value from the shared memory unit 202, the first processor sets REN 0 high, and the output of the output terminal 206D of the flip-flop 206 propagates through the read enable AND gate 214. When the second processor needs to read a value from the shared memory unit 202, the second processor sets REN 1 high, and the output of the output terminal 206D of the flip-flop 206 propagates through the read enable AND gate 216.

[0060] Reference now Figure 2, which is a schematic diagram of a system generally designated 250 constructed and operative in accordance with another embodiment of the disclosed technology for implementing an OR= instruction on DRAM memory cells accessed by a single core processor. System 250 includes a dynamic memory array 252, a processor 253, a data selector 254, a row selector 256, a row address strobe (RAS) line 258, a sense amplifier / comparator 259, a latch 260, a tri-state bus 262, a clear line 264 (active low), and a multiplexer (MUX) 266. System 250 also includes a set of write diodes 268(j), for example, write diode 268(1) is indicated as controlling the reading of column 1. Due to space considerations, only write diode 268(1) is labeled, while the remaining write diodes 268(2), 268(3), 268(4) corresponding to columns 2 to 4 from left to right (not labeled). The memory array 252 includes memory cells 252(i,j), where i represents a row of the memory 252 and j represents a column of the memory 252, for example, the memory cell in the upper left corner (corresponding to row 1, column 1) is represented by a dashed circle labeled 252(1,1). The memory array 252 is shown having 16 memory cells 252(i,j) arranged in a 4×4 grid, however, this is not intended to be limiting. Each memory cell 252(i,j) includes a switch 252S(i,j) and a capacitor 252C(i,j), such that the memory array includes an array of 16 switches coupled to 16 capacitors, for example, the switch corresponding to the memory cell 252(1,2) in the first row and second column is represented by a dashed circle labeled 252S(1,2). Similarly, the capacitor corresponding to the memory cell 252(1,3) in the first row and third column is represented by a dashed circle labeled 252C(1,3). In Figures 3A to 3G In the figure, the switch is exemplified by a field effect transistor (FET). However, it should be noted that, depending on system specifications and requirements, the switch can be implemented by a bipolar junction transistor (BJT). The memory array 252 also includes a plurality of row buses 252Row(i) and a plurality of column buses 252Col(j). Due to space limitations, only the top row 252Row(1) and the fourth column 252Col(4) are labeled, however, it should be understood that the memory array includes four row enable lines from top to bottom: 252Row(1), 252Row(2), 252Row(3) and 252Row(4); and four column buses from left to right: 252Col(1), 252Col(2), 252Col(3) and 252Col(4).

[0061] The processor 253 is electrically coupled to the memory 252 via the tri-state bus 262 and the data selector 254. For any given row i and column j of the memory array 252, the input terminal of the capacitor 252C(i,j) is electrically coupled to the corresponding first terminal of the switch 252S(i,j) (e.g., the collector of a p-type bipolar junction transistor-BJT or the drain of a p-type field effect transistor-FET), and the output terminal of the capacitor 252C(i,j) is electrically coupled to ground or a reference voltage. Along any row i of the memory array 252, for all columns j, the control terminal of the switch 252S(i,j) (e.g., the base of the BJT or the gate of the FET) is electrically coupled to the enable line 252Row(i), for example, to the control terminal of the switch 252S(1,j) through the enable line 252Row(1). For any given column j of the memory array 252, for all rows i, the second ends of the switches 252S(i,j) (e.g., the emitters of p-type BJTs or the sources of p-type FETs) are electrically coupled via column bus 252Col(j), for example, the second end of switch 252S(i,4) is electrically coupled via column bus 252Col(4). The row selector 256 is electrically coupled to all row enable lines 252Row(i). The RAS line 258 is electrically coupled to a multiplexer 266. All column buses 252Col(j) are coupled to the multiplexer 266. The zero line of the multiplexer 266 is coupled to a sense amplifier / comparator 259, and one line of the multiplexer 266 is coupled to a corresponding write diode 268(j). The sense amplifier / comparator 259 is electrically coupled to a latch 260. The latch 260 is electrically coupled to the data selector 254. The data selector 254 is electrically coupled to the row selector 256 .

[0062] Each row i of the memory array 252 implements a four-bit word, with each bit represented by a memory cell 252(i, j) of row i. Switches 252S(i, j) are enabled by row selector 256. Thus, processor 253 controls writing to memory 252 by writing a0, a1 to row selector 256, thereby writing to enable the selected row. The value written to row i by processor 253 is then stored in the corresponding capacitor 252C(i, j) of row i.

[0063] The processor 253 allows values ​​to be written to or read from the memory 252 via RAS 258. When RAS 258 is set to 0, the reading of the memory 252 is enabled for the selected memory cell 252 (i, j) of row i. By setting RAS 258 to 0, the multiplexer 266 is connected to the output of the memory 252 via the latch 260, the data selector 254 and the tri-state bus 262. The memory cell 252 (i, j) activated by the row selector 256 and the data selector 254 is read enabled. The processor 253 reads the contents of the read-activated memory cell 252 (i, j) via the tri-state bus 262.

[0064] When RAS258 is set to 1, the memory 252 is write-enabled for the selected memory cell 252(i, j). By setting RAS258 to 1, the column bus 252Col(j) is connected to the data selector 254 via the latch 260 and the write diode 268(j). The processor 253 writes a value to the memory cell 252(i, j) activated by the row selector 256 and the data selector 254 via the latch 260, the write diode 268(j), the multiplexer 266, and the column bus 252Col(j). Therefore, the capacitor 252C(i, j) of the memory cell 252(i, j) of row i is selected and stores the value received from the processor 253. Once the value 1 is written to a particular memory cell 252(i,j) to charge the corresponding capacitor 252C(i,j) of the memory cell 252(i,j), subsequent writes to the same memory cell 252(i,j), whether 0 or 1, do not affect the state of the capacitor, thereby implementing an OR= instruction. Since this operator is a USCAE operator, the execution order does not affect the final state of the memory array 252.

[0065] To reset a memory cell 252(i,j) of the memory array 252 to zero, the processor 253 selects a row for resetting by writing values ​​a0, a1 to the row selector 256. The processor 253 sets RAS258 to 1, thereby write-enabling the memory cell 252(i,j). The processor 253 writes 0 to the memory cell 252(i,j) selected by the row selector 256 and the data selector 254. The capacitor 252C(i,j) of the selected memory cell 252(i,j) is electrically coupled to the clear line 264 active low level and is discharged.

[0066] Reference now Figures 3A to 3G, which together form a schematic diagram of a system generally designated 300 constructed and operated in accordance with another embodiment of the disclosed technology for implementing multiple concurrent OR= instructions on shared DRAM storage cells concurrently accessed by multi-core processors. System 300 includes four independent DRAM controllers 320(1), 320(2), 320(3), and 320(4), each DRAM controller servicing a separate CPU processor 322(1), 322(2), 322(3), and 320(4), respectively. System 300 also includes a shared memory 302 configured to be concurrently read and written by CPU processors 322(1), 322(2), 322(3), and 320(4) via the independent DRAM controllers 320(1), 320(2), 322(3), and 320(4), respectively. Shared dynamic memory 302 is formed by an array of multiple storage cells C(i, j) corresponding to row i and column j. Each independent DRAM controller 320(1), 320(2), 320(3), and 320(4) has a connection array 303(1), 303(2), 303(3), and 303(4), respectively. The connection array 303(1), 303(2), 303(3), and 303(4) provides electrical communication between each independent DRAM controller 320(1), 320(2), 320(3), and 320(4) and the shared dynamic memory 302, so that each processing core 322(1), 322(2), 322(3), and 322(4) can read and write to the shared dynamic memory 302 simultaneously. A description of the connection between the independent DRAM controllers 320(1), 320(2), 320(3), and 320(4) and the shared memory 302 is described below with reference to Figure 3B Provided in more detail.

[0067] Each of the DRAM controllers 320(1), 320(2), 320(3), and 320(4) is substantially similar to Figure 2 The following description of DRAM controller 320(1) should be understood to relate to each of DRAM controllers 320(2), 320(3), and 320(4), where the index "1" may be replaced by 2, 3, or 4, respectively. Specifically, DRAM controller 320(1) includes a tri-state bus, data selector 304(1), latch 310(1), MUX 316(1), RAS 308(1), and row selector 306(1), which are substantially similar to the above description of the connectivity and functionality of shared memory 302. Figure 2The connectivity and functionality described above are similar to those described above, except that each capacitor is shared by DRAM controllers 320(1), 320(2), 320(3), and 320(4). Thus, processor 322(1) reads and writes any one of memory cells (i, j) via DRAM controller 320(1), such as Figure 2 Therefore, since each of the processing cores 322(1), 322(2), 322(3), 322(4) is coupled to the shared memory 302 via the DRAM controllers 320(1), 320(2), 320(3), and 320(4), respectively, each of the processing cores 322(1), 322(2), 322(3), and 322(4) simultaneously reads and writes any one of the storage units (i, j) of the shared memory 302.

[0068] Reference now Figure 3G , which shows an enlarged view of the memory cell C(1,1) of the shared memory 302, the memory cell C(1,1) corresponding to the memory cell located at row 1 column 1. The memory cell C(1,1) is understood to represent each memory cell (i,j) of the shared memory 302. Therefore, the following description of the memory cell C(1,1) is understood to be related to each memory cell (i,j) of the shared memory 302. Row enable line 303(1) ROW The switch 314(1) is integrated with the connection array 303(1) to provide a connection between the processing core 322(1) and the storage unit C(1,1); the power line 303(2) ROW The switch 314 (2) is integrated with the connection array 303 (2) to provide a connection between the processing core 322 (2) and the storage unit C (1, 1); the line 303 (3) ROW The switch 314 (3) is integrated with the connection array 303 (3) to provide a connection between the processing core 322 (3) and the storage unit C (1, 1); the power line 303 (4) ROW Switch 314(4) is integrated with connection array 303(4) to provide connection between processing core 322(4) and memory cell C(1,1).

[0069] Memory cell C(1,1) includes capacitor 312. Each of switches 314(1), 314(2), 314(3), and 314(4) is electrically coupled to one terminal of capacitor 312. The other terminal of capacitor 312 is electrically coupled to ground or a reference voltage. The gate of switch 314(1) is connected to enable line 303(1) via a row. ROW coupled to a row selector 306(1) which can be controlled by processing core 322(1); the gate of switch 314(2) is connected via row enable line 303(2) ROWcoupled to row selector 306(2) which can be controlled by processing core 322(2); the gate of switch 314(3) is connected via row enable line 303(3) ROW coupled to a row selector 306(3) controllable by a processing core 322(3); and the base of a switch 314(4) is connected via a row enable line 303(4) ROW 306(4) is coupled to a row selector 306(4) which may be controlled by a processing core 322(4). Thus, memory cell C(1,1) is simultaneously electrically coupled to each of row selectors 306(1), 306(2), 306(3) and 306(4) controlled by processing cores 322(1), 322(2), 322(3) and 322(4), respectively, via switches 314(1), 314(2), 314(3) and 314(4).

[0070] The operation of the above circuit is basically similar to Figure 2 2, but note that in addition to the four independent processing cores 322 (1), 322 (2), 322 (3) and 322 (4) can simultaneously read and write to the shared memory 302. It should also be noted that although the combination Figures 1A to 1D The described embodiments include a feedback loop in the storage unit, but in combination with Figure 2 and Figures 3A to 3G The described embodiments have no feedback loop in the memory cell.

[0071] Additional Embodiments

[0072] 1) Note that one or more of the above embodiments for implementing an OR= operation can be modified to implement an AND= operation on a shared memory by interpreting a zero voltage value as true and a non-zero voltage as false. This is the opposite of the interpretation of an OR= operation that interprets a zero voltage as false and a non-zero voltage as true.

[0073] 2) First of all, about Figure 1A , Figure 1B and Figure 1C The value received by the memory cell is the logical AND of the data to be written with the corresponding write enable signal. In these figures, the logical AND is represented by DataW_Wen0 and DataW_Wen1. Therefore, in these memory cells, there are no separate lines for the data to be written and the write enable signal. This can be done because when OR=, writing a zero to the memory cell does not change the content of the memory cell. In addition, it is possible to modify Figure 1A , Figure 1B and Figure 1C, so that there are no external read enable lines Ren0, Ren1, as shown below. The lines DataW_Wen0 and DataW_Wen1 will be renamed RW0, RW1, respectively. For i=0,1; RWi=0 indicates that a read is to be performed, and RWi=1 indicates that a write of 1 is to be performed to the OR-storage cell. RW0 is connected to the input of the first NOT gate, and the output of the first NOT gate is connected to Ren0, which is now an internal line. Similarly, RW1 is connected to the input of the second NOT gate, and the output of the NOT gate is connected to Ren1, which is now an internal line. Therefore, for i=0,1, when RWi=0, a read is performed, and when RWi=1, a write of 1 is performed to the OR-storage cell. Therefore, for each memory controller (or processor), there is only one line for initializing the read from and write to the OR-storage cell; there is no separate line for the data to be written.

[0074] 3) It should also be noted that the diagram of OR-memory SRAM is similar to Figure 3A , Figure 3B Similar, but uses flip-flops instead of capacitors. Also, there is no memory refresh circuit.

[0075] 4) Note further that Figure 3A , Figure 3B In , transistors are used to implement switches, but other technologies can also be used to implement these switches.

[0076] Those skilled in the art will appreciate that the disclosed technology is not limited to what has been specifically shown and described above. Instead, the scope of the disclosed technology is limited only by the appended claims.

Claims

1. A system for sharing concurrent access to a storage unit, comprising: at least one shared storage unit; an estimator coupled to the at least one shared memory cell and configured to evaluate an expression for performing a plurality of concurrent compound assignments on the at least one shared memory cell; as well as a plurality of processing agents coupled to an input of the estimator, The estimator allows each of the plurality of processing agents to perform a concurrent compound assignment on the at least one shared memory unit, wherein the compound assignment does not include a read operation of the plurality of processing agents on the at least one shared memory unit.

2. The system according to claim 1, wherein: The estimator executing the plurality of concurrent compound assignments is external to the plurality of processing agents.

3. The system according to claim 1, wherein: The estimator enables access to the shared memory unit when the plurality of processing agents are allowed to perform concurrent compound assignments on the at least one shared memory unit.

4. The system according to claim 1, wherein: The value received by the at least one shared memory cell is a logical AND of the data to be written using the corresponding write enable line.

5. The system according to claim 1, wherein: At least two of the plurality of processing agents are processing threads that are concurrently executed by a single processing core.

6. The system according to claim 1, wherein: At least two of the plurality of processing agents are independent processing cores.

7. The system according to claim 1, wherein: The estimator also receives a current value of the at least one shared memory cell at an input of the estimator via a feedback circuit.

8. The system according to claim 1, wherein: The compound assignment in the concurrent compound assignment is one of the following: Logical AND Logical OR; Logical XOR; add; reduce; take; remove; index; Modulus addition; Modulus minus.

9. A system for sharing concurrent access to a storage unit, comprising: at least one shared storage unit; a logic circuit coupled to the at least one shared memory cell and configured to perform one of a plurality of concurrent compound assignments of OR= and AND= on the at least one shared memory cell; as well as a plurality of processing agents coupled to the logic circuit, The logic circuit allows each of the plurality of processing agents to perform a concurrent compound assignment on the at least one shared memory unit, wherein the compound assignment does not include a read operation of the at least one shared memory unit by the plurality of processing agents.

10. The system according to claim 9, wherein: The at least one shared memory cell does not include a feedback circuit for receiving a current value of the at least one shared memory cell.

11. The system according to claim 9, wherein: For a first bit x and a second bit y, the compound assignment of the compound assignment is x OR=y, and the compound assignment is implemented by a statement selected from the group consisting of: If y == 1, then x = 1; If y == 1, then x = 1, otherwise x = x; If y == 1, then x = y; and If y == 1, then x = y, otherwise x = x.

12. The system according to claim 9, wherein: For a first bit x and a second bit y, the compound assignment of the compound assignment is x AND=y, and the compound assignment is implemented by a statement selected from the group consisting of: If y == 0, then x = 0; If y == 0, then x = 0, otherwise x = x; If y == 0, then x = y; and If y == 0, then x = y, otherwise x = x.

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