Semiconductor wafer processing method and cleaning brush head

Abstract

Some embodiments of the present disclosure provide a semiconductor wafer processing method and a cleaning brush head. The method includes using a cleaning brush head having a plurality of microstructures to perform a cleaning process on a support surface of a wafer seat. The microstructures are spaced apart from each other by a spacing and have a tapered width. The method also includes placing a semiconductor wafer on the support surface of the wafer seat. The method also includes performing a lithography process on the semiconductor wafer.

Description

Technical Field

[0001] Some embodiments disclosed herein relate to a semiconductor wafer processing method and a tool thereof, and more particularly to a semiconductor wafer lithography process and a cleaning brush head for cleaning a lithography tool. Background Art

[0002] The semiconductor integrated circuit industry has experienced a period of rapid growth. Advances in integrated circuit materials and design have resulted in each generation of integrated circuits becoming smaller and more complex than the previous generation. In the course of integrated circuit development, functional density (e.g., the number of interconnects per chip area) has generally increased, while geometry size (e.g., the smallest component (or circuit) that can be created by the process) has generally decreased. This process of miniaturization generally provides many benefits by increasing production efficiency and reducing associated costs.

[0003] However, this miniaturization has also increased the complexity of integrated circuit processing and manufacturing. In order to achieve such progress, the same progress is needed in integrated circuit processing and manufacturing.

[0004] Photolithography is a process that uses light to transfer a pattern onto a photosensitive material covering a semiconductor substrate by irradiating a master mask with a pattern. Throughout the history of the semiconductor industry, photolithography resolution has been improved by reducing the exposure wavelength of the photolithography radiation source to achieve smaller minimum feature sizes for integrated chips. Among the higher-resolution photolithography techniques, extreme ultraviolet (EUV) lithography uses extreme ultraviolet (EUV) light with an exposure wavelength between 10nm and 130nm and is a promising next-generation photolithography solution for emerging technology nodes (e.g., 32nm, 22nm, 14nm, etc.).

[0005] Although existing photolithography techniques are generally adequate for the intended purpose, they are still not completely satisfactory in all aspects. Summary of the invention

[0006] Some embodiments of the present disclosure provide a semiconductor wafer processing method. The method includes using a cleaning brush head having a plurality of microstructures to perform a cleaning process on a support surface of a wafer seat. The microstructures are spaced apart from each other by a spacing and have a tapered width. The method also includes placing a semiconductor wafer on the support surface of the wafer seat. The method also includes performing a lithography process on the semiconductor wafer.

[0007] Some embodiments of the present disclosure provide a semiconductor wafer processing method. The method includes using a cleaning brush head having a plurality of conical microstructures to perform a cleaning process on a support surface of a wafer seat. The method also includes placing a semiconductor wafer on the support surface of the wafer seat. The method also includes performing a lithography process on the semiconductor wafer.

[0008] Some embodiments of the present disclosure provide a cleaning brush head. The cleaning brush head is suitable for cleaning a supporting surface of a wafer seat supporting a semiconductor wafer, wherein the supporting surface includes a plurality of grooves having a predetermined width. The cleaning brush head includes an upper surface and a plurality of microstructures. The plurality of microstructures are spaced apart from each other by a spacing, and the microstructures gradually decrease from a first width to a second width in a direction away from the upper surface, wherein the second width is smaller than the predetermined width of the groove. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The aspects of the present disclosure can be better understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the size of each feature may be arbitrarily increased or reduced for clarity of discussion.

[0010] Figure 1 A schematic diagram showing a processing system according to some embodiments of the present disclosure;

[0011] Figure 2 A schematic diagram showing an exposure module according to some embodiments of the present disclosure;

[0012] Figure 3 show Figure 2 A magnified structural diagram of region M1;

[0013] Figure 4 A schematic diagram showing a cleaning brush head according to some embodiments of the present disclosure;

[0014] Figure 5 show Figure 4 A magnified view of the structure of region M2;

[0015] Figure 6 A side view showing a microstructure according to some embodiments of the present disclosure;

[0016] Figure 7 A schematic diagram showing the bottom surface of a microstructure according to some embodiments of the present disclosure;

[0017] Figure 8 Schematic diagram showing the bottom surface of the microstructure of various embodiments of the present disclosure;

[0018] Fig. 9 Schematic diagram showing a plurality of microstructures according to some embodiments of the present disclosure;

[0019] Fig.10A schematic top view showing a plurality of microstructures according to some embodiments of the present disclosure;

[0020] Fig.11 Schematic cross-sectional view showing a plurality of microstructures of some embodiments of the present disclosure;

[0021] Fig.12 A flowchart showing a semiconductor wafer processing method executed in some embodiments of the present disclosure;

[0022] Fig.13 A schematic diagram showing a step of a semiconductor wafer processing method performed according to some embodiments of the present disclosure;

[0023] Fig.14 Schematic diagram showing the microstructures of some embodiments of the present disclosure after being used for a predetermined period of time.

[0024]

Explanation of symbols

[0025] 1: Processing system

[0026] 3: Carrying box

[0027] 5: Semiconductor wafer

[0028] 7: Loading port

[0029] 9: Loading port

[0030] 10: Photoresist coating module

[0031] 20: Grinding module

[0032] 30: Exposure module

[0033] 31: Light Source

[0034] 32:Lighting device

[0035] 321: Adjustment mirror

[0036] 33: Photomask

[0037] 331: Light-transmitting substrate

[0038] 332: Patterned absorption layer

[0039] 333: Absorption area

[0040] 34: Objective lens module

[0041] 341:Objective

[0042] 342: Objective lens

[0043] 35: Wafer seat

[0044] 350: Support surface

[0045] 351: Wafer suction plate

[0046] 352: Mobile mechanism

[0047] 353: Upper surface

[0048] 354: protrusion

[0049] 355: Top

[0050] 356: Lattice structure

[0051] 357: Groove

[0052] 358: Pollution particles

[0053] 36: Fluid maintenance device

[0054] 37: Driving parts

[0055] 38: Infiltration fluid

[0056] 39: Beam

[0057] 40: Clean the brush head

[0058] 41: Upper surface

[0059] 411: Ring Area

[0060] 412: Ring area

[0061] 42: Microstructure

[0062] 420: Bottom

[0063] 421: bottom edge

[0064] 422: Side

[0065] 423: Edge

[0066] 424: Vertex

[0067] 425: Flat surface

[0068] 426: Outstanding Features

[0069] 43: Chip removal channel

[0070] 42a: Microstructure

[0071] 421a: bottom edge

[0072] 424a: Vertex

[0073] 43a: Chip removal channel

[0074] 42b: Microstructure

[0075] 43b: Chip removal channel

[0076] 42c: Microstructure

[0077] 421c: bottom edge

[0078] 423c: Edge

[0079] 51: Base material

[0080] 52: Photoresist layer

[0081] 511: Back

[0082] A1: Angle

[0083] A2: Angle

[0084] D1: Width

[0085] D2: Spacing

[0086] D3: First width

[0087] D4: Second width

[0088] D6: Spacing

[0089] D7: Width

[0090] D8: Width

[0091] L: Long axis direction

[0092] M1: Area

[0093] M2: Area

[0094] S10: Methods

[0095] S11: Operation

[0096] S12: Operation

[0097] S13: Operation DETAILED DESCRIPTION

[0098] The following disclosure provides many different embodiments or examples to implement the different features of the present disclosure. The following disclosure in this specification describes specific examples of various components and their arrangement in order to simplify the description of the invention. Of course, these specific examples are not intended to limit the present disclosure. For example, if the following disclosure in this specification describes forming a first feature on or above a second feature, it means that it includes an embodiment in which the first feature formed is in direct contact with the second feature, and also includes an embodiment in which an additional feature can be formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, different examples in the description of the present disclosure may use repeated reference symbols and / or words. These repeated symbols or words are for the purpose of simplification and clarity, and are not used to limit the relationship between the various embodiments and / or the described appearance structures.

[0099] Furthermore, in order to facilitate the description of the relationship between an element or feature component and another (plural) element or (plural) feature component in the accompanying drawings, spatially related terms may be used, such as "under...", "below", "lower", "above", "upper" and similar terms. It is understood that in addition to the orientations shown in the accompanying drawings, spatially related terms cover different orientations of the device in use or operation. The device may also be positioned otherwise (for example, rotated 90 degrees or located in other orientations), and the description of the spatially related terms used may be interpreted accordingly. It is understood that additional operating steps may be provided before, during and after the method, and in some method embodiments, some of the operating steps described may be replaced or omitted.

[0100] It should be noted that the embodiments discussed herein may not necessarily describe every component or feature that may be present in the structure. For example, one or more components may be omitted from the drawings, such as when the discussion of the component may be sufficient to convey the various aspects of the embodiment. Furthermore, the method embodiments discussed herein may be discussed in a particular order of proceeding, however, in other method embodiments, they may be proceeded in any reasonable order.

[0101] The manufacturing of integrated circuits has progressed from large-scale integrated circuit design to ultra-large-scale integrated circuit design. The entire integrated circuit manufacturing process has changed with the design method. Due to the large-scale, the size of a single semiconductor component has decreased, and the line width of the integrated circuit has continued to shrink, from the sub-micron stage to the deep sub-micron stage. Therefore, in addition to overcoming the difficulties in component design, the manufacturing process of integrated circuits also has difficulties in component manufacturing. For example, in the process of integrated circuits, integrated circuits use lithography to project fine patterns on the surface of semiconductor wafers. The smaller the line width of the pattern, the more difficult the lithography process is, or a more advanced lithography machine is needed to achieve the purpose of successfully transferring the pattern.

[0102] In the lithography process of integrated circuits, the pattern on the mask is transferred to the surface of the semiconductor wafer by using light projection. In the process of preparing for light projection, the projected light is accurately focused on the surface of the semiconductor wafer so that the pattern can be accurately formed on the surface of the silicon wafer. Therefore, various focusing methods are used in the lithography process of integrated circuits. It is worth noting that the exposure method of semiconductor wafers is to divide the semiconductor wafer into several exposure areas, and then perform multiple exposure processes. An exposure process is performed on one exposure area, and each exposure process requires a focusing process so that the pattern can be accurately formed on the surface of the semiconductor wafer.

[0103] In the process of focusing semiconductor wafers, the position of semiconductor wafers is adjusted to achieve accurate focusing. The way to adjust semiconductor wafers is nothing more than rotating and moving semiconductor wafers so that the surface of semiconductor wafers can be parallel to the projection lens of the lithography machine, and appropriately adjusting the height position of semiconductor wafers so that the surface of semiconductor wafers can be located within the focusing range of the lithography machine. In the process of focusing semiconductor wafers, the rotation angle of semiconductor wafers to the horizontal plane and the height of rise or fall become the focusing parameters of semiconductor wafers. Factory managers use these parameters to understand whether the semiconductor wafer is parallel to the projection lens of the lithography machine to determine whether the projected light is indeed focused on the surface of the semiconductor wafer. In the production line of semiconductor factories, several silicon wafers are used as a batch of production units. After the whole batch of silicon wafers undergoes the lithography process, the focusing parameters of the whole batch of silicon wafers are counted to determine whether these silicon wafers are aligned.

[0104] However, there are often exceptions in the process of adjusting the position of the silicon wafer. For example, there are contamination particles at the bottom of the silicon wafer, which causes a protrusion to form on a certain surface of the silicon wafer, and this surface is smaller than the range of an exposure area. Therefore, in the focusing process of the lithography process, the lithography machine uses a laser beam to scan most of an exposure area to obtain an average parameter as a basis for adjusting the position of the semiconductor wafer. However, after the semiconductor wafer is adjusted according to this average parameter, the projected light of the lithography machine still cannot accurately focus on this protruding area, causing focus misalignment in certain areas on the silicon wafer.

[0105] The above-mentioned misalignment in the lithography process caused by contamination particles or contamination on the back of the silicon wafer is difficult to correct using a general lithography process. Instead, after completing the lithography process for a batch of silicon wafers, the entire silicon wafer is inspected under a microscope to find out whether the above-mentioned situation has occurred, so as to understand the process status of the entire batch of semiconductor wafers and determine whether there is abnormal focusing. The factors causing the abnormal focusing phenomenon can be removed immediately, so that defocusing alignment will not occur in the lithography process of the next batch of silicon wafers, thereby effectively reducing the cost of integrated circuit production.

[0106] To solve the above problems, some embodiments of the present disclosure provide a cleaning method through a wafer bed, which uses a plurality of microstructures with specific geometric shapes to clean the wafer bed, so as to effectively remove contaminant particles above the wafer bed and avoid abnormal focusing during the lithography process.

[0107] Figure 1 A schematic diagram of a processing system 1 according to some embodiments of the present disclosure is shown. According to the embodiments of the present disclosure, the processing system 1 includes a photoresist coating module 10, a grinding module 20, an exposure module 30 and one or more loading ports, such as two loading ports 7 and 9. The configuration and number of modules of the processing system 1 can be increased or decreased according to demand, and are not limited to this embodiment.

[0108] The load ports 7 and 9 are configured to place the carriers 3 that can be used to load multiple semiconductor wafers 5, and the processing system 1 has openings relative to the load ports 7 and 9 for the semiconductor wafers 5 to pass through. In some embodiments, the carrier 3 located on the load port 7 is used to place the semiconductor wafers 5 to be processed, and the carrier 3 located on the load port 9 is used to place the semiconductor wafers 5 that have been processed in the processing system 1. It should be understood that the number of load ports of the processing system 1 can be increased or decreased according to demand, and is not limited to one load port. Figure 1 The embodiment shown is limited. In addition, the placement positions of the loading port 7 and the loading port 9 of the processing system 1 can also be changed. For example, the loading port 7 and the loading port 9 of the processing system 1 are arranged adjacent to each other.

[0109] In some embodiments, after the semiconductor wafer 5 enters the processing system 1, it is processed in sequence through the photoresist coating module 10, the grinding module 20 and the exposure module 30. The semiconductor wafer 5 supplied to the carrier box 3 on the loading port 7 undergoes a photoresist coating process in the photoresist coating module 10 and is sent to the grinding module 20 to planarize the photoresist. Next, the semiconductor wafer 5 is sent from the grinding module 20 to the exposure module 30 so that the photoresist on the surface of the semiconductor wafer 5 is exposed in the exposure module 30. Finally, the semiconductor wafer 5 is sent from the exposure module 30 to the carrier box 3 located on the loading port 9. Thereafter, the wafer is transferred to another semiconductor device, such as an etching device or a chemical vapor deposition (CVD) device. The movement of the semiconductor wafer 5 can be achieved through one or more robotic arms (not shown) disposed in the processing system 1. Figure 1 )implement.

[0110] In some embodiments, the processing parameters of the photoresist coating module 10, the grinding module 20, and the exposure module 30 and the transport time of the semiconductor wafer 5 through the above-mentioned robot arm can be pre-programmed in a computer or microprocessor (not shown). Figure 1 ) to perform the operation.

[0111] According to some embodiments of the present disclosure, the structural features of the exposure module 30 are described as follows:

[0112] Figure 2 A schematic diagram of an exposure module 30 of some embodiments of the present disclosure is shown. According to the embodiments of the present disclosure, the exposure module 30 is used to implement a lithography process to form a pattern on a photoresist. In some embodiments, the exposure module 30 includes a light source 31, an illumination device 32, a mask 33, an objective lens module 34, a wafer seat 35, and a fluid maintenance device 36. The light source 31 is located above the illumination device 32. The light source 31 is used to irradiate a light beam 39 to the illumination device 32.

[0113] In some embodiments, the light source 31 is a mercury lamp having a wavelength in the range of about 436 nm (G-line) to 365 nm (I-line), a Krypton Fluoride (KrF) excimer laser having a wavelength of about 248 nm, an Argon Fluoride (ArF) excimer laser having a wavelength of about 193 nm, a Fluoride (F2) excimer laser having a wavelength of about 157 nm, or other light sources having a desired wavelength (e.g., less than about 100 nm).

[0114] It can be understood from the above description of the light source that each light source may have a general wavelength distribution, or line width, rather than a precise single wavelength. For example, the I-line (e.g., 365nm) wavelength of a mercury lamp does not need to be exactly 365nm, but can be a range of wavelengths that are mainly roughly concentrated around 365nm, and the wavelengths can be higher or lower than 365nm. This range can be used to determine a minimum possible line width in the lithography process, and it has some small changes to the desired wavelength of 365nm to result in a narrower line width.

[0115] The lighting device 32 is located between the light source 31 and the light shield 33 . In some embodiments, the lighting device 32 is a condenser device for concentrating the light beam 39 onto the light shield 33 .

[0116] The lighting device 32 includes a single lens or a lens group having multiple lenses and / or other lens elements. For example, the lighting device 32 may include a microlens array, a shadow mask, and / or other structures designed to directly help light from the light source 31 to the light mask 33. In some embodiments, the lighting device 32 includes a plurality of adjustment mirrors 321 arranged in an array. In addition, the lighting device 32 includes a drive member 37. The drive member 37 is configured to move the position of the adjustment mirror 321 in a vertical direction. Alternatively, the drive member 37 is configured to move the position of the adjustment mirror 321 in a horizontal direction. Alternatively, the drive member 37 is configured to rotate the adjustment mirror 321 so that the adjustment mirror 321 is tilted relative to the horizontal plane.

[0117] The mask 33 is located between the lighting device 32 and the wafer base 35. In some embodiments, the mask 33 is located between the lighting device 32 and the objective lens module 34. The mask 33 is used to partially shield the light beam 39 and form a pattern on the semiconductor wafer 5. Different patterns can be formed on different wafers by replacing the mask 33 in the exposure module 30.

[0118] The mask 33 may be referred to as a mask or a reticle. The mask 33 includes a light-transmitting substrate 331 and a patterned absorption layer 332 disposed on the light-transmitting substrate 331. When the light beam passes through the absorption region 333 of the patterned absorption layer 332, the light beam 39 is partially or completely blocked.

[0119] The objective lens module 34 is located between the wafer base 35 and the mask 33. The objective lens module 34 is used to focus the light beam 39 onto the semiconductor wafer 5. In some embodiments, the objective lens module 34 includes a single objective lens or a plurality of objective lenses 341 and 342.

[0120] The wafer seat 35 is located under the mask 33 and the objective lens module 34. The wafer seat 35 is used to hold the semiconductor wafer 5. The wafer seat 35 includes a wafer suction plate 351 and a moving mechanism 352. The wafer suction plate 351 is used to hold the semiconductor wafer 5. In some embodiments, the wafer suction plate 351 is an electrostatic suction plate. The moving mechanism 352 is used to move the wafer suction plate 351 laterally or rotate the wafer suction plate 351. Therefore, the semiconductor wafer 5 has the ability to move in a lateral or rotational mode, so that the semiconductor wafer 5 can be aligned with the mask 33. The fluid maintenance device 36 is located between the mask 33 and the wafer seat 35 (or the semiconductor wafer 5). The fluid maintenance device 36 is used to maintain the immersion liquid 38.

[0121] In some embodiments, the semiconductor wafer 5 includes a substrate 51 and a photoresist layer 52. The photoresist layer 52 is coated on the substrate 51 by a coating process. The photoresist layer 52 reacts in an exposure process to form a pattern. The photoresist layer 52 includes positive photoresist or negative photoresist.

[0122] According to some embodiments, the substrate 51 is made of silicon, germanium or other semiconductor materials. According to some embodiments, the substrate 51 is made of a compound semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs) or indium phosphide (InP). According to some embodiments, the substrate 51 is made of an alloy semiconductor, such as silicon germanium (SiGe), silicon germanium carbon (SiGeC), gallium arsenide phosphide (GaAsP) or gallium indium phosphide (GaInP). According to some embodiments, the substrate 51 includes a crystalline film layer. For example, the substrate 51 has a crystalline film layer covering a bulk semiconductor. According to some embodiments, the substrate 51 may be a silicon-on-insulator (SOI) or a germanium-on-insulator (GOI) substrate.

[0123] The substrate 51 may include a plurality of device elements. For example, the device elements formed on the substrate 51 may include a transistor, such as metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor transistors (CMOS) transistors, bipolar junction transistors (BJT), high voltage transistors, high frequency transistors, p-channel and / or n-channel field-effect transistors (PFET) or n-channel field-effect transistors (NFET), and / or other elements. The plurality of device elements on the substrate 51 have undergone a plurality of processing steps, such as deposition, etching, ion implantation, photolithography, annealing, and / or other processes.

[0124] Figure 3 show Figure 2 FIG. 3 is an enlarged view of the structure of the region M1 of the wafer bed 35. In some embodiments, the upper surface 353 of the substrate 351 of the wafer bed 35 has a plurality of protrusions (Burl) 354 formed thereon. In addition, the top surface 355 of each protrusion 354 has a plurality of lattice structures 356. The substrate 351 supports the semiconductor wafer 51 through the top surface 355 of the protrusion 354, wherein the top surfaces 355 of the plurality of protrusions 354 form the supporting surface 350 of the wafer bed 35. In one embodiment, the lattice structure 356 includes a silicon carbide (SiC) lattice, and grooves 357 are formed between the lattice structures 356. The grooves 357 have a predetermined width between about 5 microns and 10 microns.

[0125] In some embodiments, Figure 3 As shown, the support surface 350 of the wafer bed 35 may be attached with contamination particles 358. The contamination particles 358 may come from the photoresist material remaining on the back side 511 of the previously processed semiconductor wafer 5, or may be caused by the wear of the wire of the handling tool used to carry the semiconductor wafer. These contamination particles will be stuck to the grooves 357 between the lattice structures 356 and the surface of the lattice structures 356. When the next processed semiconductor wafer 5 is placed on the support surface 350 of the wafer bed 35, the back side 511 of the semiconductor wafer 5 will not be able to be closely attached to the support surface 350 of the wafer bed 35, thereby causing the flatness of a part of the semiconductor wafer 5 to be reduced.

[0126] To improve the above problems, some embodiments of the present disclosure provide a cleaning brush head 40 for cleaning the supporting surface 350 of the wafer base 35 .

[0127] Figure 4 A schematic diagram showing a cleaning brush head 40 according to some embodiments of the present disclosure is shown. Figure 5 show Figure 4 In one embodiment, the cleaning brush head 40 is a cylinder, but the present disclosure is not limited thereto. The appearance of the cleaning brush head 40 can be changed according to needs, or a suitable gripping structure can be formed to facilitate the maintenance personnel to grasp it. In one embodiment, the cleaning brush head 40 has an upper surface 41. The upper surface 41 can be a flat surface or a circular arc surface.

[0128] like Figure 5 As shown, a plurality of microstructures 42 are formed on the upper surface 41. The microstructures 42 are arranged in rows parallel to the long axis direction L, and the microstructures 42 have a spacing D2 (the distance between the vertices 424). In addition, each row of microstructures 42 is spaced apart from each other by a spacing, thereby forming a chip removal channel 43 (that is, the chip removal channel 43 extends parallel to the long axis direction L). Moreover, in each row of microstructures 42, a chip removal channel 43 is also formed between each microstructure 43. The chip removal channel 43 has a width D1. The distance D2 is approximately 4-6 times the width D1. In an exemplary embodiment, the spacing D2 of the microstructures 42 is approximately 330 microns, and the width D1 of the chip removal channel 43 is approximately 58 microns. In this way, the contaminated particle crystals removed from the support surface 350 of the wafer seat 35 can be removed through the chip removal channel 43, thereby improving the cleaning effect.

[0129] In some embodiments, the microstructures 42 have the same height H. Specifically, Figure 5 As shown, the microstructure 42 extends outward from the upper surface 41 and terminates at a vertex 424. The height H between the vertex of the microstructure 424 and the upper surface 41 is different.

[0130] It is to be understood that the embodiments of the present disclosure may have many variations and are not limited thereto. In other embodiments, such as Figure 4 As shown, the upper surface 41 of the cleaning brush head 40 has a plurality of annular regions 411 and 412 arranged concentrically. Each of the annular regions 411 and 412 has a microstructure 42 formed thereon. The height of the microstructure 42 in the annular region 411 away from the center of the upper surface 41 of the cleaning brush head 40 is lower than the height of the microstructure 42 in the annular region 412 close to the center of the upper surface 41 of the cleaning brush head 40. Since the force may be concentrated in the central region of the cleaning brush head 40 when it is held manually, the configuration of the central region with a lower microstructure can disperse the force of pressing the support surface 350 of the wafer seat 35, thereby avoiding scratches on the support surface 350 of the wafer seat 35.

[0131] In some embodiments, the microstructure 42 is conical, and thus has a gradually decreasing width in a direction away from the upper surface 41. Figure 6 As shown, the side 422 of the microstructure 42 is triangular, the base 42 has a first width D3, and the vertex 424 has a second width D4. The first width D3 is greater than the second width D4. In an exemplary embodiment, the first width D3 is about 350 microns, and the second width D4 is equal to 0 microns or slightly greater than 0 microns. In an embodiment, the second width D4 is less than the width of the grooves 357 between the lattices 356.

[0132] In one embodiment, the side surface 422 of the microstructure 42 has a symmetrical structure (for example, the side surface 422 of the microstructure 42 is an isosceles triangle), and its bottom angle A1 (the angle between the edge 423 and the bottom 421) is between about 20 degrees and 70 degrees. In another embodiment, the side surface 422 of the microstructure 42 has an asymmetrical structure. In one embodiment, as Figure 7 As shown, the bottom surface 420 of the microstructure 42 is triangular.

[0133] In one embodiment, the microstructure 42 has a hardness similar to or higher than that of the contamination particle 358 to increase the service life. In one exemplary embodiment, the contamination particle 358 is TiN with a Vickers hardness of about 2000. In order to effectively remove the contamination particle by the cleaning process, the hardness of the microstructure 42 has a Vickers hardness between about 1200 and about 10000. In one embodiment, the hardness of the microstructure 42 has a Vickers hardness between about 1500 and about 3500.

[0134] The microstructure 42 can be made of any material with suitable hardness, such as zirconium dioxide (ZrO 2 , Vickers hardness is about 1200), silicon nitride (Si 3 N 4 , with a Vickers hardness between about 1500 and about 1600), aluminum nitride (AlN, with a Vickers hardness between about 1350 and about 1700), a composite material composed of aluminum oxide and titanium carbide (Al 2 O 3 -TiC (Vickers hardness is about 2100), silicon carbide (SiC, Vickers hardness is about 2500), diamond (Vickers hardness is about 10000) or a combination thereof.

[0135] It is understood that the shape and size of the microstructure 42 are not limited thereto, and any microstructure that can be used to clean a wafer seat can be formed on the cleaning brush head 40 of the present disclosure. Various variations of the microstructure are provided below.

[0136] Figure 8The bottom surface of the microstructure 42 of the present disclosure is shown in schematic form. In some embodiments, the bottom surface of the microstructure 42 has a shape other than Figure 7 In addition to the triangle shown, the bottom surface of the microstructure 42 can also be rectangular, circular, trapezoidal, polygonal, or a combination thereof. In some embodiments, microstructures 42 with different bottom surface shapes are arranged adjacent to each other on the upper surface 41 ( Figure 4 ). The plurality of microstructures 42 with different bottom surface shapes may have the same consistent height (ie, the distance between the vertex and the upper surface 41 of the cleaning brush head 40 ), but have different bottom surface shapes.

[0137] Fig. 9 A schematic diagram showing a microstructure 42a of some embodiments of the present disclosure. In some embodiments, the microstructure 42a is a plurality of triangular prisms parallel to each other and arranged in sequence on the long axis direction L. The microstructure 42a has a gradually decreasing width in the direction away from the upper surface 41. In the long axis direction L, there is a spacing D6 (the spacing between the vertices 424a of the microstructure 42a), and each microstructure 42a is separated by a chip removal channel 43a, and the chip removal channel 43a has a width D7, and the bottom edge 421a of the microstructure 42a has a width D8. The spacing D6 is approximately 4-6 times the width D7. In an exemplary embodiment, the width of the spacing D6 is 54 microns, the width D7 is 8.3 microns, and the width D8 is 52 microns.

[0138] Fig.10 A schematic top view of a microstructure 42b of some embodiments of the present disclosure is shown. In some embodiments, the microstructure 42b is a dot-shaped structure and has a circular or elliptical transverse cross-section. In some embodiments, multiple rows of microstructures 42b are arranged in sequence along the long axis direction L to form a matrix array. In some embodiments, there is a chip removal channel 43b between adjacent microstructures 42b.

[0139] , they are separated by a distance and are not adjacent to each other.

[0140] Fig.11 A cross-sectional view of the microstructure 42 and the microstructure 42c of some embodiments of the present disclosure is shown. In some embodiments, microstructures with different bottom angles are arranged alternately to produce different cleaning effects. Fig.11In the illustrated embodiment, the microstructures 42 and the microstructures 42c are arranged alternately in the long axis direction L, wherein the bottom angle A1 between the edge 423 and the bottom edge 421 of the microstructure 42 is different from the bottom angle A2 between the edge 423c and the bottom edge 421c of the microstructure 42c. In one embodiment, the bottom angle A1 is between about 45 degrees and about 70 degrees, and the bottom angle A2 is between about 20 degrees and about 45 degrees. In this way, the vertices of the microstructures 42 and the microstructures 42c have different sharpness, and deep cleaning can be performed on different lattice surfaces.

[0141] Fig.12 A flowchart showing a method S10 for performing a semiconductor wafer processing according to some embodiments of the present disclosure is shown. It is understood that additional operations may be provided in Fig.12 Before, during and after the operations shown. For other embodiments of the method, some of the operations described below may be replaced or reduced. The order of operations / processes may be interchangeable. The following embodiments may adopt the materials, configurations and dimensions described in the above embodiments, and their detailed description may be omitted.

[0142] The method S10 includes an operation S11, using a cleaning brush head 40 having a plurality of microstructures (e.g., microstructures 42) sequentially arranged along the long axis direction L to perform a cleaning process on the support surface 350 of the wafer bed 35. In some embodiments, the operation S11 is performed manually and is performed after the previous batch of semiconductor wafers are removed from the wafer bed 5 after completing the lithography process. When performing the cleaning process, the upper surface 41 of the cleaning brush head 40 faces the support surface 350 of the wafer bed 35, so that the microstructures 42 contact the support surface 350 of the wafer bed 35. In some embodiments, such as Fig.13 As shown, since the microstructure 42 can extend into the groove 357 to remove the contamination particles 358, the contamination particles 358 can be effectively removed from the supporting surface 350, so no contamination particles 358 will remain in the groove 357 after cleaning.

[0143] In some embodiments, Fig.14 As shown, after a predetermined time of performing operation S11, the microstructure 42 may be worn, so that the top of the microstructure 42 has a flat surface 425. At this time, since the flat surface 425 and the edges of the microstructure 42 still have protruding features 426, the support surface 350 of the wafer bed 35 can still be cleaned, and the contaminated particles in the groove 357 can be effectively removed. According to an experimental result, before the microstructure 42 is worn to the bottom edge 420, the cleaning effect of the microstructure 42 on the support surface 350 of the wafer bed 35 is always greater than the conventional use of irregularly shaped marble to clean the wafer bed 35.

[0144] The method S10 includes an operation S12 of placing the semiconductor wafer 5 on the supporting surface 350 of the wafer bed 35. In some embodiments, since the supporting surface 350 of the wafer bed 35 has been cleaned, no contamination particles remain on the supporting surface 350 of the wafer bed 35, so the semiconductor wafer 5 can be placed flat on the supporting surface 350 of the wafer bed 35.

[0145] The method S10 includes an operation S13 of performing a lithography process on the semiconductor wafer 5. In some embodiments, Figure 2 As shown, in the lithography process, the light source 31 emits a light beam 39 to the lighting device 32, and the lighting device 32 focuses the light beam 39 onto the mask 33. The mask 33 partially shields the light beam 39, and the patterned light beam is projected onto the semiconductor wafer 5 through the objective lens module 34 to expose the photoresist layer 52 on the semiconductor wafer 5. Afterwards, the wafer is transferred to another semiconductor device, such as an etching device or a chemical vapor deposition (CVD) device. The movement of the semiconductor wafer 5 can be performed by one or more robotic arms disposed in the processing system 1.

[0146] In the multiple embodiments disclosed herein, a cleaning brush head having a microstructure of a specific geometric shape is used to clean a wafer seat for carrying semiconductor wafers. Since the microstructure of the cleaning brush head can extend into the grooves on the surface of the wafer seat to remove the contamination particles remaining in the grooves, the contamination particles on the surface of the wafer seat can be effectively removed. Therefore, when the wafer seat is subsequently used to perform a lithography process of the semiconductor wafer, the semiconductor wafer can be placed flat on the wafer seat, and the process yield of the semiconductor wafer processing can be improved. On the other hand, since the cleaning brush head has a better cleaning function, the machine downtime caused by maintaining the wafer seat can also be shortened, thereby reducing production costs.

[0147] Some embodiments of the present disclosure provide a semiconductor wafer processing method. The method includes using a cleaning brush head with multiple microstructures to perform a cleaning process on a support surface of a wafer seat. The microstructures are spaced apart by a spacing and have a tapered width. The method also includes placing a semiconductor wafer on the support surface of the wafer seat. The method also includes performing a lithography process on the semiconductor wafer. In the above embodiment, the cleaning process is performed by cleaning the support surface using a microstructure with a conical cross-section. In the above embodiment, the cleaning process is performed by cleaning the support surface using a staggered arrangement of microstructures with different bottom angles. In the above embodiment, the cleaning process is performed by cleaning the support surface using a microstructure with a bottom angle between about 20 degrees and about 70 degrees. In the above embodiment, the cleaning process is performed by cleaning multiple grooves on the support surface using microstructures, and parts of the microstructures extend into the interior of the grooves to remove contaminated particles located in the grooves.

[0148] Some embodiments disclosed herein provide a semiconductor wafer processing method. The method includes using a cleaning brush head having a plurality of conical microstructures to perform a cleaning process on a support surface of a wafer seat. The method also includes placing a semiconductor wafer on the support surface of the wafer seat. The method also includes performing a lithography process on the semiconductor wafer. In the above embodiment, the cleaning process is performed by cleaning the support surface using the plurality of microstructures having a bottom angle between about 20 degrees and about 70 degrees.

[0149] Some embodiments disclosed herein provide a cleaning brush head. This cleaning brush head is suitable for cleaning a supporting surface of a wafer seat supporting a semiconductor wafer, and the supporting surface includes a plurality of grooves with a predetermined width. The cleaning brush head includes an upper surface and a plurality of microstructures. The plurality of microstructures are spaced apart from each other by a spacing, and the microstructures gradually taper from a first width to a second width in a direction away from the upper surface, wherein the second width is smaller than the predetermined width of the groove. In the above embodiment, the microstructure has a conical cross-section. In the above embodiment, the microstructures with different bottom angles are staggered along the long axis direction.

[0150] The features or examples of several embodiments are summarized above so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that the present disclosure can be easily used as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages of the embodiments or examples introduced herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications herein can be made without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor wafer processing method, characterized in that: include: A cleaning process is performed on a supporting surface of a wafer seat using a cleaning brush head having a plurality of microstructures, wherein the microstructures are spaced apart from each other by a distance and have a tapered width, wherein the plurality of microstructures protrude from a surface of the cleaning brush head, and the tapered width tapers toward the surface away from the cleaning brush head, wherein the surface of the cleaning brush head has an inner annular region and an outer annular region surrounding the inner annular region, a first portion of the plurality of microstructures in the inner annular region has a height lower than a second portion of the plurality of microstructures in the outer annular region, and the material of the first portion of the plurality of microstructures in the inner annular region and the material of the second portion of the plurality of microstructures in the outer annular region are both diamond; Placing a semiconductor wafer on the supporting surface of the wafer bed; as well as The semiconductor wafer is subjected to a lithography process.

2. The semiconductor wafer processing method according to claim 1, characterized in that: The cleaning process is performed by using the plurality of microstructures with conical cross-sections to clean the support surface.

3. The semiconductor wafer processing method according to claim 2, characterized in that: The cleaning process is performed by using a plurality of first microstructures and a plurality of second microstructures having different bottom angles and arranged in a staggered manner to clean the support surface.

4. The semiconductor wafer processing method according to claim 3, characterized in that: The bottom angles of the first microstructures are between 45 and 70 degrees, and the bottom angles of the second microstructures are between 20 and 45 degrees.

5. The semiconductor wafer processing method according to claim 1, characterized in that: The cleaning process is performed by using the plurality of microstructures having bottom angles ranging from 20 degrees to 70 degrees to clean the support surface.

6. The semiconductor wafer processing method according to claim 1, characterized in that: The cleaning process is performed by using the multiple microstructures to clean the multiple grooves on the support surface, and parts of the multiple microstructures extend into the multiple grooves to remove contamination particles located in the multiple grooves.

7. The semiconductor wafer processing method according to claim 6, characterized in that: The contaminant particles include titanium nitride particles.

8. The semiconductor wafer processing method according to claim 1, characterized in that: The plurality of microstructures are made of a material having a Vickers hardness greater than 1200.

9. The semiconductor wafer processing method according to claim 1, characterized in that: The plurality of microstructures are made of a material having a Vickers hardness of no greater than 10,000.

10. A semiconductor wafer processing method, characterized in that: include: A cleaning process is performed on a supporting surface of a wafer bed using a cleaning brush head having a plurality of conical microstructures, wherein the plurality of conical microstructures protrude from a surface of the cleaning brush head, the surface of the cleaning brush head having an inner annular region and an outer annular region surrounding the inner annular region, a first portion of the plurality of conical microstructures in the inner annular region has a height lower than a second portion of the plurality of conical microstructures in the outer annular region, and the material of the first portion of the plurality of conical microstructures in the inner annular region and the material of the second portion of the plurality of conical microstructures in the outer annular region are both diamond; Placing a semiconductor wafer on the supporting surface of the wafer bed; as well as The semiconductor wafer is subjected to a lithography process.

11. The semiconductor wafer processing method according to claim 10, characterized in that: The cleaning process is performed by using the plurality of conical microstructures having bottom angles ranging from 20 degrees to 70 degrees to clean the support surface.

12. The semiconductor wafer processing method according to claim 10, characterized in that: The plurality of pyramidal microstructures have a Vickers hardness ranging from 1200 to 10000.

13. The semiconductor wafer processing method according to claim 10, characterized in that: The supporting surface of the wafer seat is formed by a plurality of silicon carbide protrusions, and the plurality of silicon carbide protrusions are separated by a plurality of grooves.

14. The semiconductor wafer processing method according to claim 13, characterized in that: When the cleaning brush head contacts the silicon carbide protrusions during a cleaning process, the conical microstructures extend into the grooves.

15. A cleaning brush head, suitable for cleaning a supporting surface of a wafer stand supporting a semiconductor wafer, the supporting surface comprising a plurality of grooves having a predetermined width, characterized in that: The cleaning brush head includes: an upper surface; and A plurality of microstructures are spaced apart from each other and are located on the upper surface. The plurality of microstructures taper from a first width to a second width in a direction away from the upper surface, wherein the second width is smaller than the predetermined width of the groove. The upper surface of the cleaning brush head has an inner annular region and an outer annular region surrounding the inner annular region. A first portion of the plurality of microstructures in the inner annular region has a height lower than a second portion of the plurality of microstructures in the outer annular region, and the material of the first portion of the plurality of microstructures in the inner annular region and the material of the second portion of the plurality of microstructures in the outer annular region are both diamond.

16. The cleaning brush head according to claim 15, characterized in that: The plurality of microstructures have a tapered cross-section.

17. The cleaning brush head according to claim 16, characterized in that: The multiple microstructures with different bottom angles are arranged in a staggered manner.

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