Memory devices, memory systems including memory devices, and methods of operating the same

Abstract

Memory devices, memory systems including the same, and methods of operating the same are provided. The memory device includes a mode register set configured to store a first repair mode, a second repair mode, and a second repair off mode; and a repair control circuit configured to perform, in the first repair mode, a first repair operation for permanently repairing a first word line corresponding to a defective address to a first redundant word line, perform, in the second repair mode, a second repair operation for temporarily repairing the first word line corresponding to the defective address to a second redundant word line, and, in the second repair off mode, turn off repair logic configured to perform the second repair operation to access old data after the second repair operation.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2019-0175040, filed on December 26, 2019, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to memory devices and memory systems, as well as methods of operating them. Background Technology

[0003] Typically, memory devices can be repaired even after they have been packaged. This repair operation is called post-package repair. In post-package repair, faulty memory cells that were not detected in the wafer state but appeared after packaging can be repaired using an electric fuse method. Summary of the Invention

[0004] Example embodiments of the present invention will provide a memory device for performing repair operations that can improve the reliability of data, a memory system including the memory device, and a method of operating the same.

[0005] According to an exemplary embodiment of the present invention, a memory device includes: a mode register set configured to store a first repair mode, a second repair mode, and a second repair shutdown mode; and a repair control circuit configured to: perform a first repair operation in the first repair mode for permanently repairing a first word line corresponding to a defective address to a first redundant word line; perform a second repair operation in the second repair mode for temporarily repairing the first word line corresponding to the defective address to a second redundant word line; and disable repair logic configured to perform the second repair operation to access old data after the second repair operation in the second repair shutdown mode.

[0006] According to an exemplary embodiment of the present invention, a memory device includes: normal word line activation logic configured to output a normal word line activation signal in response to an activated row address being matched; a first redundancy block configured to output a post-packaging repair (PPR) word line activation signal in response to the activated row address being matched; and at least one second redundancy block configured to output a soft post-packaging repair (sPPR) word line activation signal in response to the activated row address being matched, wherein the at least one second redundancy block is deactivated in response to old data access information.

[0007] According to an exemplary embodiment of the present invention, an operation method of a memory device includes: in response to a repair request from an external device, performing a repair operation to replace a word line corresponding to an address with a redundant word line; receiving old data access information from the external device; and after receiving the old data access information, outputting old data from a memory cell connected to the word line corresponding to the address in response to a read request from the external device.

[0008] According to an exemplary embodiment of the present invention, a memory system includes: at least one memory device; and a controller configured to control the at least one memory device, wherein the at least one memory device is configured to disable sPPR logic in response to old data access information after performing a soft packaged repair (sPPR) operation, and output old data from memory cells connected to normal word lines or repair word lines corresponding to addresses to the controller. Attached Figure Description

[0009] The above and other aspects, features, and advantages of the present invention will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 This is a diagram illustrating an example of a memory system according to an exemplary embodiment;

[0011] Figure 2 This is a diagram illustrating an example of a memory device according to an exemplary embodiment;

[0012] Figure 3 This is a schematic diagram illustrating the structure of a memory device according to an example embodiment;

[0013] Figure 4 This is a schematic diagram illustrating redundant word lines in a memory device according to an example embodiment;

[0014] Figure 5 This is a diagram illustrating an example of a repair operation of a memory device according to an exemplary embodiment;

[0015] Figure 6 This is a diagram illustrating an example of an old data access operation following a repair operation of a memory device according to an example embodiment;

[0016] Figure 7 This is a diagram illustrating an example of an operation that copies old data after a repair operation on a memory device, according to an example embodiment.

[0017] Figure 8A and Figure 8B This is a conceptual illustration of the operation of the word line activation logic of a memory device according to an example embodiment;

[0018] Figure 9 This is a schematic diagram illustrating an example of sPPR logic according to an example embodiment;

[0019] Figure 10 This is a diagram illustrating an example of normal word line activation operation of a memory device according to an example embodiment;

[0020] Figure 11 This is a diagram illustrating an example of a repair word line activation operation of a memory device according to an exemplary embodiment;

[0021] Figure 12 This is a diagram illustrating an example of sPPR word line activation operation of a memory device according to an exemplary embodiment;

[0022] Figure 13 This is a diagram illustrating an example of an operation for accessing old data after a sPPR of a memory device, according to an example embodiment.

[0023] Figure 14 This is a diagram illustrating an example of an operation for accessing old data after a sPPR of a memory device, according to another example embodiment;

[0024] Figure 15 This is a flowchart illustrating an example of an operation method of a memory device according to an example embodiment;

[0025] Figure 16 This is a flowchart illustrating an example of a controller operation method according to an example embodiment;

[0026] Figure 17 This is a ladder diagram illustrating an example of a repair operation of a memory system according to an example embodiment;

[0027] Figure 18 This is a ladder diagram illustrating an example of a repair operation of a memory system according to another example embodiment;

[0028] Figure 19 This is a block diagram illustrating an example of a memory chip according to an exemplary embodiment;

[0029] Figure 20 This is a diagram illustrating an example of a computing system according to an exemplary embodiment;

[0030] Figure 21 This is a diagram illustrating an example of an electronic system for a vehicle according to an exemplary embodiment;

[0031] Figure 22 This is a diagram illustrating an example of a mobile device according to an exemplary embodiment;

[0032] Figure 23 This is a diagram illustrating an example computing system according to an example embodiment; and

[0033] Figure 24 This is a diagram illustrating an example of a data server system according to an example embodiment. Detailed Implementation

[0034] In the following description, embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0035] Figure 1 This is a diagram illustrating an example of a memory system 10 according to an exemplary embodiment. (Refer to...) Figure 1 The memory system 10 may include a memory device 100 and a controller (CTRL) 200 for controlling the memory device 100.

[0036] The memory device 100 can be implemented as a volatile memory device or a non-volatile memory device. The volatile memory device can be static random access memory (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), etc. The non-volatile memory device can be NAND flash memory, vertical NAND flash memory (VNAND), NOR flash memory, resistive random access memory (RRAM), phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), spin-transfer torque random access memory (STT-RAM), etc. In the following description, for ease of description, the memory device 100 can be implemented as DRAM.

[0037] Additionally, the memory device 100 may include a mode register set (MRS) 162 and a repair control circuit 166.

[0038] MRS 162 can be implemented to store multiple repair operation modes. These multiple repair operation modes can include hard post package repair (hPPR) mode, soft post package repair (sPPR) mode, and sPPR_OFF mode.

[0039] The repair control circuit 166 can be implemented to perform repair operations according to the repair operation modes stored in the MRS 162. In hPPR mode, the repair control circuit 166 can perform a repair operation to permanently repair the word line corresponding to the defective address as a redundant word line. In sPPR mode, the repair control circuit 166 can perform a repair operation to temporarily repair the word line corresponding to the defective address as a redundant word line. In sPPR mode, the repair address associated with the repair control circuit 166 can be received from the controller 200 and can be stored, and the repair operation can be performed based on the stored repair address.

[0040] In one example embodiment, entering hPPR mode or sPPR mode can be protected by a Mode Register Set (MRS) protection key to disable or prevent unintended hPPR programming. The sequence protection key can be the same in both hPPR and sPPR modes. In one example embodiment, entering sPPR mode can be performed via register activation. Additionally, an Activate (ACT) command can be used to send the row or row address of the memory bank to be replaced in memory device 100. In one example embodiment, after a tRCD period (e.g., the number of clock cycles between issuing the ACT command and the read / write command), a Write (WR) command can be used to select an individual memory device via the Data (DQ) bits and to send a repair address to the internal register of the selected memory device. In one example embodiment, sPPR mode can be terminated after a Write Recovery Time and a Precharge (PRE) period, and normal operation can be resumed. In one example embodiment, memory device 100 can retain soft repair information during operation. When power to memory device 100 is removed, the soft repair information can revert to a repair-limited state.

[0041] In sPPR_OFF mode, the repair control circuit 166 can turn off the sPPR logic after performing the sPPR operation, and can access the memory cell connected to the word line corresponding to the defect address and output the old data.

[0042] DRAM can comprise billions or more cells. For example, a single 16 gigabyte (GB) DRAM can contain 17,179,869,184 cells. For normal operation, all cells are likely to function correctly. DRAM may include spare redundant cells prepared for defects that may arise during the manufacturing and testing processes. Failed cells can be salvaged / repaired by replacing rows or columns containing redundant cells with rows or columns containing redundant cells. Typically, DRAM can be manufactured such that all defects arising during the production process, including manufacturing and testing, can be repaired, and all cells can function correctly.

[0043] Stress testing, which considers potential degradation that may occur during DRAM use, can include pre-generating and repairing defects that might occur in the actual use of the DRAM. However, such stress testing may not prevent all defects from occurring during the actual use of the DRAM. Recently, as a solution for defects occurring during the user phase, related circuitry has been included in the DRAM, allowing the user to directly perform repair operations through post-package repair (PPR) procedures.

[0044] DRAM PPR operations can be divided into hPPR and sPPR. hPPR can perform a repair operation by changing the physical fuse information during both the manufacturing and testing phases. In this case, all fuse information, including the corresponding fuse information, can be reloaded into the redundant processing circuitry of the address decoder. In this scenario, all data currently in the task may be lost, and a significant amount of time may be consumed until the data becomes available. For this reason, even when a failed cell occurs while the DRAM needs to be used continuously, hPPR may not be able to be performed immediately.

[0045] The aforementioned problem can be solved using sPPR (Scheduled Repair Process). sPPR is a random repair method, rather than altering the physical fuse information, and the corresponding repair information is lost upon power failure. Therefore, sPPR can perform the repair operation within a relatively short timeframe, and data at addresses other than the repaired address can be used as if it had not been lost. For this reason, when a failed cell occurs when DRAM needs to be used continuously, by replacing the corresponding failed address with a redundant address via sPPR, DRAM can be used continuously without interruption.

[0046] A typical sPPR operation can repair a failed row address to a redundant address. After the repair operation, data loss may occur because data stored in the same row other than the existing failed cell cannot be accessed. For example, in DDR5 DRAM, since a single row address can activate 8K cells, 8Kb of data may be lost during an sPPR operation even when only one failed cell exists. To prevent this, it is usually necessary to perform an operation to copy the data of the corresponding row address to another address before performing sPPR. However, problems may arise when the DRAM in use is busy and there is no time to copy 8Kb.

[0047] According to the example embodiment, the sPPR operation can access the data region prior to the execution of the sPPR operation by entering the sPPR_OFF mode after the sPPR operation is performed. In the memory system 10 according to the example embodiment, by including a memory device 100 that enables access to old data prior to the execution of the sPPR operation even after the sPPR operation is performed, data reliability and overall performance can be improved.

[0048] Figure 2 This is a diagram illustrating an example of a memory device 100 according to an exemplary embodiment. (Refer to...) Figure 2The memory device 100 may include a memory cell array 110, a row decoder 120, a column decoder 130, a sense amplifier circuit 140, an address register 150, memory bank control logic 152, a refresh counter 154, a row address multiplexer (RA MUX) 156, a column address (CA) latch 158, control logic 160, a repair control circuit 166, a timing control circuit 164, an input and output (I / O) gating circuit 170, an error correction circuit 180, and a data input and output (I / O) buffer 182.

[0049] The memory cell array 110 may include a first memory array 111 to an eighth memory array 118. However, the number of memory arrays included in the memory cell array 110 is not limited thereto.

[0050] The line decoder 120 may include a first memory bank line decoder 121 to an eighth memory bank line decoder 128 respectively connected to the first memory bank array 111 to the eighth memory bank array 118.

[0051] The column decoder 130 may include a first memory column decoder 131 to an eighth memory column decoder 138 respectively connected to the first memory array 111 to the eighth memory array 118.

[0052] The sensing amplifier circuit 140 may include a first memory sensing amplifier 141 to an eighth memory sensing amplifier 148 respectively connected to the first memory array 111 to the eighth memory array 118.

[0053] The first memory arrays 111 to 118, the first memory row decoders 121 to 128, the first memory column decoders 131 to 138, and the first memory sense amplifiers 141 to 148 can be respectively included in the first memory to the eighth memory. Each of the first memory arrays 111 to 118 can include a plurality of memory cells MC disposed at the point where the word line WL and the bit line BL intersect.

[0054] Address register 150 can receive and store address ADDR, which has bank address BANK_ADDR, row address ROW_ADDR, and column address COL_ADDR, from an external memory controller (e.g., controller 200). Address register 150 can provide the received bank address BANK_ADDR to bank control logic 152, the received row address ROW_ADDR to row address multiplexer 156, and the received column address COL_ADDR to column address latch 158.

[0055] In response to the bank address BANK_ADDR, the bank control logic 152 can generate a bank control signal. In response to the bank control signal, the bank row decoders corresponding to the bank address BANK_ADDR among the first bank row decoders 121 to the eighth bank row decoders 128 can be activated. In response to the bank control signal, the bank column decoders corresponding to the bank address BANK_ADDR among the first bank column decoders 131 to the eighth bank column decoders 138 can be activated.

[0056] Row address multiplexer 156 can receive row address ROW_ADDR from address register 150 and refresh row address REF_ADDR from refresh counter 154. Row address multiplexer 156 can selectively output row address ROW_ADDR or refresh row address REF_ADDR as row address RA. Row address RA output from row address multiplexer 156 can be applied to each of the first memory bank row decoders 121 to the eighth memory bank row decoders 128.

[0057] The bank row decoders activated by the bank control logic 152 in the first bank row decoder 121 to the eighth bank row decoder 128 can decode the row address RA output from the row address multiplexer 156 and can activate the word line corresponding to the row address. For example, the activated bank row decoder can apply a word line drive voltage to the word line corresponding to the row address. In addition, the activated bank row decoder can activate the word line corresponding to the row address and can also activate the redundant word line corresponding to the redundant row address output from the repair control circuit 166.

[0058] Column address latch 158 can receive column address COL_ADDR from address register 150 and can temporarily store the received column address COL_ADDR. Additionally, column address latch 158 can gradually increment the received column address COL_ADDR in burst mode. Column address latch 158 can apply the temporarily stored or gradually incremented column address COL_ADDR to each of the first bank column decoders 131 to the eighth bank column decoders 138.

[0059] The bank column decoders 131 through 138, activated by the bank control logic 152, can activate the sense amplifiers corresponding to the bank address BANK_ADDR and the column address COL_ADDR via the input and output gating circuit 170. Furthermore, the activated bank column decoders can perform column repair operations in response to the column repair signal CRP output from the repair control circuit 166.

[0060] Control logic 160 can be implemented to control the operation of memory device 100. For example, control logic 160 can generate control signals for memory device 100 to perform write or read operations. Control logic 160 may include a command decoder 161 for decoding commands (CMD) received from the memory controller and a mode register set 162 for setting the operating mode of memory device 100.

[0061] For example, command decoder 161 can generate operation control signals ACT, PCH, WR, and RD corresponding to the command CMD by decoding write enable signals, row address strobe signals, column address strobe signals, chip select signals, etc. Control logic 160 can provide operation control signals ACT, PCH, WR, and RD to timing control circuit 164. Operation control signals ACT, PCH, WR, and RD may include activation signal ACT, precharge signal PCH, write signal WR, and read signal RD. Timing control circuit 164 can generate a first control signal CTL1 for controlling the voltage level of word line WL and a second control signal CTL2 for controlling the voltage level of bit line BL in response to operation control signals ACT, PCH, WR, and RD, and can provide the first control signal CTL1 and the second control signal CTL2 to memory cell array 110.

[0062] Repair control circuit 166 can generate repair control signals including column repair signal CRP and fuse information for each word line. The column repair signal CRP is used to control the repair operations of at least one first cell region and a second cell region in the memory bank array based on the row address ROW_ADDR and column address COL_ADDR of the address ADDR (or access address). Repair control circuit 166 can provide redundant row addresses to the corresponding memory bank row decoder, provide the column repair signal CRP to the corresponding memory bank column decoder, and provide select and enable signals SRA to the block control circuitry associated with the corresponding redundant array block.

[0063] Additionally, in the hPPR mode stored in mode register group 162, the repair control circuit 166 can generate an hPPR word line activation signal in response to address ADDR. Furthermore, in the sPPR mode stored in mode register group 162, the repair control circuit 166 can generate an sPPR word line activation signal sPPR_WL_EN in response to address ADDR. The repair control circuit 166 can also disable the sPPR logic in the sPPR_OFF mode stored in mode register group 162 and can generate a normal word line activation signal to access old data.

[0064] In one example embodiment, the repair control circuit 166 can change the repair unit based on the address ADDR and fuse information. For example, the repair control circuit 166 can change the type and number of repair address bits based on the address ADDR and fuse information.

[0065] Each input and output gating circuit of the input and output gating circuit 170 may include input data masking logic, a read data latch for storing data output from the first memory array 111 to the eighth memory array 118, a write driver for writing data to the first memory array 111 to the eighth memory array 118, and circuitry for gating the input and output data.

[0066] The codeword CW to be read from one of the first memory arrays 111 to the eighth memory array 118 can be sensed by a sense amplifier corresponding to one of the memory arrays and can be stored in a read data latch. After error checking and correction (ECC) decoding is performed by error correction circuit 180, the codeword CW stored in the read data latch can be provided to the memory controller through data input and output buffer 182. After ECC encoding is performed in error correction circuit 180, the data DQ to be written to one of the first memory arrays 111 to the eighth memory array 118 can be written to one of the memory arrays through a write driver.

[0067] The data input and output buffer 182 can provide data DQ to the error correction circuit 180 based on the clock signal CLK provided from the memory controller during a write operation, and can provide data DQ provided from the error correction circuit 180 to the memory controller during a read operation.

[0068] Error correction circuit 180 can generate parity bits based on data bits of data DQ provided from data input and output buffer 182 during write operations, and can provide codeword CW including data DQ and parity bits to input and output gating circuit 170, which can write codeword CW onto memory bank array.

[0069] Additionally, error correction circuit 180 can be provided during a read operation with a codeword CW read from one of the memory arrays by input and output gating circuit 170. Error correction circuit 180 can perform ECC decoding on data DQ using parity bits included in the read codeword CW, can correct at least one erroneous bit included in data DQ, and can provide the corrected erroneous bit to data input and output buffer 182.

[0070] The memory device 100 according to the example embodiment can receive repair information, set a repair operation mode corresponding to the received repair information, and perform a repair operation according to the determined repair operation mode. By entering the sPPR_OFF mode, the memory device 100 can access old data even after the sPPR operation.

[0071] Figure 3 This is a schematic diagram illustrating the structure of a memory device 100 according to an example embodiment. The memory device 100 can read and / or write data using a row address applied when an activation command is received and a column address applied when a read or write command is received. A row decoder can receive the row address applied when an activation command is received and can activate a specific word line. When a single word line is activated, the memory device 100 can enter a state where access to thousands of cells connected to the corresponding word line is available via read or write commands. The memory device 100 may fail to operate properly even when a single faulty cell is included among thousands of cells.

[0072] Figure 3 The number and arrangement of memory banks, row decoders, and column decoders shown are merely examples.

[0073] Figure 4 This is a schematic diagram illustrating redundant word lines in a memory device 100 according to an example embodiment. (Refer to...) Figure 4 Redundant (repaired) word lines can be set within normal word lines. When a failed cell is generated during the manufacturing or testing phase, the word line containing the corresponding cell can be repaired as a redundant word line.

[0074] Figure 5 This is a diagram illustrating an example of a repair operation of a memory device 100 according to an exemplary embodiment. Figure 5 In this context, it can be assumed that the memory cell connected to the twelfth word line WL12 and the fourth bit line BL4 becomes a failed cell FC during the operation of the memory device 100. The controller 200 can send an sPPR command for the twelfth word line WL12 to the memory device 100 based on (e.g., in response to detecting) the presence of the failed cell FC. The memory device 100 can then replace the twelfth word line WL12 with a first redundant word line RWL1 in response to the sPPR command.

[0075] Figure 6 This is a diagram illustrating an example of old data access operations following a repair operation on a memory device 100 according to an example embodiment. (Refer to...) Figure 6 In execution Figure 5After the sPPR operation, the controller 200 can command the memory device 100 to enter the sPPR_OFF mode. Therefore, the memory device 100 can operate in the sPPR_OFF mode. When the sPPR logic is turned off in the sPPR_OFF mode, the normal word line (twelfth word line WL12) prior to the sPPR operation can be activated in response to the address received from the controller 200. Therefore, normal data from the memory cell connected to the activated twelfth word line WL12 can be output to the controller 200.

[0076] Figure 7 This is a diagram illustrating an example of an operation that copies old data after a repair operation of a memory device 100 according to an example embodiment. (Refer to...) Figure 7 The controller 200 can receive Figure 6 After storing the old data, the operating mode of the memory device 100 is changed to sPPR mode. Thereafter, the controller 200 can write the copied data recovered from the memory cell connected to the twelfth word line WL12 into the redundant memory cell connected to the first redundant word line RWL1. Therefore, the repair operation of the failed cell can be completed.

[0077] Figure 8A and Figure 8B This is a conceptual illustration of the operation of the word line activation logic of a memory device 100 according to an example embodiment.

[0078] exist Figure 8A In this context, it can be assumed that there exist two redundant frames (or redundant boxes) 321 to 32k and 320 that perform address matching operations when an active row address is received in memory device 100. The sPPR redundant frame 330 can compare the received active row address with the stored row address, and when address matching is performed as a result of the comparison, the sPPR redundant frame 330 can output the sPPR word line activation signal sPPR_WL_EN. The sPPR word line activation signal sPPR_WL_EN can be used as information for blocking normal word lines and repairing word lines.

[0079] Redundant blocks 321, 322, 323...32k (where k is an integer equal to or greater than 2) can be deactivated by the sPPR word line activation signal sPPR_WL_EN. Furthermore, even if the address matching the activated row address is executed in redundant block 322, repair word line activation can be disabled by the sPPR word line activation signal sPPR_WL_EN. Each of the redundant blocks 321, 322, 323...32k contains hPPR-related repair word line activation logic.

[0080] Additionally, the normal word line activation logic 310 can be activated by the sPPR word line activation signal sPPR_WL_EN. In other words, the normal word line activation logic 310 can block the corresponding normal word line in response to the activated row address.

[0081] Reference Figure 8B When old data access information is received in memory device 100 after the sPPR repair operation, sPPR redundancy block 330 can be deactivated. The old data access information may include information for disabling the sPPR logic. sPPR redundancy block 330 can be fixed in an address mismatch state based on the old data access information. Since the address matching the activated row address is executed in redundancy block 322, redundancy block 322 can output an sPPR word line activation signal sPPR_WL_EN. In response to the sPPR word line activation signal sPPR_WL_EN, the repair word line corresponding to the activated row address can be activated, and old data can be output from the memory cell connected to the repair word line.

[0082] Figure 9 This is a schematic diagram illustrating an example of sPPR logic 430 according to an example embodiment. (Refer to...) Figure 9 The sPPR logic 430 may include a first latch 431, a second latch 432, a first logic circuit 433, and a second logic circuit 434.

[0083] The sPPR logic 430 can receive address ADDR, activation signal ACT, sPPR signal sPPR_sg and sPPR deactivation signal sPPR_OFF_sg, and can operate as follows.

[0084] The first latch 431 can latch and output address ADDR in response to the activation signal ACT. The second latch 432 can latch and output address sPPR ADDR in response to the output value of the first logic circuit 433. In one example embodiment, each of the first latch 431 and the second latch 432 may include a flip-flop.

[0085] The first logic circuit 433 can output the corresponding output value to the second latch 432 by performing an AND operation on the activation signal ACT and the sPPR signal sPPR_sg.

[0086] The second logic circuit 434 can output the sPPR word line activation signal sPPR_WL_EN by performing an XOR operation on the latch address of the first latch 431 and the latch address of the second latch 432. The latch address of the second latch 432 can be the sPPR address. Additionally, the second logic circuit 434 can be deactivated in response to the sPPR off signal sPPR_OFF_sg.

[0087] Figure 10 This is a diagram illustrating an example of normal word line activation operation of a memory device 100 according to an exemplary embodiment. (Refer to...) Figure 10 When the line address applied when the activation command is received is an address that may not be repairable (e.g., may not need to be repaired), the normal word line activation logic 310 can output the normal word line activation signal Normal_WL_EN because no address matching is performed in redundancy blocks 321 to 32k and sPPR redundancy block 330.

[0088] Figure 11 This is a diagram illustrating an example of a repair word line activation operation of a memory device 100 according to an exemplary embodiment. (Refer to...) Figure 11 When a line address command is applied to repair a word line upon receiving an activation command, redundancy block 322 can output a repair word line activation signal PPR_WL_EN for activating the repaired word line based on (e.g., in response to) address matching. Redundancy block 322 can disable the activation of a normal word line by using the generated address matching information to block the normal word line activation logic 310.

[0089] Figure 12 This is a diagram illustrating an example of sPPR word line activation operation of a memory device 100 according to an exemplary embodiment. (Refer to...) Figure 12 When a failed cell is generated in the repaired word line and sPPR is performed on the corresponding word line, an address matching operation can be performed in redundancy block 322 and sPPR redundancy block 330. sPPR redundancy block 330 can output an sPPR word line activation signal sPPR_WL_EN corresponding to the address matching information. Since the sPPR word line activation signal sPPR_WL_EN prevents existing redundancy blocks 321 to 32k and normal word line activation logic 310, it can prevent the sPPR word line activation signal sPPR_WL_EN from activating word lines other than the word line corresponding to sPPR redundancy block 330.

[0090] Figure 13 This is a diagram illustrating an example of an operation accessing old data after a single Page Phase Registry (sPPR) in memory device 100 according to an example embodiment. Before the sPPR is executed, it could be performed after copying all data at the corresponding row address to another address. However, since a single word line connects to 8K (or more) cells, there may not often be enough spare space depending on DRAM usage. In this case, the copy operation may be unavailable.

[0091] like Figure 13As shown, the memory device 100 according to the example embodiment can access data that has not yet been sPPR performed after sPPR has been performed. For example, since the sPPR redundancy block 330 that receives old data access information is forced to have an address mismatch, the redundancy block 322 can output a repair word line activation signal PPR_WL_EN to activate the existing repair word line based on the address match.

[0092] Even after the sPPR has been executed, the memory device 100 according to the example embodiment can access old data at necessary times while the memory device 100 is operating, thus without data loss. By disabling the address matching logic of the sPPR redundancy block after the sPPR, the word line WL before the sPPR can be enabled when the corresponding address is active. For this purpose, as in Figure 13 The section marked "Old Data Access Information" indicates that information indicating access to old data prior to the sPPR may be necessary. For example, old data access information defined by the Mode Register Set (MRS) can be used as old data access information. By enabling word lines before or after the sPPR according to the corresponding information, data loss problems caused by the sPPR can be resolved.

[0093] exist Figure 13 For ease of description, it can be assumed that the line address of the sPPR being performed can be a repaired address. However, the address of the sPPR being performed is not limited to this. The address of the sPPR being performed can be a normal address.

[0094] Figure 14 This is a diagram illustrating an example of an operation for accessing old data in memory device 100 after sPPR according to another example embodiment.

[0095] like Figure 14 As shown, the address where sPPR is performed can command word lines that have not yet been repaired. Therefore, old data can be output by the normal word line activation logic 310 in response to the normal word line activation signal Normal_WL_EN. Through the implementation of the sPPR circuit and method, the memory device 100 according to the example embodiment can access word lines WL that have not yet undergone sPPR, even after sPPR has been performed, regardless of whether the existing word lines WL have been repaired; therefore, data loss can be prevented / disallowed.

[0096] Figure 15 This is a flowchart illustrating an example of an operation method of a memory device 100 according to an example embodiment. (Refer to...) Figures 1 to 15 The memory device 100 can be operated as follows.

[0097] The memory device 100 can perform a repair operation corresponding to an address in response to an external request (S110). The repair operation may include soft-packaged repair (sPPR). The memory device 100 can receive old data access information from an external entity and access the old data corresponding to the address according to the received old data access information (S120). In this case, the sPPR logic can be deactivated according to (e.g., in response to) the old data access information. Therefore, the old data can be read from the memory cell corresponding to the address. Thereafter, the memory device 100 can output the old data corresponding to the address (S130).

[0098] Even after sPPR is executed, the memory device 100 according to the example embodiment can access old data that has not yet been executed by sPPR.

[0099] In one example embodiment, when performing sPPR on a cell or row where a defect has occurred, the existing repair information for the corresponding cell or row can be maintained without change. In one example embodiment, when accessing a cell that has already undergone sPPR, access to the cell that has undergone sPPR can be prioritized over access to a normal cell or a repaired cell. For example, repair control circuitry 166 and / or controller 200 can prioritize performing sPPR over performing hPPR (e.g., a predetermined threshold for performing sPPR can be lower). In one example embodiment, access to information that has undergone sPPR can be blocked from cells that have not yet been repaired by sPPR, and cells that have not yet undergone sPPR can be accessed. In one example embodiment, when performing sPPR on cells that have not yet been repaired during semiconductor manufacturing, historical cells that have not been repaired and have not yet undergone sPPR can be accessed even after sPPR has been performed. In one example embodiment, when sPPR is performed on a cell that has a repair history in the semiconductor manufacturing process, MRS can be used to access cells that have a repair history but have not yet been sPPR performed, even after sPPR has been performed.

[0100] Figure 16 This is a flowchart illustrating an example of an operation method of the controller 200 according to an example embodiment. (Refer to...) Figures 1 to 16The controller 200 can operate as follows: The controller 200 can perform a read operation on the memory device 100 and determine whether soft-packaged repair (sPPR) is desired / necessary based on the result of the read operation. When the sPPR is determined to be desired / necessary, the controller 200 can send the sPPR command along with the corresponding address to the memory device 100 (S210). Thereafter, if desired / necessary, the controller 200 can send old data access information corresponding to the address to the memory device 100 (S220). For example, when copying old data to a memory cell connected to the word line corresponding to the repair address is desired / necessary, the controller 200 can send old data access information to the memory device 100. Thereafter, the controller 200 can access the memory device 100 using the address to read the old data (S230).

[0101] Figure 17 This is a ladder diagram illustrating an example of a repair operation of a memory system 10 according to an exemplary embodiment. (Refer to...) Figures 1 to 17 The repair operation of the memory system 10 can be performed as described below.

[0102] Controller 200 can receive data corresponding to address ADDR from memory device 100. Address ADDR can be a normal address or an hPPR address. Controller 200 can perform error correction on the received data. When the number of errors is equal to or higher than a reference value as a result of error correction, controller 200 can determine that sPPR is expected / necessary for the corresponding address. When sPPR is expected / necessary for address ADDR, controller 200 can send an sPPR command to memory device 100. Memory device 100 can execute sPPR in response to the sPPR command and can send a completion response message for sPPR to controller 200.

[0103] Subsequently, controller 200 may request memory device 100 to set sPPR_OFF mode to read old data from the memory cell connected to the word line corresponding to address ADDR. For example, controller 200 may read the old data to copy it to the memory cell connected to the sPPR word line. Memory device 100 may disable the sPPR logic based on the sPPR_OFF request. Subsequently, controller 200 may send a read command along with address ADDR to memory device 100. Memory device 100 may read the old data from the memory cell connected to the word line corresponding to address ADDR in sPPR_OFF mode in response to the read command, and may send the read old data to controller 200.

[0104] The controller 200 can send a write command along with the received old data to the memory device 100, so that the received old data can be written to the memory cell connected to the new word line (sPPR word line). The memory device 100 can write the old data to the memory cell connected to the sPPR word line in response to the write command. Thus, the old data can be copied to the new word line.

[0105] exist Figure 17 In this system, the sending of the sPPR command and the request for sPPR_OFF can be performed separately. However, the example embodiments are not limited to this. Depending on the memory system 10, the sending of the sPPR command and the request for sPPR_OFF can be performed simultaneously.

[0106] Figure 18 This is a ladder diagram illustrating an example of a repair operation of a memory system 10 according to another example embodiment. Figure 18 Repair operation of memory system 10 in the middle and Figure 17 The difference between the repair operations shown in the diagram is that the sPPR_OFF request and the sPPR command can be sent simultaneously. Figure 18 The memory device 100 in the middle.

[0107] The memory device according to the example embodiment can be implemented as a stacked memory device.

[0108] Figure 19 This is a block diagram illustrating an example memory chip according to an exemplary embodiment. (Refer to...) Figure 19 The memory chip 1000 may include first memory dies 1100 to third memory dies 1300 stacked in a direction perpendicular to the substrate, and through electrodes (e.g., through-silicon vias (TSVs), or simply vias). The number of stacked memory dies may not be limited to this. Figure 19 Examples are shown in the figure. For example, the first memory die 1100 and the second memory die 1200 may be slave dies, and the third memory die 1300 may be a master die or a buffer die.

[0109] The first memory die 1100 may include a first memory cell array 1110 and a first through-silicon via (TSV) region 1120 for accessing the first memory cell array 1110. The second memory die 1200 may include a second memory cell array 1210 and a second TSV region 1220 for accessing the second memory cell array 1210. The first TSV region 1120 may refer to a region of the first memory die 1100 with TSVs for communication between the first memory die 1100 and the third memory die 1300. Similarly, the second TSV region 1220 may refer to a region of the second memory die 1200 with TSVs for communication between the second memory die 1200 and the third memory die 1300. The TSVs may provide an electrical path between the first memory die 1100 and the third memory die 1300.

[0110] The first memory die 1100 to the third memory die 1300 can be interconnected via through-silicon vias (TSVs). For example, the number of TSVs can be hundreds to thousands, and the TSVs can be arranged in a matrix. The third memory die 1300 may include a first peripheral circuit 1310 and a second peripheral circuit 1320. The first peripheral circuit 1310 may include circuitry for accessing the first memory die 1100, and the second peripheral circuit 1320 may include circuitry for accessing the second memory die 1200. In one example embodiment, each of the peripheral circuits 1310 and 1320 can be interconnected vias for performing operations at a reference... Figures 1 to 18 The sPPR operation and sPPR_OFF method and apparatus described in the foregoing example embodiments are implemented.

[0111] The memory device 100 according to the example embodiment can be applied to a computing system.

[0112] Figure 20 This is a diagram illustrating an example of a computing system 2000 according to an exemplary embodiment. (Refer to...) Figure 20 The computing system 2000 may include at least one volatile memory module (DIMM) 2100, at least one non-volatile memory module (NVDIMM) 2200 and at least one central processing unit (CPU) 2300.

[0113] The computing system 2000 can be implemented using a computer, portable computer, ultra-mobile PC (UMPC), workstation, data server, netbook, personal digital assistant (PDA), tablet computer, cordless phone, mobile phone, smartphone, e-book reader, portable multimedia player (PMP), digital camera, digital audio recorder / player, digital camera / video recorder / player, portable game console, navigation system, wearable device, 3D television, device for receiving and transmitting information in a wireless environment, one of various electronic devices included in a home network, one of various electronic devices included in a computer network, one of various electronic devices included in a telematics network, radio frequency identification (RFID), or one of various electronic devices included in the computing system.

[0114] At least one non-volatile memory module 2200 may include at least one non-volatile memory. In one example embodiment, the at least one non-volatile memory module may include NAND flash memory, vertical NAND (VNAND) flash memory, NOR flash memory, resistive random access memory (RRAM), phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), spin-transfer torque random access memory (STT-RAM), thyristor random access memory (TRAM), etc.

[0115] In one example embodiment, at least one of memory modules 2100 and 2200 may be implemented to perform operations in reference... Figures 1 to 18 The hPPR operation, sPPR operation, and sPPR_OFF operation described in the foregoing example embodiments.

[0116] In one example embodiment, memory modules 2100 and 2200 can be connected to central processing unit 2300 via a DDRx interface (x being an integer equal to or greater than 1).

[0117] At least one central processing unit 2300 may be implemented to control one or more volatile memory modules 2100 and one or more non-volatile memory modules 2200. In one example embodiment, the central processing unit 2300 may include a general-purpose microprocessor, a multi-core processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), or a combination thereof.

[0118] The memory device 100 according to the example embodiment can be applied to an automotive system.

[0119] Figure 21 This is a diagram illustrating an example of an electronic system 3000 for a vehicle according to an exemplary embodiment. (Refer to...) Figure 21The electronic system 3000 may include an electronic controller (ECU) 3100, a memory device 3200, a dynamic range sensor (DVS) 3300, a display 3400, and a communication (COM) processor 3500.

[0120] ECU 3100 can be implemented to control overall operation. ECU 3100 can process image data received from DVS3300. ECU 3100 may include a neural processor (NPU). The NPU can rapidly obtain driving-optimized images by comparing the images received from DVS3300 with a learned model.

[0121] The memory device 3200 can be implemented to store learning models related to the operation of the NPU. The memory device 3200 may include volatile memory or non-volatile memory. For example, the memory device 3200 can be implemented using DRAM or PRAM. Additionally, the memory device 3200 can perform functions such as... Figures 1 to 18 The operation of hPPR mode, sPPR mode, and sPPR_OFF mode is shown in the diagram. Since access to old data remains available even after the sPPR operation, the memory device 3200 can perform repair operations in real time, thus improving data reliability.

[0122] The DVS 3300 can be implemented to sense the external environment of a vehicle. The DVS 3300 can output event signals in response to changes in the relative intensity of light. The DVS 3300 may include a pixel array and an address event processor; the pixel array includes multiple DVS pixels.

[0123] The display 3400 can be implemented as an image processed in the ECU 3100 or an image transmitted via the communication processor 3500.

[0124] The communication processor 3500 can be implemented, for example, to send processed images to an external device (such as an external vehicle) or to receive images from an external vehicle. Therefore, the communication processor 3500 can be implemented to perform wired or wireless communication with external devices.

[0125] The example embodiments can also be applied to mobile devices.

[0126] Figure 22 This is a diagram illustrating an example of a mobile device 4000 according to an exemplary embodiment. (Refer to...) Figure 22Mobile device 4000 may include an application processor (AP) 4100, at least one DRAM 4200, at least one storage device 4300, at least one sensor 4400, a display device 4500, an audio device 4600, a network processor 4700, and at least one input and output (I / O) device 4800. For example, mobile device 4000 may be implemented as a laptop computer, mobile phone, smartphone, tablet computer, or wearable computer.

[0127] Application processor 4100 can be implemented to control the overall operation of mobile device 4000. Application processor 4100 can execute applications that provide internet browsers, games, videos, etc. In one example embodiment, application processor 4100 may include a single core or multiple cores. For example, application processor 4100 may include multiple cores (such as dual-core, quad-core, hexa-core, etc.). In one example embodiment, application processor 4100 may also include cache memory disposed within or outside application processor 4100.

[0128] Application processor 4100 may include control unit (CNTL) 4110, neural processor (NPU) (artificial intelligence processor) 4120, and interface (IF) 4130. In one example embodiment, NPU 4120 may be optionally provided.

[0129] In one example embodiment, the application processor 4100 may be implemented as a system-on-a-chip (SoC). The kernel of the operating system driven in the SoC may include a device driver for controlling the input and output scheduler (I / O scheduler) and the storage device 4300. The device driver may control the access performance of the storage device 4300 by referring to the number of synchronization queues managed in the I / O scheduler, or it may control the CPU mode, DVFS level, etc. in the SoC.

[0130] DRAM 4200 can be connected to control device 4110. DRAM 4200 can store data required to operate application processor 4100. For example, DRAM 4200 can temporarily store operating system (OS) and application data, or it can be used as runtime space for various software codes.

[0131] DRAM 4200 can perform an sPPR shutdown operation upon request from application processor 4100. DRAM 4200 can be connected to NPU 4120. DRAM 4200 can store data related to artificial intelligence computing.

[0132] DRAM 4200 can have a relatively faster latency and bandwidth (BW) than flash memory I / O devices. DRAM 4200 can be configured by default when the mobile power is on. OS and application data can be loaded into DRAM 4200, which can be used as temporary storage space for OS and application data or as runtime space for various software code. The mobile device can perform multitasking operations to load several applications simultaneously, and the switching between applications and their running speed can be used as performance indicators of the mobile device.

[0133] Storage device 4300 can be connected to interface 4130. In one example embodiment, interface 4130 can operate via one of the following communication protocols: DDR, DDR2, DDR3, DDR4, Low Power DDR (LPDDR), Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC, Peripheral Component Interconnect (PCI), Non-Volatile Memory High Speed ​​(NVMe), Peripheral Component Interconnect High Speed ​​(PCIe), Serial Access Attached (SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Universal Storage Bus (USB) Attached SCSI (UAS), Internet Small Computer System Interface (iSCSI), Fibre Channel, and Ethernet Fibre Channel (FCoE). In one example embodiment, a storage device 4300 can be included in a mobile device 4000 by being embedded in it. In another example embodiment, a storage device 4300 can be included in a mobile device 4000 by being connected to or detached from it.

[0134] Storage device 4300 can be implemented to store user data. For example, storage device 4300 can store data collected from sensor 4400, or it can store network data, augmented reality (AR) / virtual reality (VR) data, and high-definition (HD) 4K content. Storage device 4300 may include at least one non-volatile memory device (NVM). For example, storage device 4300 may include a solid-state drive (SSD), an embedded multimedia card (eMMC), etc.

[0135] In one example embodiment, the storage device 4300 may be implemented as a separate chip in the application processor 4100, or it may be implemented together with the application processor 4100 in a single package.

[0136] In one example embodiment, the storage device 4300 can be mounted using various forms of packaging. For example, the storage device 4300 can be mounted using packages such as: package on package (PoP), ball grid array (BAG), chip-scale package (CSP), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), die in waffle pack, die in wafer form, chip on board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat package (MQFP), thin quad flat package (TQFP), small outline package (SOIC), shrink small outline package (SSOP), thin small outline package (TSOP), system-in-package (SIP), multi-chip package (MCP), wafer-level construction package (WTP), wafer-level processing stacked package (WSP), etc.

[0137] Sensor 4400 can be implemented to sense the external environment of mobile device 4000. In one example embodiment, sensor 4400 may include an image sensor for sensing images. In this case, sensor 4400 can send the generated image information to application processor 4100. In another example embodiment, sensor 4400 may include a biosensor for sensing biometric information. For example, sensor 4400 can sense fingerprints, iris patterns, vascular patterns, heart rate, blood glucose, etc., and can generate sensing data corresponding to the sensed information. However, sensor 4400 is not limited to image sensors or biosensors. Sensor 4400 according to the example embodiment may include transient sensors (such as brightness sensors, acoustic sensors, accelerometers, etc.).

[0138] The display device 4500 can be implemented to output data. For example, the display device 4500 can output image data sensed by the sensor 4400, or it can output data calculated by the application processor 4100.

[0139] The audio device 4600 can be implemented to output voice data to the outside and / or sense external voice.

[0140] The network processor 4700 can be implemented to connect and communicate with external devices via wired or wireless communication methods.

[0141] The input and output device 4800 can be implemented to input data to the mobile device 4000 and / or output data from the mobile device 4000. The input and output device 4800 may include devices that provide digital input and output functions (such as USB or storage, digital camera, SD card, touch screen, DVD, modem, network adapter, etc.).

[0142] The example implementation can be applied to various types of computing systems (e.g., CPU / GPU / NPU platforms).

[0143] Figure 23 This is a diagram illustrating an example of a computing system 5000 according to an example embodiment. (Refer to...) Figure 23 The computing system 5000 may include: a central processing unit (CPU) 5110, a graphics processing unit (GPU) 5120, a neural processing unit (NPU) 5130, and / or a dedicated processor, connected to a system bus 5001; a memory device 5210 and / or a storage device 5220, connected to the system bus 5001; and input and output (I / O) devices 5310, a modem 5320, a network device 5330, a storage controller 5341, and / or a storage device 5340, connected to an expansion (e.g., extension) bus 5002. The expansion bus 5002 may be connected to the system bus 5001 via an expansion bus interface 5003.

[0144] In one example embodiment, the CPU 5110, GPU 5120, and NPU 5130 may include on-chip caches 5111, 5121, and 5131, respectively.

[0145] In one example embodiment, CPU 5110 may include off-chip cache 5112. Although in Figure 23 Not shown, but each of the GPU 5120 and NPU 5130 may include an off-chip cache. In one example embodiment, the off-chip cache 5112 may be connected to the interior of the CPU 5110, GPU 5120 and NPU 5130 via different buses.

[0146] In one example embodiment, on-chip / off-chip cache may include volatile memory (such as dynamic random access memory (DRAM), static random access memory (SRAM), etc.) or non-volatile memory (such as NAND flash memory, phase change random access memory (PRAM), resistive random access memory (RRAM), etc.).

[0147] In one example embodiment, main memories 5114, 5124, and 5134 can be connected to CPU 5110, GPU 5120, and NPU 5130 via corresponding memory controllers 5113, 5123, and 5133, respectively. In one example embodiment, main memories 5116, 5126, and 5136 can be connected to CPU 5110, GPU 5120, and NPU 5130 via bridges 5115, 5125, and 5135, respectively. Bridges 5115, 5125, and 5135 may include memory control means for controlling the corresponding main memories 5116, 5126, and 5136. In one example embodiment, each of bridges 5115, 5125, and 5135 can be implemented as a network device, wireless network device, switch, bus, cloud, or optical channel.

[0148] In one example embodiment, each of the main memories 5124 and 5126 may include GPU memory. The GPU memory can hold commands and data interacting with the GPU. Commands and data can be copied to main memory or a storage device. The GPU memory can store image data and can have a bandwidth greater than that of the main memory. The GPU memory can divide the CPU's clock. The GPU can read image data from the GPU memory and can process the data, and can write data to the GPU memory. The GPU memory can be configured to accelerate graphics processing.

[0149] In one example embodiment, main memories 5134 and 5136 may include NPU memory. The NPU memory can hold commands and data interacting with the NPU. Commands and data can be copied to main memory or a storage device. The NPU memory can hold weight data associated with the neural network. The NPU memory can have a bandwidth greater than that of the main memory. The NPU memory can share clock cycles within the CPU. The NPU can read weight data from the NPU memory and can update the data, and can write data to the NPU memory during training. The NPU memory can be configured to accelerate machine learning, such as neural network learning or inference.

[0150] In one example embodiment, each of the main memories 5114, 5116, 5124, 5126, 5134, and 5136 can be implemented for performing operations in reference... Figures 1 to 18 The memory chip for which the repair operation was described in the aforementioned example embodiments.

[0151] In one example embodiment, the main memory may include volatile memory (such as DRAM, SRAM, etc.) or non-volatile memory (such as PRAM, RRAM, etc.). The main memory may have lower latency and capacity than secondary storage devices (e.g., memory device 5210 and memory device 5220).

[0152] CPU 5110, GPU 5120, or NPU 5130 can access secondary storage devices (e.g., memory device 5210 and storage device 5220) via system bus 5001. Memory device 5210 can be controlled by memory controller 5211. Memory controller 5211 can be connected to system bus 5001. Storage device 5220 can be controlled by storage controller 5221. Storage controller 5221 can be connected to system bus 5001.

[0153] Storage device 5220 can be implemented to store data. Storage controller 5221 can be implemented to read data from storage device 5220 and send the read data to the host. Storage controller 5221 can be implemented to store the sent data in storage device 5220 in response to a request from the host. Each of storage device 5220 and storage controller 5221 may include buffers for storing metadata, read caches for storing frequently accessed data, or caches for improving write efficiency. For example, a write cache may receive and process a specific number of write requests.

[0154] Storage device 5220 may include volatile memory (such as hard disk drive (HDD)) and non-volatile memory (such as NVRAM, SSD, storage-class memory (SCM) and novel memory).

[0155] The example implementation can be applied to a data server system.

[0156] Figure 24 This is a diagram illustrating an example of a data server system 6000 according to an example embodiment. (Refer to...) Figure 24 The data server system 6000 may include a first server 6100 (application server), a second server 6200 (storage server), a memory device 6310, and at least one storage device 6320.

[0157] Each of the first server 6100 and the second server 6200 may include at least one processor and at least one memory. In one example embodiment, each of the first server 6100 and the second server 6200 may be implemented as a memory-processor pair. In another example embodiment, each of the first server 6100 and the second server 6200 may be implemented with different numbers of processors and memory depending on its purpose.

[0158] In one example embodiment, the first server 6100 and the second server 6200 can communicate via the first network 6010. In one example embodiment, each of the first server 6100 and the second server 6200 can access the storage device 6310 via the first network 6010 and / or the second network 6020. In one example embodiment, each of the first server 6100 and the second server 6200 can access the storage device 6320 directly or indirectly via the first network 6010 or the second network 6020.

[0159] In one example embodiment, the interface I / F of storage device 6320 may include SATA, SAS, PCIe, DIMM, high-bandwidth memory (HBM), hybrid memory cube (HMC), or NVDIMM. In one example embodiment, the second network 6020 may have a connection form such as a direct-attached storage (DAS) method, a network-attached storage (NAS) method, or a storage area network (SAN) method.

[0160] In one example embodiment, each of the memory device 6310 and the storage device 6320 can send device information to the first server 6100 and / or the second server 6200 via command or autonomously. In one example embodiment, the memory device 6310 may include functions for performing operations in reference... Figures 1 to 18 The memory chip for which the repair operation was described in the aforementioned example embodiments.

[0161] The Data Server System 6000 can perform big data artificial intelligence calculations. Big data can include voice, images, video, or weight / training data.

[0162] According to the foregoing example embodiments, by using a memory device, a memory system including the memory device, and a method of operating the same, access to old data can be made available by disabling the sPPR logic via old data access information after a post-packaging repair operation.

[0163] Furthermore, by using this memory device, the memory system including the memory device, and the method of operating the memory device, access to old data can be easily performed even after a repair operation, thus improving data reliability.

[0164] Although exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A memory device, the memory device comprising: The mode register group is configured to store a first repair mode, a second repair mode, and a second repair off mode; as well as The repair control circuit is configured to: perform a first repair operation in the first repair mode to permanently repair the first word line corresponding to the defective address to a first redundant word line; perform a second repair operation in the second repair mode to temporarily repair the first word line corresponding to the defective address to a second redundant word line; and disable the repair logic configured to perform the second repair operation in the second repair shutdown mode to access old data from the memory cell connected to the first word line corresponding to the defective address after the second repair operation.

2. The memory device of claim 1, wherein, The second repair operation is determined to take precedence over the first repair operation by the repair control circuit or by a controller incorporated into the memory device.

3. The memory device of claim 1, wherein, The repair control circuit is configured to output a hard-packaged repair word line activation signal in response to the activated row address in the first repair mode.

4. The memory device of claim 1, wherein, The repair control circuit is configured to output a soft-packaged repair word line activation signal in response to the activated row address in the second repair mode.

5. The memory device of any one of claims 1-4, wherein, In response to old data access information, a portion of the word line activation logic of the memory device is deactivated.

6. The memory device of claim 5, wherein, The old data access information includes soft-encapsulated repair shutdown information for disabling the repair logic.

7. The memory device of claim 4, wherein, In response to the soft-packaged repair word line activation signal, the activation of both the repair word line and the normal word line is blocked.

8. The memory device of claim 4, wherein, In response to a comparison between the activated row address and the row address stored in the memory device, the soft-packaged repair word line activation signal is output.

9. The memory device according to any one of claims 1 to 4, in, The repair logic includes: The first latch is configured to latch the address in response to an activation signal; A second latch is configured to latch the address in response to a logically calculated value; A first logic circuit is configured to output the logic calculation value by performing an AND operation on the activation signal and the repair mode signal; and The second logic circuit is configured to output a repair word line activation signal by performing an XOR operation on the output values ​​of the first latch and the second latch. The second logic circuit is deactivated in response to the repair shutdown signal.

10. The memory device according to any one of claims 1 to 4, wherein The first repair mode is a hard-encapsulated repair mode, and The second repair mode is a repair mode after soft encapsulation.

11. A method of operating a memory device, the method comprising: In response to a repair request from an external device, a repair operation is performed to replace the word line corresponding to the address with a redundant word line; After performing the repair operation, old data access information is received from the external device; as well as After receiving the old data access information, the old data is output from the memory cell connected to the word line corresponding to the address in response to a read request from the external device.

12. The operating method according to claim 11, further comprising: The mode register group is set in response to the repair request.

13. The operating method according to claim 11, further comprising: The mode register group is set in response to the old data access information.

14. The operating method according to any one of claims 11 to 13, further comprising: Receive a write request containing the old data and the address from the external device; as well as The old data is written to the memory cell connected to the redundant word line.

15. A memory system, the memory system comprising: At least one memory device; as well as The controller is configured to control the at least one memory device. The at least one memory device is configured to: disable the soft-packing repair logic in response to old data access information after performing a soft-packing repair operation, and output old data from a memory cell connected to a normal word line or repair word line corresponding to an address received from the controller after performing the soft-packing repair operation.

16. The memory system of claim 15, wherein, The controller is configured to: determine whether soft-packing post-repair is necessary after a read operation on the at least one memory device, and, if necessary, send a soft-packing post-repair command to the at least one memory device as a result of the determination.

17. The memory system of claim 15, wherein, The controller is configured to send a soft-packing post-repair command to the at least one memory device after the soft-packing post-repair operation.

18. The memory system of claim 15, wherein, The controller is configured to send a soft-package post-repair shutdown message along with a soft-package post-repair command to the at least one memory device.

19. The memory system of claim 15, wherein, The controller is configured to send a read command for outputting the old data to the at least one memory device after the soft-pack repair operation.

20. The memory system according to any one of claims 15 to 19, wherein, When the soft-packing repair operation has not yet been performed on the old data, the old data is output by the at least one memory device.

Images