Storage device and method of operating the storage device

Abstract

A storage device and a method of operating the storage device are provided. The storage device includes a non-volatile memory device having a plurality of memory cells and a storage controller. Each memory cell is configured as one of a plurality of memory cell states, wherein different subsets of the plurality of memory cell states are associated with one of a plurality of data sets. The storage controller accesses data stored in a memory cell in a first state, performs a multiplier-accumulator (MAC) operation on the data, and configures the memory cell as a second state corresponding to the result of the MAC operation to perform an in-situ update.

Description

[0001] This patent application claims the benefit of priority to Korean Patent Application No. 10-2019-0174861, filed December 26, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0002] The present disclosure relates to a storage device, and more particularly, to a method of operating a storage device including a non-volatile memory. BACKGROUND

[0003] Neural network systems are computing systems inspired by biological neural networks. Such systems learn to perform a task by considering samples. The neural network of the system can include a plurality of nodes that learn to infer data by performing computations on input data using certain weights and subsequently passing the results as input to one or more of the nodes. The structure of the neural network, the weights, the output of the neural network, training features used to train the neural network, and data features input to the neural network can be stored in a storage device of the neural network system. Some of the stored data, such as the weights, can be updated during learning or via external stimuli through sensors. Data updates can be performed using convolution operations, such as multiplier-accumulator (MAC) operations. Neuromorphic memory devices having a cross-point structure can be included within the neural network system.

[0004] Neuromorphic memory can be programmed on a cell-by-cell basis. However, read operations performed by neuromorphic memory are not very efficient. SUMMARY

[0005] At least one example embodiment of the present disclosure provides a method of operating a non-volatile memory capable of being accessed on a memory cell-by-memory cell basis.

[0006] At least one example embodiment of the present disclosure also provides a method of operating a non-volatile memory capable of performing multiplier-accumulator (MAC) operations.

[0007] According to example embodiments of the present disclosure, a storage device is provided that includes a non-volatile memory device having a plurality of memory cells and a storage controller configured to access the non-volatile memory device. Each memory cell is set to one of a plurality of memory cell states, where different ones of the plurality of memory cell states are associated with one of a plurality of data sets. The storage controller accesses data stored in one of the plurality of memory cells in a first state, performs a multiplier-accumulator (MAC) operation on the data, and sets the one memory cell to a second state corresponding to a result of the operation to perform an in-place update.

[0008] According to example embodiments of the present disclosure, a method of operating a storage device including a non-volatile memory is provided. The method includes receiving an operation command, performing an operation on a value of a memory cell of the non-volatile memory mapped to a first state according to the operation command to generate a result, determining a second state mapped to the result of the operation, and setting the memory cell to the second state to overwrite the value with the result, where the non-volatile memory includes a plurality of memory cells each set to one of a plurality of memory cell states, where different ones of the plurality of memory cell states are associated with one of a plurality of data sets including a plurality of data sets, and each of the plurality of data sets includes a plurality of values linearly mapped to one of the different ones of the plurality of subsets, respectively.

[0009] According to example embodiments of the present disclosure, a neural network device is provided that includes a memory including a plurality of non-volatile memory cells, a non-volatile memory device configured to store a computer program, and a processor. Each memory cell is set to one of a plurality of memory cell states, where different ones of the plurality of memory cell states are associated with one of a plurality of data sets. The memory stores data. The processor is configured to perform an operation on the data by driving a neural network via running the program. The processor performs the operation on data stored in one of the plurality of non-volatile memory cells and mapped to a first state to generate a result, and sets the one non-volatile memory cell to a second state mapped to the result of the operation. BRIEF DESCRIPTION OF DRAWINGS

[0010] The inventive concept will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1This is a block diagram of a storage device 20 according to an exemplary embodiment of the present disclosure.

[0012] Figure 2 yes Figure 1 The block diagram of the storage controller 100 shown is shown in the figure.

[0013] Figure 3 To show in more detail Figure 1 Block diagram of non-volatile memory device 200.

[0014] Figure 4 Various methods for mapping and distributing memory cells are shown.

[0015] Figure 5 and Figure 6 Linear mapping values ​​of memory cells according to exemplary embodiments of the inventive concept are shown.

[0016] Figure 7A and Figure 7B This is a diagram illustrating a method of operating a storage device according to an exemplary embodiment of the inventive concept.

[0017] Figure 8 The memory cell and the flag cell of the storage device according to an exemplary embodiment of the inventive concept are shown.

[0018] Figure 9 This is for explaining the operation of exemplary embodiments based on the inventive concept. Figure 8 A diagram illustrating a method for using a storage device is shown.

[0019] Figures 10 to 12 This is a flowchart illustrating a method of operating a storage device according to an exemplary embodiment of the inventive concept.

[0020] Figure 13 This is a diagram illustrating a method for operating a storage device when a non-volatile memory device deteriorates, according to an exemplary embodiment of the inventive concept.

[0021] Figure 14 An example of a storage device applied to a neural network device 1000 according to an exemplary embodiment of the inventive concept is shown.

[0022] Figure 15 This is a cross-sectional view of a non-volatile memory device according to an exemplary embodiment of the inventive concept. Detailed Implementation

[0023] In the following description, exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0024] Figure 1 This is a block diagram of a storage device 20 according to an exemplary embodiment of the present disclosure.

[0025] Reference Figure 1 The storage device 20 according to an embodiment of the present disclosure includes a storage controller 100 (e.g., a memory controller) and a non-volatile memory device (NVM) 200.

[0026] According to some exemplary embodiments, the host 10 (e.g., host device) connected to the storage device 20 may include portable electronic devices such as personal / portable computers, personal digital assistants (PDAs), portable multimedia players (PMPs), and smartphones, high-definition televisions (HDTVs), etc.

[0027] According to some exemplary embodiments, the storage device 20 may be implemented as internal memory embedded in an electronic device, and may be, for example, a universal flash memory (UFS) device, an embedded multimedia card (eMMC), or a solid-state drive (SSD). In some embodiments, the storage device 20 may be implemented as external memory capable of being inserted into or removed from an electronic device, and may be, for example, a UFS memory card, a compact flash memory (CF) card, a secure digital card (SD) card, a micro SD card, a mini SD card, an extreme digital (xD) card, or a memory stick.

[0028] The non-volatile memory device 200 may be NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), etc.

[0029] Storage controller 100 is connected to host 10 and non-volatile memory device 200. Storage controller 100 is configured to provide an interface between non-volatile memory device 200 and host 10. For example, storage controller 100 provides control signal CMD and address ADD to non-volatile memory device 200. For example, control signal CMD may be based on a request received from host 10 (such as a read request or a write request). Furthermore, storage controller 100 exchanges data with non-volatile memory device 200. For example, storage controller 100 may receive data and write requests from host 10 and write data to non-volatile memory device 200. For example, storage controller 100 may apply control signal CMD to non-volatile memory device 200 in response to receiving a read request from host 10, and non-volatile memory device 200 may read data in response to the applied control signal CMD and output the read data to storage controller 100.

[0030] In response to a request from host 10, storage controller 100 accesses non-volatile memory device 200. Storage controller 100 can control read operations, write (or program) operations, erase operations, and background operations of non-volatile memory device 200. For example, to control a read operation, storage controller 100 can send a read control signal CMD. read The address ADD is sent to the non-volatile memory device 200. For example, to control a write operation, the memory controller 100 can send a write control signal CMD. write And the data to be written. For example, to control the erase operation, the storage controller 100 can send an erase control signal CMD. erase And address ADD. Furthermore, the storage controller 100 can perform background operations on the non-volatile memory device 200 (such as wear leveling, garbage collection, and bad block management). For example, wear leveling may include ensuring that no memory block is written more than a certain number of times. For example, garbage collection may include copying valid pages from several memory blocks to a single memory block and then erasing several blocks to free up space. For example, bad block management may include continuously tracking memory blocks that store codewords that cannot be corrected and avoiding using these memory blocks for future write operations.

[0031] In some embodiments, the memory controller 100 can control the non-volatile memory device 200 to read data by applying the same read voltage to selected word lines. The non-volatile memory device 200 can use a read voltage with a predetermined threshold voltage to read stored data, and transmits the read data to the memory controller 100 each time data is read. The read data can be transmitted to the memory controller 100 on a page-by-page basis. For example, the non-volatile memory device 200 may include a page buffer, which can be overwritten with the next page of read data, outputting the contents of the page buffer to the memory controller 100, and repeating this process until all read data has been transmitted to the memory controller 100.

[0032] In one exemplary embodiment, the storage controller 100 can access a first state of data stored in a memory cell, perform an operation on the value mapped to the first state, and in-place update the result of the operation to a second state. In this specification, in-place update can refer to a situation where the memory cell storing data before the operation is the same as the memory cell where data has been written (programmed or updated) after the operation. In one exemplary embodiment, the in-place update overwrites the memory cell that already stores data, rather than first erasing the memory cell.

[0033] Figure 2 yes Figure 1 The block diagram of the storage controller 100 shown is shown in the figure.

[0034] Reference Figure 2 According to an exemplary embodiment, the storage controller 100 includes a host interface (I / F) 110, a processor 120 (e.g., a central processing unit (CPU)), a memory 130, a register 140, programmable logic 150, and a non-volatile memory interface (NVM I / F) 160.

[0035] The components of the storage controller 100 are interconnected via a data bus 101. The data bus 101 may include multiple channels. In one exemplary embodiment, the channels may indicate communication paths that are driven independently of each other and communicate with connected devices based on the same communication method.

[0036] Host interface 110 can be connected to host 10. According to an exemplary embodiment, host interface 110 can be based on at least one of various interfaces, such as Double Data Rate (DDR), Low Power DDR (LPDDR), Universal Serial Bus (USB), Multimedia Card (MMC), Peripheral Component Interconnect (PCI), PCI High Speed ​​(PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Device (IDE), Mobile Industry Processor Interface (MIPI), Non-Volatile Memory High Speed ​​(NVM-e), and Universal Flash Memory (UFS)).

[0037] Processor 120 can perform operational control and operation on each element of storage controller 100 in response to write commands, read commands, erase commands, or other commands received from host 10 in relation to the operation of storage device 20. According to an exemplary embodiment of the inventive concept, processor 120 performs a multiplier-accumulator (or multiply-accumulate, MAC) operation for convolution operations required by a neural network. In one exemplary embodiment, the MAC operation includes multiplication and addition operations. For example, a first weight associated with a first input edge of a node in an artificial neural network can be multiplied by a first data input received through the first edge using a multiplier of the MAC operation to generate a first result; a second weight associated with a second input edge of the node can be multiplied by a second data input received through the second edge using a multiplier to generate a second result; the first and second results can be added together using an accumulator of the MAC operation to generate the node's output.

[0038] Memory 130 stores non-volatile data required for the operation of memory controller 100. According to some embodiments, memory 130 may include cache, read-only memory (ROM), programmable read-only memory (PROM), erasable PROM (EPROM), electrically erasable programmable read-only memory (EEPROM), phase-change RAM (PRAM), flash memory, static RAM (SRAM), or dynamic RAM (DRAM).

[0039] Register 140 can be a working memory that temporarily stores write data received from host 10 or read data received from non-volatile memory device 200, as well as operation results generated during control operations of processor 120. Register 140 can also be referred to as buffer memory.

[0040] Programmable logic 150 can perform some of the operations performed by processor 120. For example, some operations of processor 120 can be offloaded to programmable logic 150. According to an exemplary embodiment of the inventive concept, programmable logic 150 is a programmable logic device (PLD) including a plurality of gate arrays (e.g., a field-programmable gate array (FPGA)). PLDs can be used to design digital circuits that perform specific operations.

[0041] The nonvolatile memory interface 160 may also be referred to as a nonvolatile memory controller and can access the nonvolatile memory device 200 to control the operation of each of the plurality of nonvolatile memories. In one exemplary embodiment, the nonvolatile memory interface 160 may be connected to the nonvolatile memory device 200 via at least one channel to write, read, or erase data.

[0042] The non-volatile memory device 200 is provided as the storage medium of the storage device 20. For example, the non-volatile memory device 200 may be configured as a NAND flash memory with a large storage capacity.

[0043] Figure 3 To show in more detail Figure 1 Block diagram of non-volatile memory device 200.

[0044] Reference Figure 3 The non-volatile memory device 200 according to an exemplary embodiment of the present disclosure includes a memory cell array 260, control logic 210, a row decoder 250, a page buffer 220, and an input / output buffer 230.

[0045] The memory cell array 260 includes multiple memory blocks BLK0 to BLKn-1 (where n is an integer greater than 1). Each of the memory blocks BLK0 to BLKn-1 includes multiple pages. Each page includes multiple memory cells. Each memory cell is located at the intersection of the word line WL and the bit line BL.

[0046] The memory cell array 260 may include a flag cell area and a memory cell area corresponding to the main memory.

[0047] In the main memory where data is stored, each memory cell can be a multi-level cell that stores two or more bits of data. Each memory cell can store multiple bits of data. Each memory cell can include one or more datasets. Each dataset can include two or more mapped states.

[0048] According to an exemplary embodiment of the inventive concept, when an operation command is received from the host 10, the storage controller 100 performs an operation on the value of a memory cell in a first state to generate a result, and sets the memory cell to a second state corresponding to the result of the operation to perform an in-situ update. Here, the second state may belong to the same memory cell as the first state, but it may also belong to the same dataset as the dataset to which the first state belongs, or it may belong to a dataset adjacent to the dataset to which the first state belongs. Referring later... Figure 7A and Figure 7B This will be described in detail.

[0049] According to an exemplary embodiment of the inventive concept, the memory cell array 260 includes a flag unit that stores various information about the memory cells.

[0050] According to some embodiments, the flag unit may include one or more states corresponding to the number of datasets included in the memory unit. For example, if there are three datasets, the flag unit may include four states, including an erase state, and may be 2-bit flag data corresponding to the four states.

[0051] According to an exemplary embodiment of the inventive concept, the flag unit includes degradation information of multiple states contained in the memory unit. The degradation information flag unit may be one or more bits of flag data.

[0052] Control logic 210 controls the overall operation of the non-volatile memory device 200. Control logic 210 can be configured to control voltage generator 240. That is, control logic 210 can respond to inputs from memory controller 100 (see...). Figure 1The control signal CMD controls the voltage generator 240 to generate the voltages (e.g., predetermined high voltages) required for write, read, and erase operations. For example, during a read operation, the control logic 210 applies the read voltage Vrd and read pass voltage Vread to the memory cell array 260 via the row decoder 250. Furthermore, the control logic 210 draws voltages from the memory controller 100 (see...) Figure 1 The received address ADD is transmitted to each of the line decoder 250 and the page buffer 220.

[0053] Page buffer 220 operates as a write driver or a sense amplifier depending on the operating mode. For example, page buffer 220 operates as a sense amplifier during a read operation. During a read operation, page buffer 220 receives a page of data from memory cell array 260. Specifically, page buffer 220 receives either the least significant bit (LSB) or most significant bit (MSB) of a page corresponding to a page address from memory cell array 260.

[0054] Input / output buffer 230 is configured to exchange data with an external device. Data received from the external device is transmitted to page buffer 220 via data line DL. For example, input / output buffer 230 can transmit received data to page buffer 220 via data line DL. Data received from page buffer 220 is output to an external device (e.g., memory controller 100). For example, input / output buffer 230 can transmit read data to memory controller 100. For example, input / output buffer 230 may include known elements (such as a data buffer).

[0055] The first memory block BLK0 in the memory cell array 260 includes multiple memory cell groups (not shown).

[0056] Memory cells arranged in a row can form a group of memory cells (e.g., a page). Furthermore, a group of memory cells can be connected to one of multiple word lines (WL).

[0057] For example, the first memory block BLK0 may include first pages Page 1 to page m (where m is an integer greater than 1, and m is equivalent to M). Each of pages Page 1 to Page M may include first sectors to sector k (where k is an integer greater than 1). Each of sectors 1 to sector k includes multiple memory cells (not shown) sharing a word line. Each memory cell may be a multi-level cell storing multiple bits.

[0058] Despite Figure 3Only the first memory block BLK0 is shown, but all first memory blocks BLK0 to the nth memory block BLKn-1 can be configured similarly. In the case of NAND flash memory, read and write operations can be performed on a cell-by-cell basis using an in-situ update method.

[0059] Figure 4 Various methods for mapping and distributing memory cells are shown. Figure 5 and Figure 6 Linear mapping values ​​of memory cells according to exemplary embodiments of the inventive concept are shown.

[0060] In the illustrated embodiment, it is assumed that a memory cell is a four-level cell (QLC) capable of storing 4 bits. However, this is merely an exemplary embodiment, and the present disclosure is not limited thereto. Embodiments of the present disclosure are applicable to any multi-level cell capable of storing two or more bits of data.

[0061] Reference Figure 4 When the memory cell is a 4-bit multi-level cell, the memory cell can be in the erase state E and one of the first state P1 to the fifteenth state P15, and can be programmed (written to) any of the states. Figure 4 The horizontal axis represents the threshold voltage (V) of the memory cell. th The states can be divided by threshold voltages RP1 to RP15. That is, the results of programming in erase state E and in the first state P1 to the fifteenth state P15 during programming operations can be divided by sequentially applying threshold voltages RP1 to RP15 to the selected word lines.

[0062] When a first threshold voltage RP1 is applied to the control gate of a memory cell, the memory cell is turned on if it is in erase state E, but turned off if it is in first state P1 (or any other state besides erase state E). Current flows through the memory cell when it is on. No current flows through the memory cell when it is off. Therefore, the data stored in the memory cell can be distinguished based on whether the memory cell is on or off.

[0063] The logic level assignment of the data can vary depending on the embodiment. According to some embodiments, data '1' can be stored when the memory cell is turned on by applying a first threshold voltage RP1, and data '0' can be stored when the memory cell is turned off. Alternatively, according to one embodiment, data '0' can be stored when the memory cell is turned on, and data '1' can be stored when the memory cell is turned off.

[0064] In the case of QLC, 4 bits of data can be assigned to each state as shown in the accompanying drawings. In one embodiment, data '1111' can be assigned to the erase state E, and data '1110' can be assigned to the first state P1. However, the data assigned to each state is not limited to the example shown and can be changed and subsequently assigned accordingly.

[0065] To access data across multiple layers of cells, multiple bit pages can be included. A QLC can be divided into four bit pages, 1P to 4P, for outputting data. Bit pages 1P to 4P can output data via page buffers U, M, L, and F, respectively.

[0066] The state of a memory cell can be represented using various linear mapping methods. The value mapped to each state is a linear value. That is, the erase state E and the first state P1 to the nth state Pn (where n is an integer greater than 0) can have sequentially and constantly increasing values. Optionally, the memory cell can be linearly mapped in a manner that includes one or more datasets. Each dataset can include two or more states.

[0067] The memory controller 100 performs write operations in the direction from low threshold voltage to high threshold voltage. Therefore, the memory controller 100 can store the result of the operation only in the rightward direction. That is, assuming the value before the operation is stored as a first state and the value after the operation is stored as a second state, the second state can have a higher threshold voltage than the first state. In other words, the second state can be shifted to the right of the first state. Due to the nature of write (programming) operations in non-volatile memory, the second state will not shift to the left.

[0068] According to some embodiments, each of the multiple states of a memory cell can be mapped to a decimal number, a hexadecimal number, or a value in some other number system.

[0069] Figure 4 The states of the memory cells shown can be linearly mapped to values ​​0 to 15 as decimal numbers (DEC) according to some embodiments, or linearly mapped to values ​​0 to 9 and A to F as hexadecimal numbers (HEX) according to some embodiments. In this case, because the values ​​mapped to decimal numbers (0 to 15) or the values ​​mapped to hexadecimal numbers do not overlap, they can refer to a dataset.

[0070] Optionally, refer to Figure 5In the embodiment shown, memory cells can be linearly mapped to eight datasets, each dataset including two states mapped to values ​​0 and 1 respectively. Values ​​0 and 1 in the datasets are linear values, and the set numbers 0 to 7 of datasets 0 to 7 can also increase linearly with each other.

[0071] Optionally, refer to Figure 6 In the embodiment shown, the fifteen states of a memory cell, excluding the erase state E, can be mapped to three datasets (dataset 0 to dataset 2), each dataset comprising five linear values ​​(-2, -1, 0, 1, and 2). In this case, since the erase state E, which is not included in the dataset, represents the state of the memory cell before it was programmed, it can be mapped to invalid.

[0072] Figure 6 Each dataset contains five values. The values, each mapped to a state included in a dataset, can be set in various ways. For example, although in Figure 6 In this example, the values ​​are set to -2, -1, 0, 1, and 2, but the dataset can alternatively be set to 0, 1, 2, 3, and 4. However, this disclosure is not limited to this, and the values ​​can also be mapped to other linear values ​​required according to the system design.

[0073] A storage device according to an exemplary embodiment of the present disclosure can perform write operations on non-volatile memory in such a way as on a cell-by-cell basis: mapping multiple datasets having multiple values ​​to multiple states of memory cells, and performing operations based on the mapped values.

[0074] Figure 7A and Figure 7B This is a diagram illustrating a method of operating a storage device according to an exemplary embodiment of the inventive concept.

[0075] Reference Figure 7A In the example shown, the value V in a dataset can be set to -2, -1, 0, 1, and 2, and can be linearly mapped to states other than the erase state. For example, datasets 0, 1, and 2 can be mapped sequentially to states P1 through P15 in such a direction. Specifically, dataset 0 is mapped to states P1 through P5, dataset 1 is mapped to states P6 through P10, and dataset 2 is mapped to states P11 through P15. Furthermore, the values ​​V of -2, -1, 0, 1, and 2 are mapped to states P1 through P5, P6 through P10, or P11 through P15 in the corresponding datasets, respectively.

[0076] The storage device begins operation in state P1. For example, a memory cell is in state P1 before operation begins, and state P1 is associated with dataset 0. The current value mapped to state P1 is -2. For example, the memory cell can be interpreted as storing the value -2 before operation. Adding (+) 4 to state P1 yields the value 2, causing an offset to state P5, which is mapped to the value 2. For example, if the operation includes adding 4 to the value stored in the memory cell, a first voltage can be applied to the memory cell via the data line to set the memory cell to state P5, associated with dataset 0. In the next operation, subtracting (-) 3 from the value 2 yields the value -1. For example, if the operation also includes subtracting 3 from the value 2 stored in the memory cell, a second voltage higher than the first voltage can be applied to the memory cell via the bit line to set the memory cell to state P7, associated with dataset 1. Due to the programming nature of non-volatile memory, the storage device offsets to state P7, the next adjacent dataset 1, instead of offsetting to state P2, which is mapped to the value -1.

[0077] If the value -1 is multiplied by 2 in the next operation, the current value becomes -2. The storage device is offset to the state P11 of the next adjacent dataset 2, which is mapped to the current value -2. For example, if the operation also includes multiplying the value -1 stored in the memory cell by 2, a third voltage higher than the second voltage can be applied to the memory cell via the bit line to set the memory cell to state P11 associated with dataset 2. If the value -2 is divided by 2 in the next operation, the current value becomes -1. Because values ​​in the same dataset are mapped in the increasing direction, the storage device is offset to state P12. For example, if the operation also includes dividing the value -2 stored in the memory cell by 2, a fourth voltage higher than the third voltage can be applied to the memory cell via the bit line to set the memory cell to state P12 associated with dataset 2.

[0078] Reference Figure 7B In the example shown, the value V in a dataset can be set to 0, 1, 2, 3, and 4, and can be linearly mapped to states other than the erase state. For example, datasets 0, 1, and 2 can be mapped sequentially to states P1 through P15 in such a direction. Specifically, dataset 0 can be mapped to states P1 through P5, dataset 1 can be mapped to states P6 through P10, and dataset 2 can be mapped to states P11 through P15. Furthermore, the values ​​V of 0, 1, 2, 3, and 4 can be mapped to states P1 through P5, P6 through P10, or P11 through P15 in the corresponding datasets, respectively.

[0079] The storage device begins operation in state P1. The current value mapped to state P1 is 0. Adding (+) 4 to state P1 yields the value 4, causing an offset to state P5, which maps to value 4. In the next operation, subtracting (-) 3 from value 4 yields the value 1. Due to the programming nature of non-volatile memory, the storage device offsets to state P7, the next adjacent dataset 1, instead of offsetting to state P2, which maps to value 1.

[0080] If the value 1 is multiplied by 2 in the next operation, the current value becomes 2. The storage device shifts to state P8, which maps to the current value 2. If the value 2 is divided by 2 in the next operation, the current value becomes 1. Since values ​​in the same dataset cannot be mapped in ascending order, the storage device shifts to state P12.

[0081] In other words, the storage device can perform operations on the values ​​mapped to each state, check the position information of the second state mapped to the result value of the operation, and update the position information of the second state. Here, it is checked whether the result value is the value of the second state in the direction of increasing from the value of the first state. Then, the result value is written (updated to or overwritten to) the second state.

[0082] In an exemplary embodiment, when control logic 210 is commanded to update a memory cell from a first value to a second value, control logic 210 determines the current dataset associated with the memory cell, determines the current state of the memory cell within the current dataset (e.g., determines the position of the current state within the current dataset) (where the current state corresponds to the first value), determines whether the memory cell can be offset to the right from the current state (e.g., the current position) to a new first state (e.g., a new first position) within the current dataset for setting the memory cell to the second value, and applies an appropriate voltage to the memory cell to set the memory cell to the new first state based on the determination that the memory cell can be offset to the right to the new first state. For example, refer to... Figure 7A If the memory cell is currently in a first state P1 and is to be updated to the value -1, then because the current dataset is dataset 0, the offset to the right from state P1 within dataset 0 can reach state P2 with the value -1. Therefore, control logic 210 can apply an appropriate voltage to the memory cell to set the memory cell to state P2. If control logic 210 determines that the memory cell cannot be offset to the right to a new first state within the current dataset for setting the memory cell to a second value, then control logic 210 determines a new second state (e.g., a new second position) within the next dataset for setting the memory cell to the second value and applies an appropriate voltage to the memory cell to set the memory cell to the new second state. For example, refer to... Figure 7AIf the memory cell is in state P2 and will be updated to value -2, since the current dataset is dataset 0, the offset to the right within dataset 0 cannot reach value -2. Therefore, control logic 210 determines that state P6 in the next dataset 1 allows the memory cell to be set to value -2. Thus, control logic 210 can apply an appropriate voltage to the memory cell to set the memory cell to state P6.

[0083] Figure 8 The memory cell and the flag cell of the storage device according to an exemplary embodiment of the inventive concept are shown. Figure 9 This is for explaining the operation of exemplary embodiments based on the inventive concept. Figure 8 A diagram illustrating a method for using a storage device is shown.

[0084] Reference Figure 8 Non-volatile memory devices may include memory cell areas and flag cell areas.

[0085] The flag cell area can store status information corresponding to each memory cell. According to some embodiments, the flag cell can be a multi-layered cell. According to some embodiments, the status information can include at least one of operation information and degradation information for each memory cell.

[0086] Operational information indicates whether the state of the stored current value is included in the dataset belonging to the memory cell. More specifically, operational information indicates whether the current value has been processed by the dataset.

[0087] The operation information flag unit may include a number of bits corresponding to the number of datasets included in the memory unit. In the case of the QLC shown in the figure, since there are three datasets, the operation information flag unit may be 2 bits. Specifically, dataset 0 may correspond to flag unit state P1, dataset 1 may correspond to flag unit state P2, and dataset 2 may correspond to flag unit state P3.

[0088] Degradation information is information indicating the degree to which each memory cell has degraded according to its operation. That is, degradation information is log information about the progress of degradation and may include, for example, program / erase (P / E) cycles, read counts, retention time, programming time, and programming / read temperature, but the degradation information according to the present embodiment is not limited to these.

[0089] In one embodiment, the flag unit for a P / E cycle can be one or more bits. In a memory cell, a dataset belonging to a state where the number of P / E cycles exceeds a predetermined value (> a predetermined number A) can be determined as invalid, while other datasets can be determined as valid. In this state, the memory cell can be driven. In other embodiments, similar to the embodiment where P / E cycles are used as degradation information, in a memory cell, when P / E cycles, read counts, retention time, programming time, and / or programming / read temperature do not meet (e.g., are higher or lower than) predetermined values, the corresponding dataset can be determined as invalid, while other datasets can be determined as valid.

[0090] Now refer to Figure 8 and Figure 9 The flag cell states when the operation is performed are described in more detail. First, for the current value -2 (state P1), only the flag cell state P1 corresponding to the dataset 0 to which the state P1 of the memory cell (QLC) belongs is updated to 1, and the flag cell states P2 and P3 are updated to 0.

[0091] In the first operation, if the current value -2 (state P1) is added to 4, the current value becomes 2 (state P5). Considering the aging of memory cells, the flag cell states P1 and P2 corresponding to dataset 0 and dataset 1 before and after state P5 of the memory cell are updated to 1, and the flag cell state P3 is updated to 0.

[0092] In the second operation, if the current value 2 (state P5) is subtracted by 3, the current value becomes -1 (state P7). The flag cell state P2 corresponding to dataset 1 to which the memory cell state P7 belongs is updated to 1, and the flag cell state P3 is updated to 0. At this time, the flag cell state P1 corresponding to dataset 0 is 1.

[0093] In the third operation, if the current value -1 (state P7) is multiplied by 2, the current value becomes -2 (state P11), and the flag cell state P3 corresponding to dataset 2, to which the memory cell state P11 belongs, is updated to 1. At this time, the flag cell state P1 corresponding to dataset 0 is 1, and the flag cell state P2 corresponding to dataset 1 is 1.

[0094] In the fourth operation, if the current value -2 (state P11) is divided by 2, the current value becomes -1 (state P12), and the flag cell state P3 corresponding to dataset 2, to which the memory cell state P12 belongs, is updated to 1. At this time, the flag cell state P1 corresponding to dataset 0 is 1, and the flag cell state P2 corresponding to dataset 1 is 1.

[0095] although Figure 8The status information of the flag unit shown is 1 when the dataset is activated and 0 when the dataset is not activated, but it can also be mapped differently according to other embodiments.

[0096] In other words, the flag cell can be used to determine the range of read voltages during read operations on non-volatile memory. When the memory device accesses the current value (e.g., the current value - 1 after the fourth operation described above) to perform an operation, it only needs to check the flag cell and then apply a threshold voltage value corresponding to the dataset (e.g., dataset 1) corresponding to the flag cell state (e.g., flag cell state P2). Therefore, the efficiency of the read operation can be improved.

[0097] Figures 10 to 12 This is a flowchart illustrating a method of operating a storage device according to an exemplary embodiment of the inventive concept.

[0098] The storage device can perform operations based on the value of each state mapped to a memory cell, and write (or overwrite) the result of the operation to the memory cell. In other words, the storage device can write data to the non-volatile memory device on a cell-by-cell basis (in other words, data can be updated in place to the corresponding memory cell).

[0099] Reference Figure 10 In the case of a write operation, when the storage device performs an operation on the current value of a memory cell in the first state to generate a result, and receives a write (programming) command for writing the result of the operation (operation S10), the storage device performs a write operation on the memory cell to set the memory cell to the second state corresponding to the result of the operation (operation S11). The storage device updates the state of the flag cell corresponding to the dataset to which the second state belongs (operation S12).

[0100] Reference Figure 11 In the case of a read operation, when the storage device intends to read the current value of a memory cell in a first state, the storage device first reads the flag cell corresponding to the memory cell indicated by the address received along with the read command (operation S20). After checking the dataset activation information in the flag cell, the storage device accesses the memory cell by applying a read voltage within the threshold voltage range of the activated dataset (operations S21 to S2n) (where n is an integer greater than 0). For example, if the threshold voltage range includes several read voltages, the storage device may apply one or more of these voltages to the memory cell.

[0101] Reference Figure 12, in the case of an erase operation, the storage device sets the memory cell to the erase state E. Thus, the storage device erases the memory cell (operation S31), while resetting the flag cell corresponding to the memory cell to the erase state E (operation S32).

[0102] That is, according to Figures 10 to 12 the embodiment, when the storage device performs a read operation, a write operation, or an erase operation on a memory cell, it can update information about the operation to the corresponding flag cell.

[0103] Figure 13 is a diagram for explaining a method of operating a storage device when a non-volatile memory device deteriorates according to an exemplary embodiment of the inventive concept.

[0104] Referring to Figure 13 , the deterioration information can be stored in the flag cell area.

[0105] According to some embodiments, the deterioration information flag cell can be a single-level cell or a multi-level cell.

[0106] For the P / E cycle as an embodiment of the deterioration information, the flag cell corresponding to the P / E cycle can have a corresponding bit for each data set. The deterioration information flag cell can be stored as 0 when the number of P / E cycles of the memory cell is equal to or less than a predetermined number A, and can be written as 1 when the number of P / E cycles exceeds the predetermined number A.

[0107] In the illustrated embodiment, when the number of P / E cycles of data set 2 exceeds the predetermined number A, the storage device writes 1 into the flag cell as the deterioration information of data set 2.

[0108] The storage device first reads the deterioration information flag cell and then accesses the corresponding memory cell to perform a read operation, a write operation, or an erase operation.

[0109] For example, in a read operation, the storage device can disable all states P11 to P15 belonging to data set 2 based on the deterioration information flag cell, and remap the threshold voltages RP1' to RP10' and the invalid and data sets 0 and 1 to other states E and P1 to P10. Because in the case of multi-level cells, the gap between threshold voltages is very small, if the threshold voltages are mapped to the remaining states other than the disabled state, the gap between threshold voltages can be increased (W1 < W2), thereby improving the read reliability.

[0110] Figure 14 shows an example in which a storage device according to an exemplary embodiment of the inventive concept is applied to a neural network device 1000.

[0111] Referring toFigure 14 The neural network device 1000 can be implemented as various types of devices (such as personal computers, server devices, mobile devices, and embedded devices). Specifically, the neural network device 1000 can be, but is not limited to, smartphones, tablets, augmented reality (AR) devices, Internet of Things (IoT) devices, autonomous vehicles, robots, or medical devices that use neural networks to perform speech recognition, image recognition, image classification, etc. Furthermore, the neural network device 1000 can be, but is not limited to, a dedicated hardware accelerator installed on the above devices, or a hardware accelerator (such as a neural processor (NPU), tensor processor (TPU), or neural engine as a dedicated module for driving neural networks).

[0112] The neural network device 1000 includes a processor 1120 and a memory 1110. Only elements relevant to the current embodiment are shown in the neural network device 1000. Therefore, those skilled in the art will understand that, in addition to... Figure 14 In addition to the components shown, other general-purpose components may also be included.

[0113] Processor 1120 controls the overall functions used to run neural network device 1000. For example, processor 1120 controls the overall operation of neural network device 1000 by running a program stored in memory 1110 of neural network device 1000. Processor 1120 may be implemented as a central processing unit (CPU), graphics processing unit (GPU), or application processor (AP) included in neural network device 1000, but this disclosure is not limited thereto.

[0114] The memory 1110 is hardware that stores various types of data processed in the neural network device 1000. For example, the memory 1110 may store data processed by the neural network device 1000 and data to be processed. Furthermore, the memory 1110 may store applications, drivers, etc., that will be driven by the neural network device 1000. According to some embodiments, the memory 1110 may be… Figure 1 The non-volatile memory device 200 shown is included. According to one embodiment, the memory 1110, which is a non-volatile memory, may include random access memory (RAM) (such as DRAM or SRAM), ROM, EEPROM, CD-ROM, Blu-ray or other optical disc storage devices, hard disk drive (HDD), SSD or flash memory.

[0115] Processor 1120 can read neural network data (e.g., image data, feature map data, or kernel data) from memory 1110 and write neural network data (e.g., image data, feature map data, or kernel data) to memory 1110, and uses the read / write data to execute the neural network (e.g., an artificial neural network). When the neural network is executed, processor 1120 can repeatedly perform convolution operations between the input feature maps and kernels to generate data about the output feature maps. Processor 1120 can be coupled with... Figure 1 The memory controller 100 shown operates similarly. The processor 1120 can perform a very large number (operation count) of convolution operations in the range of hundreds of millions to tens of billions, and the number of times the processor 1120 accesses the memory 1110 to perform convolution operations can increase dramatically.

[0116] The neural network device 1000 according to an embodiment may include neuromorphic hardware. According to some embodiments, the neuromorphic hardware may be disposed separately from or may be part of the memory 1110. The neuromorphic hardware can perform convolutional neural network (CNN) mapping. The neuromorphic hardware can perform operations using only on-chip memory without using external memory. For example, the neuromorphic hardware can perform CNN mapping using only on-chip memory without using external memory (e.g., off-chip memory). Therefore, it can perform operations during image processing without memory updates.

[0117] Figure 15 This is a cross-sectional view of a non-volatile memory device according to an exemplary embodiment of the inventive concept.

[0118] Reference Figure 15 The memory device 400 may have a chip-to-chip (C2C) architecture. The memory device 400 is referenced... Figure 1 and Figure 3 An exemplary embodiment of the memory device. A C2C structure can refer to a structure formed by fabricating an upper chip including cell regions (CELL) on a first wafer, fabricating a lower chip including peripheral circuit regions (PERI) on a second wafer different from the first wafer, and then connecting the upper and lower chips in a bonding manner. For example, the bonding manner may include a method of electrically connecting a bonding metal formed on the topmost metal layer of the upper chip to a bonding metal formed on the topmost metal layer of the lower chip. For example, when the bonding metal can be formed of copper (Cu), the bonding manner can be a Cu-Cu bonding; the bonding metal can also be formed of aluminum or tungsten.

[0119] Each of the peripheral circuit area PERI and cell area CELL of memory device 400 may include an external pad (or “solder pad”) bonding area PA, a word line bonding area WLBA, and a bit line bonding area BLBA.

[0120] The Peripheral Circuit Area (PERI) may include a first substrate 210, an interlayer insulating layer 215, a plurality of circuit elements 220a, 220b, and 220c formed on the first substrate 210, first metal layers 230a, 230b, and 230c respectively connected to the plurality of circuit elements 220a, 220b, and 220c, and second metal layers 240a, 240b, and 240c formed on the first metal layers 230a, 230b, and 230c. In one example embodiment, the first metal layers 230a, 230b, and 230c may be formed of tungsten, which has relatively high resistance, and the second metal layers 240a, 240b, and 240c may be formed of copper, which has relatively low resistance.

[0121] exist Figure 15 In the example embodiments shown, although the first metal layers 230a, 230b, and 230c and the second metal layers 240a, 240b, and 240c are shown and described, they are not limited thereto, and one or more metal layers may be further formed on the second metal layers 240a, 240b, and 240c. At least a portion of the one or more metal layers formed on the second metal layers 240a, 240b, and 240c may be formed of aluminum or the like, having a lower resistance than the copper used to form the second metal layers 240a, 240b, and 240c.

[0122] Interlayer insulating layer 215 may be disposed on first substrate 210 and cover multiple circuit elements 220a, 220b and 220c, first metal layers 230a, 230b and 230c and second metal layers 240a, 240b and 240c. Interlayer insulating layer 215 may include insulating material (such as silicon oxide, silicon nitride, etc.).

[0123] Lower bonding metals 271b and 272b can be formed on the second metal layer 240b in the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 271b and 272b in the peripheral circuit region PERI can be electrically connected to the upper bonding metals 371b and 372b in the cell region CELL in a bonding manner. The lower bonding metals 271b and 272b and the upper bonding metals 371b and 372b can be formed of aluminum, copper, tungsten, etc.

[0124] A cell region (CELL) may include at least one memory block. The cell region (CELL) may include a second substrate 310 and a common-source line 320. On the second substrate 310, multiple word lines 331 to 338 (i.e., 330) may be stacked in a direction perpendicular to the upper surface of the second substrate 310 (Z-axis direction). At least one string select line and at least one ground select line may be arranged above and below the multiple word lines 330, respectively, and the multiple word lines 330 may be disposed between the at least one string select line and the at least one ground select line.

[0125] In the bit line bonding area BLBA, the channel structure CH can extend in a direction perpendicular to the upper surface of the second substrate 310 and pass through multiple word lines 330, at least one string select line, and at least one ground select line. The channel structure CH may include a data storage layer, a channel layer, a buried insulating layer, etc., and the channel layer may be electrically connected to the first metal layer 350c and the second metal layer 360c. For example, the first metal layer 350c may be a bit line contact, and the second metal layer 360c may be a bit line. In one example embodiment, the bit line 360c may extend in a first direction (Y-axis direction) parallel to the upper surface of the second substrate 310.

[0126] exist Figure 15 In the example embodiment shown, the region provided with the channel structure CH, bit line 360c, etc., can be defined as a bit line bonding region BLBA. In the bit line bonding region BLBA, bit line 360c can be electrically connected to circuit element 220c that provides page buffer 393 in the peripheral circuit area PERI. For example, bit line 360c can be connected to upper bonding metals 371c and 372c in the cell area CELL, and upper bonding metals 371c and 372c can be connected to lower bonding metals 271c and 272c connected to the circuit element 220c of the page buffer 393.

[0127] In the word line bonding area (WLBA), multiple word lines 330 can extend in a second direction (X-axis direction) parallel to the upper surface of the second substrate 310 and can be connected to multiple cell contact plugs 341 to 347 (i.e., 340). The multiple word lines 330 and the multiple cell contact plugs 340 can be connected to each other in a pad provided by at least a portion of the multiple word lines 330 extending at different lengths along the second direction. A first metal layer 350b and a second metal layer 360b can be sequentially connected to the upper portion of the multiple cell contact plugs 340 connected to the multiple word lines 330. The multiple cell contact plugs 340 can be connected to the peripheral circuitry area (PERI) in the word line bonding area (WLBA) via upper bonding metals 371b and 372b of the cell area (CELL) and lower bonding metals 271b and 272b of the peripheral circuitry area (PERI).

[0128] Multiple unit contact plugs 340 may be electrically connected to circuit element 220b providing a line decoder 394 in the peripheral circuitry area (PERI). In one example embodiment, the operating voltage of circuit element 220b providing the line decoder 394 may differ from the operating voltage of circuit element 220c providing the page buffer 393. For example, the operating voltage of circuit element 220c providing the page buffer 393 may be greater than the operating voltage of circuit element 220b providing the line decoder 394.

[0129] A common-source electrode contact plug 380 can be disposed in the external pad bonding region PA. The common-source electrode contact plug 380 can be formed of a conductive material (such as a metal, metal compound, polysilicon, etc.) and can be electrically connected to the common-source electrode 320. A first metal layer 350a and a second metal layer 360a can be sequentially stacked on the upper part of the common-source electrode contact plug 380. For example, the region where the common-source electrode contact plug 380, the first metal layer 350a, and the second metal layer 360a are disposed can be defined as the external pad bonding region PA.

[0130] Input / output pads 205 and 305 can be positioned within the external pad mating area PA. (See reference...) Figure 15 A lower insulating film 201 covering the lower surface of the first substrate 210 can be formed below the first substrate 210, and a first input / output pad 205 can be formed on the lower insulating film 201. The first input / output pad 205 can be connected to at least one of a plurality of circuit elements 220a, 220b, and 220c disposed in the peripheral circuit area PERI via a first input / output contact plug 203, and can be separated from the first substrate 210 via the lower insulating film 201. Furthermore, a side insulating film can be disposed between the first input / output contact plug 203 and the first substrate 210 to electrically separate the first input / output contact plug 203 and the first substrate 210.

[0131] Reference Figure 15 An upper insulating film 301 covering the upper surface of the second substrate 310 can be formed on the second substrate 310, and a second input / output pad 305 can be disposed on the upper insulating film 301. The second input / output pad 305 can be connected to at least one of a plurality of circuit elements 220a, 220b, and 220c disposed in the peripheral circuit area PERI via a second input / output contact plug 303. For example, refer to Figure 15 The lower bonding metals 271a and 272a can be disposed on the second metal layer 240a connected to the circuit element 220a via the first metal layer 230a. The second input / output contact plug 303 connected to the second input / output pad 305 can be electrically connected to the lower bonding metals 271a and 272a via the upper metal pattern disposed in the uppermost metal layer of the cell area CELL, and thereby connected to, for example, the circuit element 220a.

[0132] According to one embodiment, the second substrate 310 and the common-source electrode 320 may not be located in the area where the second input / output contact plug 303 is provided. Furthermore, the second input / output pad 305 may not overlap with the word line 330 in the third direction (Z-axis direction). See also... Figure 15 The second input / output contact plug 303 can be separated from the second base 310 in a direction parallel to the upper surface of the second base 310, and can pass through the interlayer insulation layer 315 of the cell area to connect to the second input / output pad 305.

[0133] According to embodiments, the first input / output pad 205 and the second input / output pad 305 can be selectively formed. For example, the memory device 400 may include only the first input / output pad 205 disposed on the first substrate 210 or the second input / output pad 305 disposed on the second substrate 310. Alternatively, the memory device 400 may include both the first input / output pad 205 and the second input / output pad 305.

[0134] In each of the outer pad bonding region PA and bit line bonding region BLBA, which are respectively included in the cell region CELL and the peripheral circuit region PERI, the metal pattern in the uppermost metal layer can be set as a dummy pattern, or the uppermost metal layer can be absent.

[0135] In the external pad bonding region PA, the memory device 400 may include a lower metal pattern 273a in the uppermost metal layer of the peripheral circuit region PERI, which corresponds to and has the same shape as the upper metal pattern 372a in the uppermost metal layer of the cell region CELL. In the peripheral circuit region PERI, the lower metal pattern 273a in the uppermost metal layer of the peripheral circuit region PERI may not be connected to a contact. Similarly, in the external pad bonding region PA, an upper metal pattern corresponding to and having the same shape as the lower metal pattern in the uppermost metal layer of the peripheral circuit region PERI may be formed in the uppermost metal layer of the cell region CELL. In the external pad bonding region PA, a contact 371a may be disposed on the upper metal pattern 372a, which may be electrically connected to the common source contact plug 380 via the contact 371a, a portion of the second metal layer 360a, and a portion of the first metal layer 350a.

[0136] Lower bonding metals 271b and 272b can be formed on the second metal layer 240b in the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 271b and 272b of the peripheral circuit region PERI can be electrically connected to the upper bonding metals 371b and 372b of the cell region CELL via Cu-Cu bonding.

[0137] Furthermore, in the bit line bonding area (BLBA), an upper metal pattern 392, corresponding to the lower metal pattern 252 formed in the uppermost metal layer of the peripheral circuit area (PERI) and having the same shape as the lower metal pattern 252 of the PERI, can be formed in the uppermost metal layer of the cell area (CELL). Contacts may not be formed on the upper metal pattern formed in the uppermost metal layer of the cell area (CELL). In the bit line bonding area (BLBA), a contact 251 can be disposed on the lower metal pattern 252, and the lower metal pattern 252 can be connected to at least a portion of the second metal layer 240c of the PERI via the contact 251.

[0138] In one example embodiment, a reinforcing metal pattern (e.g., upper metal pattern 372a and lower metal pattern 252) having the same shape as the metal pattern formed in the uppermost metal layer of one of the cell region CELL and the peripheral circuit region PERI can be formed in the uppermost metal layer of the other of the cell region CELL and the peripheral circuit region PERI, and the contact may not be formed on the reinforcing metal pattern.

[0139] In summarizing the specific embodiments, those skilled in the art will understand that many variations and modifications can be made to these exemplary embodiments without fundamentally departing from the principles of the inventive concept.

Claims

1. A storage device, comprising: a non-volatile memory device including a plurality of memory cells each set to one of a plurality of memory cell states, wherein different ones of the plurality of memory cell states are associated with one of a plurality of data sets; and a storage controller configured to access the non-volatile memory device, wherein the storage controller accesses data stored in one of the plurality of memory cells in a first one of the plurality of memory cell states, performs a multiplier-accumulator operation on the data, and sets the one memory cell to a second one of the plurality of memory cell states corresponding to a result of the multiplier-accumulator operation to perform an in-place update without erasing the one memory cell by overwriting data of the one memory cell with the result.

2. The memory device of claim 1, wherein, each of the plurality of data sets includes a plurality of values respectively mapped to one of the plurality of subsets of the plurality of memory cell states.

3. The memory device of claim 2, wherein, the plurality of values are linearly mapped to respective memory cell states in a corresponding one of the plurality of subsets of the plurality of memory cell states, and each of the plurality of values is an integer.

4. The memory device of claim 3, wherein, when the result of the multiplier-accumulator operation is positioned to the right of a value mapped to the first state in a current data set to which the first state belongs, the second state to which the result of the multiplier-accumulator operation is mapped belongs to the current data set.

5. The memory device of claim 3, wherein, when the result of the multiplier-accumulator operation is positioned to the left of a value mapped to the first state in a current data set to which the first state belongs, the second state to which the result of the multiplier-accumulator operation is mapped belongs to a next data set adjacent to the current data set.

6. The storage device of any one of claims 1 to 5, wherein, a threshold voltage of the second state is greater than a threshold voltage of the first state.

7. The storage device of any one of claims 1 to 5, wherein, the non-volatile memory device includes a plurality of flag cells respectively corresponding to the plurality of memory cells and storing information about the plurality of memory cells.

8. The memory device of claim 7, wherein, each of the plurality of flag cells includes activation information indicating which of the plurality of data sets have been activated during in-place updates to a corresponding one of the plurality of memory cells, and the storage controller accesses the activated data sets based on the activation information.

9. The memory device of claim 7, wherein, each of the plurality of flag cells includes program / erase cycle information of the corresponding memory cell, and the storage controller remaps states belonging to data sets other than at least one data set to new threshold voltages based on the program / erase cycle information.

10. The memory device of claim 7, wherein, when erasing one of the plurality of memory cells, the storage controller erases a flag cell corresponding to the one memory cell being erased.

11. A method of operating a storage device including a non-volatile memory device, the method comprising: receiving an operation command; performing an operation on a value of a memory cell of the non-volatile memory device mapped to a first one of a plurality of memory cell states according to the operation command to generate a result; determining a second state of the plurality of memory cell states that maps to a result of the operation; and overwriting a value of the memory cell with the result without erasing the memory cell to set the memory cell to the second state, wherein the non-volatile memory device includes a plurality of memory cells each set to one of a plurality of memory cell states, wherein different ones of the plurality of memory cell states are associated with one of a plurality of data sets, and each of the plurality of data sets includes a plurality of values that respectively linearly map to one of the plurality of subsets.

12. The method of claim 11, wherein, The non-volatile memory device includes a plurality of flag cells that respectively store information corresponding to respective ones of the plurality of memory cells, and each of the plurality of flag cells includes one or more states corresponding to respective ones of the plurality of data sets.

13. The method of claim 12, prior to the operation being performed, the method further comprising: accessing the plurality of flag cells; and checking whether each of the plurality of data sets has been activated.

14. The method of claim 12 or 13, wherein, Activation information of the data set to which the first and second states belong as a result of the operation is updated to the flag cells corresponding to the data set to which the first and second states belong.

15. A neural network device comprising: a memory including a plurality of non-volatile memory cells and storing data, each non-volatile memory cell set to one of a plurality of memory cell states, wherein different ones of the plurality of memory cell states are associated with one of a plurality of data sets; a non-volatile memory device configured to store a computer program; and a processor configured to perform an operation on the data by driving a neural network via running the computer program, wherein the processor performs the operation on data stored in one of the plurality of non-volatile memory cells and mapping to a first state of the plurality of memory cell states to generate a result, and the processor sets the one of the plurality of non-volatile memory cells to a second state of the plurality of memory cell states that maps to a result of the operation by overwriting the data stored in the one of the plurality of non-volatile memory cells with the result without erasing the one of the plurality of non-volatile memory cells.

16. The neural network device of claim 15, wherein, Each of the plurality of data sets includes a plurality of values that respectively map to one of the plurality of subsets of the plurality of memory cell states.

17. The neural network device of claim 15, wherein, The operation is an addition, subtraction, multiplication, or division for a convolution operation.

18. The neural network device of claim 15, wherein, The memory is located within the non-volatile memory device.

19. The neural network device of any one of claims 15-18, wherein, The memory includes a plurality of flag cells that respectively store information corresponding to respective ones of the plurality of non-volatile memory cells, and each of the plurality of flag cells stores flag information corresponding to respective ones of the plurality of data sets.

20. The neural network device of claim 19, wherein, The flag unit stores deterioration information of the nonvolatile memory cell, and the processor remaps a state other than at least one deteriorated state to a new threshold voltage based on the deterioration information.

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