Method for identifying and addressing plasma discharges during semiconductor processing

Abstract

A method for identifying and addressing plasma discharges. A plasma discharge detection system detects unwanted plasma discharge events in a semiconductor processing chamber. The plasma discharge detection system includes one or more cameras located around the semiconductor processing chamber. The cameras capture images from within the semiconductor processing chamber. The plasma discharge detection system includes a control system that receives the images from the cameras. The control system analyzes the images and detects plasma discharges in the semiconductor processing chamber based on the images. The control system can adjust the semiconductor process in real time in response to detecting a plasma discharge. The present disclosure can result in better uniformity in semiconductor wafers and their integrated circuits.

Description

Field of the Invention

[0001] This disclosure relates to the field of semiconductor processing. More specifically, this disclosure relates to a method for identifying and addressing plasma discharges during a semiconductor process to detect abnormal plasma discharges. Background Art

[0002] The fabrication of integrated circuits is typically accomplished by performing a large number of processing steps on a semiconductor wafer. The processing steps typically result in the formation of a large number of transistors in a highly complex arrangement in combination with a semiconductor substrate. The processing steps also result in the formation of dielectric layers, metal interconnects, vias, plugs, and other integrated circuit structures and components.

[0003] Many semiconductor processes utilize plasma. During plasma-based semiconductor processes, undesired plasma discharges may occur within the processing environment. Undesired plasma discharges can include arcing, corona discharge, or spark. Undesired plasma discharges can have a negative impact on the semiconductor process and may even directly damage the semiconductor wafer. As a result, it may be necessary to discard the affected semiconductor wafers. Summary of the Invention

[0004] A method for identifying and addressing plasma discharges according to an embodiment of the present disclosure includes: capturing an image of a semiconductor processing chamber 102 by one or more cameras 108; processing the image by a control system 110; and detecting the plasma discharge within the semiconductor processing chamber by the control system based on the image.

[0005] A system for identifying and addressing plasma discharges according to an embodiment of the present disclosure includes: a semiconductor processing chamber 102; one or more cameras 108 positioned to capture an image of the semiconductor processing chamber; and a control system 110 communicatively coupled to the one or more cameras and configured to detect a plasma discharge within the semiconductor processing chamber based on the image and adjust the semiconductor process in response to detecting the plasma discharge.

[0006] A method for identifying and addressing plasma discharges according to an embodiment of the present disclosure includes: performing a semiconductor process on a semiconductor wafer 104 in a semiconductor processing chamber 102; capturing a video stream of the interior of the semiconductor processing chamber during the semiconductor process by one or more cameras 108; detecting an arc within the semiconductor processing chamber by processing the video stream by a control system 110; and adjusting the semiconductor process within the semiconductor processing chamber in response to detecting an arc within the semiconductor processing chamber. Brief Description of the Drawings

[0007] Figure 1 is a block diagram of a semiconductor processing system including a discharge detection system according to one embodiment.

[0008] Figure 2 is an illustrative diagram of a semiconductor processing system including a plasma discharge detection system according to one embodiment.

[0009] Figure 3 is an illustrative diagram of camera placement in a semiconductor processing system according to one embodiment.

[0010] Figure 4 Illustrates a plurality of curves indicating the spectral sensitivity of various types of cameras according to one embodiment.

[0011] Figure 5 is a block diagram of a video signal output circuit system according to one embodiment.

[0012] Figure 6 is a block diagram of a control system of a plasma discharge detection system according to one embodiment.

[0013] Figure 7 is a flowchart of a method for detecting plasma discharge in a semiconductor process chamber according to one embodiment.

[0014] Figure 8 is a flowchart of a method for detecting plasma discharge in a semiconductor process chamber according to one embodiment.

[0015] [Description of symbols]

[0016] 100: Semiconductor processing system / System

[0017] 102: Semiconductor process chamber / Clean environment

[0018] 104: Wafer / Semiconductor wafer

[0019] 106: Semiconductor processing equipment

[0020] 108: Camera

[0021] 110: Control system

[0022] 112: Bottom electrode

[0023] 114: Top electrode

[0024] 116: Radio frequency power supply

[0025] 118: Hole

[0026] 120: Plasma region

[0027] 122: Anode glow region

[0028] 124: Cathode glow region

[0029] 126: Arc event / analysis model

[0030] 127: Corona discharge event

[0031] 130: Optical system

[0032] 140: Curve graph

[0033] 141, 152: Filter

[0034] 142, 154: Signal processor

[0035] 144, 150: Communication system

[0036] 146: Power supply

[0037] 148: Video signal output circuit system

[0038] 156: Analysis model

[0039] 158: Process controller

[0040] 700, 800: Method

[0041] 702, 704, 706, 708, 802, 804, 806: Step Detailed implementation mode

[0042] In the following description, many thicknesses and materials are described for each layer and structure within an integrated circuit die. Specific dimensions and materials of various embodiments are given by way of example. Those skilled in the art should recognize, in accordance with the present disclosure, that other dimensions and materials may be used in many instances without departing from the scope of the present disclosure.

[0043] The following disclosure provides many different embodiments or examples for implementing different features of the subject matter. Specific examples of components and arrangements are set forth below to simplify the description. Of course, these are only examples and are not intended to be limiting. For example, forming a first feature on or above a second feature in the following description may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature are not in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0044] In addition, for ease of explanation, spatially relative terms such as "beneath", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or feature illustrated in the figures to another (other) element or feature. Such spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0045] In the following description, certain specific details are set forth to provide a thorough understanding of various embodiments of the present disclosure. However, those skilled in the art will understand that the present disclosure may be practiced without these specific details. In other instances, well-known structures associated with electronic components and fabrication techniques have not been described in detail to avoid unnecessarily obscuring the description of the embodiments of the present disclosure.

[0046] Unless the context requires otherwise, throughout the specification and the claims above, the word "comprise" and its variations (such as "comprises" and "comprising") shall be construed in an open, inclusive sense, i.e., "including but not limited to".

[0047] Ordinal numbers such as first, second, and third, etc. used herein do not necessarily imply a sense of ranking order, but may only be used to distinguish between multiple instances of an action or structure.

[0048] References to "an embodiment" or "embodiments" in this specification mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the phrases "in an embodiment" or "in embodiments" that appear throughout this specification do not necessarily all refer to the same embodiment. Moreover, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0049] Unless the context clearly dictates otherwise, the singular forms "a", "an", and "the" as used in this specification and the appended claims include plural referents. It should also be noted that, unless the context clearly dictates otherwise, the term "or" is generally used in its inclusive sense, including "and / or".

[0050] Embodiments of the present disclosure utilize plasma detection technology to improve semiconductor processes. Embodiments of the present disclosure capture a video stream of a semiconductor process chamber, analyze the video stream by a control system, and identify abnormal plasma discharges within the semiconductor process chamber. The control system then adjusts parameters of the semiconductor process in response to detecting the abnormal plasma discharge to reduce or eliminate the abnormal plasma discharge in real time. This enables the semiconductor process to produce better uniformity in semiconductor wafers and their integrated circuits. Additionally, since the wafers are not damaged or scrapped due to abnormal plasma discharges, the wafer yield is greatly increased.

[0051] Figure 1 FIG. 4 is a block diagram of a semiconductor processing system 100 according to an embodiment. The semiconductor processing system 100 includes: a semiconductor process chamber 102 for performing one or more semiconductor processes on a wafer 104. The semiconductor processing system 100 is configured to detect an undesired plasma discharge within the semiconductor process chamber 102.

[0052] In one embodiment, the semiconductor process chamber 102 is for performing one or more semiconductor processes on a wafer 104. The wafer 104 is a semiconductor wafer. Typically, a semiconductor wafer undergoes a large number of processes during fabrication. These processes may include thin film deposition, photoresist patterning, etching processes, dopant implantation processes, annealing processes, and other types of processes. After all the processing steps are completed, the wafer 104 is diced into multiple individual integrated circuits.

[0053] In one embodiment, the semiconductor process chamber 102 is for performing one or more plasma-based semiconductor processes on a wafer 104. Plasma-based processes may include generating a plasma within the semiconductor process chamber 102. The plasma may assist in thin film deposition processes, etching processes, doping processes, ashing processes, polymerization processes, or other types of processes.

[0054] The semiconductor processing system 100 includes semiconductor processing equipment 106. The semiconductor processing equipment 106 assists in performing semiconductor processes. The semiconductor processing equipment 106 may include equipment for assisting in thin film deposition processes, etching processes, ion implantation processes, annealing processes, lithography processes, and other types of processes. The semiconductor processing equipment 106 may include components for generating a plasma within the semiconductor process chamber 102. Some of the semiconductor processing equipment 106 may be entirely located within the semiconductor process chamber 102. Some of the semiconductor processing equipment 106 may be partially located within the semiconductor process chamber 102 and partially located outside the semiconductor process chamber 102. Some of the semiconductor processing equipment 106 may be entirely located outside the semiconductor process chamber 102.

[0055] The semiconductor processing apparatus 106 may include electrical components for generating an electric field, voltage, magnetic field, electrical signal, or other type of electrical effect. Accordingly, the semiconductor processing apparatus 106 may include electrodes, wiring, radio frequency power supplies, transmitters, receivers, or other types of electrical devices that may be used in semiconductor processes.

[0056] The semiconductor processing apparatus 106 may include devices for managing gases or flows within the semiconductor processing chamber 102. The processing apparatus may include components for introducing gases or fluids into the semiconductor processing chamber 102, for removing gases or fluids from the semiconductor processing chamber, and for monitoring and controlling the flow rate, presence, or composition of gases within the semiconductor processing chamber 102. The semiconductor processing apparatus 106 may include devices for maintaining a selected pressure within the interior of the semiconductor processing chamber 102.

[0057] During processing steps performed on the semiconductor wafer 104, an undesired plasma discharge may occur within the semiconductor processing chamber 102. The undesired plasma discharge may include an arc, corona discharge, or spark. An arc is an instantaneous flow of high current within the semiconductor processing chamber 102 (typically between two conductive elements within the semiconductor processing chamber 102, or between a conductor and the semiconductor wafer 104). Arcs may occur due to the accumulation of static electrical charges between objects or materials within the semiconductor processing chamber 102. Static electrical charges may accumulate on electrodes within the semiconductor processing chamber 102, on the wafer 104, on the walls of the semiconductor processing chamber 102, on processing equipment within the semiconductor processing chamber 102, within the gases present within the semiconductor processing chamber 102, or otherwise. An arc may occur when the electric field becomes large enough due to the accumulation of static electrical charges or due to other factors.

[0058] In a corona discharge, current flows from a conductor having a high electrical potential into a fluid (e.g., air) by ionizing the fluid to create a plasma region around an electrode. The ions generated eventually transfer the charge to a nearby region of low electrical potential, or recombine to form neutral gas molecules.

[0059] If an arc or corona discharge occurs in the vicinity of the semiconductor wafer 104, the semiconductor wafer 104 may be damaged. For example, if an arc causes a large current to flow between a portion of the semiconductor wafer 104 and another object or material within the semiconductor processing chamber 102, the current may damage the semiconductor wafer 104. If the semiconductor wafer 104 is damaged, some of the integrated circuit dies produced by the semiconductor wafer 104 may not function properly. In some cases, the semiconductor wafer 104 may be completely damaged such that the entire semiconductor wafer 104 needs to be discarded. This can result in significant losses of time, materials, and money.

[0060] In one embodiment,Figure 1 The semiconductor processing system 100 is capable of detecting and controlling unwanted plasma discharges in the semiconductor processing chamber 102 in real time. The semiconductor processing system 100 includes a plasma discharge detection system. The plasma discharge detection system includes one or more cameras 108 and a control system 110. The cameras 108 cooperate with the control system 110 to detect arcs within the semiconductor processing chamber 102.

[0061] In one embodiment, the one or more cameras 108 are positioned to capture video images of the interior of the semiconductor processing chamber 102. The one or more cameras 108 are configured to continuously capture a video stream of the interior of the semiconductor processing chamber 102 during semiconductor processing. Images in the form of a video stream are used to detect plasma discharges within the semiconductor processing chamber 102.

[0062] In one embodiment, the one or more cameras 108 are located outside the semiconductor processing chamber 102. The semiconductor processing chamber 102 may include one or more windows or apertures through which light can pass from the interior of the semiconductor processing chamber 102 to the one or more cameras 108. Alternatively, the walls of the semiconductor processing chamber 102 may be transparent, enabling the one or more cameras 108 to capture images of the interior of the semiconductor processing chamber 102. In this way, the one or more cameras 108 can capture a video stream of the interior of the semiconductor processing chamber 102.

[0063] In one embodiment, the semiconductor processing system 100 includes multiple cameras located at different positions around the semiconductor processing chamber 102. Specifically, the multiple cameras 108 may be arranged such that images of the interior of the semiconductor processing chamber 102 can be captured from multiple angles. Additionally or alternatively, the multiple cameras 108 may be arranged such that individual cameras or a group of cameras can be positioned to capture images of a specific portion of the semiconductor processing chamber 102.

[0064] In one embodiment, the one or more cameras 108 are located inside the semiconductor processing chamber 102. The one or more cameras 108 may be located at selected positions within the semiconductor processing chamber 102 to capture images from various angles and positions. A single camera or a group of cameras 108 can be positioned to capture images of a specific area of the semiconductor processing chamber 102.

[0065] In one embodiment, the one or more cameras 108 are configured to be able to identify the location of plasma discharges within the semiconductor processing chamber 102. The video stream captured by the one or more cameras 108 enables the control system 110 to determine the exact location of arcs and other types of plasma discharge events within the semiconductor processing chamber 102.

[0066] In one embodiment, camera 108 includes: multiple types of cameras, each configured to capture images in a specific spectrum. For example, the first type of camera 108 may primarily capture light in the visible spectrum. The second type of camera 108 may primarily capture light in the infrared spectrum. The third type of camera 108 may primarily capture light in the ultraviolet spectrum. The various types of cameras may capture overlapping spectra of light. Camera 108 may include multiple cameras of each type.

[0067] In one embodiment, control system 110 is communicatively coupled to camera 108. Camera 108 captures a stream of images and provides image data to control system 110. The image data may correspond to a digital representation of the stream of images captured by camera 108. As will be described in more detail below, camera 108 may be coupled to or may include filters and signal processing circuitry that may format or otherwise process the image data before sending the image data to control system 110.

[0068] In one embodiment, control system 110 receives an image or image data from camera 108 or from an intermediate signal processor or transmitter. Control system 110 processes the image and determines based on the image whether a plasma discharge has occurred within semiconductor processing chamber 102. Thus, control system 110 may determine whether a plasma discharge has occurred within semiconductor processing chamber 102 by analyzing the images provided by the one or more cameras 108.

[0069] Control system 110 may receive images wirelessly from camera 108. Camera 108 may be coupled to control system 110 via one or more wireless connection protocols, the one or more wireless connection protocols including but not limited to Bluetooth, wireless fidelity (Wi-Fi), or ZigBee protocol. Without departing from the scope of the present disclosure, other wireless communication protocols may be utilized. Thus, semiconductor processing system 100 may include a wireless transceiver or transmitter coupled to camera 108 located around or within semiconductor processing chamber 102. The wireless transceiver or transmitter may transmit the images to control system 110.

[0070] In one embodiment, the semiconductor processing system 100 includes a power source coupled to the camera 108 and, if present, a wireless communication system coupled to the camera 108. The power source can include a battery or a wired connection to a stable power source. In one embodiment, the semiconductor processing system 100 includes an energy harvesting device for recharging the battery or for otherwise powering the camera 108 and the wireless communication system. The energy harvesting device can harvest energy from heat, light, acoustic vibrations, or various types of motion.

[0071] In one embodiment, the camera 108 is connected to the control system 110 by a wired connection. Thus, the camera 108 can communicate with the control system 110 via the wired connection that transmits to the control system 110.

[0072] In one embodiment, when the control system 110 receives an image from the camera 108, the control system 110 can filter the image. Thus, the control system 110 can include one or more filters. The image is transmitted to the filters to remove optical characteristics that do not contribute to identifying plasma discharges. The filters can also remove certain types of images. After the image has passed through the one or more filters, the image is ready for further processing and analysis by the control system 110.

[0073] In one embodiment, the image can be passed through a filter before being transmitted to the control system 110. Thus, the camera 108 can be coupled to one or more electrical filters or other circuitry to remove unwanted optical artifacts, enhance specific optical characteristics, or reduce noise before transmitting the image to the control system 110. This enables the control system 110 to more easily identify unwanted plasma discharges based on the image.

[0074] In one embodiment, the control system 110 includes an analysis model. The analysis model is trained through a machine learning process to identify arcs within the semiconductor processing chamber 102. The analysis model can analyze the image or image-based data to identify arcs within the semiconductor processing chamber 102.

[0075] In one embodiment, the machine learning process is a supervised machine learning process. A supervised machine learning process is typically distinguished from an unsupervised machine learning process by using labels during the learning process. For example, a classifier model is trained to classify data items. In an instance of system 100, the classifier model can be trained to classify images from a camera into those that include an electric arc or those that do not include an electric arc. The machine learning process trains the classifier model to correctly classify images from the camera. The machine learning process utilizes a training set of images that include or do not include an electric arc. The images are labeled to identify which images include an electric arc and which images do not include an electric arc. During the machine learning process, the classifier model is trained to classify the images in a manner that matches the labels. In other words, the machine learning process trains the classifier model to correctly classify each image as including or not including an electric arc. Thus, the supervised machine learning process trains the classifier analysis model to classify data items in a manner that matches the labels. In this way, the machine learning process is a supervised process.

[0076] The supervised machine learning process for controlling the analysis model of system 110 can include generating training set data. Generating the training set data can include acquiring images or a stream of images from known plasma discharge events. Generating the training set data can include acquiring images known not to include plasma discharge events. The training set data can be labeled to identify images representative of electric arcs and images not representative of plasma discharge events.

[0077] Known electric arc events in the training set data can include: various types of plasma discharge events, including arcs, corona discharges, or sparks between various objects or locations within the clean environment 102. Known plasma discharge events can also include: plasma discharge events that contact the semiconductor wafer 104 or devices that hold or support the semiconductor wafer 104.

[0078] The supervised machine learning process can include passing the training set data through the analysis model. The analysis model classifies each video signal or set of video signals from the training set into a plasma discharge event or not a plasma discharge event. The classification is then compared to the label. The parameters or weights of one or more classification functions of the analysis model are adjusted and the images of the training set are passed through the analysis model again. The classification is then compared to the label and the function is adjusted accordingly. This process is repeated iteratively until the analysis model can reliably classify the images in a manner that matches the labels.

[0079] In one embodiment, the image is converted into a vector form before being transmitted to the analysis model. Accordingly, the analysis model analyzes the vectorized representation of the image. Thus, analyzing the image using the analysis model may include analyzing the vectorized version of the image or other types of representations of the image.

[0080] In one embodiment, the analysis model includes a classifier model, a multi-class classifier model, or a binary classifier model. The analysis model may include a neural network-based classifier model. The classifier model may include a logistic regression model, a Naive Bayes model, a stochastic gradient descent model, a K-nearest neighbors model, a decision tree model, a random forest model, or other types of classifier models. Without departing from the scope of the present disclosure, the analysis model may also include other types of classifier models or models different from classifier models.

[0081] In one embodiment, the analysis model includes an unsupervised machine learning model. An unsupervised machine learning process generally does not include labeled data. Accordingly, the training set for the unsupervised learning process includes data items for which no labels are available. In this case, the training set may include many images of the interior of the semiconductor processing chamber 102. The training set images include images with arcs and images without arcs. However, unlike a supervised machine learning process, the training set images do not include labels identifying which images include arcs and which images do not include arcs. In this case, the unsupervised machine learning process learns to group images that are similar to each other. These groups may subsequently be identified as corresponding to arcs or no arcs. Thus, the unsupervised machine learning process may train the analysis model to identify patterns and similarities between data items. This may be used to cluster the data items.

[0082] The analysis model of the control system 110 may be trained using an unsupervised machine learning process to identify patterns in images indicative of arcs within the semiconductor processing chamber 102. After training, the analysis model may be used to group images that are similar to each other. This may be used to cluster video images into arc images and non-arc images.

[0083] When the control system 110 receives an image, the image may be filtered or formatted and then provided to the analysis model. The analysis model analyzes the image and determines whether a portion of the video signal represents an arc within the semiconductor processing chamber 102. The analysis model outputs an indication of arc or no arc for each video signal sample passed through the analysis model.

[0084] The control system 110 can utilize a pattern recognition system different from the machine learning analysis model to detect arcs based on images. In one embodiment, an expert encodes a rule-based analysis model with rules that define how data items should be analyzed and classified. Thus, the rule-based analysis model can be encoded to classify data items based on predetermined rules, rather than training the analysis model through a machine learning process. The analysis model of the control system 110 can utilize a rule-based system to recognize arc sounds. The control system 110 can utilize a rule-based analysis system or other types of analysis systems to recognize time-domain or frequency-domain patterns or characteristics indicating an arc within the clean environment 102. For example, rule-based analysis can include automatically reducing the voltage between the top electrode and the bottom electrode in response to detecting an arc, automatically adjusting the pressure of the semiconductor process chamber 102 in response to detecting an arc, or automatically stopping the semiconductor process in response to detecting an arc.

[0085] In one embodiment, the control system 110 generates a three-dimensional (3D) model of the plasma discharge within the semiconductor process chamber 102. Specifically, the control system 110 can receive video images from multiple cameras and can construct a 3D model of the plasma discharge within the semiconductor process chamber. Multiple video streams from multiple positions / angles enable the control system 110 to generate the 3D model. The 3D model can be based on optical characteristics, thermal characteristics (through infrared imaging), or a combination of optical and thermal characteristics. The analysis model of the control system 110 can analyze the 3D model and can determine whether there is an abnormal plasma discharge and the location of the plasma discharge based on the 3D model. The analysis model can perform a pattern recognition process on the 3D model.

[0086] In one embodiment, when the control system 110 recognizes a plasma discharge within the semiconductor process chamber 102, the control system 110 can take various real-time actions in response to the plasma discharge. The control system 110 can take actions to reduce or otherwise manage the plasma discharge within the semiconductor process chamber 102 in real time.

[0087] In one embodiment, the control system 110 can determine whether the plasma discharge is at a level dangerous to the semiconductor wafer 104. If the plasma discharge is at a level not yet dangerous to the semiconductor wafer 104, the control system 110 can avoid taking any corrective actions. As an alternative or in addition, the control system 110 can output a notification indicating a non-dangerous arc level within the semiconductor process chamber 102. The notification can be received and viewed by personnel monitoring the semiconductor process within the clean environment 102.

[0088] In one embodiment, the control system 110 may determine that the level of plasma discharge is dangerous. In such a case, the control system 110 may take steps to reduce or avoid further plasma discharge within the semiconductor processing chamber 102. The control system 110 may be communicatively coupled to the semiconductor processing apparatus 106 or a device associated with the semiconductor processing apparatus 106. The control system 110 may control the semiconductor processing apparatus 106 to adjust parameters associated with the semiconductor process to reduce or avoid further arcing within the semiconductor processing chamber 102.

[0089] In one example, the semiconductor process is a plasma-based process (e.g., plasma etching) or plasma enhanced chemical vapor deposition or plasma enhanced physical vapor deposition. The semiconductor processing apparatus 106 may include devices that perform or facilitate plasma-based processes. The control system 110 may cause the semiconductor processing apparatus 106 to adjust parameters of the plasma-based process. For example, plasma-based processes often apply high voltages within the semiconductor processing chamber 102 or to gases entering the clean environment 102. The control system 110 may cause a reduction in these voltages to reduce or eliminate dangerous arcing within the semiconductor processing chamber 102. As an alternative, the control system 110 may adjust other parameters of the plasma-based semiconductor process to reduce or eliminate dangerous arcing within the semiconductor processing chamber 102.

[0090] In one example, arcing may occur between the walls of the semiconductor processing chamber 102 and other devices or materials within the semiconductor processing chamber 102. The arcing may be due to the accumulation of dielectric material on the walls or devices within the semiconductor processing chamber 102. The control system 110 may cause the automation system to clean or otherwise remove dielectric material from portions of the clean environment 102 associated with the plasma discharge. This may help reduce arcing.

[0091] In one example, arcing may occur partially based on the temperature or deposition rate during various semiconductor processes. The control system 110 may reduce the temperature within the clean environment 102 or adjust the deposition rate in response to detecting arcing.

[0092] In one example, arcing may occur partially based on the concentration of various types of gases within the semiconductor processing chamber 102 during the semiconductor process. The control system 110 may cause the semiconductor processing apparatus 106 to adjust the flow rate of one or more gases within the semiconductor processing chamber 102 to reduce or avoid dangerous arcing.

[0093] In one embodiment, the control system 110 may cause the semiconductor processing apparatus 106 to completely stop the semiconductor process in response to detecting an abnormal, unwanted, or dangerous plasma discharge within the semiconductor process chamber 102. To avoid severe damage to the semiconductor wafer 104, in some cases, the control system 110 may determine that the best course of action is to completely stop the semiconductor process until other adjustments can be made to reduce or prevent the abnormal plasma discharge within the semiconductor process chamber 102.

[0094] In one embodiment, the control system 110 may include portions external to the semiconductor process chamber 102, portions within the semiconductor process chamber 102, and / or portions executed within the cloud. Thus, the control system 110 may have various processing, memory, and data transfer resources distributed across multiple locations. The control system 110 may also include virtual memory, processing, and data transfer resources within the cloud.

[0095] Figure 2 is an illustrative diagram of a semiconductor processing system 100 according to an embodiment. The semiconductor processing system 100 includes a semiconductor process chamber 102 that includes a top electrode 114, a bottom electrode 112, and a wafer 104 positioned on the bottom electrode 112. One or more cameras 108 are located within or external to the semiconductor process chamber 102. A radio frequency (RF) power supply 116 is coupled to the top electrode 114 and the bottom electrode 112. The control system 110 is coupled to the camera 108 and the RF power supply 116. The semiconductor processing system 100 detects an abnormal or unwanted plasma discharge within the semiconductor process chamber 102. The bottom electrode 112, the top electrode 114, and the RF power supply 116 are Figure 1 examples of semiconductor processing equipment.

[0096] In one embodiment, the cameras 108 are located at different positions surrounding the semiconductor process chamber 102. The cameras 108 may be located above the semiconductor wafer 104 and below the bottom electrode 112. The bottom electrode 112 may also be a chuck configured to hold the wafer 104.

[0097] In one embodiment, the RF power supply 116 drives the top electrode 114 and the bottom electrode 112 to generate plasma in the plasma region 120 by applying an alternating current (AC) voltage within the RF range between the top electrode 114 and the bottom electrode 112. The plasma may be generated from a gas within the semiconductor process chamber 102. The gas may include argon, oxygen, nitrogen, or other gases.

[0098] A glow discharge is associated with the plasma region 120. The optical and thermal characteristics of the glow discharge can depend on the type of gas and the type of semiconductor process associated with the plasma region 120. For example, etching processes, implantation processes, deposition processes, and other types of plasma-assisted semiconductor processes generate plasma, and specifically, optical and thermal characteristics. The glow discharge can also depend on various process parameters such as direct current (DC) voltage, radio frequency power, pressure, temperature, etc. An abnormal discharge can be located by comparing two or more spatial positions of an image. The video characteristics of the glow discharge depend on processing the wafer material into a pattern structure, pattern density, and other factors.

[0099] In Figure 2 the example, the plasma generation process results in an anode glow region 122 adjacent to the top electrode 114. In this example, the top electrode 114 is the anode. The plasma generation process also results in a cathode glow region 124 adjacent to the bottom electrode cathode. In this example, the bottom electrode 112 is the cathode. The main plasma region 120 is located between the anode glow region 122 and the cathode glow region 124.

[0100] In one embodiment, abnormal or undesired plasma discharge events can occur during plasma generation. For example, an arc event 126 may occur between the top electrodes 114 in the wafer 104. Such an arc event can cause severe damage to a portion of the wafer or to the entire wafer 104. Another abnormal and undesired plasma discharge event that may occur is Figure 2 the corona discharge event 127 shown in

[0101] The one or more cameras 108 can be positioned to capture video of the interior environment of the semiconductor process chamber 102. The video image or the image data generated from the video image is provided to the control system 110. The control system 110 analyzes the video image to detect the arc event 126 and the corona discharge event 127. The control system 110 can identify the exact locations of the arc event 126 and the corona discharge event 127. The control system 110 can then respond in real time to adjust the parameters of the semiconductor process, thereby reducing or eliminating the undesired plasma discharge events.

[0102] Figure 3FIG. is an illustrative view of a portion of a semiconductor processing system 100 according to one embodiment. The semiconductor processing system 100 includes a semiconductor processing chamber 102 and a plurality of cameras 108 located outside the semiconductor processing chamber 102. The semiconductor processing chamber 102 may include a plurality of holes 118 that allow light to pass from the interior of the semiconductor processing chamber 102 to the cameras 108. These holes may correspond to transparent portions of the semiconductor processing chamber 102. Alternatively, the semiconductor processing chamber wall may be completely transparent.

[0103] In one embodiment, the cameras 108 are positioned to take images from multiple angles. The positioning of the cameras 108 may also enable each camera 108 to focus on a specific area within the semiconductor processing chamber 102. In one embodiment, Figure 2 each camera 108 shown in may correspond to a set of cameras. Each set of cameras may include cameras sensitive to the spectra of various lights. For example, each set of cameras may include one or more cameras sensitive to infrared light. Each set of cameras may include one or more cameras sensitive to visible light. Each set of cameras may include one or more cameras sensitive to ultraviolet light. Additionally or alternatively, each set of cameras 108 may include cameras facing different directions.

[0104] In one embodiment, a plasma discharge event occurs at a specific area of the semiconductor wafer 104. Each of the cameras 108 receives the light generated by the arc event 126. Each of the cameras 108 takes an image based on the light. The cameras 108 may transmit the images to a control system 110 ( Figure 3 not shown in). The control system 110 may detect the plasma discharge event based on the images. The control system 110 may also identify the location of the plasma discharge event based on the images and the known positions of the cameras 108.

[0105] Referring to Figure 2 and Figure 3 In the example of, in Figure 2 , the arc event 126 has contacted a specific portion of the semiconductor wafer 104. The control system 110 may identify the location of the arc event 126 on the semiconductor wafer 104. Since the analysis model can be trained to identify the optical characteristics of the arc contacting the semiconductor wafer, the control system can determine that the arc event 126 contacts the semiconductor wafer 104. The control system can determine the location of the arc event by analyzing the images from each of the multiple cameras with known positions. The location of the arc event 126 will correspond to a specific portion of the semiconductor wafer 104. The specific location corresponds to one or more integrated circuit dies to be separated from the semiconductor wafer 104. The control system 110 may label the individual integrated circuits from this area of the semiconductor wafer 104 as potentially damaged. These integrated circuit dies may be discarded after dicing.

[0106] In one embodiment, the control system 110 may determine that an arc event 126 is likely to cause significant damage to the semiconductor wafer 104 based on the characteristics of the image. The control system 110 may output an alert that a technician should inspect the semiconductor wafer 104. As an alternative, the control system may determine that the semiconductor wafer 104 should be discarded.

[0107] In one embodiment, the light emitted by an arc event varies according to various factors associated with the arc event. For example, during a thin film growth or deposition process associated with the semiconductor wafer 104, the light associated with the arc event may vary based on the type of gas present within the semiconductor process chamber 102. The arc optical pattern may vary with process parameters such as the voltage present within the semiconductor process chamber 102 or the vacuum level within the semiconductor process chamber 102. The arc video pattern may vary with the type of semiconductor process, which includes wet etching, dry etching, physical vapor deposition, chemical vapor deposition, or other types of processes. The arc video pattern may vary based on the type of material that has been damaged (e.g., an oxide layer, a photoresist layer, a metal layer, a semiconductor layer, or other types of materials associated with the semiconductor wafer 104). The arc video pattern may vary based on the type of damage (e.g., the size of the damaged area, the shape of the damaged area, or other factors associated with the damage outcome). The arc video pattern may vary based on the occurrence of fragmentation of the semiconductor wafer 104 or other structures or devices located within the semiconductor process chamber 102.

[0108] The control system 110 may be trained to recognize the optical patterns associated with all of the various parameters of an arc event. The control system 110 may perform diagnostics and may adjust the parameters of the semiconductor process based on the specific optical and thermal patterns associated with various types of arc events.

[0109] In one embodiment, the control system 110 may sense whether an arc event has contacted the wafer support. The control system 110 may sense the location on the wafer support that has been affected by the arc event. The location may be detected based on the image and the known location of the camera 108. The control system 110 may detect the arc and the location of the arc at other locations and relative to other materials or devices located within the semiconductor process chamber 102.

[0110] Although not shown in Figure 3 , each camera 108 or group of cameras may be coupled to additional circuitry that includes wired or wireless communication devices, a power source, an energy harvesting device, filters, signal processors, or other electronic circuitry that may assist in detecting an arc within the semiconductor process chamber 102.

[0111] In one embodiment, the semiconductor processing system 100 may include an optical system 130. The optical system 130 may include various optical elements for directing, focusing, or conditioning light from the interior of the semiconductor processing chamber 102. The optical system 130 may direct light from the interior of the semiconductor processing chamber 102 to the camera 108. The optical system 130 may include lenses, mirrors, waveguides, filters, polarizers, or other optical components configured to direct, focus, or condition light before it reaches the camera 108.

[0112] As described herein, the optical characteristics of a current discharge event may include thermal characteristics. Electromagnetic radiation in the infrared spectrum is often highly indicative of thermal characteristics. Accordingly, the camera 108 is configured to capture infrared images. The captured images represent both the optical and thermal properties of the plasma discharge event.

[0113] In one embodiment, the camera 108 may be directly coupled to the wall of the semiconductor processing chamber 102. In such a case, the camera 108 may be located in or on the aperture 118. In one embodiment, the camera 108 may be partially or entirely located within the semiconductor processing chamber.

[0114] As previously described, the array of cameras 108 enables the control system 110 to generate a 3D model of the plasma discharge within the semiconductor processing chamber 102. The control system 110 may detect an abnormal plasma discharge based on the 3D model.

[0115] Figure 4 FIG. 140 illustrates a graph of the relative sensitivity percentages of various types of cameras in each different portion of the electromagnetic spectrum, according to one embodiment. The camera 108 may include an ultraviolet-sensitive camera, a standard camera that is primarily sensitive to visible light, and an infrared-sensitive camera that is primarily sensitive to infrared light. The curves shown in FIG. 140 illustrate the respective sensitivities of the various types of cameras. Specifically, in the Figure 4 example, the ultraviolet-sensitive camera is sensitive to light having wavelengths between 200 nanometers and 600 nanometers. The standard camera is sensitive to light having wavelengths between 400 nanometers and 700 nanometers. The infrared-sensitive camera is sensitive to light having wavelengths between 600 nanometers and 1200 nanometers. Thus, this set of cameras together provides good sensitivity to light having wavelengths between 200 nanometers and 1200 nanometers. Without departing from the scope of the present disclosure, cameras having sensitivities different from those Figure 4 shown and described above may be utilized.

[0116] Figure 5FIG. 0 is a block diagram of a video signal output circuit system 148 of a semiconductor processing system 100 according to an embodiment. According to one embodiment, the video signal output circuit system 148 includes one or more cameras 108, a filter 141, a signal processor 142, a communication system 144, and a power supply 146. The video signal output circuit 148 may correspond to a circuit system package located within the semiconductor processing chamber 102.

[0117] Referring Figures 1 to 3 and Figure 5 FIGS. 1 and 2, the semiconductor processing system 100 includes a plurality of cameras 108 located around or within the semiconductor processing chamber 102. In one embodiment, the semiconductor processing system 100 may include a corresponding video signal output circuit system 148 at the location of each camera 108 or group of cameras 108. Thus, each camera 108 or group of cameras 108 is part of a corresponding video signal output circuit system 148.

[0118] Each camera or group of cameras captures an image, generates an image, and transmits the image to the filter 141. The filter 141 filters the image for selected optical characteristics or noise and transmits the filtered image to the signal processor 142. The signal processor 142 processes the image and provides the image to the communication system 144. The communication system 144 outputs the image to the control system 110. The communication system 144 may include a wireless communication system or a wired communication system. The power supply 146 powers the video signal output circuit system 148. The power supply 146 may include an energy harvesting device. Although not shown in FIGS. 3-5, portions of the control system 110 may be included in the video signal output circuit system 148. Without departing from the scope of the present disclosure, the video signal output circuit system 148 may include other components or configurations. Figure 5 FIGS. 3-5

[0119] Figure 6 FIG. 6 is a block diagram of a control system 110 of a semiconductor processing system 100 according to an embodiment. The control system 110 includes a communication system 150, a filter 152, a signal processor 154, an analysis model 156, and a process controller 158.

[0120] The communication system 150 communicates with the camera 108 or with the video signal output circuit system 148. The communication system 150 may include a wireless communication system that communicates wirelessly with the video signal output circuit system 148. The communication system 150 may include a wired communication system that communicates with the video signal output circuit system 148 via a wired connection. The communication system 150 receives the image from the camera 108.

[0121] The communication system 150 provides an image to the filter 152. The filter 152 can filter out optical characteristics or background noise from the image. The control system 110 can include multiple filters 152.

[0122] The signal processor 154 receives the image from the filter 152. The signal processor 154 processes the image. The signal processor 154 can place the image in a format that can be utilized by the analysis model 156.

[0123] The analysis model 156 analyzes the image and determines whether the image indicates that an arc has occurred within the semiconductor processing chamber 102. The analysis model 126 can be trained through a machine learning process, as described previously with respect to Figure 1 that. The machine learning process can train the analysis model 126 to recognize various types of plasma discharges within the semiconductor processing chamber 102 based on the image.

[0124] The process controller 158 communicates with the semiconductor processing apparatus 106 and controls the semiconductor processing apparatus 106. For example, if the analysis model 156 indicates that an unwanted plasma discharge exists within the semiconductor processing chamber 102, the process controller 158 can cause the semiconductor processing apparatus 106 to adjust the semiconductor process in real time. The process controller 158 can also cause the semiconductor processing apparatus 106 to stop the semiconductor process in response to detecting an arc within the semiconductor processing chamber 102.

[0125] The control system 110 can include components and systems located within the semiconductor processing chamber 102 and components located outside the semiconductor processing chamber 102. Those skilled in the art will recognize, in accordance with this disclosure, that the control system 110 can include other components and systems, or other configurations of components and systems, without departing from the scope of this disclosure.

[0126] Figure 7 is a flowchart of a method 700 for detecting an arc within a semiconductor processing chamber according to an embodiment. At step 702, the method 700 includes performing a semiconductor process on a semiconductor wafer within the semiconductor processing chamber. An example of a semiconductor wafer is Figure 1 the semiconductor wafer 104. An example of a semiconductor processing chamber is Figure 1 the semiconductor processing chamber 102. At step 704, the method 700 includes capturing a video stream during the semiconductor process by one or more cameras. An example of one or more cameras is Figure 1 the camera 108. At step 706, the method includes detecting an arc within the semiconductor processing chamber by processing the video stream by the control system. An example of a control system is Figure 1control system 110. At step 708, method 700 includes adjusting a semiconductor process within a semiconductor process chamber in response to detecting a plasma discharge within the semiconductor process chamber.

[0127] Figure 8 is a flowchart of a method 800 for detecting a plasma discharge event within a semiconductor process chamber according to an embodiment. At step 802, method 800 includes taking an image of a semiconductor process chamber by one or more cameras. An example of one or more cameras is Figure 1 camera 108. An example of a semiconductor process chamber is Figure 1 semiconductor process chamber 102. At step 804, method 800 includes processing the image by a control system. An example of a control system is Figure 1 control system 110. At step 806, method 800 includes detecting a plasma discharge within the semiconductor process chamber by the control system based on the image.

[0128] In one embodiment, a method for identifying and addressing a plasma discharge includes: taking an image of a semiconductor process chamber by one or more cameras; processing the image by a control system; and detecting a plasma discharge within the semiconductor process chamber by the control system based on the image.

[0129] In some embodiments, capturing an image includes: capturing an image in the visible spectrum; capturing an image in the infrared spectrum; or capturing an image in the ultraviolet spectrum. In some embodiments, capturing an image includes capturing an infrared image, wherein processing the image includes generating a thermal distribution based on the infrared image. In some embodiments, it further includes detecting the plasma discharge based on the thermal distribution. In some embodiments, detecting the plasma discharge includes detecting an arc or a corona discharge. In some embodiments, detecting an arc includes determining, by the control system, characteristics of the image corresponding to an arc or a corona discharge. In some embodiments, capturing an image includes capturing an image by multiple types of cameras. In some embodiments, it further includes generating a three-dimensional model of the interior of the semiconductor process chamber based on the image; and detecting the plasma discharge within the semiconductor process chamber based on the three-dimensional model. In some embodiments, it further includes determining the location of the plasma discharge within the semiconductor process chamber based on the image and the position of the camera. In some embodiments, it further includes adjusting, by the control system, a semiconductor process within the control system in response to detecting the plasma discharge. In some embodiments, it further includes training an analysis model of the control system through a machine learning process to detect the plasma discharge within the semiconductor process chamber; and detecting the plasma discharge by analyzing the image using the analysis model. In some embodiments, capturing an image includes capturing a video stream.

[0130] In one embodiment, a system for identifying and addressing plasma discharges includes: a semiconductor process chamber; and one or more cameras positioned to capture images of the semiconductor process chamber. The system includes: a control system communicatively coupled to the one or more cameras and configured to detect a plasma discharge within the semiconductor process chamber based on the image and to adjust a semiconductor process in response to detecting the plasma discharge.

[0131] In some embodiments, the control system includes an analysis model trained through a machine learning process to identify plasma discharges based on an image. In some embodiments, the one or more cameras include: one or more cameras configured to capture infrared images; one or more cameras configured to capture visible light images; or one or more cameras configured to capture ultraviolet images. In some embodiments, it further includes a wireless communication system that communicatively couples the cameras to the control system. In some embodiments, it further includes imaging optics configured to transfer light from the semiconductor process chamber to the one or more cameras.

[0132] In one embodiment, a method for identifying and addressing plasma discharges includes: performing a semiconductor process on a semiconductor wafer in a semiconductor process chamber; capturing a video stream during the semiconductor process by one or more cameras; and detecting an arc in the semiconductor process chamber by processing the video stream by a control system. The method includes adjusting the semiconductor process in the semiconductor process chamber in response to detecting an arc in the semiconductor process chamber.

[0133] In some embodiments, adjusting the semiconductor process includes one or more of the following: adjusting the flow rate of one or more gases entering the semiconductor process chamber; adjusting the pressure in the semiconductor process chamber; adjusting the voltage or electric field applied in the semiconductor process chamber; and stopping the semiconductor process. In some embodiments, it further includes determining by the control system whether the semiconductor wafer is damaged due to the plasma discharge.

[0134] Embodiments of the present disclosure utilize plasma detection technology to improve semiconductor processes. Capturing a video stream of the semiconductor process chamber, analyzing the video stream by a control system, and identifying abnormal plasma discharges provide many benefits. For example, the control system can adjust the parameters of the semiconductor process to reduce or eliminate unwanted plasma discharges in real time. This results in better uniformity in the semiconductor wafer and its integrated circuits. Additionally, since the wafer is not damaged or scrapped due to abnormal plasma discharges, the process yield is greatly improved.

[0135] The various embodiments described above can be combined to provide further embodiments. If desired, various aspects of the embodiments can be modified to incorporate concepts from various patents, applications, and publications to provide further embodiments.

[0136] Based on the above detailed description, these and other changes can be made to the embodiments. Generally, in the above claims, the terms used should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be construed to include all possible embodiments and the entire scope of equivalent structures to which this claim is entitled. Therefore, the claims are not limited by the present disclosure.

Claims

1. A method for identifying and addressing plasma discharges, comprising: Performing a plasma-assisted semiconductor process on a wafer in a semiconductor process chamber including a top electrode and a wafer located on a bottom electrode, wherein the plasma-assisted semiconductor process generates an anode glow region adjacent to the top electrode, a cathode glow region adjacent to the bottom electrode, and a plasma region between the anode glow region and the cathode glow region; During the plasma-assisted semiconductor process, using multiple sets of cameras located around the semiconductor process chamber to capture images of the plasma in the semiconductor process chamber from different angles and positions, each set of cameras including an infrared camera, a visible light camera, and an ultraviolet camera; Processing the images by a control system; Generating a three-dimensional model of the plasma in the semiconductor process chamber based on the images; Detecting an arc in the semiconductor process chamber based on the three-dimensional model; Based on the three-dimensional model, during the plasma-assisted semiconductor process, using the control system to detect an arc passing through the anode glow region, the plasma region, and the cathode glow region between the top electrode and the wafer in the semiconductor process chamber; Determining the position of the arc on the wafer in the semiconductor process chamber based on the images and the angles and positions of the multiple sets of cameras; And In response to detecting the arc, using the control system to adjust the plasma-assisted semiconductor process during the plasma-assisted semiconductor process.

2. The method according to claim 1, wherein capturing the images includes: Capturing an image in the visible spectrum; Capturing an image in the infrared spectrum; Or Capturing an image in the ultraviolet spectrum.

3. The method according to claim 1, wherein capturing the images includes capturing infrared images, and wherein processing the images includes generating a thermal distribution based on the infrared images.

4. The method according to claim 3 further comprises: Detecting the arc based on the thermal distribution.

5. The method according to claim 1, wherein detecting the arc includes the control system determining characteristics of the images corresponding to the arc.

6. The method according to claim 1, further comprising: Training an analysis model of the control system through a machine learning process to detect an arc in the semiconductor process chamber; And Detecting the arc by analyzing the images using the analysis model.

7. A method for identifying and addressing plasma discharges, comprising: Performing a plasma-assisted semiconductor process on a wafer in a semiconductor process chamber including a top electrode and a wafer located on a bottom electrode, wherein the plasma-assisted semiconductor process generates an anode glow region adjacent to the top electrode, a cathode glow region adjacent to the bottom electrode, and a plasma region between the anode glow region and the cathode glow region; When performing the plasma-assisted semiconductor process, images of the plasma in the semiconductor process chamber are captured from different angles and positions using multiple sets of cameras located around the semiconductor process chamber, and each set of cameras includes an infrared camera, a visible light camera, and an ultraviolet camera; During the plasma-assisted semiconductor process, a three-dimensional model of the plasma in the semiconductor process chamber is generated by processing the video stream using a control system to detect a plasma arc in the semiconductor process chamber, wherein detecting the plasma arc includes detecting an arc between the top electrode and the wafer through the anode glow region, the plasma region, and the cathode glow region; Determine the position of the arc on the wafer in the semiconductor process chamber based on the images, angles, and positions of the multiple sets of cameras; And In response to detecting the arc in the semiconductor process chamber, adjust the plasma-assisted semiconductor process in the semiconductor process chamber during the plasma-assisted semiconductor process.

8. The method according to claim 7, wherein adjusting the plasma-assisted semiconductor process includes one or more of the following: Adjust the flow rate of one or more gases entering the semiconductor process chamber; Adjust the pressure in the semiconductor process chamber; Adjust the voltage or electric field applied in the semiconductor process chamber; And Stop the plasma-assisted semiconductor process.

9. The method according to claim 7, further comprising: The control system determines whether the wafer is damaged due to the arc.

10. A method for identifying and addressing plasma discharges, comprising: Performing a plasma-assisted semiconductor process on the wafer in a semiconductor process chamber including a top electrode and a wafer located on a bottom electrode, wherein the plasma-assisted semiconductor process generates an anode glow region adjacent to the top electrode, a cathode glow region adjacent to the bottom electrode, and a plasma region between the anode glow region and the cathode glow region; Using multiple sets of cameras located around the semiconductor process chamber to capture images of the plasma in the semiconductor process chamber from different angles and positions, and each set of cameras includes an infrared camera, a visible light camera, and an ultraviolet camera; Generate a three-dimensional model of the plasma in the semiconductor process chamber based on the images; During the plasma-assisted semiconductor process, a control system communicatively coupled to one or more cameras detects an arc passing through the anode glow region, the plasma region, and the cathode glow region between the top electrode and the wafer in the semiconductor process chamber based on the three-dimensional model; Determine the position of the arc on the wafer in the semiconductor process chamber based on the images and the angles and positions of the multiple sets of cameras; And In response to detecting the arc in the semiconductor process chamber, adjust the plasma-assisted semiconductor process in the semiconductor process chamber during the plasma-assisted semiconductor process.

11. The method according to claim 10, further comprising: The analysis model of the control system is trained by a machine learning process to identify the arc based on the images.

12. The method according to claim 10 further comprises wirelessly transmitting the image to the control system.

13. A system for identifying and addressing plasma discharges, comprising: A semiconductor processing chamber, comprising A top electrode, and A bottom electrode; Multiple sets of cameras located around the semiconductor processing chamber and configured to capture a plurality of images of the plasma inside the semiconductor processing chamber from different angles and positions, each set of cameras including an infrared camera, a visible light camera, and a ultraviolet camera; And A control system communicatively coupled to the multiple sets of cameras, wherein the control system is configured to: Control a plasma-assisted semiconductor process inside the semiconductor processing chamber, wherein the plasma-assisted semiconductor process generates an anode glow region adjacent to the top electrode, a cathode glow region adjacent to the bottom electrode, and a plasma region between the anode glow region and the cathode glow region; Generate a three-dimensional model of the plasma inside the semiconductor processing chamber based on the plurality of images; Detect an arc passing through the anode glow region, the plasma region, and the cathode glow region between the top electrode and the wafer during the plasma-assisted semiconductor process based on the three-dimensional model; Determine the position of the arc on the wafer inside the semiconductor processing chamber based on the images and the positions of the multiple sets of cameras; Adjust the plasma-assisted semiconductor process during the plasma-assisted semiconductor process in response to detecting the arc.

14. The system according to claim 13, wherein the plurality of images include: Images in the visible spectrum; Images in the infrared spectrum; Or Images in the ultraviolet spectrum.

15. The system according to claim 13, wherein the plurality of images include infrared images, and wherein the control system is configured to generate a heat distribution based on the infrared images.

16. The system according to claim 15, wherein the control system is configured to detect the arc based on the heat distribution.

17. The system according to claim 13, wherein the control system is configured to detect characteristics of the plurality of images corresponding to the arc.

18. The system according to claim 13, wherein the control system is configured to detect the arc by analyzing the images using an analysis model trained through a machine learning process.

19. A system for identifying and addressing plasma discharges, comprising: A semiconductor processing chamber, comprising A top electrode, and A bottom electrode; Multiple sets of cameras located around the semiconductor processing chamber to capture a plurality of images of the plasma inside the semiconductor processing chamber from different angles and positions, each set of cameras including an infrared camera, a visible light camera, and a ultraviolet camera; And A control system communicatively coupled to the multiple sets of cameras and configured to: Control a plasma-assisted thin film deposition process within the semiconductor process chamber, wherein the plasma-assisted thin film deposition process generates an anode glow region adjacent to the top electrode, a cathode glow region adjacent to the bottom electrode, and a plasma region between the anode glow region and the cathode glow region; Generate a three-dimensional model of the plasma within the semiconductor process chamber based on the plurality of images; Based on the three-dimensional model, during the plasma-assisted thin film deposition process, use an analysis model trained through a machine learning process to detect an arc passing through the anode glow region, the plasma region, and the cathode glow region between the top electrode and the wafer; Determine the location of the arc on the wafer within the semiconductor process chamber based on the images and the positions of the plurality of camera sets; Adjust the plasma-assisted thin film deposition process during the plasma-assisted thin film deposition process in response to detecting the arc.

20. The system according to claim 19, wherein the plurality of images include: Infrared spectroscopic images; Visible spectroscopic images; Or Ultraviolet spectroscopic images.

21. The system according to claim 19, further comprising a wireless communication system to communicatively couple the plurality of camera sets to the control system.

22. The system according to claim 19, further comprising imaging optics configured to transfer light from the semiconductor process chamber to the plurality of camera sets.

23. A system for identifying and addressing plasma discharges, comprising: A semiconductor process chamber, including A top electrode, and A bottom electrode; A plurality of output circuits, each of the output circuits including: A camera set, wherein each of the infrared camera, visible light camera, and ultraviolet camera in the camera set is configured to capture a plurality of images of the plasma inside the semiconductor process chamber; and A signal processor, coupled to the camera set, wherein the camera set is located around the semiconductor process chamber at different angles and positions; and A control system, coupled to each of the plurality of output circuits and configured to: Control a plasma-assisted semiconductor process to generate an anode glow region adjacent to the top electrode, a cathode glow region adjacent to the bottom electrode, and a plasma region between the anode glow region and the cathode glow region; Receive the plurality of images from each of the camera sets Generate a three-dimensional model of the plasma within the semiconductor process chamber based on the plurality of images; Based on the three-dimensional model, during the plasma-assisted semiconductor process, detect an arc within the semiconductor process chamber passing through the anode glow region, the plasma region, and the cathode glow region between the top electrode and the wafer; Determine the location of the arc on the wafer within the semiconductor process chamber based on the images and the positions of the camera set; In response to detecting the arc within the semiconductor process chamber, adjust the plasma-assisted semiconductor process within the semiconductor process chamber during the plasma-assisted semiconductor process.

24. The system according to claim 23, wherein each of the output circuits includes a communication system coupled to the signal processor and is configured to output a plurality of the images to the control system.

25. The system according to claim 23, wherein the images include: Images in the visible spectrum; Images in the infrared spectrum; Images in the ultraviolet spectrum.

Images