Flash memory device, method for forming the same, and flash memory cell array

Abstract

A flash memory device, a method for forming the same, and a flash memory cell array, the flash memory device including a floating gate electrode formed in a substrate semiconductor layer doped with a first conductivity type, a pair of active regions doped with a second conductivity type formed in the substrate semiconductor layer and laterally separated by the floating gate electrode, an erase gate electrode formed in the substrate semiconductor layer and laterally offset from the floating gate electrode, and a control gate electrode covering the floating gate electrode. The floating gate electrode may be formed in a first opening in the substrate semiconductor layer, and the erase gate electrode may be formed in a second opening in the substrate semiconductor layer. Multiple examples of the flash memory device may be configured as a two-dimensional array of flash memory cells.

Description

Technical Field

[0001] The present disclosure relates to a flash memory device and a method for forming the same, and a flash memory cell array. Background Art

[0002] Flash memory devices store charge in a floating gate by inducing charge tunneling through a tunneling dielectric. Over time, repeated charge tunneling through the tunneling dielectric may damage the tunneling dielectric. Therefore, a damaged tunneling dielectric may adversely affect the reliability of the flash memory device. In addition, the stacking of the floating gate and the control gate above the semiconductor channel may form a noticeable topography of the flash memory device, which may hinder the subsequent patterning of the covering structure. An erase gate can reduce damage to the tunneling gate. However, the use of an erase gate requires a higher precision than the floating gate when covering the erase gate. Therefore, methods and structures are needed to reduce damage to the tunneling dielectric during operation of the flash memory device and reduce the precision required to cover the gate during the manufacture of the flash memory device. Summary of the invention

[0003] According to an embodiment of the present disclosure, a flash memory device is provided, including a floating gate electrode formed in a substrate semiconductor layer doped with a first conductive type, a pair of active regions doped with a second conductive type formed in the substrate semiconductor layer and laterally separated from the floating gate electrode, an erase gate electrode formed in the substrate semiconductor layer and laterally offset from the floating gate electrode, and a control gate electrode covering the floating gate electrode.

[0004] According to an embodiment of the present disclosure, a flash memory cell array is provided, comprising a two-dimensional array of floating gate electrodes formed in a substrate semiconductor layer doped with a first conductive type, a two-dimensional array of erase gate electrodes formed in the substrate semiconductor layer and laterally offset from the two-dimensional array of floating gate electrodes along a first horizontal direction, a two-dimensional array of active regions doped with a second conductive type formed in the substrate semiconductor layer and laterally offset from the two-dimensional array of floating gate electrodes along a second horizontal direction different from the first horizontal direction, and a two-dimensional array of control gate electrodes covering a corresponding one of the two-dimensional array of floating gate electrodes, wherein each floating gate electrode is located between a pair of adjacent active regions in the two-dimensional array of active regions.

[0005] According to an embodiment of the present disclosure, a method for forming a flash memory device is provided, including forming a first opening in a substrate semiconductor layer having a first conductivity type doping, forming a tunneling dielectric and a floating gate electrode in the first opening, forming a second opening in the substrate semiconductor layer adjacent to the first opening, forming an erase gate dielectric and an erase gate electrode in the second opening, forming a control gate dielectric and a control gate electrode above the floating gate electrode, and forming a pair of active regions in the substrate semiconductor layer by implanting dopants having a second conductivity type doping, wherein the pair of active regions are laterally separated by the floating gate electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the present disclosure can be best understood from the following detailed description. It should be noted that, in accordance with standard methods in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A is a top view of an exemplary structure after a shallow trench isolation structure is formed in a semiconductor layer of a substrate according to an embodiment of the present disclosure;

[0008] Figure 1B It is along Figure 1A A vertical cross-sectional view of an exemplary structure of plane BB′;

[0009] Figure 2A is a top view of an exemplary structure after a first opening is formed in a semiconductor layer of a substrate according to an embodiment of the present disclosure;

[0010] Figure 2B It is along Figure 2A A vertical cross-sectional view of an exemplary structure of plane BB′;

[0011] Figure 3A is a top view of an exemplary structure after forming a tunnel dielectric layer and a floating gate electrode layer according to an embodiment of the present disclosure;

[0012] Figure 3B It is along Figure 3A A vertical cross-sectional view of an exemplary structure of plane BB′;

[0013] Figure 4A is a top view of an exemplary structure after forming a tunneling dielectric and a floating gate electrode according to an embodiment of the present disclosure;

[0014] Figure 4B It is along Figure 4A A vertical cross-sectional view of an exemplary structure of plane BB′;

[0015] Figure 5Ais a top view of an exemplary structure after forming a second opening in a semiconductor layer of a substrate according to an embodiment of the present disclosure;

[0016] Figure 5B It is along Figure 5A A vertical cross-sectional view of an exemplary structure of plane BB′;

[0017] Fig. 6A is a top view of an exemplary structure after forming an erased gate dielectric layer and an erased gate electrode layer according to an embodiment of the present disclosure;

[0018] Figure 6B It is along Fig. 6A A vertical cross-sectional view of an exemplary structure of plane BB′;

[0019] Fig. 7A is a top view of an exemplary structure after forming an erased gate dielectric and an erased gate electrode according to an embodiment of the present disclosure;

[0020] Figure 7B It is along Fig. 7A A vertical cross-sectional view of an exemplary structure of plane BB′;

[0021] Fig. 8A is a top view of an exemplary structure after forming a control gate dielectric layer and a control gate electrode layer according to an embodiment of the present disclosure;

[0022] Figure 8B It is along Fig. 8A A vertical cross-sectional view of an exemplary structure of plane BB′;

[0023] Fig.9A is a top view of an exemplary structure after forming a control gate electrode and a control gate dielectric according to an embodiment of the present disclosure;

[0024] Fig. 9B It is along Fig.9A A vertical cross-sectional view of an exemplary structure of plane BB′;

[0025] Fig. 10A is a top view of an exemplary structure after forming a dielectric gate spacer according to an embodiment of the present disclosure;

[0026] Fig. 10B It is along Fig. 10A A vertical cross-sectional view of an exemplary structure of plane BB′;

[0027] Fig.11A is a top view of an exemplary structure after forming an active region according to an embodiment of the present disclosure;

[0028] Fig. 11B It is along Fig.11A A vertical cross-sectional view of an exemplary structure of plane BB′;

[0029] Fig. 11C It is along Fig.11A A vertical cross-sectional view of an exemplary structure of a plane CC′;

[0030] Fig.11D is FIG. 11A to FIG. 11C A top view of a logic region of an exemplary structure during a process step of FIG.

[0031] Fig.11E It is along Fig.11D A vertical cross-sectional view of an exemplary structure of a plane EE′;

[0032] Fig. 12A is a top view of an exemplary structure after forming a planarized dielectric layer and various contact via structures according to an embodiment of the present disclosure;

[0033] Fig. 12B It is along Fig. 12A A vertical cross-sectional view of an exemplary structure of plane BB′;

[0034] Fig. 12C It is along Fig. 12A A vertical cross-sectional view of an exemplary structure of a plane CC′;

[0035] Fig.13 is a flow chart illustrating steps for forming an exemplary structure according to one embodiment of the present disclosure.

[0036]

Explanation of symbols

[0037] 8:Semiconductor substrate

[0038] 10: Substrate semiconductor layer

[0039] 12: Shallow Trench Isolation Structure

[0040] 17: First photoresist layer

[0041] 19: First Opening

[0042] 20: Tunneling Dielectric

[0043] 20L: Tunneling dielectric layer

[0044] 22: floating gate electrode

[0045] 22L: floating gate electrode layer

[0046] 27: Second photoresist layer

[0047] 29: Second opening

[0048] 30: Erase gate dielectric

[0049] 30L: Erase gate dielectric layer

[0050] 32: Erase gate electrode

[0051] 32L: Erase gate electrode layer

[0052] 40: Control gate dielectric

[0053] 40L: Control gate dielectric layer

[0054] 42: Control gate electrode

[0055] 42L: Control gate electrode layer

[0056] 46: Dielectric gate spacer

[0057] 47: The third photoresist layer

[0058] 62,66: Active zone

[0059] 70: Planarization dielectric layer

[0060] 82,84,86,88: Contact through-hole structure

[0061] 132: Source region

[0062] 132D: Deep Source Polar Region

[0063] 132E: Source extension region

[0064] 135: Semiconductor Channel

[0065] 138: Drain region

[0066] 138D: Deep drain region

[0067] 138E: Drain extension region

[0068] 140: Gate dielectric

[0069] 142: Gate electrode

[0070] 146: Gate spacer

[0071] 301, 401: first silicon oxide layer

[0072] 302,402: Silicon nitride layer

[0073] 303,403: Second silicon oxide layer

[0074] 1810,1820,1830,1840,1850,1860: Steps

[0075] BB′,CC′,EE′: plane

[0076] d1: first depth

[0077] d2: second depth

[0078] hd1: first horizontal direction

[0079] hd2: second horizontal direction

[0080] P1: First spacing

[0081] P2: Second spacing

[0082] UC:Unit Flash Memory Unit DETAILED DESCRIPTION

[0083] In order to realize the different features of the mentioned subject matter, the following disclosure provides many different embodiments or examples. Specific examples of components, configurations, etc. are described below to simplify the present disclosure. Of course, these are merely examples and are not restrictive. For example, in the following description, forming a first feature on or above a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0084] In addition, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and the like, may be used herein to facilitate describing the relationship of one element or feature to another element or feature as shown in the figures. Spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive symbols used herein may also be interpreted accordingly. Unless otherwise expressly stated, each element having the same element number is deemed to have the same material composition and have a thickness within the same thickness range.

[0085] The present disclosure relates to a semiconductor device, and more particularly to a flash memory device including a buried floating gate and a buried erase gate and a method of forming the same.

[0086] In general, the methods and structures of the present disclosure may be used to provide a flash memory device including a buried floating gate electrode and a buried erase gate electrode. The use of the buried erase gate electrode increases the lifetime of the tunneling dielectric. In addition, the buried configuration of the floating gate electrode and the erase gate electrode may reduce the topography of the flash memory device. Thus, during the formation of the control gate electrode, a better focus of the lithographic image used to form the element may be provided. The flash memory device may be formed in a two-dimensional array configuration. Various features and aspects of embodiments of the present disclosure are now described with reference to the accompanying drawings.

[0087] See also Figure 1A and Figure 1B , depicts an exemplary structure including a semiconductor substrate 8 according to an embodiment of the present disclosure, wherein the semiconductor substrate 8 may include a substrate semiconductor layer 10. The semiconductor substrate 8 may be a bulk semiconductor substrate, wherein the substrate semiconductor layer 10 may extend from the front surface to the back surface, or may be a semiconductor-on-insulator (SOI) substrate including a buried insulator layer (not shown) below the substrate semiconductor layer 10 and a handling substrate (not shown) below the buried insulator layer. For example, the semiconductor substrate 8 may be a commercially available single crystal bulk semiconductor substrate or a commercially available semiconductor-on-insulator substrate.

[0088] The substrate semiconductor layer 10 may include a single crystal semiconductor material or a polycrystalline semiconductor material. In one embodiment, the entire substrate semiconductor layer 10 may include a single crystal semiconductor material, such as single crystal silicon. The semiconductor material of the substrate semiconductor layer 10 may be doped with a first conductivity type, which may be a p-type or an n-type. The atomic concentration of the dopant of the first conductivity type in the substrate semiconductor layer 10 may be between 1.0×10 14 / cm 3 Up to 3.0×10 17 / cm 3 In one embodiment, the substrate semiconductor layer 10 may be composed mainly of silicon and a dopant of the first conductivity type.

[0089] A shallow trench isolation structure 12 may be formed in an upper portion of the substrate semiconductor layer 10. For example, a shallow trench having a depth in the range of 50 nanometers to 500 nanometers may be formed through the top surface of the substrate semiconductor layer 10, but greater or lesser depths may also be used. The shallow trench may be formed by coating and patterning a photoresist layer over the top surface of the substrate semiconductor layer 10, and transferring the pattern in the photoresist layer to the upper portion of the substrate semiconductor layer 10 using an anisotropic etching process. The photoresist layer may then be removed by, for example, ashing. A dielectric material may be deposited in the shallow trench, and a planarization process such as a chemical mechanical polishing (CMP) process may be used to remove excess portions of the dielectric from above a horizontal plane including the top surface of the substrate semiconductor layer 10. The remaining portion of the dielectric material filling the shallow trench comprises a shallow trench isolation structure 12. In one embodiment, the shallow trench isolation region may define device regions that are laterally spaced apart along a first horizontal direction hd1. Each device region extends laterally along a first horizontal direction hd1 between an adjacent pair of shallow trench isolation structures 12. Each device region may have a uniform width along the first horizontal direction hd1 and may extend laterally along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. Each shallow trench isolation structure 12 may have a width in the range of 30 nanometers to 300 nanometers along the first horizontal direction hd1, but a larger or smaller width may also be used. The shallow trench isolation structures 12 may be configured as a periodic one-dimensional array having a first pitch P1, i.e., the lateral distance of the repeated pattern along the first horizontal direction hd1. Although portions of two device regions are used to describe the present disclosure, it should be understood that the exemplary structure may include multiple device regions and that the structure shown may be repeated along the first horizontal direction hd1 and along the second horizontal direction hd2.

[0090] See also Figure 2A and Figure 2B , a first photoresist layer 17 may be coated on the top surface of the semiconductor substrate 8. The first photoresist layer 17 may be lithographically patterned to form an array of openings through the layer. The openings in the first photoresist layer 17 may be located in the device region between the pairs of adjacent shallow trench isolation structures 12. The pattern of the openings in the first photoresist layer 17 may be a two-dimensional periodic pattern having a first pitch P1 along a first horizontal direction hd1 and a second pitch P2 along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. In this embodiment, the opening pattern in the first photoresist layer 17 may be a rectangular two-dimensional periodic array.

[0091] An anisotropic etching process may be performed to transfer the opening pattern in the first photoresist layer 17 to the substrate semiconductor layer 10. The first opening 19 may be formed in a region of the substrate semiconductor layer 10 below the opening in the first photoresist layer 17. The first opening 19 formed in the substrate semiconductor layer 10 is also referred to as a floating gate opening. The horizontal cross-sectional shape of each first opening 19 may be a rectangle, a rounded rectangle (a shape obtained by rounding the four corners of a rectangle), a circle, an ellipse, or any other curved two-dimensional shape with or without straight sides. In one embodiment, the horizontal cross-sectional shape of each first opening 19 may be a substantially rectangular shape (such as Figure 2A and Figure 2B ). The lateral dimension of each first opening 19 along the first horizontal direction hd1 may be in the range of from 20 nanometers to 200 nanometers, such as from 40 nanometers to 100 nanometers, but smaller and larger lateral dimensions may also be used. The lateral dimension of each first opening 19 along the second horizontal direction hd2 may be in the range of from 20 nanometers to 200 nanometers, such as from 40 nanometers to 100 nanometers, but smaller and larger lateral dimensions may also be used. The bottom surface of each first opening 19 may be located at a first depth d1 from a horizontal plane including the top surface of the substrate semiconductor layer 10. The first depth d1 may be in the range of from 20 nanometers to 200 nanometers, such as from 40 nanometers to 100 nanometers, but smaller and larger first depths d1 may also be used. The first photoresist layer 17 may be subsequently removed, for example, by ashing.

[0092] See also Figure 3A and Figure 3B , a tunneling dielectric layer 20L may be formed on the bottom surface and sidewalls of the first opening 19 and over the top surface of the substrate semiconductor layer 10. The tunneling dielectric layer 20L includes a tunneling dielectric material, i.e., a dielectric material through which charge carriers (e.g., electrons or holes) can tunnel. For example, the tunneling dielectric layer 20L may include a thermal oxide formed by thermal oxidation of a surface portion of the substrate semiconductor layer 10, which may be physically exposed to the first opening 19 or located on the top surface of the substrate semiconductor layer 10. The thickness of the tunneling dielectric layer 20L may be in the range of 2 nanometers to 6 nanometers, although lesser or greater thicknesses may also be used. In one embodiment, the horizontal and vertical portions of the tunneling dielectric layer 20L may have a uniform thickness.

[0093] A floating gate electrode layer 22L may then be formed over the tunneling dielectric layer 20L. The floating gate electrode layer 22L includes a floating gate material, i.e., a material that may be used to form a floating gate electrode. For example, the floating gate electrode layer 22L may include a doped semiconductor material (e.g., p-type doped polysilicon or n-type doped polysilicon), a metal nitride material (e.g., titanium nitride or tantalum nitride), and / or an elemental metal or an intermetallic alloy. Other suitable materials are also within the contemplated scope of the present disclosure. In an illustrative example, the floating gate electrode layer 22L includes doped polysilicon. The thickness of the floating gate electrode layer 22L may be selected such that the remaining volume of the first opening 19 is filled by the floating gate electrode layer 22L. The floating gate electrode layer 22L may be deposited by a conformal deposition process, such as a chemical vapor deposition (CVD) process.

[0094] See also Figure 4A and Figure 4B , a planarization process may be performed to remove portions of the floating gate electrode layer 22L and the tunneling dielectric layer 20L located above a horizontal plane including the top surface of the substrate semiconductor layer 10. The planarization process may use a chemical mechanical planarization (CMP) process and / or a recess etching process. In one embodiment, a chemical mechanical planarization process may be performed to planarize the floating gate electrode layer 22L and the tunneling dielectric layer 20L. Each remaining portion of the tunneling dielectric layer 20L located in a corresponding first opening 19 includes a tunneling dielectric 20. Each remaining portion of the floating gate electrode layer 22L located in a corresponding first opening 19 includes a floating gate electrode 22. The tunneling dielectric 20 and the floating gate electrode 22 may be formed in each first opening 19. The tunneling dielectric 20 and the floating gate electrode 22 may have a top surface located in a horizontal plane, which includes the top surface of the substrate semiconductor layer 10. Each floating gate electrode 22 may be formed within and laterally surrounded by a corresponding tunnel dielectric 20 .

[0095] Each floating gate electrode 22 may be formed in a corresponding first opening 19, which extends vertically from the top surface of the substrate semiconductor layer 10 toward the back surface of the substrate semiconductor layer 10. Each tunneling dielectric 20 may be formed on the sidewall and bottom surface of the corresponding first opening 19. A two-dimensional array of floating gate electrodes 22 may be formed in the substrate semiconductor layer 10 having the first conductivity type doping. The two-dimensional array of floating gate electrodes 22 may be a periodic array having a first pitch P1 along the first horizontal direction hd1 and a second pitch P2 along the second horizontal direction hd2. A two-dimensional array of tunneling dielectrics 20 may be formed in the substrate semiconductor layer 10. The two-dimensional array of tunneling dielectrics 20 may be a periodic array having a first pitch P1 along the first horizontal direction hd1 and a second pitch P2 along the second horizontal direction hd2.

[0096] See also Figure 5A and Figure 5B , a second photoresist layer 27 may be coated on the top surface of the semiconductor substrate 8. The second photoresist layer 27 may be lithographically patterned to form an array of openings passing therethrough. The openings in the second photoresist layer 27 may be located near a region of the first opening 19 including the tunneling dielectric 20 and the floating gate electrode 22. In one embodiment, the openings in the second photoresist layer 27 may be positioned so that each opening in the second photoresist layer 27 is laterally offset from a corresponding one of the first openings 19 along a first horizontal direction hd1. In one embodiment, in a plan view (i.e., in a top view along a direction perpendicular to the top surface of the semiconductor substrate 8), the periphery of each opening in the second photoresist layer 27 may overlap with the periphery of a corresponding one of the first openings 19. The pattern of the openings in the second photoresist layer 27 may be a two-dimensional periodic pattern having a first pitch P1 along the first horizontal direction hd1 and a second pitch P2 along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. In such an embodiment, the pattern of the openings in the second photoresist layer 27 may be a rectangular two-dimensional periodic array. In one embodiment, each opening in the second photoresist layer 27 may have sidewalls covering and contacting the top surface of a corresponding one of the tunnel dielectrics 20 .

[0097] An anisotropic etching process may be performed to transfer the opening pattern in the second photoresist layer 27 into the substrate semiconductor layer 10. Second openings 29 may be formed in the area of ​​the substrate semiconductor layer 10 below the openings in the second photoresist layer 27. The second openings 29 formed in the substrate semiconductor layer 10 are also referred to as erase gate openings. Each second opening 29 may be formed near a corresponding one of the first openings 19. In one embodiment, the chemistry of the anisotropic etching process may be selected so that the anisotropic etching process selectively etches the semiconductor material of the substrate semiconductor layer 10 rather than the dielectric material of the tunnel dielectric 20. Thus, the outer sidewalls of each second opening 29 may coincide with the outer sidewalls of a corresponding one of the tunnel dielectrics 20.

[0098] The horizontal cross-sectional shape of each second opening 29 may be a rectangle, a rounded rectangle (a shape obtained by rounding the four corners of a rectangle), a circle, an ellipse, or any other curved two-dimensional shape with or without straight sides. In one embodiment, the horizontal cross-sectional shape of each second opening 29 may be substantially rectangular. The lateral dimension of each second opening 29 along the first horizontal direction hd1 may be in the range of from 20 nanometers to 200 nanometers, such as from 40 nanometers to 100 nanometers, but smaller and larger lateral dimensions may also be used. The lateral dimension of each second opening 29 along the second horizontal direction hd2 may be in the range of from 20 nanometers to 200 nanometers, such as from 40 nanometers to 100 nanometers, but smaller and larger lateral dimensions may also be used. The bottom surface of each second opening 29 may be located at a second depth d2 from a horizontal plane including the top surface of the substrate semiconductor layer 10. The second depth d2 may be less than, greater than, or equal to the first depth d1. The second depth d2 may be in the range of from 200 nanometers to 200 nanometers, such as from 40 nanometers to 100 nanometers, but smaller and larger second depths d2 may also be used. In one embodiment, the second depth d2 may be less than the first depth d1. The second photoresist layer 27 may be subsequently removed, for example, by ashing.

[0099] See also Fig. 6A and Figure 6B , an erase gate dielectric layer 30L may be formed on the bottom surface and sidewalls of the second opening 29 and over the top surface of the substrate semiconductor layer 10. The erase gate dielectric layer 30L may include an erase gate dielectric material through which charge carriers (such as electrons or holes) may tunnel. For example, the erase gate dielectric layer 30L may include an ONO stack, i.e., a stack of a first silicon oxide layer 301, a silicon nitride layer 302, and a second silicon oxide layer 303. For example, the ONO stack may be formed by depositing a silicon oxide material (e.g., by thermal decomposition of tetraethyl orthosilicate glass) or thermal conversion of a physically exposed surface portion of the substrate semiconductor layer 10 to form the first silicon oxide layer 301, depositing the silicon nitride layer 302, and converting a surface portion of the silicon nitride layer 302 into the second silicon oxide layer 303 using a thermal oxidation process. The thickness of the erase gate dielectric layer 30L may be in the range of 2 nanometers to 6 nanometers, although lesser or greater thicknesses may also be used. In one embodiment, the horizontal and vertical portions of the erase gate dielectric layer 30L may have uniform thicknesses.

[0100] An erase gate electrode layer 32L may then be formed on the erase gate dielectric layer 30L. The erase gate electrode layer 32L includes a gate electrode material. For example, the erase gate electrode layer 32L may include a doped semiconductor material (such as p-type doped polysilicon or n-type doped polysilicon), a metal nitride material (such as titanium nitride or tantalum nitride), and / or an elemental metal or an intermetallic alloy. Other suitable materials are also within the contemplated scope of the present disclosure. In an illustrative example, the erase gate electrode layer 32L includes doped polysilicon. The thickness of the erase gate electrode layer 32L may be selected so that the remaining volume of the second opening 29 may be filled by the erase gate electrode layer 32L. The erase gate electrode layer 32L may be deposited by a conformal deposition process, such as a chemical vapor deposition (CVD) process.

[0101] See also Fig. 7A and Figure 7B , a planarization process may be performed to remove portions of the erase gate electrode layer 32L and the erase gate dielectric layer 30L that are located above a horizontal plane including the top surface of the substrate semiconductor layer 10. The planarization process may use a chemical mechanical planarization (CMP) process and / or a recess etching process. In one embodiment, a chemical mechanical planarization process may be performed to planarize the erase gate electrode layer 32L and the erase gate dielectric layer 30L. Each remaining portion of the erase gate dielectric layer 30L located in a corresponding second opening 29 includes an erase gate dielectric 30. Each remaining portion of the erase gate electrode layer 32L located in a corresponding second opening 29 includes an erase gate electrode 32. The erase gate dielectric 30 and the erase gate electrode 32 may be formed in each second opening 29. The erase gate dielectric 30 and the erase gate electrode 32 may have a top surface located in a horizontal plane that includes the top surface of the substrate semiconductor layer 10. Each erase gate electrode 32 may be formed within a corresponding erase gate dielectric 30 , and may be laterally surrounded by the erase gate dielectric 30 .

[0102] Each erase gate electrode 32 may be formed in a corresponding second opening 29, which extends vertically from the top surface of the substrate semiconductor layer 10 toward the back surface of the substrate semiconductor layer 10. Each erase gate dielectric 30 may be formed on the sidewall and bottom surface of the corresponding second opening 29. A two-dimensional array of erase gate electrodes 32 may be formed in the substrate semiconductor layer 10 having the first conductive type doping. The two-dimensional array of erase gate electrodes 32 may be a periodic array having a first pitch P1 along the first horizontal direction hd1 and a second pitch P2 along the second horizontal direction hd2. A two-dimensional array of erase gate dielectrics 30 may be formed in the substrate semiconductor layer 10. The two-dimensional array of erase gate dielectrics 30 may be a periodic array having a first pitch P1 along the first horizontal direction hd1 and a second pitch P2 along the second horizontal direction hd2.

[0103] The floating gate electrodes 22 and the erase gate electrodes 32 may be formed in the substrate semiconductor layer 10. In one embodiment, each erase gate electrode 32 may be laterally spaced apart from the nearest floating gate electrode 22 along the first horizontal direction hd1. In one embodiment, each erase gate electrode 32 may be formed at a position laterally spaced apart from the nearest floating gate electrode 22 along the first horizontal direction hd1, i.e., laterally offset. In one embodiment, each erase gate electrode 32 may be laterally spaced apart from the nearest floating gate electrode 22 by a vertical portion of the tunnel dielectric 20 and a vertical portion of the erase gate dielectric 30. In such an embodiment, the lateral spacing between each erase gate electrode 32 and the nearest floating gate electrode 22 may be the sum of the thickness of the tunnel dielectric 20 and the thickness of the erase gate dielectric 30. The two-dimensional array of erase gate electrodes 32 may be formed in the substrate semiconductor layer 10 and may be laterally offset from the two-dimensional array of floating gate electrodes 22 along the first horizontal direction hd1. The offset direction between each pair of adjacent erase gate electrodes 32 and floating gate electrodes 22 is referred to as the axial direction in this case. Each set of adjacent tunnel dielectrics 20, floating gate electrodes 22, erase gate dielectrics 30, and erase gate electrodes 32 may be mirror-symmetric about a vertical plane extending horizontally along the axial direction. In the illustrated example, the axial direction may be the first horizontal direction hd1.

[0104] See also Fig. 8A and Figure 8B, a control gate dielectric layer 40L may be deposited over the top surface of the substrate semiconductor layer 10. The control gate dielectric layer 40L may be deposited directly on the top surfaces of the tunneling dielectric 20, the floating gate electrode 22, the erase gate dielectric 30, and the erase gate electrode 32. In one embodiment, the top surfaces of the tunneling dielectric 20, the floating gate electrode 22, the erase gate dielectric 30, and the erase gate electrode 32 may be coplanar with the top surface of the substrate semiconductor layer 10. The control gate dielectric layer 40L includes a control gate dielectric material having a sufficient thickness to prevent tunneling of charge carriers during operation. For example, the control gate dielectric layer 40L may include an ONO stack, i.e., a stack of a first silicon oxide layer 401, a silicon nitride layer 402, and a second silicon oxide layer 403. For example, the ONO stack may be formed by depositing a silicon oxide material (e.g., by thermal decomposition of ethyl orthosilicate glass) or thermally converting the physically exposed surface portions of the substrate semiconductor layer 10, the floating gate electrode 22, and the erased gate electrode 32 to form a first silicon oxide layer 401, depositing a silicon nitride layer 402, and using a thermal oxidation process to convert the surface portion of the silicon nitride layer 402 into a second silicon oxide layer 403. The thickness of the control gate dielectric layer 40L may be in the range of 3 nanometers to 12 nanometers, although lesser or greater thicknesses may also be used. The control gate dielectric layer 40L may be formed as a planar material layer having a uniform thickness throughout.

[0105] A control gate electrode layer 42L may then be formed on the control gate dielectric layer 40L. The control gate electrode layer 42L includes a gate electrode material. For example, the control gate electrode layer 42L may include a doped semiconductor material (such as p-type doped polysilicon or n-type doped polysilicon), a metal nitride material (such as titanium nitride or tantalum nitride), and / or an elemental metal or an intermetallic alloy. Other suitable materials are also within the contemplation of the present disclosure. In an illustrative example, the control gate electrode layer 42L includes doped polysilicon. The thickness of the control gate electrode layer 42L may be in a range from 50 nanometers to 300 nanometers, such as from 100 nanometers to 200 nanometers, but smaller and larger thicknesses may also be used. The control gate electrode layer 42L may be deposited by a conformal deposition process such as a chemical vapor deposition (CVD) process, or may be deposited by a non-conformal deposition process such as a physical vapor deposition (PVD) process (i.e., sputtering).

[0106] See also Fig.9A and Fig. 9B, a third photoresist layer 47 may be coated over the control gate electrode layer 42L and may be lithographically patterned to form a patterned photoresist layer including discrete photoresist material portions. The patterned portions of the photoresist material of the third photoresist layer 47 may be formed in regions overlapping the two-dimensional array of floating gate electrodes 22. In one embodiment, each floating gate electrode 22 may be completely covered by the lithographically patterned portions of the third photoresist layer 47. In one embodiment, the sidewalls of the discrete patterned portions of the third photoresist layer 47 may be formed in the region of the top surface of the tunneling dielectric 20. In one embodiment, the discrete patterned portions of the third photoresist layer 47 may be formed as a periodic two-dimensional array of photoresist material portions having a first pitch P1 along a first horizontal direction hd1 and a second pitch P2 along a second horizontal direction hd2.

[0107] The control gate dielectric layer 40L and the control gate electrode layer 42L are formed on a flat surface with no or minimal topographical changes. The lithographic patterning process for patterning the third photoresist layer 47 can form a lithographic image with a focal plane located within the third photoresist layer 47. Since the third photoresist layer 47 does not have any topographical changes during image formation, the third photoresist layer 47 can be patterned with high pattern fidelity.

[0108] An anisotropic etching process (e.g., a reactive ion etching process) may be performed to transfer the pattern in the third photoresist layer 47 through the control gate electrode layer 42L and the control gate dielectric layer 40L. The control gate electrode layer 42L and the control gate dielectric layer 40L may be anisotropically etched using the patterned third photoresist layer 47 as an etching mask. The patterned portion of the control gate electrode layer 42L includes the control gate electrode 42, and the patterned portion of the control gate dielectric layer 40L includes the control gate dielectric 40. A vertical stack of the control gate dielectric 40 and the control gate electrode 42 may be formed above each floating gate electrode 22. Each control gate dielectric 40 may be directly located on the top surface of the underlying floating gate electrode 22. Therefore, the control gate dielectric 40 may contact the entire top surface of the underlying floating gate electrode 22, and may contact the inner periphery of the top surface of the underlying tunnel dielectric 20. Each control gate electrode 42 covers the corresponding underlying floating gate electrode 22 and is vertically separated from the corresponding underlying floating gate electrode 22 by the control gate dielectric 40. Each tunnel dielectric 20 laterally surrounds the corresponding floating gate electrode 22 and contacts the bottom surface of the corresponding control gate dielectric 40. A two-dimensional array of control gate electrodes 42 may be formed, which may be a periodic two-dimensional array having a first pitch P1 along a first horizontal direction hd1 and a second pitch P2 along a second horizontal direction hd2. The third photoresist layer 47 may be subsequently removed, for example, by ashing.

[0109] See also Fig. 10A and Fig. 10B , a dielectric spacer material layer can be conformally deposited on the physically exposed surfaces of the control gate electrode 42, the control gate dielectric 40, and various structures formed in the semiconductor substrate 8. The dielectric spacer material layer includes a dielectric material such as silicon oxide or silicon nitride. Other suitable materials are also within the scope of the present disclosure. Conformal deposition of the dielectric spacer material layer can be achieved, for example, by a chemical vapor deposition process, such as a low pressure chemical vapor deposition (LPCVD) process. The thickness of the dielectric spacer material layer can be in a range from 5 nanometers to 80 nanometers, such as from 10 nanometers to 40 nanometers, but smaller and larger thicknesses can also be used. The thickness of the dielectric spacer material layer is less than the lateral dimension of each erase gate dielectric 30 along the first horizontal direction hd1, so that the top surface of each erase gate electrode 32 can be physically exposed after the dielectric gate spacer is formed.

[0110] An anisotropic etching process may be performed to remove horizontally extending portions of the dielectric spacer material layer. Horizontally extending portions of the dielectric spacer material layer are removed from above the top surface of the control gate electrode 42 and from above the top surface of the semiconductor substrate 8, wherein the portion removed from the top surface of the semiconductor substrate 8 is laterally spaced from the control gate electrode 42 by a thickness greater than the dielectric spacer material layer. Vertically extending portions of the dielectric spacer material layer laterally surrounding a corresponding one of the control gate electrodes 42 constitute dielectric gate spacers 46. Each dielectric gate spacer 46 may have a generally tubular configuration and may thus be topologically homeomorphic to a torus. The lateral thickness of each dielectric gate spacer 46 may be the same as the thickness of the dielectric spacer material layer and may thus be in a range from 5 nanometers to 80 nanometers, such as from 10 nanometers to 40 nanometers, although smaller and larger thicknesses may also be used. After forming the dielectric gate spacers 46, the top surfaces of the erase gate electrode 32 and the erase gate dielectric 30 may be physically exposed. Each dielectric gate spacer 46 contacts the top surface of the vertical portion of the erase gate dielectric 30. In one embodiment, each dielectric gate spacer 46 may contact at least a portion of and / or the entire periphery of a top surface of an underlying tunnel dielectric 20. In one embodiment, each dielectric gate spacer 46 may contact all sidewalls of a corresponding control gate electrode 42 and a top surface of a corresponding underlying tunnel dielectric 20, which may be formed in the substrate semiconductor layer 10 and laterally surround the floating gate electrode 22.

[0111] See also FIG. 11A to FIG. 11E By performing at least one mask ion implantation process, each active region 62 , active region 66 , source region 132 , and drain region 138 may be formed in each region of the exemplary structure. FIG. 11A to FIG. 11C A memory region is shown in which a two-dimensional array of flash memory cells is formed. Fig.11Dand Fig.11E The diagram shows the logic region in which logic elements (such as field effect transistors of control circuits that control the operation of the flash memory cells) are formed. Fig. 8A and Figure 8B In the process step of , a logic gate dielectric layer may be formed in the logic region to replace the control gate dielectric layer 40L. For example, the silicon nitride layer 402 and the first silicon oxide layer 401 are removed from the logic region before the second silicon oxide layer 403 is formed. While the second silicon oxide layer 403 is formed, a silicon oxide layer may be formed in the logic region on the top surface of the substrate semiconductor layer 10. While the control gate electrode layer 42L is formed in the memory array region, the control gate electrode layer 42L may be formed in the logic region. The control gate electrode layer 42L and the silicon oxide layer in the logic region may be patterned to form gate stacks, each of which may include a gate dielectric 140 and a gate electrode 142. While the dielectric gate spacers 46 are formed, gate spacers 146 may be formed around each gate stack (including the gate dielectric 140 and the gate electrode 142).

[0112] Before and / or after forming the gate spacers 146, electron dopants (e.g., p-type dopants or n-type dopants) may be implanted into the unmasked portions of the substrate semiconductor layer 10 in the logic region to form source regions 132 and drain regions 138. Each source region 132 may include a source extension region 132E and a deep source region 132D, and each drain region 138 may include a drain extension region 138E and a deep drain region 138D. Each surface portion of the substrate semiconductor layer 10 located below the gate stack (gate dielectric 140 and gate electrode 142) and between a pair of source regions 132 and drain regions 138 constitutes a semiconductor channel 135. The logic region may include a p-type field effect transistor (i.e., a field effect transistor including a p-type doped source region, a p-type doped drain region, and an n-type doped channel region) and an n-type field effect transistor (i.e., a field effect transistor including an n-type doped source region, an n-type doped drain region, and a p-type doped channel region).

[0113] A subset of the masked ion implantation process used to form the source region 132 and the drain region 138 of the field effect transistor can be used to implant a second conductivity type dopant into discrete surface portions of the substrate semiconductor layer 10 in the memory array region. The second conductivity type is opposite to the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa.

[0114] The dopants of the second conductivity type implanted in the memory array region may form active regions 62 and 66. During operation of the flash memory cell, the active regions 62 and 66 may be used as source regions or drain regions. The active regions 62 and 66 may include axial active regions 62, which are laterally offset from the closest floating gate electrode 22 along an axial direction (such as the first horizontal direction hd1). In addition, the active regions 62 and 66 may include lateral active regions 66, which are laterally offset from the closest floating gate electrode 22 along a lateral direction, which is a horizontal direction perpendicular to the axial direction. In the illustrative example, the lateral direction may be the second horizontal direction hd2.

[0115] In one embodiment, each lateral active region 66 may be formed between a pair of tunnel dielectrics 20 that are laterally spaced apart along a lateral direction, such as the second horizontal direction hd2. Each axial active region 62 may be spaced apart from the closest floating gate electrode 22 along an axial direction, such as the first horizontal direction hd1. The axial active region 62 may be located on the opposite side of the erase gate electrode 32 relative to the closest floating gate electrode 22. The lateral active region 66 may contact the sidewalls of the pair of tunnel dielectrics 20. The sidewalls of the tunnel dielectric 20 contacting the corresponding lateral active region 66 may be parallel to the first horizontal direction hd1. The axial active region 62 may contact the sidewalls of the closest tunnel dielectric 20. The sidewalls of the tunnel dielectric 20 contacting the corresponding axial active region 62 may be parallel to the second horizontal direction hd2. The axial active region 62 may contact a corresponding one of the shallow trench isolation structures 12.

[0116] A pn junction may be formed at each interface between the active region 62, the active region 66 and the substrate semiconductor layer 10. The axial active region 62 may be formed as a two-dimensional periodic array of axial active regions 62, the array having a first pitch P1 along the first horizontal direction hd1 and a second pitch P2 along the second horizontal direction hd2. The lateral active region 66 may be formed as a two-dimensional array of lateral active regions 66, the array having a first pitch P1 along the first horizontal direction hd1 and a second pitch P2 along the second horizontal direction hd2.

[0117] A pair of active regions (e.g., a pair of lateral active regions 66) may be formed in the substrate semiconductor layer 10 by implanting dopants having the second conductivity type for each flash memory cell. The pair of active regions may be laterally separated by the floating gate electrode 22 therebetween. For example, the pair of active regions are formed on opposite sides of the floating gate electrode 22 and are laterally separated along a second horizontal direction hd2 that is perpendicular to the first horizontal direction hd1.

[0118] In an embodiment where a plurality of flash memory cells may be formed in a two-dimensional array configuration, a pair of adjacent flash memory cells that are laterally spaced apart along a second horizontal direction hd2 may share a lateral active region 66. In such an embodiment, a two-dimensional array of active regions (e.g., a two-dimensional array of lateral active regions 66) may be formed within the substrate semiconductor layer 10. The two-dimensional array of lateral active regions 66 may have a second conductivity type of doping and may be laterally offset from the two-dimensional array of floating gate electrodes 22 along a second horizontal direction hd2 that is different from the first horizontal direction hd1. Each floating gate electrode 22 may be located between a pair of adjacent lateral active regions 66 within the two-dimensional array of lateral active regions 66.

[0119] In one embodiment, each dielectric gate spacer 46 may contact all sidewalls of the corresponding control gate electrode 42, each top surface of a pair of active regions (such as a pair of lateral active regions 66), and the top surface of the underlying tunneling dielectric 20 formed in the substrate semiconductor layer 10 and laterally surrounding the corresponding floating gate electrode 22.

[0120] See also FIG. 12A to FIG. 12C , a planarization dielectric layer 70 may be deposited over the two-dimensional array of control gate electrodes 42 and the semiconductor substrate 8. The planarization dielectric layer 70 includes a self-planarizing dielectric material or a dielectric material that can be planarized by a planarization process. For example, the planarization dielectric layer 70 may include a flowable oxide (FOX), an undoped silicate glass, or a doped silicate glass. In an embodiment where the planarization dielectric layer 70 is planarizable, a chemical mechanical planarization process may be performed to form a horizontal top surface covering the top surface of the control gate electrode 42. The planarization dielectric layer 70 laterally surrounds and covers each control gate electrode 42 and the dielectric gate spacer 46. The planarization dielectric layer 70 may contact the top surface of each erase gate electrode 32.

[0121] A photoresist layer (not shown) may be coated on the planarization dielectric layer 70 and may be lithographically patterned to form openings in areas covering the control gate electrode 42, the erase gate electrode 32, the axial active region 62, and the lateral active region 66. An anisotropic etching process may be performed to transfer the pattern of the openings in the photoresist layer through the planarization dielectric layer 70. A via cavity may be formed extending vertically through the planarization dielectric layer 70. The via cavity includes a control gate contact via cavity extending to a corresponding one of the control gate electrodes 42, an erase gate contact via cavity extending to a corresponding one of the erase gate electrodes 32, an axial contact via cavity extending to a corresponding one of the axial active regions 62, and a lateral contact via cavity extending to a corresponding one of the lateral active regions 66.

[0122] Optionally, a metal semiconductor alloy region (not shown) may be formed on the physically exposed surfaces of the control gate electrode 42, the erase gate electrode 32, the axial active region 62, and the lateral active region 66. A metal material that forms a metal semiconductor alloy with a semiconductor material may be deposited on the physically exposed top surfaces of the control gate electrode 42, the erase gate electrode 32, the axial active region 62, and the lateral active region 66, and an annealing process may be performed to induce the formation of the metal semiconductor alloy material. In one embodiment, the metal semiconductor alloy may include a metal silicide. The metal material may include, for example, tungsten, titanium, cobalt, nickel, or a metal alloy thereof. Other suitable materials are also within the contemplated scope of the present disclosure. A selective wet etching process may be used to selectively remove unreacted portions of the metal material relative to the metal semiconductor alloy.

[0123] At least one metal material may be deposited in the remaining volume of the various through-hole cavities. The at least one metal material may include, for example, a metal nitride liner (such as TiN, TaN or WN) and a metal fill material (such as tungsten, copper, cobalt, ruthenium or molybdenum). Other suitable materials are also within the scope of the present disclosure. The excess portion of the at least one metal material covering the top surface of the planarized dielectric layer 70 may be removed by a planarization process, which may use a chemical mechanical planarization process and / or a recess etching process. The remaining portion of the at least one metal material in the various through-hole cavities includes contact via structure 84, contact via structure 88, contact via structure 82, and contact via structure 86. The various contact via structures include a control gate contact via structure 84 contacting the top surface of a corresponding one of the control gate electrodes 42, an erase gate contact via structure 88 contacting the top surface of a corresponding one of the erase gate electrodes 32, an axial active region contact via structure 82 contacting the top surface of a corresponding one of the axial active regions 62, and a lateral active region contact via structure 86 contacting the top surface of a corresponding one of the lateral active regions 66.

[0124] Each flash memory cell includes a control gate contact through-hole structure 84 formed in the planarization dielectric layer 70 and contacting the control gate electrode 42, a pair of active region contact through-hole structures (such as a pair of lateral active region contact through-hole structures 86) formed in the planarization dielectric layer 70 and contacting the top surfaces of a pair of active regions (such as a pair of lateral active regions 66), and an erase gate contact through-hole structure 88 formed in the planarization dielectric layer 70 and contacting the top surface of the erase gate electrode 32.

[0125] In an embodiment in which a two-dimensional array of flash memory cells can be formed, a lateral active region 66 can be shared between a pair of adjacent flash memory cells. In one embodiment, the flash memory cell array includes a two-dimensional periodic array of unit flash memory cells UC. The unit flash memory cells UC can be repeated in the two-dimensional periodic array, the array has a first pitch P1 along the first horizontal direction hd1, and the array has a second pitch P2 along the second horizontal direction hd2. Each of the two-dimensional array of floating gate electrodes 22, the two-dimensional array of erase gate electrodes 32, the two-dimensional array of lateral active regions 66, and the two-dimensional array of control gate electrodes 42 can have the same first pitch P1 along the first horizontal direction hd1, and the same second pitch P2 along the second horizontal direction hd2.

[0126] Each unit flash memory cell UC in the two-dimensional periodic array includes a floating gate electrode 22 in the two-dimensional array of floating gate electrodes 22, an erase gate electrode 32 in the two-dimensional array of erase gate electrodes 32, an active region (such as the lateral active region 66) in the two-dimensional array of active regions (such as the lateral active region 66), and a control gate electrode 42 in the two-dimensional array of control gate electrodes 42. Each active region (such as each lateral active region 66) located between a pair of floating gate electrodes 22 laterally spaced apart along the second horizontal direction hd2 may contact a pair of tunnel dielectrics 20, which contact corresponding floating gate electrodes 22 in the pair of floating gate electrodes 22.

[0127] Each floating gate electrode 22 in the flash memory cell array may be located in a corresponding first opening 19, which extends vertically from the top surface of the substrate semiconductor layer 10 toward the back surface of the substrate semiconductor layer 10, and each erase gate electrode 32 in the flash memory cell array may be located in a corresponding second opening 29, which extends vertically from the top surface of the substrate semiconductor layer 10 toward the back surface of the substrate semiconductor layer 10.

[0128] According to various embodiments of the present disclosure, a flash memory device is provided, including a floating gate electrode 22 formed in a substrate semiconductor layer 10 having a first conductive type doping, a pair of active regions (such as a pair of lateral active regions 66) having a second conductive type doping formed in the substrate semiconductor layer 10 and laterally separated by the floating gate electrode 22, an erase gate electrode 32 formed in the substrate semiconductor layer 10 and laterally deviated (for example, along a first horizontal direction hd1) from the floating gate electrode 22, and a control gate electrode 42 covering the floating gate electrode 22.

[0129] According to various embodiments of the present disclosure, a flash memory cell array is provided, including a two-dimensional array of floating gate electrodes 22 that can be formed in a substrate semiconductor layer 10 with a first conductive type doping, a two-dimensional array of erase gate electrodes 32 that can be formed in the substrate semiconductor layer 10 and laterally deviate from the two-dimensional array of floating gate electrodes 22 along a first horizontal direction hd1, a two-dimensional array of active regions (such as lateral active regions 66) with a second conductive type doping that can be formed in the substrate semiconductor layer 10 and laterally deviate from the two-dimensional array of floating gate electrodes 22 along a second horizontal direction hd2 different from the first horizontal direction hd1, and a two-dimensional array of control gate electrodes 42 covering a corresponding one of the floating gate electrodes 22, wherein each floating gate electrode 22 is located between a pair of adjacent active regions within the two-dimensional array of active regions.

[0130] See also Fig.13 , this flowchart depicts steps for forming an exemplary structure of the present disclosure. Referring to step 1810, a first opening 19 may be formed in a substrate semiconductor layer 10 having a first conductivity type doping. Referring to step 1820, a tunneling dielectric 20 and a floating gate electrode 22 may be formed in the first opening 19. Referring to step 1830, a second opening 29 may be formed in the substrate semiconductor layer 10 adjacent to the first opening 19. Referring to step 1840, an erase gate dielectric 30 and an erase gate electrode 32 may be formed in the second opening 29. Referring to step 1850, a control gate dielectric 40 and a control gate electrode 42 may be formed on the floating gate electrode 22. Referring to step 1860, a pair of active regions (e.g., a pair of lateral active regions 66) may be formed in the substrate semiconductor layer 10 by implanting dopants having a second conductivity type doping, wherein the pair of active regions are laterally separated by the floating gate electrode 22.

[0131] Each flash memory cell may be programmed by providing an electrical bias on a pair of active regions adjacent to the floating gate electrode 22. For example, a pair of lateral active regions 66 adjacent to the floating gate electrode 22 may be electrically biased to provide a potential difference therebetween, and a control gate electrode 42 overlying the floating gate electrode 22 may be electrically biased to induce charge carriers (e.g., electrons) to tunnel from a channel portion of the substrate semiconductor layer 10 located below the floating gate electrode 22, through the tunneling dielectric 20, and into the floating gate electrode 22. Alternatively, a pair of axial active regions 62 and lateral active regions 66 may be used to provide a potential difference therebetween, while applying a programming voltage to the control gate electrode 42 to induce charge carriers to tunnel into the floating gate electrode 22.

[0132] Each flash memory cell can be sensed by applying an electrical bias to a pair of lateral active regions 66 adjacent to the floating gate electrode 22 to provide a potential difference therebetween, and by applying a sensing voltage to the control gate electrode 42 overlying the floating gate electrode 22. The magnitude of the sensing voltage is less than the programming voltage and insufficient to tunnel charge carriers (e.g., electrons) into the floating gate electrode 22. The amount of charge in the floating gate electrode 22 controls the magnitude of the current flowing through the channel portion of the substrate semiconductor layer 10 below the floating gate electrode 22. Therefore, the state of the flash memory cell can be determined by the sensing operation, and its state is represented by the amount of charge trapped in the floating gate electrode 22. Alternatively, a pair of axial active regions 62 and lateral active regions 66 can be used to provide a potential difference for the sensing operation, while applying a sensing voltage (of a magnitude less than the programming voltage) to the control gate electrode 42 to measure the magnitude of the current flowing through the channel portion of the substrate semiconductor layer 10 below the floating gate electrode 22.

[0133] Each flash memory cell can be erased by applying an electrical bias to the erase gate electrode 32. For example, if electrons are trapped in the floating gate electrode 22, a large positive bias can be applied to the erase gate electrode 32 to induce electrons to tunnel from the floating gate electrode 22 to the erase gate electrode 32. A negative bias can be applied to the control gate electrode 42 to assist electrons to tunnel from the floating gate electrode 22 to the erase gate electrode 32.

[0134] Various structures and methods disclosed herein can be used to provide a flash memory device, wherein each floating gate electrode 22 and each erase gate electrode 32 are buried in the substrate semiconductor layer 10 and are located below a horizontal plane including the flat top surface of the substrate semiconductor layer 10. During a programming operation, a vertical portion of a tunneling dielectric 20 and a horizontal bottom portion of the tunneling dielectric 20 can be used to tunnel charge carriers into the floating gate electrode 22, wherein the vertical portion extends laterally along a first horizontal direction hd1. During an erase operation, another different vertical portion of the tunneling dielectric 20 extending laterally along a second horizontal direction hd2 can be used to tunnel charge carriers away from the floating gate electrode 22. Therefore, the lifetime of the tunneling dielectric 20 can be extended, and the flash memory device can be operated under more programming and erase operations.

[0135] According to an embodiment of the present disclosure, a flash memory device is provided, including a floating gate electrode formed in a substrate semiconductor layer doped with a first conductive type, a pair of active regions doped with a second conductive type formed in the substrate semiconductor layer and laterally separated from the floating gate electrode, an erase gate electrode formed in the substrate semiconductor layer and laterally offset from the floating gate electrode, and a control gate electrode covering the floating gate electrode.

[0136] In some embodiments, the top surface of the floating gate electrode is located at a horizontal plane including the top surface of the substrate semiconductor layer. In some embodiments, the top surface of the erase gate electrode is located at a horizontal plane including the top surface of the substrate semiconductor layer. In some embodiments, the floating gate electrode is located in a first opening, the first opening extends vertically from the top surface of the substrate semiconductor layer toward the back surface of the substrate semiconductor layer, and the tunneling dielectric is located on the sidewalls and bottom surface of the first opening. In some embodiments, the erase gate electrode is located in a second opening, the second opening extends vertically from the top surface of the substrate semiconductor layer toward the back surface of the substrate semiconductor layer, and the erase gate dielectric is located on the sidewalls and bottom surface of the second opening. In some embodiments, the erase gate electrode is laterally separated from the floating gate electrode by a vertical portion of the tunneling dielectric and a vertical portion of the erase gate dielectric. In some embodiments, the bottom surface of the first opening is located at a first depth from the horizontal plane including the top surface of the substrate semiconductor layer, the bottom surface of the second opening is located at a second depth from the horizontal plane including the top surface of the substrate semiconductor layer, and the second depth is different from the first depth. In some embodiments, the flash memory device further includes a control gate dielectric located on the top surface of the floating gate electrode, and a tunnel dielectric laterally surrounding the floating gate electrode and contacting the bottom surface of the control gate dielectric. In some embodiments, the erase gate electrode is laterally spaced from the floating gate electrode along a first horizontal direction, and the pair of active regions are laterally spaced from each other along a second horizontal direction perpendicular to the first horizontal direction. In some embodiments, the flash memory device further includes a dielectric gate spacer contacting all sidewalls of the control gate electrode, each top surface of the pair of active regions, and a top surface of the tunnel dielectric formed in the substrate semiconductor layer and laterally surrounding the floating gate electrode, and a planarization dielectric layer laterally surrounding and covering the control gate electrode, the dielectric gate spacer, and contacting the top surface of the erase gate electrode. In some embodiments, the flash memory device further includes a control gate contact via structure formed in the planarization dielectric layer and contacting the control gate electrode, a pair of active region contact via structures formed in the planarization dielectric layer and contacting the top surface of the pair of active regions, and an erase gate contact via structure formed in the planarization dielectric layer and contacting the top surface of the erase gate electrode.

[0137] According to an embodiment of the present disclosure, a flash memory cell array is provided, comprising a two-dimensional array of floating gate electrodes formed in a substrate semiconductor layer doped with a first conductive type, a two-dimensional array of erase gate electrodes formed in the substrate semiconductor layer and laterally offset from the two-dimensional array of floating gate electrodes along a first horizontal direction, a two-dimensional array of active regions doped with a second conductive type formed in the substrate semiconductor layer and laterally offset from the two-dimensional array of floating gate electrodes along a second horizontal direction different from the first horizontal direction, and a two-dimensional array of control gate electrodes covering a corresponding one of the two-dimensional array of floating gate electrodes, wherein each floating gate electrode is located between a pair of adjacent active regions in the two-dimensional array of active regions.

[0138] In some embodiments, each of the two-dimensional array of floating gate electrodes, the two-dimensional array of erase gate electrodes, the two-dimensional array of active regions, and the two-dimensional array of control gate electrodes has the same first pitch along the first horizontal direction, and has the same second pitch along the second horizontal direction. In some embodiments, the flash memory cell array includes a two-dimensional periodic array of unit flash memory cells, each unit flash memory cell in the two-dimensional periodic array of unit flash memory cells includes a floating gate electrode in the two-dimensional array of floating gate electrodes, an erase gate electrode in the two-dimensional array of erase gate electrodes, an active region in the two-dimensional array of active regions, and a control gate electrode in the two-dimensional array of control gate electrodes, and each active region located between a pair of floating gate electrodes laterally spaced apart along the second horizontal direction contacts a pair of tunnel dielectrics, the pair of tunnel dielectrics contacting a corresponding floating gate electrode in the pair of floating gate electrodes. In some embodiments, each floating gate electrode in the flash memory cell array is located in a corresponding first opening, the first opening extending vertically from the top surface of the substrate semiconductor layer toward the back surface of the substrate semiconductor layer, and each erase gate electrode in the flash memory cell array is located in a corresponding second opening, the second opening extending vertically from the top surface of the substrate semiconductor layer toward the back surface of the substrate semiconductor layer.

[0139] According to an embodiment of the present disclosure, a method for forming a flash memory device is provided, including forming a first opening in a substrate semiconductor layer having a first conductivity type doping, forming a tunneling dielectric and a floating gate electrode in the first opening, forming a second opening in the substrate semiconductor layer adjacent to the first opening, forming an erase gate dielectric and an erase gate electrode in the second opening, forming a control gate dielectric and a control gate electrode above the floating gate electrode, and forming a pair of active regions in the substrate semiconductor layer by implanting dopants having a second conductivity type doping, wherein the pair of active regions are laterally separated by the floating gate electrode.

[0140] In some embodiments, the method further includes depositing a tunneling dielectric layer on a bottom surface and sidewalls of the first opening and above a top surface of the substrate semiconductor layer, depositing a floating gate electrode layer on the tunneling dielectric layer, and removing portions of the floating gate electrode layer and the tunneling dielectric layer from above a horizontal plane including the top surface of the substrate semiconductor layer, wherein the remaining portion of the floating gate electrode layer includes the floating gate electrode, and the remaining portion of the tunneling dielectric layer includes the tunneling dielectric. In some embodiments, the method further includes depositing an erase gate dielectric layer on a bottom surface and sidewalls of the second opening and above a top surface of the substrate semiconductor layer, depositing an erase gate electrode layer on the erase gate dielectric layer, and removing portions of the erase gate electrode layer and the erase gate dielectric layer from above a horizontal plane including the top surface of the substrate semiconductor layer, wherein the remaining portion of the erase gate electrode layer includes the erase gate electrode, and the remaining portion of the erase gate dielectric layer includes the erase gate dielectric. In some embodiments, the method further includes depositing a control gate dielectric layer on the floating gate electrode, the erase gate electrode, and the substrate semiconductor layer, depositing a control gate electrode layer on the control gate dielectric layer, masking a portion of the control gate electrode layer with a patterned photoresist layer, the portion covering the floating gate electrode, and anisotropically etching the control gate electrode layer and the control gate dielectric layer using the patterned photoresist layer as an etch mask, wherein the patterned portion of the control gate electrode layer includes the control gate electrode, and the patterned portion of the control gate dielectric layer includes the control gate dielectric. In some embodiments, the erase gate electrode is formed at a position laterally spaced apart from the floating gate electrode along a first horizontal direction, and a pair of active regions are formed on opposite sides of the floating gate electrode and laterally spaced apart along a second horizontal direction perpendicular to the first horizontal direction.

[0141] The features of some embodiments are summarized above so that those skilled in the art can better understand the concepts of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications can be made without departing from the spirit and scope of the present disclosure.

Claims

1. A flash memory device, characterized in that: include: A floating gate electrode is formed in a substrate semiconductor layer having a doping of a first conductivity type; a tunnel dielectric laterally surrounding the floating gate electrode; a pair of active regions formed in the substrate semiconductor layer, the pair of active regions having a doping of a second conductivity type and the pair of active regions being laterally separated along a first horizontal direction by the floating gate electrode and a first vertical portion of the tunnel dielectric; an erase gate electrode formed in the substrate semiconductor layer and laterally offset from the floating gate electrode, wherein the erase gate electrode and the floating gate electrode are laterally separated along a second horizontal direction by a second vertical portion of the tunnel dielectric; and A control gate electrode covers the floating gate electrode.

2. The flash memory device according to claim 1, wherein: A top surface of the floating gate electrode is located at a horizontal plane including a top surface of the substrate semiconductor layer.

3. The flash memory device according to claim 2, wherein: A top surface of the erase gate electrode is located at the horizontal plane including the top surface of the substrate semiconductor layer.

4. The flash memory device according to claim 1, wherein: in: The floating gate electrode is located in a first opening, and the first opening vertically extends from a top surface of the substrate semiconductor layer toward a back side surface of the substrate semiconductor layer; and The tunnel dielectric is located on the sidewalls and a bottom surface of the first opening.

5. The flash memory device according to claim 4, wherein: in: The erase gate electrode is located in a second opening, and the second opening vertically extends from the top surface of the substrate semiconductor layer toward the back surface of the substrate semiconductor layer; and A erased gate dielectric is located on the sidewalls and a bottom surface of the second opening.

6. The flash memory device according to claim 5, wherein: The erase gate electrode is laterally spaced apart from the floating gate electrode by the second vertical portion of the tunnel dielectric and a vertical portion of the erase gate dielectric.

7. The flash memory device according to claim 5, wherein: in: The bottom surface of the first opening is located at a first depth from a horizontal plane including the top surface of the substrate semiconductor layer; The bottom surface of the second opening is located at a second depth from the horizontal plane including the top surface of the substrate semiconductor layer; and The second depth is different from the first depth.

8. The flash memory device according to claim 1, wherein: Further including: a control gate dielectric disposed on a top surface of the floating gate electrode, The tunnel dielectric laterally surrounds the floating gate electrode and contacts a bottom surface of the control gate dielectric.

9. The flash memory device according to claim 1, wherein: in: The pair of active regions are laterally spaced apart from each other along the second horizontal direction perpendicular to the first horizontal direction.

10. The flash memory device according to claim 1, wherein: Further including: a dielectric gate spacer contacting all sidewalls of the control gate electrode, each top surface of the pair of active regions, and a top surface of the tunnel dielectric formed in the substrate semiconductor layer and laterally surrounding the floating gate electrode; and A planarized dielectric layer laterally surrounds and covers the control gate electrode and the dielectric gate spacer and contacts a top surface of the erase gate electrode.

11. The flash memory device according to claim 10, wherein: Further including: a control gate contact via structure formed in the planarized dielectric layer and contacting the control gate electrode; a pair of active region contact via structures formed in the planarized dielectric layer and contacting the top surface of the pair of active regions; and An erase gate contact via structure is formed in the planarized dielectric layer and contacts the top surface of the erase gate electrode.

12. A flash memory cell array, characterized in that: include: A two-dimensional array of floating gate electrodes is formed in a substrate semiconductor layer having a doping of a first conductivity type; a two-dimensional array of erased gate electrodes formed in the substrate semiconductor layer and laterally offset from the two-dimensional array of floating gate electrodes along a first horizontal direction, wherein each erased gate electrode is laterally separated from a corresponding floating gate electrode in the two-dimensional array of floating gate electrodes by a first vertical portion of a tunnel dielectric along the first horizontal direction; a two-dimensional array of active regions formed in the substrate semiconductor layer, the two-dimensional array of active regions having a doping of a second conductivity type and laterally offset from the two-dimensional array of floating gate electrodes along a second horizontal direction different from the first horizontal direction, wherein each floating gate electrode and a second vertical portion of the tunnel dielectric are located between a pair of adjacent active regions in the two-dimensional array of active regions; and A two-dimensional array of control gate electrodes covers a corresponding one of the two-dimensional arrays of floating gate electrodes.

13. The flash memory cell array according to claim 12, wherein: Each of the floating gate electrode two-dimensional array, the erase gate electrode two-dimensional array, the active region two-dimensional array, and the control gate electrode two-dimensional array has a same first pitch along the first horizontal direction and a same second pitch along the second horizontal direction.

14. The flash memory cell array according to claim 13, wherein: in: The flash memory cell array includes a two-dimensional periodic array of unit flash memory cells; Each unit flash memory cell in the two-dimensional periodic array of unit flash memory cells includes a floating gate electrode in the two-dimensional array of floating gate electrodes, an erase gate electrode in the two-dimensional array of erase gate electrodes, an active region in the two-dimensional array of active regions, and a control gate electrode in the two-dimensional array of control gate electrodes; and Each of the active regions between a pair of floating gate electrodes laterally spaced apart along the second horizontal direction contacts a pair of tunnel dielectrics that contact corresponding floating gate electrodes within the pair of floating gate electrodes.

15. The flash memory cell array according to claim 13, wherein: in: Each floating gate electrode in the flash memory cell array is located in a corresponding first opening, and the first opening vertically extends from a top surface of the substrate semiconductor layer toward a back side surface of the substrate semiconductor layer; as well as Each erase gate electrode in the flash memory cell array is located in a corresponding second opening, and the second opening vertically extends from the top surface of the substrate semiconductor layer toward the back side surface of the substrate semiconductor layer.

16. A method of forming a flash memory device, characterized in that: include: Forming a first opening in a doped substrate semiconductor layer having a first conductivity type; forming a tunneling dielectric and a floating gate electrode in the first opening; forming a second opening in the substrate semiconductor layer adjacent to the first opening; forming an erased gate dielectric and an erased gate electrode in the second opening, wherein the erased gate electrode and the floating gate electrode are laterally separated along a first horizontal direction by a first vertical portion of the tunnel dielectric; forming a control gate dielectric and a control gate electrode over the floating gate electrode; and A pair of active regions are formed in the substrate semiconductor layer by implanting a doped dopant having a second conductivity type, wherein the pair of active regions are laterally separated along a second horizontal direction by the floating gate electrode and a second vertical portion of the tunnel dielectric.

17. The method according to claim 16, characterized in that Further including: Depositing a tunnel dielectric layer on a bottom surface and sidewalls of the first opening and over a top surface of the substrate semiconductor layer; depositing a floating gate electrode layer on the tunnel dielectric layer; and Portions of the floating gate electrode layer and the tunneling dielectric layer are removed from above a horizontal plane including the top surface of the substrate semiconductor layer, wherein a remaining portion of the floating gate electrode layer includes the floating gate electrode, and a remaining portion of the tunneling dielectric layer includes the tunneling dielectric.

18. The method according to claim 16, characterized in that Further including: Depositing a wipe-off gate dielectric layer on a bottom surface and sidewalls of the second opening and over a top surface of the substrate semiconductor layer; depositing an erase gate electrode layer on the erase gate dielectric layer; and Portions of the erase gate electrode layer and the erase gate dielectric layer are removed from above a horizontal plane including the top surface of the substrate semiconductor layer, wherein a remaining portion of the erase gate electrode layer includes the erase gate electrode, and a remaining portion of the erase gate dielectric layer includes the erase gate dielectric.

19. The method according to claim 16, characterized in that Further including: Depositing a control gate dielectric layer on the floating gate electrode, the erase gate electrode and the substrate semiconductor layer; depositing a control gate electrode layer on the control gate dielectric layer; Using a patterned photoresist layer to mask a portion of the control gate electrode layer, the portion covering the floating gate electrode; and The control gate electrode layer and the control gate dielectric layer are anisotropically etched using the patterned photoresist layer as an etching mask, wherein a patterned portion of the control gate electrode layer includes the control gate electrode, and a patterned portion of the control gate dielectric layer includes the control gate dielectric.

20. The method of claim 16, wherein: in: The pair of active regions are formed on opposite sides of the floating gate electrode and are laterally spaced apart along the second horizontal direction perpendicular to the first horizontal direction.

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