Direct current conversion circuit

Abstract

Embodiments of the present disclosure provide a direct current conversion circuit. The direct current conversion circuit includes a first transistor coupled between a first power supply and a switching node, a second transistor coupled between the switching node and a ground, and a protection circuit coupled to the switching node and configured to adjust a turn-on speed of the second transistor based on a voltage of the switching node to prevent the first transistor and the second transistor from being turned on at the same time. According to embodiments of the present disclosure, the turn-on speed of the transistors can be adjusted and, thereby, the risk of short-circuit damage of the transistors is reduced.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the field of electronic circuits, and more particularly, to a direct current conversion circuit with transistor protection feature. BACKGROUND

[0002] Direct current conversion circuits such as buck circuits, boost circuits, buck-boost circuits, etc. have been widely used in consumer electronics, industry, communication networks, automotive electronics, etc. In a direct current conversion circuit, transistors are usually provided to change the flow direction of power to achieve a desired voltage conversion level. Each transistor is usually provided with a dedicated or common drive circuit to control its turn-on and turn-off. Although a typical direct current conversion circuit is also provided with a circuit to prevent more than two transistors on the same branch from being turned on at the same time to avoid short circuit, in some operating conditions, there is still a risk of different transistors being turned on at the same time. This can cause a very high current to flow through the transistors, and thus cause damage to the transistors and other circuit components. Therefore, there is a need for improved circuit design with a protection feature for transistors. SUMMARY

[0003] Embodiments of the present disclosure provide an improved solution for protecting transistors in a direct current conversion circuit from short circuit damage.

[0004] In one aspect of the present disclosure, a direct current conversion circuit is provided. The direct current conversion circuit includes a first transistor coupled between a first power supply and a switching node, a second transistor coupled between the switching node and a ground, and a protection circuit coupled to the switching node and configured to adjust a turn-on speed of the second transistor based on a voltage of the switching node to prevent the first transistor and the second transistor from being turned on at the same time.

[0005] According to embodiments of the present disclosure, the safety and reliability of the direct current conversion circuit can be further improved.

[0006] The summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. The summary is not intended to identify key features or essential features of the disclosure, and is not intended to limit the scope of the disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0007] The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings in which like reference characters refer to like parts throughout the figures, and in which:

[0008] Figure 1 a schematic circuit diagram of a direct current conversion circuit is shown;

[0009] Figure 2 a schematic flowchart illustrating the operation timing of the DC conversion circuit;

[0010] Figure 3 a schematic waveform illustrating the switch node voltage (V SW ) of the DC conversion circuit;

[0011] Figure 4 a schematic circuit diagram of the DC conversion circuit according to one embodiment of the present disclosure;

[0012] Figure 5 a schematic block diagram of the protection circuit of the DC conversion circuit according to one embodiment of the present disclosure; and

[0013] Figure 6 a schematic circuit diagram of the protection circuit of the DC conversion circuit according to one embodiment of the present disclosure. DETAILED DESCRIPTION

[0014] The principles of the present disclosure will now be described with reference to a number of example embodiments illustrated in the drawings. While the preferred embodiments of the present disclosure are shown in the drawings, it is understood that the embodiments are merely for the purpose of better understanding the present disclosure and implementing the same, and are not intended to limit the scope of the present disclosure in any way.

[0015] The term "comprising" and variations thereof as used herein are intended to mean "including but not limited to." The term "or" as used herein is intended to mean "and / or." The term "based on" means "based, at least in part, on." The term "one example embodiment" and "an embodiment" means "at least one example embodiment." The term "another embodiment" means "at least one additional embodiment." The terms "a first," "a second," etc. can refer to different or the same objects. Other explicitly and implicitly recited definitions can also be included below.

[0016] It can be understood that the circuit elements such as resistors, capacitors, or inductors, etc. shown in singular form herein are not limited to a single device, but can include parallel or series connection of multiple devices having the same or similar functions. For example, a single resistor can include series, parallel, or mixed connection of multiple resistors.

[0017] As previously mentioned, the DC conversion circuits that are currently widely used are typically equipped with protection circuits that prevent simultaneous conduction of switching devices (such as transistors) in the same leg. Such protection circuits are necessary because simultaneous conduction of transistors in the same leg would result in very high currents flowing through the transistors and, thus, can result in damage to the transistors and other circuit components. As will be discussed below, conventionally implemented DC conversion circuits typically only provide rudimentary short circuit protection that often fails to meet protection requirements under certain operating conditions, particularly during transient processes such as transistor switching. The DC conversion circuit according to embodiments of the present disclosure is capable of automatically adjusting the speed at which transistors are turned on in accordance with the operating conditions of the circuit, thereby avoiding the occurrence of excessively high transient values during the transient period of transistor turn-on that are prone to causing short circuit phenomena.

[0018] Figure 1 A schematic circuit diagram of a DC conversion circuit 100 is shown. As an example, the DC conversion circuit 100 is a DC buck circuit. It is to be understood that embodiments of the present application are not limited to DC buck circuits. In some embodiments, the DC conversion circuit can comprise a boost circuit, a buck-boost circuit.

[0019] In the DC conversion circuit 100, a high-side transistor (or first transistor, HS) 124 and a low-side transistor (or second transistor, LS) 126, which are main switching devices, are shown connected in series with an input voltage node (VIN) 104 and a ground node (PGND) 114. The HS 124 and the LS 126 each include an anti-parallel diode as part thereof. The HS 124 and the LS 126 are driven by a HS drive circuit 120 and a LS drive circuit 122, respectively.

[0020] The HS drive circuit (first drive circuit) 120 is powered by a supply voltage (BOOT) 102, one input of which is connected to a HS control node 106 via a low-to-high voltage (L2H) circuit. The HS control node (HSON) 106 inputs a signal for controlling the HS 124, where a high level signal ("1") indicates turning on the HS 124 and a low level signal ("0") indicates turning off the HS 124.

[0021] The LS drive circuit (second drive circuit) 122 is powered by VCC, one input of which is connected to a LS control node 108 via a supply domain conversion circuit (LVL). The LVL is used to implement a supply domain conversion from VDD to VCC. The LS control node (LSON) 108 inputs a signal for controlling the LS 126, where a high level signal ("1") indicates turning on the LS 126 and a low level signal ("0") indicates turning off the LS 126.

[0022] A switch node (SW) 110 is disposed between the HS 124 and the LS 126. A boot capacitor (Cboot) 130 is connected in parallel with the HS drive circuit 120 between the BOOT 102 and the SW 110. The boot capacitor 130 is mainly used to provide sufficient energy required to guarantee the ability to achieve correct logic and output drive capability to the HS drive circuit 120. Since the voltage difference (V BOOT -V SW ) across the boot capacitor 130 is the same as the voltage difference (V BOOT -V SW ) across the BOOT 102 and the SW 110, it is possible to determine whether the boot capacitor 130 needs to be charged to replenish energy by detecting the value of V BOOT -V SW . The charging of the boot capacitor 130 can be achieved by turning on the LS 126.

[0023] A supply voltage detection circuit 132 is also connected in parallel between the BOOT 102 and the SW 110 and is used to detect the voltage difference V BOOT -V SW as described above. The supply voltage detection circuit 132 outputs a signal BOOTUV_HV which switches to high (“1”) when V BOOT -V SW is below a first threshold voltage, such as 2V, which indicates that there is an under-voltage between the BOOT 102 and the SW 110, and therefore the boot capacitor 130 needs to be charged by, for example, turning on the LS 126. The BOOTUV_HV switches from high to low (“0”) when V BOOT -V SW is above a second threshold voltage, such as 2.2V, which indicates that the voltage between the BOOT 102 and the SW 110 meets the requirement and the HS drive circuit 120 can work normally, where the second threshold voltage is greater than the first threshold voltage. The supply voltage detection circuit 132 is connected to a second input terminal of the LS drive circuit 122 via a high-to-low (H2L) circuit.

[0024] One end of an output inductor 134 is connected to the SW 110 and the other end is connected to an output voltage node (VOUT) 112. One end of an output capacitor 136 is also connected to the VOUT 112 and the other end is connected to ground. The output inductor 134 and the output capacitor 136 form an LC resonant circuit.

[0025] The simultaneous conduction prevention circuit (XCON) 128 receives the output signal HSG from the HS drive circuit 120 and the output signal LSG from the LS drive circuit 122, and outputs to the second input terminal of the HS drive circuit 120 and the third input terminal of the LS drive circuit 122, respectively. The XCON 128 functions to prevent simultaneous conduction of the HS 124 and the LS 126.

[0026] For the purpose of illustrating the working principle of the XCON 128, reference is made below to Figure 2 , Figure 2 A schematic flowchart of the working timing 200 of the DC conversion circuit 100 is shown.

[0027] The working timing 200 starts at block 202, where the DC conversion circuit 100 is in an OFF state, and the HS 124 and the LS 126 are in an OFF state. At block 204, the DC conversion circuit 100 is powered on, and if the voltage difference V BOOT -V SW satisfies the requirement (e.g., detected by the power supply detection circuit 132 as being greater than a second threshold voltage), the HS 124 is controlled by the HS drive circuit 120 to be turned on, such that the HS 124 is in an ON state.

[0028] At this time, V SW is equal to the input voltage V IN 104, and V IN104 is charged via the output inductor 134. When the HS 124 on-time reaches a predetermined target value, at block 206, the HS 124 is turned off by the HS drive circuit 120 so that the HS 124 is in the off state. Then, at block 208, it is detected by the XCON 128 whether the HS 124 is in the off state (e.g., by the HSG), and if the result is yes, the operation sequence jumps to block 210, otherwise it jumps to block 208 until the result is yes. At block 210, the LS 126 is turned on by the LS drive circuit 122 so that the LS 126 is in the on state. Thus, blocks 208 and 210 achieve that the LS 126 is on if and only if the HS 124 is in the off state. When the LS 126 on-time reaches a predetermined target value, at block 212, the LS 126 is turned off by the LS drive circuit 122 so that the LS 126 is in the off state. Similarly, at block 214, it is detected by the XCON 128 whether the LS 126 is in the off state (e.g., by the LSG), and if the result is yes, the operation sequence jumps to block 204 to turn on the HS 124, otherwise it jumps to block 214 until the result is yes. Blocks 214 and 204 achieve that the HS 124 is on if and only if the LS 126 is in the off state. The operation sequence 200 then loops until the DC-DC converter 100 is in the non-operation state again.

[0029] Although it can be seen from Figure 2 that the XCON 128 can achieve the purpose of preventing the simultaneous on of the HS 124 and the LS 126 during normal operation, in some other cases, the XCON 128 can hardly meet the protection requirement.

[0030] Now back to Figure 1 , Figure 1 It is also shown that a pre-bias voltage circuit is connected to the VOUT 112. The pre-bias voltage circuit is formed by a pre-bias voltage source 138 and a diode (Dl) 140, and is mainly used to pre-load voltage when the DC-DC converter 100 starts. Assuming that the voltage of the pre-bias voltage source 138 is V PB , then V OUT = V PB -V D1 when the DC-DC converter 100 starts. Thus, V OUT will raise the value of V SW . At this time, V BOOT -V SWsmaller, so that the power supply detection circuit 132 is more likely to output the high level of BOOTUV_HV indicating the presence of an under-voltage. Since BOOTUV_HV is input to the LS drive circuit 122 directly via H2L, the LS 126 will be turned on quickly, causing a rapid drop in V SW . Since the HS drive circuit 120 has not yet loaded V BOOT , it lacks driving ability, and due to factors such as the parasitic capacitance present at the HS drive circuit 120, the HS 124, and the SW node, the rapid drop in V SW will couple the gate-source voltage Vgs of the HS 124 to an undesirable value. If during this time the gate-source voltage Vgs is raised above the turn-on voltage of the HS 124, the phenomenon of simultaneous turn-on of the HS 124 and the LS 126 will occur, causing a large current to flow in both the HS 124 and the LS 126 to cause damage to both the HS 124 and the LS 126. Furthermore, the higher the value of V PB , the faster the turn-on speed of the LS 126, the greater the rate and amplitude of the drop in V SW , the higher the value of the coupled Vgs of the HS 124, and the higher the risk of short-circuiting and damage to both the HS 124 and the LS 126.

[0031] In another scenario, assume that the DC conversion circuit 100 is operating in light-load DCM (discontinuous conduction mode). At this time, there is a period in which the HS 124 and the LS 126 are both in the off state, and in this period V SW = V OUT . At this time, if there is a static current in the HS drive circuit 120, the static current will continuously discharge the bootstrap capacitor 130. When the bootstrap capacitor 130 is discharged such that V BOOT -V SW is lower than the first threshold voltage, the LS 126 will be turned on to charge the bootstrap capacitor 130. Since at this time the value of V BOOT -V SW is relatively low, the driving ability is weak, so there is also a situation in which V SW drops rapidly and the gate-source voltage Vgs of the HS 124 is raised. When Vgs is raised above the turn-on voltage of the HS 124, the phenomenon of simultaneous turn-on of the HS 124 and the LS 126 will occur, causing a large current to flow in both the HS 124 and the LS 126 to cause damage to both the HS 124 and the LS 126.

[0032] Referring to Figure 3 , Figure 3 , a graph showing the switching node voltage V SWthe exemplary waveform 300. Waveform 300 represents V SW the relative amplitude, and corresponds to the DCM mode of operation described above. From Figure 3 It can be seen that V SW initially equals V OUT and subsequently changes due to HS 124 and LS 126 being turned on, respectively. Thereafter, V SW = V OUT At 302, the situation occurs where LS 126 is turned on quickly to charge bootstrap capacitor 130. It can be seen that the higher the value of V OUT the faster LS 126 is turned on, the greater the rate and magnitude of the drop of V SW and the higher the value of Vgs of the coupled HS 124, resulting in a higher risk of both HS 124 and LS 126 shorting and being damaged.

[0033] In yet another scenario, the parasitic capacitance at SW 110 is large, either inherently due to the circuit or due to the human setup of the buffer circuit. Under light load conditions, the parasitic capacitance at SW 110 can satisfy the load current demand during the dead time before LS 126 is turned on while HS 124 is turned off. Thus, V SW does not drop as usual through the freewheeling diode of LS 126, but remains high due to the discharge of the parasitic capacitance at SW 110. As a result, after the dead time ends, if LS 126 is turned on quickly, there is again a situation of V SW quickly dropping, and can eventually lead to both HS 124 and LS 126 shorting and being damaged. The smaller the peak inductor current, the higher V IN the faster LS 126 is turned on, the greater the rate and magnitude of the drop of V SW and the higher the value of Vgs of the coupled HS 124, resulting in a higher risk of both HS 124 and LS 126 shorting and being damaged.

[0034] It can be seen that under the various transient operating conditions exemplified above, XCON 128 will have difficulty meeting the requirement of protecting both HS 124 and LS 126 from shorting and damage. To this end, there is a need for improvement of DC conversion circuit 100 to enhance safety.

[0035] A DC conversion circuit according to embodiments of the present disclosure will be described in detail below.

[0036] Reference is first made to Figure 4 , Figure 4A schematic circuit diagram of a direct conversion circuit 400 according to one embodiment of the present disclosure is shown. The direct conversion circuit 400 is similar to the direct conversion circuit 100 shown in Figure 1 Thus, similar elements have the same or similar reference numbers, and operate in the same or similar manner, and so are not further described.

[0037] The direct conversion circuit 400 also includes a high-side transistor HS 124 and a low-side transistor LS 126. In some embodiments, the transistors can include, but are not limited to, bipolar transistors, metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar transistors (IGBTs), and combinations thereof. The HS 124 is driven by the HS drive circuit 120, and the LS 126 is driven by the LS drive circuit 122.

[0038] The direct conversion circuit 400 differs from the direct conversion circuit 100 shown in Figure 1 that the direct conversion circuit 400 is further provided with a protection circuit 420 connected between the power supply detection circuit 132 and the LS drive circuit 122. The protection circuit 420 receives signals from the power supply detection circuit 132, the switch node SW 110, and the HS control node HSON 106, and outputs a conduction control signal (LSD_speed) at its output 404 to the second input terminal of the LS drive circuit 122 based on at least one of the signals from the power supply detection circuit 132, the switch node SW 110, and the HS control node HSON 106. In one example, the conduction control signal (LSD_speed) at its output 404 to the second input terminal of the LS drive circuit 122 is outputted based on all three of the signals from the power supply detection circuit 132, the switch node SW 110, and the HS control node HSON 106.

[0039] The signal BOOTUV_HV outputted by the power supply detection circuit 132 is converted to the signal BOOTUV by the H2L circuit, and is inputted to the protection circuit 420 at the node 402. The protection circuit 420 determines whether the LS 126 should be turned on fast or slow based on V SW , BOOTUV, and HSON, and outputs the LSD_speed signal to control the LS drive circuit 122 to adjust the speed at which the LS 126 is turned on. Slowly turning on the LS 126 can effectively prevent the situation where the HS 124 and the LS 126 are turned on at the same time due to the fast drop of V SW The working principle of the protection circuit 420 will be described in detail below.

[0040] Furthermore, for the purpose of clarity, Figure 4 the direct conversion circuit 400 in Figure 1the pre-bias voltage circuit shown in FIG. 4. It can be appreciated that in one example, the DC conversion circuit 400 can include Figure 1 the pre-bias voltage circuit shown in FIG. 4.

[0041] Reference is now made to Figure 5 , Figure 5 A schematic block diagram of a protection circuit 420 of the DC conversion circuit 400 according to one embodiment of the disclosure is shown. The protection circuit 420 includes a delay circuit 502, a switch node detection circuit 504, a latch circuit 506, a capacitor voltage detection circuit 508, and a logic AND gate 510.

[0042] The delay circuit 502 receives and delays the signal from the HSON 106. In some embodiments, the delay circuit 502 only delays the falling edge of the HSON signal from high to low, but not the high level HSON signal. In some embodiments, the delay circuit 502 can be implemented by an RC delay circuit, a 555 timer circuit, a monostable delay circuit, and a transistor delay circuit. In some embodiments, the time of delay by the delay circuit 502 is predetermined by the switching characteristics of the LS 126.

[0043] The delay circuit 502 outputs a signal SWHi_Clear, and also outputs a signal to the logic AND gate 510. When the HSON signal is high, the SWHi_Clear is also high. The high level SWHi_Clear signal enables the switch node detection circuit 504, while the low level SWHi_Clear signal disables the switch node detection circuit 504. When the HSON signal switches from high to low, the SWHi_Clear signal also switches from high to low after being delayed, while when the HSON signal switches from low to high, the SWHi_Clear signal switches from low to high without being delayed. The signal output by the delay circuit 502 to the logic AND gate 510 is low when the HSON signal is high, and is high when the HSON signal is low. In other words, the delay circuit 502 also outputs the inverse of the HSON signal.

[0044] The switch node detection circuit 504 receives the signal from the SW 110 and the SWHi_Clear signal, and outputs a SW_Hi signal to the latch circuit 506. In some embodiments, when the SWHi_Clear signal is low, the switch node detection circuit 504 is disabled, thereby causing the switch node detection circuit 504 to output a low level SW_Hi signal. In some embodiments, when the SWHi_Clear signal is low, the switch node detection circuit 504 is enabled, and outputs the SW_Hi signal based on V SWthe value of V SW the value of V SW the value of V SW is sufficiently large.

[0045] Latch circuit 506 receives SWHi_Clear signal and SW_Hi signal, and outputs a signal to logic AND gate 510 based on these two signals. In some embodiments, when SWHi_Clear signal is low, latch circuit 506 is in a hold mode, thereby causing the output signal of latch circuit 506 to persist in the previous state. In some embodiments, when SWHi_Clear signal is high, the output signal of latch circuit 506 is the inverse of SW_Hi signal. In other words, when SWHi_Clear signal is high and SW_Hi signal is low, latch circuit 506 outputs a high signal. When SWHi_Clear signal is high and SW_Hi signal is high, latch circuit 506 outputs a low signal. In some embodiments, the above-described latching function of latch circuit 506 can be implemented with a commonly used latch architecture, or with discrete logic elements.

[0046] Capacitor voltage detection circuit 508 receives BOOTUV signal, and outputs the inverse of BOOTUV signal to logic AND gate 510. In other words, when supply voltage detection circuit 132 detects that the voltage difference across bootstrap capacitor 130 is less than a predetermined threshold, such as the first threshold voltage described above, capacitor voltage detection circuit 508 outputs a low signal to logic AND gate 510.

[0047] The AND gate 510 receives output signals from the delay circuit 502, the switch node detection circuit 504, the latch circuit 506, and the capacitor voltage detection circuit 508, and outputs the result of the AND operation of these output signals as the LSD_speed signal. The LSD_speed signal is further input to the LS driver circuit 122 to control whether the LS driver circuit 122 quickly turns on LS 126. When the LSD_speed signal is high, fast turn-on of LS 126 is allowed; when the LSD_speed signal is low, slow turn-on of LS 126 is allowed. Thus, the protection circuit 420 controls whether LS 126 is turned on quickly or slowly. In this document, fast turn-on of LS 126 means that the transistor used to drive LS 126 in the driver circuit 122 is larger, resulting in a faster turn-on speed for LS 126. The turn-on speed of LS 126 can be adjusted by selecting or adjusting transistors of different sizes in the drive circuit 122 (e.g., by the LSD_speed signal). In some embodiments, the turn-on time of LS 126 under fast turn-on conditions is 1 / 5 to 1 / 10 of the turn-on time of LS 126 under slow turn-on conditions.

[0048] Specifically, in protection circuit 420, V is only allowed during the delay time (dead time) after HSON is in the high-to-low level step transition. SW Below the predetermined threshold, and V BOOT -V SW The LS 126 is only allowed to turn on rapidly when the voltage exceeds another predetermined threshold (such as the second threshold voltage described above). Otherwise, due to V... SW V BOOT -V SW The values ​​of these parameters do not meet the requirements for fast turn-on, so only slow turn-on of LS 126 is allowed. This avoids short circuits and damage to both HS 124 and LS 126 caused by fast turn-on of LS 126.

[0049] It should be understood that Figure 5 The architecture of the protection circuit 420 shown is merely an example, and those skilled in the art can conceive of other embodiments for determining the transistor's turn-on speed condition. For example, Figure 5 The AND gate 510 in the circuit can be replaced by a NAND gate. In this case, the same function can be achieved by inverting the output signals from the delay circuit 502, the switch node detection circuit 504, the latch circuit 506, and the capacitor voltage detection circuit 508.

[0050] The following reference Figure 6 The following describes a specific structural example of the protection circuit 420.Figure 6 A schematic circuit diagram of the protection circuit 420 of the direct current conversion circuit 400 according to one embodiment of the present disclosure is shown.

[0051] In Figure 6 , the delay circuit 502 includes a delay circuit 602 and an inverter 604, both of which are connected to the HSON node 106. The delay circuit 602 receives the HSON signal and delays the falling edge of the high-to-low transition of the HSON signal. In other words, when the HSON signal transitions from high to low, the delay circuit 602 also outputs a high-to-low transition of the SWHi_Clear signal after a delay time. The inverter 604 outputs the inverse of the HSON signal. Thus, the inverter 604 outputs a high signal only when the HSON signal is low.

[0052] The switch node detection circuit 504 includes transistors 606 and 610, a resistor 608, a flip-flop 612, and an inverter 614. The transistor 606, the resistor 608, and the transistor 610 are connected in series, and the source of the transistor 606 is connected to the SW 110. The SW_LV node is the node between the resistor 608 and the source of the transistor 610. In some embodiments, the transistors 606 and 610 can include, but are not limited to, bipolar transistors, metal oxide semiconductor field effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs), and combinations thereof.

[0053] When the SWHi_Clear signal is low, the input node SW_LV of the flip-flop 612 is at low (ground) because the transistor 606 is off and the transistor 610 is on, thus causing the flip-flop 612 to output a low SW_Hi signal. At this time, the switch node detection circuit 504 is in a disabled state. When the SWHi_Clear signal is high, the transistor 606 is on and the transistor 610 is off. At this time, the voltage at SW_LV is positively correlated with V SW . When V SW is higher than a predetermined threshold, the voltage at SW_LV causes the flip-flop 612 to output a SW_Hi signal with a high level, and when V SW is lower than the predetermined threshold, the voltage at SW_LV causes the flip-flop 612 to output a SW_Hi signal with a low level. Thus, the high and low levels of the SW_Hi signal represent the magnitude of V SW . The flip-flop 612 functions to output a SW_Hi signal with standard high and low levels, and can take various suitable forms such as a Schmitt trigger.

[0054] The latch circuit 506 includes logic OR gates 616 and 620 and inverters 618 and 622. As mentioned above, when the SWHi_Clear signal is low, the latch circuit 506 is in a hold mode, and when the SWHi_Clear signal is high, the output signal of the latch circuit 506 is the inverse of the SW_Hi signal.

[0055] The capacitor voltage detection circuit 508 includes an inverter 624 to output the inverse of the BOOTUV signal from 402.

[0056] Finally, the logic AND gate 510 outputs the logical AND operation result of the output signals as the LSD_speed signal.

[0057] Figure 6 The illustrated schematic circuit diagram further illustrates the working principle of the protection circuit 420. Specifically, when the HSON signal is high, it indicates that the HS 124 is being turned on, whereby the inverter 604 outputs a low signal to set the LSD_speed signal to low, thereby disabling the high speed turn-on of the LS 126. Subsequently, if the HSON signal is detected to transition from high to low, the SWHi_Clear still remains high for the delay time of the delay circuit 602. During the delay time, the switch node detection circuit 504 is enabled and outputs a high or low SW_Hi signal depending on the magnitude of VSW, and thereby triggers the latch circuit 506 to output the inverse of the SW_Hi signal. In other words, if VSW is greater than a predetermined threshold, the latch circuit 506 outputs a low signal to disable the high speed turn-on of the LS 126, and if VSW is less than the predetermined threshold, the latch circuit 506 outputs a high signal to possibly enable the high speed turn-on of the LS 126. Further, if the HSON signal is detected to transition from high to low beyond the delay time, the switch node detection circuit 504 is disabled and the high speed turn-on of the LS 126 is disabled. In either of the above cases, if the BOOTUV signal with high is input at 402, the inverter 624 outputs a low signal to disable the high speed turn-on of the LS 126. SW greater than a predetermined threshold, the latch circuit 506 outputs a low signal to disable the high speed turn-on of the LS 126, and if VSW is less than the predetermined threshold, the latch circuit 506 outputs a high signal to possibly enable the high speed turn-on of the LS 126. Further, if the HSON signal is detected to transition from high to low beyond the delay time, the switch node detection circuit 504 is disabled and the high speed turn-on of the LS 126 is disabled. In either of the above cases, if the BOOTUV signal with high is input at 402, the inverter 624 outputs a low signal to disable the high speed turn-on of the LS 126. SW less than the predetermined threshold, the latch circuit 506 outputs a high signal to possibly enable the high speed turn-on of the LS 126. Further, if the HSON signal is detected to transition from high to low beyond the delay time, the switch node detection circuit 504 is disabled and the high speed turn-on of the LS 126 is disabled. In either of the above cases, if the BOOTUV signal with high is input at 402, the inverter 624 outputs a low signal to disable the high speed turn-on of the LS 126.

[0058] In summary, the high speed turn-on of the LS 126 is enabled if and only if the HSON is in the delay time after the high to low step, VSW is less than the predetermined threshold, and VBOOTUV is high. SW less than the predetermined threshold, the latch circuit 506 outputs a high signal to possibly enable the high speed turn-on of the LS 126. Further, if the HSON signal is detected to transition from high to low beyond the delay time, the switch node detection circuit 504 is disabled and the high speed turn-on of the LS 126 is disabled. In either of the above cases, if the BOOTUV signal with high is input at 402, the inverter 624 outputs a low signal to disable the high speed turn-on of the LS 126. BOOT -V SWThe fast conduction of the LS 126 is allowed only when the voltage is higher than, for example, the second threshold voltage. In other cases, the fast conduction of the LS 126 is prohibited. It can be seen that the direct current conversion circuit according to the embodiments of the present disclosure realizes the control of the conduction speed of the LS 126, and thereby realizes the transistor short-circuit protection for the transient process, improving the operation safety and reliability of the direct current conversion circuit.

[0059] Although Figure 4 The direct current conversion circuit 400 shown in FIG. 4 is in the form of a step-down circuit, but those skilled in the art should understand that the direct current conversion circuit 400 can also be a step-up circuit. Since there is also a risk of short circuit and damage due to the fast conduction of the transistor in the direct current step-up circuit, the direct current conversion circuit according to the embodiments of the present disclosure can also be applied to the step-up circuit.

[0060] The above description is only optional embodiments of the present disclosure and is not intended to limit the present disclosure. Those skilled in the art can make various modifications and changes to the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A DC-DC converter circuit, comprising: The first transistor is coupled between the first power supply and the switching node; The second transistor is coupled between the switching node and ground; as well as A protection circuit, coupled to the switching node, is configured to adjust the turn-on speed of the second transistor based on the voltage of the switching node to prevent the first transistor and the second transistor from turning on simultaneously. The DC-DC conversion circuit further includes: A first driving circuit is coupled to the first transistor and powered by a second power source; A second driving circuit is coupled to the second transistor; and A power supply detection circuit is connected in parallel between the second power supply and the switching node. The protection circuit includes: A delay circuit, coupled to the first driving circuit, is configured to delay the input signal from the first driving circuit; A switch node detection circuit, coupled to the delay circuit, is configured to generate a signal indicating the magnitude of the voltage at the switch node; A latching circuit is coupled to the delay circuit and the switching node detection circuit; The capacitor voltage detection circuit is coupled to the power supply detection circuit; and A logic AND gate is configured to receive multiple output signals from the delay circuit, the switch node detection circuit, the latch circuit, and the capacitor voltage detection circuit, and to generate a logic AND signal of the multiple output signals.

2. The DC-DC conversion circuit according to claim 1, wherein the protection circuit is further configured to adjust the turn-on speed of the second transistor based on the output signal of the power supply detection circuit.

3. The DC-DC conversion circuit according to claim 1, wherein the protection circuit is further configured to adjust the conduction speed of the second transistor based on the control signal of the first drive circuit.

4. The DC-DC conversion circuit according to claim 1, wherein the DC-DC conversion circuit includes a buck circuit, a boost circuit, and a buck-boost circuit.

5. The DC-DC conversion circuit according to claim 1 further includes: A bootstrap capacitor is coupled in parallel between the second power source and the switching node.

6. The DC-DC converter circuit according to claim 1, wherein the switching node is coupled to the output node of the DC-DC converter circuit via an LC oscillation circuit.

7. The DC-DC converter circuit according to claim 1, wherein the protection circuit comprises: A switch node detection circuit, coupled to the switch node, is configured to generate a first signal indicating the magnitude of the voltage at the switch node; as well as A logic circuit is configured to generate a control signal based on the first signal to adjust the conduction speed of the second transistor.

8. The DC-DC converter circuit according to claim 7, wherein the protection circuit further comprises: A delay circuit, coupled to the first driving circuit, is configured to delay an input signal from the first driving circuit and generate a second signal based on the input signal; as well as A latching circuit, coupled to the delay circuit and the switching node detection circuit, is configured to generate a third signal based on the delayed input signal and the first signal; The logic circuitry is further configured to generate the control signal based on the second signal and the third signal.

9. The DC-DC converter circuit according to claim 7, wherein the protection circuit further comprises: A capacitor voltage detection circuit is coupled to the power supply detection circuit and configured to generate a fourth signal based on the output signal of the power supply detection circuit; The logic circuit is further configured to generate the control signal based on the fourth signal.

10. The DC-DC conversion circuit of claim 8, wherein the duration of the delay is predetermined based on the switching characteristics of the second transistor.

11. A DC-DC converter circuit, comprising: The first transistor is coupled between the first power supply and the switching node; The second transistor is coupled between the switching node and ground; A first driving circuit is coupled to the first transistor and powered by a second power supply to drive the first transistor. A second driving circuit is coupled to the second transistor to drive the second transistor; A power detection circuit is coupled in parallel between the second power supply and the switching node; as well as The protection circuit is configured to adjust the turn-on speed of the second transistor based on at least one of the voltage of the switching node, the output signal of the power supply detection circuit, and the input signal of the first drive circuit. The protection circuit includes: A switch node detection circuit, coupled to the switch node, and configured to generate a first signal indicating the amplitude of the voltage at the switch node; and A logic circuit is configured to generate a control signal based on the first signal to adjust the conduction speed of the second transistor. The protection circuit further includes: A delay circuit, coupled to the first driving circuit, is configured to delay the input signal from the first driving circuit and generate a second signal based on the input signal; and A latching circuit, coupled to the delay circuit and the switching node detection circuit, is configured to generate a third signal based on the delayed input signal and the first signal; The logic circuitry is further configured to generate the control signal based on the second signal and the third signal.

12. The DC-DC conversion circuit according to claim 11, wherein the DC-DC conversion circuit includes a buck circuit, a boost circuit, and a buck-boost circuit.

13. The DC-DC conversion circuit according to claim 11, further comprising: A bootstrap capacitor is coupled in parallel between the second power source and the switching node and is configured to store the energy required for the normal operation of the first drive circuit.

14. The DC-DC converter circuit of claim 11, wherein the switching node is coupled to the output node of the DC-DC converter circuit via an LC oscillator circuit.

15. The DC-DC converter circuit according to claim 11, wherein the protection circuit further comprises: A capacitor voltage detection circuit is coupled to the power supply detection circuit and configured to generate a fourth signal based on the output signal of the power supply detection circuit; The logic circuit is further configured to generate the control signal based on the fourth signal.

16. The DC-DC conversion circuit of claim 11, wherein the delay time of the delay circuit is predetermined based on the switching characteristics of the second transistor.

Images