Display module and method for manufacturing display module

Abstract

A display module includes: a glass substrate; a thin film transistor layer, which is arranged in a first area of ​​the glass substrate; a plurality of connection pads, which are arranged in a second area extending from the first area of ​​the glass substrate and are electrically connected to the thin film transistor layer; a plurality of test pads, which are arranged in a third area extending from the second area of ​​the glass substrate and are electrically connected to the plurality of connection pads, respectively; and a plurality of connection wirings, which electrically connect the plurality of connection pads and the plurality of test pads.

Description

Technical Field

[0001] Devices and methods consistent with the present disclosure relate to a display module structure and a manufacturing method thereof, wherein the display module structure includes a thin film transistor substrate in a self-luminous display device using light emitting diodes (LEDs), a plurality of LEDs are mounted on the thin film transistor substrate, and the thin film transistor substrate can be easily tested and manufactured. Background Art

[0002] A self-luminous display element that displays an image without using a color filter and a backlight may use an LED inorganic self-luminous element that emits light by itself.

[0003] The LED is operated by a thin film transistor (TFT), and is provided on a thin film transistor substrate including a plurality of thin film transistors.

[0004] The manufactured thin film transistor substrate determines whether the manufactured thin film transistor substrate is electrically operable by applying an electric signal to a connection pad formed on the thin film transistor substrate and transmitting the electric signal to the LED.

[0005] However, in electrical testing of a thin film transistor substrate of a display module, when the size of an LED and the size of a corresponding connection pad are reduced, it may be difficult to perform the electrical testing of the thin film transistor substrate. Summary of the invention

[0006] Technical issues

[0007] Provided are a display module having a thin film transistor substrate with improved electrical test convenience and manufacturing efficiency and a method for manufacturing the display module.

[0008] Technical Solution

[0009] According to an embodiment, a display module is provided, including: a glass substrate; a thin film transistor layer, which is arranged in a first area of ​​the glass substrate; a plurality of connection pads, which are arranged in a second area extending from the first area of ​​the glass substrate and are electrically connected to the thin film transistor layer; a plurality of test pads, which are arranged in a third area extending from the second area of ​​the glass substrate and are electrically connected to the plurality of connection pads, respectively; and a plurality of connection wirings, which electrically connect the plurality of connection pads and the plurality of test pads.

[0010] A plurality of connection wirings may be disposed in the second and third regions of the glass substrate. The plurality of connection wirings may include at least one of molybdenum (Mo), titanium (Ti), and TiMo, and insulating layers may be disposed above and below the plurality of connection wirings, respectively.

[0011] The plurality of test pads may be removed after performing the substrate test, and the plurality of test pads may be disposed in a zigzag shape along the third region.

[0012] An area of ​​each of the plurality of test pads may be greater than an area of ​​each of the plurality of connection pads.

[0013] The plurality of test pads may be integrally formed with the plurality of connection pads to correspond to each other.

[0014] The display module may further include a plurality of low resistance wirings disposed between each of the plurality of test pads and the plurality of connection wirings.

[0015] The glass substrate may be in a quadrilateral shape, and the third region may include two adjacent side surface portions of the glass substrate.

[0016] The plurality of connection wirings may include a plurality of sub-connection wirings spaced apart from each other by a predetermined interval.

[0017] According to another embodiment, a display module is provided, including: a glass substrate; a thin film transistor layer formed on a first surface of the glass substrate; a plurality of light emitting diodes (LEDs) mounted on the thin film transistor layer; a plurality of connection pads formed on the first surface; a plurality of driving pads formed on a second surface of the glass substrate; a plurality of side wirings configured to electrically connect the plurality of connection pads and a plurality of driving pads corresponding to each of the plurality of connection pads; and a plurality of connection wirings configured to connect the plurality of connection pads and a plurality of test pads in a virtual area extending to an edge area of ​​the glass substrate, wherein the plurality of test pads and portions of each of the plurality of connection wirings corresponding to the plurality of test pads can be removed after performing a substrate test.

[0018] The plurality of connection wirings may be electrically connected to the plurality of side wirings.

[0019] Each of the plurality of connection wirings may be covered with a first insulating layer on one surface and with a second insulating layer on another surface.

[0020] A plurality of connection pads may be integrally formed with the plurality of removed test pads, and one surface of each of the plurality of connection wirings may be connected to the plurality of connection pads.

[0021] Each of the plurality of connection wirings may include a plurality of sub-connection wirings spaced apart from each other by a predetermined interval.

[0022] According to another embodiment, a manufacturing method of a display module is provided, the manufacturing method including: forming a thin film transistor substrate layer of a thin film transistor substrate on a glass substrate; forming a plurality of test pads along a dummy area outside the glass substrate; testing whether the thin film transistor substrate operates by contacting a test needle with the plurality of test pads; removing the dummy area including the plurality of test pads; forming a plurality of side wirings along at least one side surface of the glass substrate from which the dummy area is removed; and transferring a plurality of light emitting diodes (LEDs) onto the thin film transistor layer.

[0023] The forming of the plurality of test pads may further include forming a plurality of connection wirings on the thin film transistor layer, the plurality of connection wirings being configured to electrically connect each of the plurality of thin film transistors and each of the plurality of test pads.

[0024] The forming of the plurality of test pads may further include: forming a first insulating layer on an upper portion of the plurality of connection wirings; and forming a second insulating layer on a lower portion of the plurality of connection wirings.

[0025] Removing the dummy area may further include simultaneously cutting a portion of the glass substrate, a plurality of connection wirings, and the first insulating layer and the second insulating layer by laser.

[0026] The manufacturing method may further include: after removing the dummy area, polishing the removed glass substrate along a cut surface of the glass substrate.

[0027] The manufacturing method may further include: after removing the dummy area, chamfering at least one corner of the cut surface of the glass substrate.

[0028] The forming of the plurality of side wirings may further include: providing the plurality of side wirings to connect a plurality of connection pads provided on one surface of the glass substrate and a plurality of driving pads provided on another surface of the glass substrate.

[0029] According to another embodiment, a display module is provided, including: a glass substrate; a thin film transistor layer, which is arranged on the glass substrate; a plurality of connection pads, which are connected to the thin film transistor layer; a plurality of test pads, which are connected to the plurality of connection pads; and a plurality of connection wirings, which connect the plurality of connection pads and the plurality of test pads. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and / or other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following description with reference to the accompanying drawings, in which:

[0031] Figure 1 is a top view showing a thin film transistor substrate according to an embodiment;

[0032] Figure 2According to the embodiment along Figure 1 A cross-sectional view taken along line AA;

[0033] Figure 3A is a diagram showing the Figure 1 A top view of a dummy area etched in a structure of FIG.

[0034] Figure 3B According to the embodiment along Figure 3A A cross-sectional view taken along line EE of ;

[0035] Figure 3C is a diagram showing a method according to an embodiment of the present invention. Figure 3B A cross-sectional view of the chamfered structure of the structure shown;

[0036] Figure 4A is a diagram showing the Figure 3A A top view of a side wiring formed in a structure;

[0037] Figure 4B According to the embodiment along Figure 4A A cross-sectional view taken along line FF;

[0038] Figure 4C is a block diagram showing a light emitting diode (LED) and a driving driver according to an embodiment;

[0039] Figure 5 is a top view showing an arrangement of a plurality of display modules manufactured according to an embodiment;

[0040] Figure 6 is a flowchart showing a process of manufacturing a thin film transistor substrate according to an embodiment;

[0041] Fig. 7A is a diagram showing a method according to an embodiment of the present invention. Figure 1 an enlarged view of a portion B of;

[0042] Figure 7B is a top view showing another example of the connection wiring according to the embodiment;

[0043] Figure 7C is a top view showing still another example of the connection wiring according to the embodiment;

[0044] Figure 8 is a cross-sectional view showing a thin film transistor substrate according to another embodiment;

[0045] Fig. 9 is a diagram showing a method according to an embodiment of the present invention. Figure 8 A plan view of the second area A2 and the virtual area DA shown;

[0046] Fig.10is a flow chart showing a process of manufacturing a display module using a thin film transistor substrate according to another embodiment;

[0047] Fig.11 is a cross-sectional view showing a display module according to another embodiment;

[0048] Fig.12 is a cross-sectional view showing a thin film transistor substrate according to still another embodiment;

[0049] Fig.13 is a diagram showing a method according to an embodiment of the present invention. Fig.12 A plan view of the second area A2 and the virtual area DA shown;

[0050] Fig.14 is a cross-sectional view showing a display module according to still another embodiment. DETAILED DESCRIPTION

[0051] In order to fully understand the configuration and effect of the present disclosure, the embodiments of the present disclosure will be described with reference to the accompanying drawings. However, the present disclosure is not limited to the embodiments disclosed herein, but can be implemented in various forms and can be modified in various ways. However, the description of the embodiments is provided only to make the present disclosure complete, and to fully inform those skilled in the art of the scope of the present disclosure. In the accompanying drawings, for ease of description, the size of the components is shown to be larger than the actual size, and the proportion of each component can be enlarged or reduced.

[0052] When a component is referred to as being "on another component" or "in contact with another component", it is understood that the component may be directly in contact with or connected to another component, and another component may exist between them. On the other hand, when a component is referred to as being "directly on another component" or "directly in contact with another component", it is understood that a third component may not exist between them. Other expressions describing the relationship between components, such as "between", "directly between", etc., should be interpreted similarly.

[0053] Terms such as "first" and "second" can be used to describe various components, but the components should not be limited by these terms. These terms are only used to distinguish one component from another component. For example, without departing from the scope of the present disclosure, a first component can be referred to as a second component, and similarly, a second component can also be referred to as a first component.

[0054] Singular expressions may include plural expressions unless the context clearly indicates otherwise. The terms "include" or "have" are intended to indicate that the features, quantities, steps, operations, components, parts, or combinations thereof described in the specification are present, and may be interpreted as one or more other features, quantities, steps, operations, components, parts, or combinations thereof may be added.

[0055] The display module according to the present disclosure can be installed and applied to wearable devices, portable devices, handheld devices, and electronic products or electronic devices that require various displays of a single unit, and can be applied to display devices such as monitors of personal computers (PCs), high-resolution TVs and signs (or digital signs), electronic displays, etc. through multiple assembly arrangements of a matrix type.

[0056] Unless otherwise defined, the terms used in the embodiments herein may be construed as terms commonly known to those skilled in the art.

[0057] Below, we will refer to Figure 1 and Figure 2 The structure of the thin film transistor substrate 1 according to the embodiment is described.

[0058] Figure 1 is a top view showing a thin film transistor substrate 1 according to an embodiment, Figure 2 It is along Figure 1 A cross-sectional view taken along line AA.

[0059] The thin film transistor substrate 1 may include a glass substrate 50, a plurality of thin film transistors 70 arranged on a surface 50a of the glass substrate 50, a plurality of connecting pads 20 electrically connected to the plurality of thin film transistors 70 and arranged on a surface 50a of the glass substrate 50, a plurality of test pads 30 arranged along an edge of a surface 50a of the glass substrate 50, and a connecting wiring 40 for electrically connecting each of the plurality of connecting pads 20 and each of the plurality of test pads 30.

[0060] The thin film transistor substrate 1 may operate a plurality of LEDs 90 disposed on the thin film transistor substrate 1 to implement a display screen of a display device.

[0061] The thin film transistor substrate 1 may form a structure in which a thin film transistor layer 140 including a plurality of thin film transistors 70 is coupled to a glass substrate 50 .

[0062] Therefore, the driving driver 130 (eg, Figure 4C As shown in FIG. 1 , the driving driver 130 may be disposed on the thin film transistor substrate 1. In addition, the driving driver 130 may be implemented on the thin film transistor substrate 1 in the form of a chip on glass (COG).

[0063] The glass substrate 50 may form a base layer of the thin film transistor substrate 1 , and the thin film transistor layer 140 may be formed on the glass substrate 50 .

[0064] In particular, the thin film transistor layer 140 may include a plurality of thin film transistors 70 , a plurality of connection pads 20 , a plurality of test pads 30 , and connection wirings 40 .

[0065] The thin film transistor layer 140 may be formed by repeating processes of lamination, etching, etc. on the glass substrate 50 .

[0066] The glass substrate 50 may have predetermined softness, and may be formed of a material having predetermined light transmittance.

[0067] The glass substrate 50 may have a quadrilateral shape.

[0068] The thin film transistor 70 may be disposed on one surface 50 a of the glass substrate 50 , and may be disposed in the thin film transistor layer 140 .

[0069] The thin film transistor 70 may control and drive the plurality of LEDs 90 , and may be electrically connected to at least one LED 90 .

[0070] Therefore, the thin film transistor 70 can selectively drive the LED 90 by controlling the current flowing through the LED 90. That is, the thin film transistor 70 can be used as a switch for controlling a pixel, which is a basic unit of a display.

[0071] For example, the thin film transistor 70 may be electrically connected to a first electrode pad 81 and a second electrode pad 82 disposed on the thin film transistor 70 .

[0072] Therefore, the thin film transistor 70 receiving the electrical signal for driving the LED 90 from the driving driver 130 may control the operation of the LED 90 by selectively allowing current to flow to the LED 90 through the first electrode pad 81 and the second electrode pad 82 .

[0073] In addition, there may be a plurality of thin film transistors 70 arranged in a matrix form.

[0074] In addition, the thin film transistor 70 may be disposed under the LED 90. However, the position of the thin film transistor 70 is not limited thereto, but may be disposed at a position adjacent to the LED 90 to drive the LED 90.

[0075] The plurality of connection pads 20 may be electrically connected to the plurality of thin film transistors 70 and may be arranged in an L-shape on the glass substrate 50. In addition, the plurality of connection pads 20 may be arranged along an edge of the glass substrate 50 or may be arranged along two edges of the glass substrate 50 facing each other.

[0076] For example, a plurality of connection pads 20 may be provided on one side of each column and each row of a plurality of LEDs 90 arranged in a matrix form.

[0077] In particular, the plurality of connection pads 20 may include first connection pads 20-1 arranged on the thin film transistor substrate 1 along a vertical direction, ie, along at least one column, and second connection pads 20-2 arranged on the thin film transistor substrate 1 along a horizontal direction, ie, along at least one row.

[0078] The first connection pad 20 - 1 may be connected to the first driving driver 130 - 1 , and may receive a control signal for sequentially controlling horizontal lines of the plurality of LEDs 90 arranged in a matrix form by one line per image frame from the first driving driver 130 - 1 .

[0079] The second connection pad 20 - 2 may be connected to the second driving driver 130 - 2 , and may receive a control signal for sequentially controlling vertical lines of the plurality of LEDs 90 arranged in a matrix form by one line per image frame from the second driving driver 130 - 2 .

[0080] In addition, the connection pads 20 may not be included in the dummy area DA, but may be used as a reference for forming the dummy area DA. For example, the dummy area DA may include a plurality of test pads 30, and may include a space between each of the plurality of test pads 30 and each of the plurality of connection pads 20. Therefore, the dummy area DA may be spaced apart from the plurality of connection pads 20 by a predetermined interval, and may be formed along a direction in which the plurality of first connection pads 20-1 and the plurality of second connection pads 20-2 are arranged.

[0081] In addition, the first connection pads 20 - 1 may be disposed on the thin film transistor substrate 1 along a vertical direction, and the second connection pads 20 - 2 may be disposed on the thin film transistor substrate 1 along a horizontal direction.

[0082] In addition, the connection pad 20 may include a connection pad transfer portion 21 electrically connected to the thin film transistor 70 and the test pad 30 , and a connection pad portion 22 forming a connection surface of the connection pad 20 .

[0083] The connection pad transmission portion 21 may be provided in the thin film transistor layer 140 , and may transmit a signal received from the connection pad portion 22 to the thin film transistor 70 .

[0084] The connection pad part 22 may protect the connection pad transfer part 21 from the outside, and may be electrically connected to the connection pad transfer part 21 to transmit a signal received from the driving driver 130 to the connection pad transfer part 21 .

[0085] The connection pad transfer part 21 and the connection pad part 22 may be formed of a conductive material, and each of them may be made of a different material. That is, the connection pad transfer part 21 may be made of one material, and the connection pad part 22 may be made of another material.

[0086] For example, the connection pad 20 may have a length and a width of approximately 50 μm or less, respectively.

[0087] The test pad 30 may be provided along an edge of one surface 50 a of the glass substrate 50 , and may be electrically connected to the connection pad 20 through the connection wiring 40 .

[0088] Here, when the glass substrate 50 has a quadrilateral shape, the edge may include a side surface portion of the glass substrate 50. That is, for example, in the glass substrate 50 having a rectangular shape, the edge may include at least one of a vertical side surface 50-1 of the glass substrate 50 and a horizontal side surface 50-2 adjacent to the vertical side surface 50-1.

[0089] Furthermore, the test pad 30 is not limited to a pad but may be referred to as a terminal.

[0090] Therefore, the test pad 30 can be electrically connected to the components included in the thin film transistor layer 140, such as the connection pad 20 and the thin film transistor 70. Therefore, it is possible to check whether the thin film transistor substrate 1 is electrically connected by selectively contacting the electric needle N to the test pad 30. In addition, the manufacturer can check whether the manufactured thin film transistor substrate 1 operates normally.

[0091] The test pad 30 may include a test pad transfer portion 31 , a test pad portion 32 , and a low resistance wiring 33 .

[0092] The test pad transfer part 31 may be provided in the thin film transistor layer 140 and may be electrically connected to the connection pad 20 through the connection wiring 40. For example, the test pad transfer part 31 may be electrically connected to the connection pad transfer part 21 through the connection wiring 40 formed in the thin film transistor layer 140.

[0093] The test pad part 32 may protect the test pad transfer part 31 from the outside, and may be electrically connected to the connection pad part 22 to transmit a signal received from the driving driver 130 to the connection pad transfer part 21 .

[0094] The test pad transfer portion 31 and the test pad portion 32 may be formed of a conductor, and each of them may be made of a different material.

[0095] The low resistance wiring 33 may be provided between each of the plurality of test pads 30 and the connection wiring 40. In addition, there may be a plurality of low resistance wirings 33 configured to be provided between each of the plurality of test pads 30 and the connection wiring 40.

[0096] For example, the low resistance wiring 33 may be provided between the test pad transfer portion 31 and the connection wiring 40 .

[0097] The low resistance wiring 33 may be made of a material having lower resistance than the test pad transfer portion 31 and the test pad portion 32. For example, the low resistance wiring 33 may be made of aluminum (Al), copper (Cu), or the like.

[0098] Therefore, the low resistance wiring 33 can adjust the minimum resistance requirement value during the electrical test of the thin film transistor substrate 1. Therefore, by adjusting the value of the test current flowing into the thin film transistor substrate 1 through the low resistance wiring 33, it is possible to prevent a high current from flowing into the thin film transistor substrate 1 and damaging the components inside the thin film transistor substrate 1.

[0099] In addition, if the minimum resistance required value of the thin film transistor substrate 1 is not low, the low resistance wiring 33 may not be formed.

[0100] The test pad 30 may be configured in plurality, and a cross-sectional area of ​​each of the plurality of test pads 30 may be greater than a cross-sectional area of ​​each of the plurality of connection pads 20 .

[0101] For example, the test pad 30 may have a quadrilateral shape having a length and a width of about 200 μm. Therefore, when performing an electrical test on the manufactured thin film transistor substrate 1 , the test needle N may more easily contact the test pad 30 having a larger cross-sectional area than the connection pad 20 .

[0102] Therefore, an electrical test of the manufactured thin film transistor substrate 1 can be more easily performed, and the test needle N can stably contact the test pad 30 , thereby improving test performance and efficiency.

[0103] Furthermore, even if the test pad 30 is damaged during electrical testing of the manufactured thin film transistor substrate 1, the test pad 30 can be removed and replaced in a subsequent process. Therefore, the problem of unstable driving of the thin film transistor substrate 1 due to damaged connection pads 20 can be prevented.

[0104] In addition, the number of the plurality of test pads 30 may correspond to the number of the plurality of connection pads 20. That is, one test pad 30 may be electrically connected to one connection pad 20.

[0105] Therefore, by testing each of the plurality of test pads 30 , it is possible to test whether the components of the thin film transistor layer 140 connected to each of the plurality of connection pads 20 operate normally.

[0106] In addition, the plurality of test pads 30 may be disposed in a zigzag configuration along the edge of the glass substrate 50. Accordingly, the number of the plurality of test pads 30 may correspond to the number of the plurality of connection pads 20, and a space for disposing the plurality of test pads 30 may be minimized.

[0107] For example, since the plurality of connection pads 20 have a tiny size, thousands of connection pads can be arranged in a line at predetermined intervals. Therefore, even when the plurality of test pads 30 are arranged from as few as several tens to as many as several thousand, the plurality of test pads 30 can be completely arranged on the thin film transistor substrate 1 without expanding the size of the manufactured thin film transistor substrate 1.

[0108] That is, even if the dummy area DA including the area provided with the plurality of test pads 30 on the manufactured thin film transistor substrate 1 is removed, the removed portion on the manufactured thin film transistor substrate 1 can be minimized by minimizing the dummy area DA. Therefore, the thin film transistor substrate 1 can be easily tested by the plurality of test pads 30, and the manufacturing cost can be reduced by minimizing the area occupied by the plurality of test pads 30.

[0109] The connection wiring 40 may electrically connect the connection pad 20 and the test pad 30, and may be formed in the thin film transistor layer 140. The connection wiring 40 may be made of a material having low flexibility.

[0110] For example, the connection wiring 40 may be made of at least one of molybdenum (Mo), titanium (Ti), and TiMo. However, the connection wiring is not limited thereto. Therefore, even if the dummy area DA is removed along the first cutting line C-1 and the second cutting line C-2 included in the dummy area DA, byproducts generated by the connection wiring 40 may be minimized.

[0111] In particular, when the connection wiring 40 is made of an elastic material, many byproducts may be generated along the first cutting line C-1 and the second cutting line C-2 during the cutting process. Therefore, an additional process of removing the generated byproducts may be required in a subsequent process.

[0112] Therefore, when the connection wiring 40 is made of a non-elastic or rigid material, by minimizing the generation of by-products during the cutting process, the process of removing the by-products may be minimized or omitted, thereby reducing the manufacturing cost.

[0113] In addition, the connection wiring 40 may be formed in the form of one layer of the thin film transistor layer 140 .

[0114] In addition, since the connection wiring 40 connects each of the plurality of test pads 30 and each of the plurality of connection pads 20, the connection wiring 40 may be configured in plurality. For example, the number of the connection wiring 40 may correspond to the number of the plurality of test pads 30 and the plurality of connection pads 20.

[0115] In addition, the first insulating layer 61 and the second insulating layer 62 may be respectively provided on the upper and lower portions of the connection wiring 40. For example, the first insulating layer 61 may be provided on the upper portion of the connection wiring 40, and the second insulating layer 62 may be provided on the lower portion of the connection wiring 40.

[0116] That is, the first insulating layer 61 and the second insulating layer 62 may be formed to surround the connection wiring 40 .

[0117] Therefore, when current flows through the connection wiring 40 , the current is prevented from flowing into the space outside the connection wiring 40 , thereby improving the stability of the electrical test of the thin film transistor substrate 1 .

[0118] The first insulating layer 61 and the second insulating layer 62 may be formed integrally with the layer formed around the thin film transistor 70. That is, in the process of forming the thin film transistor layer 140 on the glass substrate 50, the first insulating layer 61 and the second insulating layer 62 may be formed.

[0119] Furthermore, if necessary, polysilicon (p-Si) may be disposed under each of the first insulating layer 61 and the second insulating layer 62 .

[0120] In addition, the first insulating layer 61 and the second insulating layer 62 may be in contact with each other at a position where the connection wiring 40 is not formed.

[0121] In addition, the first insulating layer 61 and the second insulating layer 62 may be formed of an organic insulating layer or an inorganic insulating layer, and the material constituting each insulating layer may be different.

[0122] Between the glass substrate 50 and the second insulating layer 62, a buffer layer 63 may be formed to relieve strain caused by the difference in lattice constant and thermal expansion coefficient between the glass substrate 50 and the thin film transistor layer 140. The buffer layer 63 may be made of GaN, AlN, AlGaN, or SiNx, which are highly heat-resistant materials to enable GaN layer deposition by a metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) process.

[0123] In addition, the thin film transistor substrate 1 may include a plurality of electrode pads formed on each of the plurality of thin film transistors 70 , and a plurality of LEDs 90 are disposed on the plurality of electrode pads.

[0124] For example, the plurality of electrode pads may include a first electrode pad 81 and a second electrode pad 82 representing different electrodes.

[0125] Therefore, if Figure 3B As shown, the first electrode 95 of the LED 90 may be disposed on the first electrode pad 81 , and the second electrode 96 of the LED 90 may be disposed on the second electrode pad 82 .

[0126] Therefore, the electrical signal transmitted from the thin film transistor 70 may be transmitted to the LED 90 through the plurality of electrode pads 81 and 82 .

[0127] In addition, the plurality of thin film transistors 70 and the plurality of electrode pads 81 and 82 may be arranged in a matrix on the glass substrate 50. Therefore, the plurality of LEDs 90 mounted on the plurality of electrode pads 81 and 82 may also be arranged in a matrix on the glass substrate 50.

[0128] Next, we will refer to Figures 1 to 6 A manufacturing process of the thin film transistor substrate 1 according to the embodiment is described.

[0129] Figure 1 is a top view showing a thin film transistor substrate 1 according to an embodiment, Figure 2 It is along Figure 1 The cross-sectional view taken along line AA, Figure 3A It is shown from Figure 1 Top view of the structure with the virtual area DA removed, Figure 3B It is along Figure 3A The cross-sectional view taken along line EE of Figure 3C It is shown Figure 3B A cross-sectional view of the chamfered structure of the structure shown, Figure 4A It is shown in Figure 3A A top view of the side wiring 100 formed in the structure, Figure 4B It is along Figure 4A The cross-sectional view taken along line FF is Figure 4C is a block diagram showing LED90 and driving driver 130, Figure 5 is a top view showing an arrangement of a plurality of display modules 10 and 11 manufactured, and Figure 6 is a flowchart showing a method of manufacturing the thin film transistor substrate 1 according to the embodiment.

[0130] First, if Figure 1 and Figure 2 As shown, a plurality of test pads 30 may be formed along the edge of the glass substrate 50. In particular, a thin film transistor layer 140 may be formed on the glass substrate 50 (S1).

[0131] Here, the thin film transistor layer 140 may include a plurality of connection pads 20 , a plurality of test pads 30 , a connection wiring 40 , first and second inorganic insulating layers 61 and 62 , and a plurality of electrode pads 81 and 82 .

[0132] That is, in the process of forming the plurality of test pads 30 , the thin film transistor layer 140 may be formed through an iterative process of stacking and etching.

[0133] For example, in the operation of forming the plurality of test pads 30 , the connection wiring 40 electrically connecting each of the plurality of thin film transistors 70 provided on the glass substrate 50 and each of the plurality of test pads 30 may be formed.

[0134] Furthermore, in the operation of forming the plurality of test pads 30 , insulating layers 61 and 62 may be formed on the upper and lower portions of the connection wiring 40 .

[0135] Next, if Figure 2 As shown, the test needle N may contact the plurality of test pads 30 to test whether the manufactured thin film transistor substrate 1 operates normally ( S2 ).

[0136] In particular, each of the multiple test pads 30 can be electrically connected to each of the multiple connection pads 20 through the connection wiring 40, and each of the multiple connection pads 20 can be electrically connected to the multiple thin film transistors 70 through the electrical wiring formed in the thin film transistor layer 140.

[0137] Therefore, in a state where the test needle N is in contact with the plurality of test pads 30 , current is allowed to flow through the test needle N, thereby making it possible to test whether current can flow through the plurality of transistors 70 .

[0138] Here, the number of test pins N can be set to be less than the number of test pads 30 to determine whether the thin film transistor substrate 1 is operating by repeatedly contacting multiple test pads 30, or the number of test pins N can be set to be equal to or greater than the number of test pads 30 to determine whether the thin film transistor substrate 1 is operating by simultaneously contacting multiple test pads 30.

[0139] Furthermore, the test pin N is only an example, and various configurations may be used to perform electrical testing, such as a test pad.

[0140] Therefore, before performing an additional process on the manufactured thin film transistor substrate 1, it is possible to inspect whether the thin film transistor substrate 1 is defectively manufactured.

[0141] Here, the additional process may refer to various processes such as disposing a plurality of LEDs 90 on the thin film transistor substrate 1 or removing the dummy area DA of the thin film transistor substrate 1 .

[0142] Therefore, it may be determined whether an additional process needs to be performed, thereby improving the manufacturing efficiency of the thin film transistor substrate 1 .

[0143] In addition, the cross-sectional area of ​​each of the plurality of test pads 30 may be larger than the cross-sectional area of ​​each of the plurality of connection pads 20. Therefore, since the test needle N does not contact the plurality of fine-sized connection pads 20 but contacts the plurality of test pads 30, the test needle N may stably perform electrical testing on the plurality of test pads 30.

[0144] Therefore, during the test, since the cross-sectional area of ​​the plurality of test pads 30 is large, the possibility that the test needle N can contact the plurality of test pads 30 increases, and the test can be stably performed. In other words, the test efficiency and stability of the manufactured thin film transistor substrate 1 can be improved.

[0145] In addition, during the test process, even if the plurality of test pads 30 are damaged, the plurality of test pads 30 can be removed and replaced. Therefore, in a state where the plurality of LEDs 90 are set, the plurality of damaged test pads 30 will not affect the display module 10 ( Figure 3A ) operation.

[0146] Next, after the test of the manufactured thin film transistor substrate 1 is completed, the predetermined dummy area DA of the glass substrate 50 where the plurality of test pads 30 are disposed may be removed ( S3 ).

[0147] Here, the operation of removing the dummy area DA may refer not only to removing the glass substrate 50 but also to removing a portion of the thin film transistor layer 140 formed on the glass substrate 50. For example, in the operation of removing the dummy area DA, the glass substrate 50, the insulating layers 61, 62, and the connection wiring 40 may be removed at the same time.

[0148] The dummy area DA may be an area including a plurality of connection pads 20 on the manufactured thin film transistor substrate 1. In particular, the dummy area DA may include an edge area of ​​the thin film transistor substrate 1.

[0149] For example, the dummy area DA may include one vertical side surface 50 - 1 and one horizontal side surface 50 - 2 of the glass substrate 50 .

[0150] In addition, the dummy area DA may include a first cutting line C-1 and a second cutting line C-2 between the plurality of connection pads 20 and the plurality of test pads 30 of the glass substrate 50. In particular, the first cutting line C-1 may be disposed between the first connection pad 20-1 and the plurality of test pads 30 disposed in one column, and the second cutting line C-2 may be disposed between the second connection pad 20-2 and the plurality of test pads 30 disposed in one row.

[0151] Here, the first cutting line C-1 and the second cutting line C-2 may be perpendicular to each other. However, the intersection of the first cutting line C-1 and the second cutting line C-2 is not limited thereto.

[0152] In addition, in the operation of removing the dummy area DA, the glass substrate 50 may be removed so that the plurality of connection pads 20 electrically connected to the plurality of thin film transistors 70 and disposed on one surface of the glass substrate 50 are located at the edge of the etched glass substrate 50 .

[0153] That is to say, Figure 3A As shown, after the dummy area DA is removed, the glass substrate 50 and the thin film transistor substrate 1 may have a first cut surface 50 - 1 a in a vertical direction and a second cut surface 50 - 2 a in a horizontal direction adjacent to the first cut surface 50 - 1 a .

[0154] For example, the first cut surface 50 - 1 a may be parallel to the first connection pads 20 - 1 arranged in a column, and the second cut surface 50 - 2 a may be parallel to the second connection pads 20 - 2 arranged in a row.

[0155] In addition, in the operation of removing the dummy area DA, the glass substrate 50 may be removed by laser emitted from a laser cutter. However, the means for removing the glass substrate 50 is not limited to laser, and the glass substrate 50 may also be removed by various mechanical devices such as a grinder.

[0156] In addition, if Figure 2 and Figure 3A As shown, after etching is performed along the first cutting line C-1 and the second cutting line C-2, the first cutting surface 50-1a and the second cutting surface 50-2a of the glass substrate 50 may be polished along the polishing line D.

[0157] Therefore, after the cutting process, by-products generated in the glass substrate 50 and the thin film transistor layer 140 may be removed by polishing the first cutting surface 50 - 1 a and the second cutting surface 50 - 2 a of the glass substrate 50 .

[0158] In addition, by smoothing the first cut surface 50-1a and the second cut surface 50-2a of the glass substrate 50, the side wiring 100 formed on the first cut surface 50-1a and the second cut surface 50-2a can be stably formed without being lifted or disconnected. Therefore, when the manufactured display modules 10 and 20 operate, the electric signal transmitted from the driving driver 130 provided at the rear surface of the display modules 10 and 20 can be stably transmitted to the plurality of LEDs 90 through the side wiring 100.

[0159] In addition, if Figure 3C As shown, after the cutting process is performed along the first cutting line C-1 and the second cutting line C-2, corners of the first cutting surface 50-1a and the second cutting surface 50-2a of the glass substrate 50 may be chamfered.

[0160] That is, one surface of at least one of the thin film transistor layer 140 and the glass substrate 50 may be chamfered to form a chamfered surface CF. In particular, the chamfered surface CF may be formed on the first cut surface 50 - 1 a and the second cut surface 50 - 2 a of the glass substrate 50 .

[0161] Therefore, the shortest distance of the side wiring 100 connecting the plurality of connection pads 20 disposed on one surface of the glass substrate 50 and the plurality of driving pads 110 disposed on the other surface of the glass substrate 50 can be reduced, thereby reducing the loss of current and signals. In addition, the side wiring 100 can be structurally prevented from being disconnected by the sharp corners of the first cutting surface 50-1a and the second cutting surface 50-2a.

[0162] In addition, the plurality of LEDs 90 may be disposed on the plurality of electrode pads 81 and 82 formed on the plurality of thin film transistors 70 .

[0163] However, the operation of arranging the plurality of LEDs 90 may be performed after the operation of testing the manufactured thin film transistor substrate 1 .

[0164] Here, the LED 90 may be made of an inorganic light emitting material having width, length, and height dimensions of about 100 μm or less, and may be a micro LED that is disposed on the thin film transistor substrate 1 and emits light by itself.

[0165] refer to Figure 3A and Figure 4C , LED 90 may be composed of a single pixel 90', and one pixel may include a red LED 91 emitting red light, a green LED 92 emitting green light, and a blue LED 93 emitting blue light as sub-pixels, and a pixel driving circuit 94 for driving the plurality of sub-pixels.

[0166] That is, one pixel 90' may include a red LED 91 emitting red light, a green LED 92 emitting green light, a blue LED 93 emitting blue light, and a pixel driving circuit 94 for driving a plurality of sub-pixels.

[0167] Sub-pixels 91, 92, and 93 may be arranged in a matrix or sequentially in one pixel 90'. However, the arrangement of sub-pixels 91, 92, and 93 is only an example, and sub-pixels 91, 92, and 93 may be provided in various forms within each single pixel 90'.

[0168] The LED 90 may have a fast response speed, low power consumption, and high brightness, and thus has attracted attention as a light emitting device for next generation displays. In particular, the LED 90 may have a higher efficiency of converting electricity into photons than a conventional LCD.

[0169] In other words, LED 90 has a higher "brightness per watt" than conventional LCD displays. As a result, LED 90 can emit the same brightness with approximately half the energy required by conventional LCDs.

[0170] In addition, LED 90 can achieve high resolution, excellent color, contrast and brightness, thereby accurately representing a wide range of colors and achieving a clear screen even in bright sunlight. In addition, since LED 90 generates less heat, it ensures a long service life without deformation.

[0171] Furthermore, the LED 90 may be a flip chip.

[0172] Next, if Figure 4A and Figure 4B As shown, a plurality of driving pads 110 and a plurality of link pads 120 connected to the plurality of driving pads 110 may be formed on the other surface 50 b of the etched glass substrate 50 .

[0173] The plurality of driving pads 110 may be disposed at positions facing positions where the plurality of connection pads 20 are formed.

[0174] In addition, the plurality of link pads 120 may be disposed adjacent to the plurality of driving pads 110 , and may be electrically connected to the driving driver 130 .

[0175] After forming multiple driving pads 110 and multiple connecting pads 120, side wiring 100 can be formed along the first cutting surface 50-1a and the second cutting surface 50-2a of the glass substrate 50 to connect the multiple connecting pads 20 set on one surface 50a of the glass substrate 50 and the multiple driving pads 110 set on the other surface 50b of the glass substrate 50.

[0176] Therefore, the manufactured thin film transistor substrate 1 may be operated as a first display module 10 capable of implementing one display screen after undergoing various processes.

[0177] In particular, signal information of the display screen can be generated from a driving driver 130 set on the other surface 50b of the first display module 10, and the signal information can be sent to the LED 90 through the link pad 120, the driving pad 110, the side wiring 100, the connecting pad 20 and the thin film transistor 70 connected to the driving driver 130.

[0178] Therefore, when the LED 90 receiving the signal information of the display screen is operated, the first display module 10 can realize the display screen.

[0179] In addition, if Figure 5 As shown, the second display module 11 having the same manufacturing structure as the first display module 10 can be arranged in parallel with the first display module 10 to realize one display screen.

[0180] That is, the plurality of display modules 10 and 11 may be arranged according to the size of a display to be implemented by each of the display modules 10 and 11 manufactured in a module form to form one display screen.

[0181] For example, when the first display module 10 and the second display module 11 are disposed parallel to each other in the horizontal direction, the display screen may be implemented to have a longer length in the horizontal direction than in the vertical direction.

[0182] Alternatively, when the first display module 10 and the second display module 11 are disposed parallel to each other in the vertical direction, the display screen may be implemented to have a longer length in the vertical direction than in the horizontal direction.

[0183] Therefore, display screens of various sizes and shapes can be implemented according to the number and shape of the arranged plurality of display modules.

[0184] In the following, reference will be made to Fig. 7A The structure of the connection wiring 40 according to the embodiment is described.

[0185] Fig. 7A is a top view showing the connection wiring 40 according to the embodiment.

[0186] like Fig. 7A As shown, the connection wiring 40 may electrically connect one test pad 30 and one connection pad 20. In this case, the connection wiring 40 may be formed to have a predetermined length with respect to the test pad 30 and the connection pad 20.

[0187] Below, we will refer to Figure 7BThe structure of a connection wiring 40 ′ according to a modified example is described.

[0188] Figure 7B is a top view showing a connection wiring 40 ′ according to another embodiment.

[0189] like Figure 7B As shown, each connection wiring 40' may include a plurality of sub-connection wirings 40'-1 and 40'-2 spaced apart from each other by a predetermined interval.

[0190] For example, the plurality of sub-connection wirings 40 ′- 1 and 40 ′- 2 may be provided with a separation space S provided between the sub-connection wirings 40 ′- 1 and 40 ′- 2 , and the number of the plurality of sub-connection wirings may vary.

[0191] Therefore, since the plurality of sub-connection wirings 40 ′- 1 and 40 ′- 2 are provided with the separation spaces S spaced apart from each other, byproducts generated in the connection wiring 40 ′ may be reduced according to the separation spaces S when cutting is performed between the connection pad 20 and the test pad 30 .

[0192] Therefore, when the connection wiring 40 ′ is made of a non-elastic or strong material, by minimizing the generation of by-products during the cutting process, the process of removing the by-products may be minimized or omitted, thereby reducing the manufacturing cost.

[0193] In addition, by preventing byproducts from being included in the side wiring 100 when the side wiring 100 is connected to the connection pad 20 , stable signal transmission may be achieved in the display modules 10 and 11 .

[0194] In the following, reference will be made to Figure 7C The structure of a connection wiring 40 ″ according to another embodiment is described.

[0195] Figure 7C is a top view showing a connection wiring 40 ″ according to another embodiment.

[0196] like Figure 7C As shown, each connection wiring 40" may include a plurality of sub-connection wirings 40"-1 and 40"-2 spaced apart from each other by a predetermined interval, and a connection portion 40"-3 formed adjacent to each of a plurality of connection pads 20 and each of a plurality of test pads 30.

[0197] In particular, the connection parts 40 ″ - 3 may be respectively formed at one end and the other end of the plurality of sub-connection wirings 40 ″ - 1 and 40 ″ - 2 , and the cross-sectional area of ​​the connection wiring 40 ″ may be increased.

[0198] By adjusting the resistance based on the cross-sectional area of ​​the connection wiring 40", the current value between the connection pad 20 and the test pad 30 can be adjusted, and when cutting is performed between the connection pad 20 and the test pad 30, the by-products generated in the connection wiring 40" can be reduced according to the separation space S.

[0199] Figure 8 is a cross-sectional view showing a thin film transistor substrate according to another embodiment, Fig. 9 It is shown Figure 8 A plan view of the second area A2 and the virtual area DA is shown.

[0200] refer to Figure 8 and Fig. 9 According to another embodiment, the thin film transistor substrate 1a may have a dummy area DA in which a plurality of test pads are provided similarly to the above-described thin film transistor substrate 1. In this case, when the test of the thin film transistor substrate 1a is completed, the dummy area DA may be removed.

[0201] A thin film transistor substrate 1 a according to another embodiment may have substantially the same structure as that of the above-described thin film transistor substrate 1 , but may be different in some configurations.

[0202] Hereinafter, the structure of a thin film transistor substrate 1 a according to another embodiment will be described.

[0203] According to another embodiment, a thin film transistor substrate 1a may include a glass substrate 250, a thin film transistor layer 500 formed in a first area A1 of the glass substrate 250, a plurality of connection pads 220 disposed in a second area A2 of the glass substrate 250, and a plurality of test pads 230 disposed in a dummy area DA of the glass substrate 250.

[0204] A buffer layer 271 contacting a bottom surface of the thin film transistor layer 500 may be disposed on an upper surface of the glass substrate 250. The buffer layer 271 may relieve strain caused by differences in lattice constant and thermal expansion coefficient between the glass substrate 250 and the thin film transistor layer 500.

[0205] The virtual area DA of the glass substrate 250 may be defined as a portion of the glass substrate 250 when manufacturing the display module 10a (eg, Fig.11 The virtual area DA is an area as the outermost part of the glass substrate 250 to be removed during the cutting process in the process of cutting (as shown in FIG. 1 ). In this case, when the glass substrate 250 has a quadrilateral shape, the virtual area DA may be an area including at least one of the four sides. The virtual area DA and the second area A2 may also be divided with the cutting line C as a boundary.

[0206] In a state where the dummy area DA is removed by the cutting process, the first area A1 of the glass substrate 250 may be defined as an area occupied by the thin film transistor layer 500, and the second area A2 may be defined as an edge area of ​​the glass substrate 250. That is, when the dummy area DA is removed, the second area A2 may correspond to the outermost portion of the glass substrate 250.

[0207] The thin film transistor layer 500 may include gate wirings 251a and 251b, data wirings 253a, 253b, 255a and 255b, Vdd power wirings 211a and 211b connected to some of the data wirings 253a and 255b, VSs power wirings 213 and 215, and pixel electrodes 215a and 215b.

[0208] In this case, the plurality of thin film transistor layers 500 may include a gate insulating layer 272, and first to fifth insulating layers 273, 274, 275, 276, and 277 sequentially stacked upward from the upper surface of the buffer layer 271. The first to fifth insulating layers 273, 274, 275, 276, and 277 may be made of an inorganic or organic insulating material. For example, the first insulating layer 273, the third insulating layer 275, and the fifth insulating layer 277 may be made of an inorganic insulating material, and the second insulating layer 274 and the fourth insulating layer 276 may be made of an organic insulating material.

[0209] The first insulating layer 273, the second insulating layer 274, the fourth insulating layer 276, and the fifth insulating layer 277 may be formed up to the dummy area DA. In particular, the connection wiring 240 that electrically connects the plurality of connection pads 220 and the plurality of test pads 230 may be disposed between the fourth insulating layer 276 and the fifth insulating layer 277 in the first area A1. Therefore, the upper and lower portions of the connection wiring 240 may be covered by the fourth insulating layer 276 and the fifth insulating layer 277.

[0210] The plurality of connection pads 220 disposed in the second area A2 of the glass substrate 250 and the plurality of test pads 230 disposed in the dummy area DA may be electrically connected to each other through a connection wiring 240. The connection wiring 240 may be a wiring extending from the VSS power wiring 213.

[0211] refer to Fig. 9 The connection wiring 240 may be formed to be disposed across the second area A2 and the dummy area DA. Therefore, when cutting is performed along the cutting line C, a portion 242a of the connection wiring 240 may be exposed on the cut surface of the thin film transistor substrate 1a in a state where the dummy area DA is removed.

[0212] The connection wiring 240 may include a first connection portion 241 to which the connection pad 220 is electrically connected to an upper surface thereof, a second connection portion 243 to which the test pad 230 is electrically connected to an upper surface thereof, and a bridge portion 242 to connect the first connection portion 241 and the second connection portion 243 to each other. A portion 242a of the bridge portion 242 may be disposed in the second area A2, and the remaining portion 242b may be located in the dummy area DA.

[0213] In this case, the width of the bridge portion 242 may be thinner than the widths of the first and second connection portions 241 and 243. However, the width of the bridge portion 242 is not limited thereto and may be formed to be the same as the widths of the first and second connection portions 241 and 243.

[0214] In addition, the thin film transistor layer 500 can be formed by a low temperature polycrystalline silicon (LTPS) TFT process or an oxide TFT process, and according to each process, at least some of the gate wirings 251a and 251b, the data wirings 253a, 253b, 255a and 255b, the Vdd power wirings 211a and 211b, the Vss power wirings 213 and 215, and the connection wiring 240 can be made of a low resistance metal material.

[0215] For example, in the case of a thin film transistor layer 500 formed by a LTPS TFT process, the gate wirings 251a and 251b may be made of molybdenum (Mo) having high heat resistance, while the data wirings 253a, 253b, 255a and 255b, the Vdd power wirings 211a and 211b, the Vss power wirings 213 and 215, and the connection wiring 240 may be made of aluminum (Al) which is a low resistance metal material.

[0216] In addition, in the case of the thin film transistor layer 500 formed by the oxide TFT process, the gate wirings 251a and 251b, the data wirings 253a, 253b, 255a and 255b, the Vdd power wirings 211a and 211b, the Vss power wirings 213 and 215, and the connection wiring 240 are all made of aluminum (Al) or copper (Cu) which is a low-resistance metal material.

[0217] In the case where the connection wiring 240 is formed of a low-resistance metal material, the minimum resistance requirement value can be adjusted when the thin film transistor substrate 1a is electrically tested. Therefore, by adjusting the value of the test current flowing in the thin film transistor substrate 1a via the connection wiring 240, it is possible to prevent a high current from flowing into the thin film transistor substrate 1a and damaging the components inside the thin film transistor substrate 1a.

[0218] The thin film transistor substrate 1a may include a plurality of driving pads 310 on the other surface of the glass substrate 250 and a plurality of link pads 320 electrically connected to the corresponding driving pads through wirings 340. In this case, the wirings 340 may be covered by an insulating layer 341.

[0219] The plurality of driving pads 310 , the plurality of link pads 320 , the wirings 340 , and the insulating layer 341 may be formed together when forming the thin film transistor layer 500 , may be formed subsequently after forming the thin film transistor layer 500 , or may be formed after removing the dummy area DA.

[0220] Below, we will refer to Fig.10 and Fig.11 A process of manufacturing a display module 10a using a thin film transistor substrate 1a according to another embodiment is sequentially described. Since the process of manufacturing the display module 10a is the same as the process of manufacturing the display module 10 described above, it will be schematically described.

[0221] Fig.10 is a flowchart showing a process of manufacturing a display module using a thin film transistor substrate according to another embodiment, Fig.11 is a cross-sectional view showing a display module according to another embodiment.

[0222] First, a thin film transistor substrate 1 a provided with a plurality of test pads 230 in a dummy area DA may be prepared ( S11 ).

[0223] Next, an electrical test of the thin film transistor substrate 1a may be performed (S12). In this case, the test pin N (eg Figure 2 ) to contact a plurality of test pads 230 to perform an electrical test. During such an electrical test, by adjusting the value of the test current flowing into the thin film transistor substrate 1a via the connection wiring 240 which is a low resistance wiring, it is possible to prevent a high current from flowing into the thin film transistor substrate 1a and damaging the components inside the thin film transistor substrate 1a.

[0224] When the electrical test of the thin film transistor substrate 1 a is completed, the plurality of test pads 230 are no longer required, and therefore, the dummy area DA is removed from the thin film transistor substrate 1 a along the cutting line C ( S13 ).

[0225] Next, a process of polishing the cut surface of the thin film transistor substrate 1a may be performed (S14). Byproducts generated in the glass substrate 250 and the thin film transistor layer 500 may be removed through the polishing process.

[0226] When the polishing process is completed, the corners of the cut surface of the thin film transistor substrate 1a (in this case, the cut surface is formed into a flat surface by the polishing process) are chamfered (S15). If the corners of the cut surface of the thin film transistor substrate 1a are removed by the chamfering process, a flat surface such as the one shown in FIG. Fig.11 Chamfered surfaces CF1 and CF2 are shown.

[0227] The chamfered surfaces CF1 and CF2 of the thin film transistor substrate 1a can prevent in advance the side wiring 280 formed on the cut surface of the thin film transistor substrate 1a from being disconnected by the edge sharp corners.

[0228] If the chamfering process is completed, a plurality of side wirings 280 may be formed to electrically connect a plurality of connection pads 220 disposed on one surface of the glass substrate 250 and a plurality of driving pads 310 disposed on the other surface of the glass substrate 250 ( S16 ).

[0229] Both end portions 281 and 283 of each side wiring 280 may be formed to cover at least a portion of the connection pad 220 and the driving pad 310 , respectively, and a central portion 282 thereof may be formed to cover the chamfered surfaces CF1 and CF2 and the cut surface of the glass substrate 250 .

[0230] Next, the LED may be transferred or inserted so that the LED is electrically connected to the plurality of pixel electrodes 215a and 215b provided in the thin film transistor layer 500 (S17). In this case, the LED transfer may be performed by any one of a laser transfer method, a press transfer method, a roller transfer method, and an electrostatic transfer method.

[0231] Fig.12 is a cross-sectional view showing a thin film transistor substrate according to still another embodiment, Fig.13 It is shown Fig.12 The plan view of the second area A2 and the virtual area DA shown, Fig.14 is a cross-sectional view showing a display module according to still another embodiment.

[0232] A thin film transistor substrate 1b according to another embodiment may have a structure substantially the same as that of the thin film transistor substrate 1a described above, but may differ in that a connection pad and a test pad are integrally formed. Hereinafter, a thin film transistor substrate 1b according to another embodiment will be described, but a configuration different from that of the thin film transistor substrate 1a will be described in more detail.

[0233] refer to Fig.12 and Fig.13, the integrated pad 420 may be formed by integrally forming the above-mentioned connection pad 220 and the test pad 230 , and the integrated pad 420 may have the same function as that of the above-mentioned connection pad 220 and the test pad 230 .

[0234] The integrated pad 420 may include a connection pad portion 421 electrically connected to a first connection portion 441 of a connection wiring 440 , a test pad portion 423 electrically connected to a second connection portion 443 of the connection wiring 440 , and a link portion 422 electrically connected along a bridge portion 442 of the connection wiring 440 .

[0235] A portion 422 a of the link portion 422 may correspond to a portion 442 a of the bridge portion 442 , and a remaining portion 422 b of the link portion 422 may be disposed at a position corresponding to the remaining portion 442 b of the bridge portion 442 .

[0236] Therefore, when the dummy area DA is removed along the cutting line C, a portion 422 a of the link portion of the integration pad 420 and a portion 442 a of the bridge portion 442 of the connection wiring 440 may be exposed at the cutting surface of the glass substrate 250 .

[0237] refer to Fig.14 The thin film transistor substrate 10b in a state where the dummy area DA is removed may have a portion 422a of the link portion of the integrated pad provided to the chamfered surface CF1. Therefore, one end portion 581 of the side wiring 580 may be formed to cover only the portion 422a of the link portion of the integrated pad.

[0238] However, the one end portion 581 of the side wiring 580 is not limited thereto, and may also be formed to cover the portion 422 a of the link portion of the integrated pad and the connection pad portion 421 .

[0239] In addition, the other end portion 583 of the side wiring 580 can be formed to cover at least a portion of the driving pad 310, and the central portion 582 thereof can be formed to cover the corresponding chamfered surfaces CF1 and CF2 and the cut surface of the glass substrate 250.

[0240] Although various embodiments have been described above individually, the corresponding embodiments are not necessarily implemented individually, but may also be implemented such that the configuration and operation thereof are combined with the configuration and operation of one or more other embodiments.

[0241] Although the embodiments of the present disclosure have been illustrated and described above, the present disclosure is not limited to the above specific embodiments, but can be variously modified by those skilled in the art without departing from the scope and spirit of the present disclosure. Such modifications should not be understood separately from the technical spirit or prospect of the present disclosure.

[0242] Industrial Applicability

[0243] Devices and methods consistent with the present disclosure relate to a display module structure and a manufacturing method thereof, wherein the display module structure includes a thin film transistor substrate in a self-luminous display device using light emitting diodes (LEDs), a plurality of LEDs are mounted on the thin film transistor substrate, and the thin film transistor substrate can be easily tested and manufactured.

Claims

1. A display module, comprising: Glass substrate; A thin film transistor layer is disposed in the first region of the glass substrate; a plurality of connection pads disposed in a second region of the glass substrate extending from the first region and electrically connected to the thin film transistor layer; a plurality of test pads, which are disposed in a third region of the glass substrate extending from the second region and are electrically connected to the plurality of connection pads, respectively; as well as a plurality of connection wirings electrically connecting the plurality of connection pads and the plurality of test pads in the second area and the third area, The plurality of connection wirings electrically connect each of the plurality of test pads to each of the plurality of thin film transistors formed in the thin film transistor layer.

2. The display module according to claim 1, wherein the plurality of connection wirings are also provided in the second region and the third region of the glass substrate, wherein the plurality of connection wirings include at least one of molybdenum Mo, titanium Ti and TiMo, and Insulating layers are respectively provided on the upper and lower parts of the plurality of connecting wirings.

3. The display module according to claim 1, wherein the plurality of test pads are removed after performing a substrate test, and The plurality of test pads are arranged in a zigzag shape along the third region. 4 . The display module according to claim 3 , wherein an area of ​​each of the plurality of test pads is greater than an area of ​​each of the plurality of connection pads. 5 . The display module according to claim 1 , wherein the plurality of test pads and the plurality of connection pads are integrally formed corresponding to each other. 6 . The display module according to claim 1 , further comprising a plurality of low-resistance wirings provided between each of the plurality of test pads and the plurality of connection wirings.

7. The display module according to claim 1, wherein the glass substrate has a quadrilateral shape, and The third region includes two adjacent side surface portions of the glass substrate. 8 . The display module according to claim 1 , wherein the plurality of connection wirings include a plurality of sub-connection wirings spaced apart from each other by a predetermined interval.

9. A method for manufacturing a display module, the method comprising: forming a thin film transistor layer of a thin film transistor substrate on a glass substrate; forming a plurality of test pads outside the glass substrate along a dummy area; testing whether the thin film transistor substrate operates by contacting a test needle with the plurality of test pads; removing the dummy area including the plurality of test pads; forming a plurality of side wirings along at least one side surface of the glass substrate from which the dummy area is removed; as well as transferring a plurality of light emitting diodes (LEDs) onto the thin film transistor layer, The forming of the plurality of test pads further comprises: forming a plurality of connection wirings on the dummy area, and The plurality of connection wirings are configured to electrically connect the plurality of test pads to each of a plurality of thin film transistors formed in the thin film transistor layer.

10. The manufacturing method according to claim 9, wherein the forming of the plurality of test pads further comprises: forming a first insulating layer on the upper portions of the plurality of connection wirings; And forming a second insulating layer under the plurality of connection wirings.

11. The manufacturing method according to claim 10, wherein removing the dummy area further comprises: A portion of the glass substrate, the plurality of connection wirings, and the first insulating layer and the second insulating layer are simultaneously cut by laser.

12. The manufacturing method according to claim 9, further comprising: After the dummy area is removed, the removed glass substrate is polished along the cut surface of the glass substrate.

13. The manufacturing method according to claim 9, further comprising: After removing the dummy area, at least one corner of the cut surface of the glass substrate is chamfered.

14. The manufacturing method according to claim 9, wherein the forming of the plurality of side wirings further comprises: The plurality of side surface wirings are provided to connect a plurality of connection pads provided on one surface of the glass substrate and a plurality of driving pads provided on the other surface of the glass substrate.

Images