A control method, device, and multi-chip package structure for a chip operating mode

Abstract

The present invention relates to the technical field of multi-chip packaging, and specifically relates to a control method, device, and multi-chip packaging structure for the working mode of a chip. The method includes: obtaining the working voltage comparison result of a first working voltage vdd1 and a second working voltage vdd2; controlling the working mode of an input driver according to the working voltage comparison result, so that the first chip operates in a working mode adapted to the working mode of the input driver. According to the working voltage comparison result of the first working voltage vdd1 and the second working voltage vdd2, the present invention controls the working mode of the input driver, so that the first chip operates in a working mode adapted to the working mode of the input driver, reducing the interference of incorrect working states, leakage, etc. on tests such as chip screening, and improving the system function debugging efficiency of multi-chip packaging.

Description

Technical Field

[0001] The present invention relates to the technical field of multi-chip packaging, and particularly to a method and device for controlling the working mode of a chip and a multi-chip packaging structure. Background Art

[0002] In recent years, due to physical limitations, the semiconductor technology under the guidance of "Moore's Law" has slowed down in the deep sub-micron stage. In order to meet the development of computers or electronic systems towards high bandwidth, high complexity, and functional diversity, advanced multi-chip packaging technology has become a key innovative path for continuously optimizing system performance and cost, and is a continuation of "Moore's Law" in computers or electronic systems.

[0003] Multi-chip package (MCP) can integrate multiple chips of different sizes, different manufacturing processes, and different materials into a single package housing, including stacking methods such as 2D, 2.5D, and 3D, and is applied to systems such as advanced mobile communication / computation and high-bandwidth memory.

[0004] Before packaging, the chips in a multi-chip package are not electrically connected by interconnections, or even after the multi-chip package is completed, due to a certain chip not being powered on or the power-on not being completed, its input / output circuit is in a floating state, resulting in incorrect working states, leakage, etc. of the chips, thereby interfering with the screening of faulty chips and affecting the debugging of the entire system function of the multi-chip package.

[0005] Therefore, how to improve the debugging efficiency of the system function of a multi-chip package is a technical problem that needs to be solved urgently at present. Summary of the Invention

[0006] The purpose of the present invention is to provide a method and device for controlling the working mode of a chip and a multi-chip packaging structure to improve the debugging efficiency of the system function of a multi-chip package.

[0007] To achieve the above purpose, the embodiments of the present invention provide the following solutions:

[0008] In a first aspect, the embodiments of the present invention provide a method for controlling the working mode of a chip in a multi-chip package, the method comprising:

[0009] Obtaining a comparison result of the working voltages of a first working voltage vdd1 and a second working voltage vdd2; wherein, vdd1 is the working voltage of a first chip; vdd2 is the working voltage of a second chip;

[0010] According to the comparison result of the operating voltages, control the operating mode of the input driver so that the first chip operates in an operating mode adapted to the operating mode of the input driver; wherein, the second chip is connected to the first chip through the input driver.

[0011] In a possible embodiment, the obtaining the comparison result of the first operating voltage vdd1 and the second operating voltage vdd2 includes:

[0012] Obtain the comparison result of the operating voltages according to the output signal of the operating voltage monitor.

[0013] In a possible embodiment, the controlling the operating mode of the input driver according to the comparison result of the operating voltages includes:

[0014] If vdd1 and vdd2 in the comparison result of the operating voltages satisfy vdd2 ≤ k·vdd1, adjust the input driver to an internal pull-down mode or an internal pull-up mode so that the first chip operates in the default operating mode in which the second chip is not powered on normally; where k is a positive number less than 1;

[0015] If vdd1 and vdd2 in the comparison result of the operating voltages satisfy k·vdd1 < vdd2 ≤ vdd1, control the input driver to convert the vdd2 voltage domain input signal into a vdd1 voltage domain output signal through the levelshifter path so that the first chip operates in the normal operating mode in which the second chip has completed power-on;

[0016] If vdd1 and vdd2 in the comparison result of the operating voltages satisfy vdd1 < vdd2, control the input driver to convert the vdd2 voltage domain input signal into a vdd1 voltage domain output signal through the buffer path so that the first chip operates in the normal operating mode.

[0017] In a second aspect, an embodiment of the present invention provides a multi-chip package structure, the interior of the structure includes a first chip and a second chip, and the structure further includes:

[0018] An operating voltage monitor, whose input terminals are respectively connected to the operating voltage vdd1 of the first chip and the operating voltage vdd2 of the second chip, and is used to output the comparison result of the operating voltages of vdd1 and vdd2;

[0019] An input driver, whose input terminal is connected to the output terminal of the operating voltage monitor, and is used to control the operating mode of the input driver according to the comparison result of the operating voltages so that the first chip operates in an operating mode adapted to the operating mode of the input driver; wherein, the second chip is connected to the first chip through the input driver.

[0020] In a possible embodiment, the working voltage monitor includes a first voltage dividing circuit, a second voltage dividing circuit, a first comparator, a second comparator, an en_lvsft output terminal, and a flag_vdd2on output terminal;

[0021] The first voltage dividing circuit is connected between vdd2 and ground and includes a first voltage dividing point;

[0022] The second voltage dividing circuit is connected between vdd1 and ground and includes a high-voltage voltage dividing point and a low-voltage voltage dividing point;

[0023] The first voltage dividing point is respectively connected to the inverting input terminal of the first comparator and the non-inverting input terminal of the second comparator;

[0024] The high-voltage voltage dividing point is connected to the non-inverting input terminal of the first comparator;

[0025] The low-voltage voltage dividing point is connected to the inverting input terminal of the second comparator;

[0026] The output terminal of the first comparator is connected to the en_lvsft output terminal; wherein, the en_lvsft output terminal is connected to the en_ls input terminal of the input driver;

[0027] The output terminal of the second comparator is connected to the flag_vdd2on output terminal; wherein, the flag_vdd2on output terminal is connected to the en_in input terminal of the input driver.

[0028] In a possible embodiment, the input driver includes a level shifter path and a buffer path;

[0029] Wherein, the level shifter path is used to convert a vdd2 voltage domain input signal into a vdd1 voltage domain output signal when k·vdd1 < vdd2 ≤ vdd1, so that the first chip operates in a normal operating mode after the second chip is powered on; the buffer path is used to convert a vdd2 voltage domain input signal into a vdd1 voltage domain output signal when vdd1 < vdd2, so that the first chip operates in the normal operating mode; k is a positive number less than 1.

[0030] In a possible embodiment, in the level shifter path:

[0031] The signal input terminal of the input driver is connected to the gate of the first MOS transistor through a first inverter and a second inverter in sequence; the second MOS transistor and the third MOS transistor are connected in parallel between VDD1 and the source of the first MOS transistor; the drain of the first MOS transistor is grounded;

[0032] The fourth MOS transistor and the fifth MOS transistor are connected in parallel between the drain of the sixth MOS transistor and the ground; the source of the sixth MOS transistor is connected to VDD1; the gate of the sixth MOS transistor is connected to the source of the first MOS transistor; the gate of the third MOS transistor is connected to the drain of the sixth MOS transistor; the gate of the fourth MOS transistor is connected to the output terminal of the first inverter;

[0033] The seventh MOS transistor, the eighth MOS transistor, the ninth MOS transistor and the tenth MOS transistor are connected in series between VDD1 and the ground; the drain of the sixth MOS transistor is respectively connected to the gate of the eighth MOS transistor and the gate of the ninth MOS transistor;

[0034] The EN_IN input terminal of the input driver is connected to the gate of the second MOS transistor; the EN_IN input terminal is also connected to the gate of the fifth MOS transistor through a third inverter;

[0035] The EN_LS input terminal of the input driver is connected to the gate of the seventh MOS transistor; the EN_LS input terminal is also connected to the gate of the tenth MOS transistor through a fourth inverter;

[0036] The drain of the eighth MOS transistor is connected to the signal output terminal of the input driver through a fifth inverter;

[0037] Among them, the first MOS transistor, the fourth MOS transistor, the fifth MOS transistor, the ninth MOS transistor and the tenth MOS transistor have the same channel type; the second MOS transistor, the third MOS transistor, the sixth MOS transistor, the seventh MOS transistor and the eighth MOS transistor have the same channel type; the first MOS transistor and the second MOS transistor have different channel types.

[0038] In a possible embodiment, in the buffer path:

[0039] The eleventh MOS transistor, the twelfth MOS transistor, the thirteenth MOS transistor and the fourteenth MOS transistor are connected in series between VDD2 and the ground; the signal input terminal of the input driver is respectively connected to the gate of the twelfth MOS transistor and the gate of the thirteenth MOS transistor;

[0040] The EN_LS input terminal is also connected to the gate of the eleventh MOS transistor; the EN_LS input terminal is also connected to the gate of the fourteenth MOS transistor through a fourth inverter;

[0041] The drain of the twelfth MOS transistor is connected to the signal output terminal of the input driver through a fifth inverter;

[0042] Among them, the channel types of the eleventh MOS transistor and the twelfth MOS transistor are the same as those of the second MOS transistor; the channel types of the thirteenth MOS transistor and the fourteenth MOS transistor are the same as those of the first MOS transistor.

[0043] In a possible embodiment, the input driver further has an internal pull-down mode or an internal pull-up mode, which is used to output a pull-down low-level signal or a pull-up high-level signal when vdd2 ≤ k·vdd1, so that the first chip operates in a default operating mode in which the second chip is not normally powered on.

[0044] In a possible embodiment, the first chip is connected to the second chip through an output driver.

[0045] In a possible embodiment, the output driver includes a sixth inverter and a seventh inverter;

[0046] The signal input terminal of the output driver is connected to the signal output terminal of the output driver through the sixth inverter and the seventh inverter in sequence.

[0047] In a third aspect, an embodiment of the present invention provides a control device for the operating mode of a chip in a multi-chip package. The device includes:

[0048] A first acquisition module, configured to acquire a comparison result of the operating voltages of a first operating voltage vdd1 and a second operating voltage vdd2; wherein, vdd1 is the operating voltage of the first chip; vdd2 is the operating voltage of the second chip;

[0049] A first control module, configured to control the operating mode of the input driver according to the comparison result of the operating voltages, so that the first chip operates in an operating mode adapted to the operating mode of the input driver; wherein, the second chip is connected to the first chip through the input driver.

[0050] In a possible embodiment, the first acquisition module includes:

[0051] A second acquisition module, configured to acquire the comparison result of the operating voltages according to the output signal of an operating voltage monitor.

[0052] In a possible embodiment, the first control module includes:

[0053] A second control module, configured to adjust the input driver to an internal pull-down mode or an internal pull-up mode when vdd1 and vdd2 in the comparison result of the operating voltages satisfy vdd2 ≤ k·vdd1, so that the first chip operates in a default operating mode in which the second chip is not normally powered on; wherein, k is a positive number less than 1;

[0054] A third control module, configured to control the input driver to convert an input signal in the vdd2 voltage domain into an output signal in the vdd1 voltage domain through a level shifter path when k·vdd1 < vdd2 ≤ vdd1 in the working voltage comparison result, so that the first chip operates in a normal operating mode after the second chip is powered on;

[0055] A fourth control module, configured to control the input driver to convert an input signal in the vdd2 voltage domain into an output signal in the vdd1 voltage domain through a buffer path when vdd1 < vdd2 in the working voltage comparison result, so that the first chip operates in the normal operating mode.

[0056] In a fourth aspect, an embodiment of the present invention provides a multi-chip packaged microsystem, including: the multi-chip packaging structure according to any one of the second aspects.

[0057] In a fifth aspect, an embodiment of the present invention provides a computer system, including a multi-chip packaged microsystem, and the multi-chip packaged microsystem executes the steps of any one of the methods in the first aspect.

[0058] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0059] According to the working voltage comparison result of the first working voltage vdd1 and the second working voltage vdd2, the present invention controls the working mode of the input driver, so that the first chip operates in a working mode adapted to the working mode of the input driver, reducing the interference of incorrect working states, leakage, etc. on tests such as chip screening, and improving the system function debugging efficiency of multi-chip packaging. Description of the Drawings

[0060] In order to more clearly illustrate the technical solutions in the embodiments of the present specification or the prior art, the following will briefly introduce the drawings required for use in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present specification. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0061] Figure 1 is a schematic diagram of a microsystem composed of a typical 3D multi-chip package;

[0062] Figure 2 is Figure 1 the schematic diagram of the microsystem;

[0063] Figure 3It is a flowchart of a method for controlling the chip operating mode in a multi-chip package provided by an embodiment of the present invention;

[0064] Figure 4 It is a schematic structural diagram of a multi-chip package structure provided by an embodiment of the present invention;

[0065] Figure 5 It is a schematic structural diagram of a multi-chip package structure provided by an embodiment of the present invention;

[0066] Figure 6 is Figure 5 A connection diagram of the vdd2 operating voltage monitor in the multi-chip package structure shown;

[0067] Figure 7 is Figure 5 A connection diagram of the input driver in the multi-chip package structure shown;

[0068] Figure 8 is Figure 5 A connection diagram of the output driver in the multi-chip package structure shown;

[0069] Figure 9 is Figure 5 A schematic diagram of the working principle of the multi-chip package structure shown;

[0070] Figure 10 An embodiment of the present invention also provides a control device for the chip operating mode in a multi-chip package.

[0071] Explanation of reference numerals: dieA is the first chip, dieB is the second chip, 100 is the operating voltage monitor, 101 is the first comparator, 102 is the second comparator, 103 is the first voltage dividing circuit, 104 is the second voltage dividing circuit, 200 is the input driver, 210 is the levelshifter path, 211 is the first inverter, 212 is the second inverter, 213 is the third inverter, 214 is the fourth inverter, 215 is the fifth inverter, 220 is the buffer path, 300 is the output driver, 301 is the sixth inverter, 302 is the seventh inverter, M1 is the first MOS transistor, M2 is the second MOS transistor, M3 is the third MOS transistor, M4 is the fourth MOS transistor, M5 is the fifth MOS transistor, M6 is the sixth MOS transistor, M7 is the seventh MOS transistor, M8 is the eighth MOS transistor, M9 is the ninth MOS transistor, M10 is the tenth MOS transistor, M11 is the eleventh MOS transistor, M12 is the twelfth MOS transistor, M13 is the thirteenth MOS transistor, M14 is the fourteenth MOS transistor. Detailed implementation manners

[0072] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention belong to the scope protected by the embodiments of the present invention.

[0073] Figure 1 is a schematic diagram of a typical micro-system composed of 3D multi-chip packaging, which includes two chips: die A and die B. The operating voltages of the two chips are different, and the functions of the chips can be the same or different; signal interconnections connector (such as through-silicon vias TSV, hybrid bonding wires Hybrid Bonding, etc.) can achieve electrical connection between die A and die B, and signal interconnections Bonding (such as ordinary bonding wires Bonding Wire, solder bumps Solder Bump, etc.) achieve electrical connection between chips and between chips and the outside world through metal traces in the packaging substrate substrate.

[0074] Since each chip in the multi-chip packaging operates in a different power domain and implements the same or different functions, each chip requires a suitable input / output circuit (i.e., InputOutput circuit, hereinafter referred to as IO circuit) to achieve communication between different chips and between the chips and the outside world, so as to achieve the function of a complete micro-system. Figure 2 is Figure 1Schematic diagram of the microsystem. Die A consists of a core circuit dieA_core and an input / output circuit IOA, implementing functions such as control and calculation. Die B consists of a core circuit dieB_core and an input / output circuit IOB, implementing functions such as storage, digital-to-analog conversion, and data exchange. The input / output circuit IOA includes several output drivers and several input drivers. The output drivers of die A enhance the driving ability of the signals processed by dieA_core and output them to the input drivers of die B through the interconnect line 31. The input drivers of die A are vdd2 to vdd1 level shifters (i.e., levelshifters), which convert the input vdd2 power domain signal IO_n to the vdd1 power domain and then deliver it to dieA_core121. The die B on the right operates in the vdd2 power domain and consists of a core circuit dieB_core and an input / output circuit IOB. DieB_core implements its corresponding functions (such as storage, digital-to-analog conversion, data exchange, etc.). The input / output circuit IOB includes several output drivers and input drivers. The output drivers of die B enhance the driving ability of the signals processed by dieB_core and output them to the input drivers of dieA11 through the interconnect line 3n. The input drivers of die B are vdd1 to vdd2 level shifters, which convert the input vdd1 power domain signal IO_1 to the vdd2 power domain and then deliver it to dieB_core.

[0075] When analyzing and researching the technical problem of the low efficiency of the system function debugging scheme for multi-chip packaging in the prior art, the inventors of the present invention found that:

[0076] Before chip packaging, the IO circuits of each chip are not electrically connected through interconnect lines, and the inputs of their IO circuits are in a floating state, which may lead to incorrect working states of the chips and leakage at the same time, thus interfering with the test results of the chips and being unfavorable for screening defective chips.

[0077] Even after multiple chips are packaged, if a certain die is not powered on or the power-on is not completed, the inputs of the IO circuits in other dies connected to it are in a floating state, which may lead to uncertain working states and is thus unfavorable for the debugging of the entire system function.

[0078] All the above reasons affect the efficiency of the system function debugging scheme for multi-chip packaging in the prior art.

[0079] In addition, since each die operates in a different power domain and some dies have a relatively wide power voltage range in different working modes, the input drivers composed of a single level shifter (levelshifter) may not be able to meet the requirements of functions and performances under a wide range of power voltages at the same time.

[0080] To this end, the present invention hopes to reduce the interference of the inappropriate working mode of the chip on the system function debugging of the multi-chip package by accurately controlling the working mode of the chip in the multi-chip package, thereby improving the debugging efficiency of the system function of the multi-chip package.

[0081] As Figure 3 The figure shows a flowchart of a method for controlling the working mode of a chip in a multi-chip package provided by an embodiment of the present invention. The embodiment of this method can be applied to the multi-chip package structure described below, and specifically includes steps 11 to 12.

[0082] Step 11, obtain the working voltage comparison result of the first working voltage vdd1 and the second working voltage vdd2.

[0083] Wherein, vdd1 is the working voltage of the first chip dieA; vdd2 is the working voltage of the second chip dieB.

[0084] Specifically, the working voltage comparison of the first working voltage vdd1 and the second working voltage vdd2 can be implemented based on the working voltage monitor 100 with voltage comparison function, and specifically includes step 21.

[0085] Step 21, obtain the working voltage comparison result according to the output signal of the working voltage monitor 100.

[0086] Specifically, a voltage comparator can be set inside the working voltage monitor 100 to implement the working voltage comparison of the first working voltage vdd1 and the second working voltage vdd2.

[0087] Of course, the first working voltage vdd1 and the second working voltage vdd2 can also be converted into corresponding digital signals, and the numerical sizes of the corresponding digital signals can be directly used to compare the voltages of the two. Of course, based on the purpose of this step, other solutions can also be used to implement the operation of this step, which is not limited here.

[0088] Step 12, control the working mode of the input driver 200 according to the working voltage comparison result, so that the first chip dieA works in a working mode adapted to the working mode of the input driver 200.

[0089] Wherein, the second chip dieB is connected to the first chip dieA through the input driver 200.

[0090] Specifically, between the first chip dieA and the second chip dieB, since the input / output lines cannot be directly detected, there may be no electrical connection between the first chip dieA and the second chip dieB. Even if there is an electrical connection between the first chip dieA and the second chip dieB, the second chip dieB may be in an unpowered state or may be in a state where power-on is not completed. At this time, the first chip dieA is prone to leakage, incorrect working states, etc., affecting the debugging and detection of multi-chip packaging.

[0091] At the same time, in some cases, the voltage domain range of the input signal is too wide, and the input driver 200 composed of a single level shifter may not be able to meet the requirements of both function and performance simultaneously. This makes it possible for performance mismatches and other faults to occur even when the first chip dieA operates in a normal working mode.

[0092] In this embodiment, the working mode of the first chip dieA is matched with the working mode of the input driver 200, enabling the first chip dieA to operate in the correct working mode, avoiding the first chip dieA operating in a working mode that is not suitable for the working mode of the input driver 200, reducing interference from incorrect working states, leakage, etc. to the chip probe test, and improving the system function debugging efficiency of multi-chip packaging.

[0093] Here, this embodiment also provides a control scheme for the input driver 200, specifically including steps 31 to 33.

[0094] Step 31, if vdd1 and vdd2 in the working voltage comparison result satisfy vdd2 ≤ k·vdd1, then adjust the input driver 200 to the internal pull-down mode or the internal pull-up mode, so that the first chip dieA operates in the default working mode when the second chip dieB is not normally powered on; where k is a positive number less than 1.

[0095] Specifically, when vdd1 and vdd2 in the working voltage comparison result satisfy vdd2 ≤ k·vdd1, it indicates that there is an abnormal electrical connection between the first chip dieA and the second chip dieB, or the second chip dieB is not powered on, or the second chip dieB has not completed power-on, or the second chip dieB is not normally powered on between the first chip dieA and the second chip dieB. At this time, the input driver 200 is adjusted to the internal pull-down mode or the internal pull-up mode, directly outputting a pull-down low-level signal or a pull-up high-level signal to the first chip dieA, triggering the first chip dieA to enter the default working mode for dealing with the situation where the second chip dieB is not normally powered on.

[0096] Specifically, the value of k can be flexibly selected based on the requirements of the actual application scenario.

[0097] Step 32, if in the working voltage comparison result, vdd1 and vdd2 satisfy k·vdd1 < vdd2 ≤ vdd1, control the input driver 200 to convert the vdd2 voltage domain input signal into a vdd1 voltage domain output signal through the levelshifter path 210, so that the first chip dieA operates in the normal working mode after the second chip dieB is powered on. Here, the levelshifter path can be a kind of level conversion circuit, which can realize the conversion between the vdd1 voltage domain and the vdd2 voltage domain.

[0098] Specifically, when vdd1 and vdd2 in the working voltage comparison result satisfy k·vdd1 < vdd2 ≤ vdd1, in this step, directly use the levelshifter path 210 in the input driver 200 to convert the vdd2 voltage domain input signal, and limit the voltage of this input signal between 0 and vdd1. The levelshifter path 210 can be implemented by using an existing levelshifter circuit, which will not be elaborated here.

[0099] Step 33, if in the working voltage comparison result, vdd1 and vdd2 satisfy vdd1 < vdd2, control the input driver 200 to convert the vdd2 voltage domain input signal into a vdd1 voltage domain output signal through the buffer path 220, so that the first chip dieA operates in the normal working mode.

[0100] Specifically, when vdd1 and vdd2 in the working voltage comparison result satisfy vdd1 < vdd2, in this step, directly use the buffer path 220 in the input driver 200 to convert the vdd2 voltage domain input signal, and limit the voltage of this input signal between 0 and vdd1. The buffer path 220 can be implemented by using an existing buffer circuit, which will not be elaborated here.

[0101] Through the cooperation of Step 32 and Step 33 in this embodiment, it is possible to adapt to the vdd2 voltage domain input signal with a relatively wide voltage domain, improving the adaptability of the chip.

[0102] The above method embodiments can be implemented based on any of the multi-chip packaging structures described below, and other multi-chip packaging structures can also be used to implement the above method embodiments, which are not limited here.

[0103] Based on the same inventive concept as the method, an embodiment of the present invention also provides a multi-chip packaging structure, which can implement the above method embodiments. As Figure 4The figure shows a schematic structural diagram of the multi-chip package structure, which includes two first chips dieA and second chips dieB for implementing different functions.

[0104] The structure further includes: a working voltage monitor 100, whose input terminals are respectively connected to the working voltage vdd1 of the first chip dieA and the working voltage vdd2 of the second chip dieB, for outputting the comparison result of the working voltages of vdd1 and vdd2; an input driver 200, whose input terminal is connected to the output terminal of the working voltage monitor 100, for controlling the working mode of the input driver 200 according to the working voltage comparison result, so that the first chip dieA operates in a working mode adapted to the working mode of the input driver 200; wherein, the second chip dieB is connected to the first chip dieA through the input driver 200.

[0105] Specifically, between the first chip dieA and the second chip dieB, since the input-output lines cannot be directly detected, there may be no electrical connection between the first chip dieA and the second chip dieB; even if there is an electrical connection between the first chip dieA and the second chip dieB, the second chip dieB may be in an unpowered state or in a state where the power-on is not completed. At this time, the first chip dieA is prone to leakage, incorrect working state, etc., affecting the debugging and detection of the multi-chip package.

[0106] At the same time, in some cases, the voltage domain range of the input signal is too wide, and the input driver 200 composed of a single level shifter may not be able to meet the requirements of both function and performance at the same time. This makes it possible for faults such as performance mismatch to occur even when the first chip dieA operates in a normal working mode.

[0107] In this embodiment, the working mode of the first chip dieA is matched with the working mode of the input driver 200, so that the first chip dieA can operate in the correct working mode, avoiding interference from incorrect working states, leakage, etc. of the first chip dieA to the chip screening test, and improving the system function debugging efficiency of the multi-chip package.

[0108] In addition, in this embodiment, through the cooperation of the level shifter path 210 and the buffer path 220, it can adapt to input signals with a relatively wide voltage domain vdd2, improving the adaptability of the chip.

[0109] As Figure 5 shown is a schematic structural diagram of a multi-chip package structure provided by an embodiment of the present invention. Figure 6 is Figure 5Schematic diagram of the connection of the vdd2 operating voltage monitor in the multi-chip package structure shown. Among them: The operating voltage monitor 100 is a vdd2 operating voltage monitor, including a first voltage dividing circuit 103, a second voltage dividing circuit 104, a first comparator 101, a second comparator 102, an en_lvsft output terminal, and a flag_vdd2on output terminal.

[0110] The first voltage dividing circuit 103 is connected between vdd2 and ground and includes a first voltage dividing point vr_vdd2. Figure 5 In the form of two resistors connected in series is adopted to construct the first voltage dividing circuit 103. Of course, other implementation methods of voltage dividing circuits can also be used.

[0111] The second voltage dividing circuit 104 is connected between vdd1 and ground and includes a high-voltage dividing point vrh_vdd1 and a low-voltage dividing point vrl_vdd1. The voltage of vrh_vdd1 is higher than the voltage of vrl_vdd1. Figure 6 In the form of three resistors connected in series is adopted to construct the second voltage dividing circuit 104. Of course, other implementation methods of voltage dividing circuits can also be used.

[0112] The first voltage dividing point vr_vdd2 is respectively connected to the inverting input terminal of the first comparator 101 and the non-inverting input terminal of the second comparator 102; the high-voltage dividing point vrh_vdd1 is connected to the non-inverting input terminal of the first comparator 101; the low-voltage dividing point vrl_vdd1 is connected to the inverting input terminal of the second comparator.

[0113] The output terminal of the first comparator 101 is connected to the en_lvsft output terminal, which can output an en_lvsft signal; among them, the en_lvsft output terminal is connected to the en_ls input terminal of the input driver 200; the output terminal of the second comparator 102 is connected to the flag_vdd2on output terminal, which can output a flag_vdd2on signal; among them, the flag_vdd2on output terminal is connected to the en_in input terminal of the input driver 200.

[0114] The en_lvsft signal is a high-level signal or a low-level signal. Specifically, it is judged whether it is a high-level signal or a low-level signal according to the voltage amplitude of the en_lvsft signal. Among them, a high-level signal refers to a signal exceeding the high-voltage threshold, and a low-level signal refers to a signal lower than the low-voltage threshold. For example, when the en_lvsft signal exceeds 2.2V, the en_lvsft signal is a high-level signal, and when the en_lvsft signal is lower than 0.5V, the en_lvsft signal is a low-level signal.

[0115] In Figure 6In the connection schematic diagram of the vdd2 operating voltage monitor shown, when the voltage at the positive input terminal of the first comparator 101 is greater than the voltage at its negative input terminal, the en_lvsft signal output by the first comparator 101 is a high-level signal; conversely, the en_lvsft signal output by the first comparator 101 is a low-level signal.

[0116] The flag_vdd2on signal is either a high-level signal or a low-level signal. Specifically, it is determined whether it is a high-level signal or a low-level signal based on the voltage amplitude of the flag_vdd2on signal. Here, a high-level signal refers to a signal exceeding the high-voltage threshold, and a low-level signal refers to a signal below the low-voltage threshold. For example, when the flag_vdd2on signal exceeds 2.2V, the flag_vdd2on signal is a high-level signal; when the flag_vdd2on is below 0.5V, the flag_vdd2on signal is a low-level signal.

[0117] In Figure 6 In the connection schematic diagram of the vdd2 operating voltage monitor shown, when the voltage at the positive input terminal of the second comparator 102 is greater than the voltage at its negative input terminal, the flag_vdd2on signal output by the second comparator 102 is a high-level signal; conversely, the flag_vdd2on signal output by the second comparator 102 is a low-level signal.

[0118] In this embodiment, based on the level of the en_lvsft signal and the level of the flag_vdd2on signal, the comparison between vdd1 and vdd2 can be achieved, thereby obtaining a specific operating voltage comparison result.

[0119] As Figure 7 Shown is Figure 5 In the connection schematic diagram of the input driver in the multi-chip package structure shown, the input driver 200 includes a level shifter path 210 and a buffer path 220;

[0120] Among them, the level shifter path 210 is used to convert the vdd2 voltage domain input signal into a vdd1 voltage domain output signal when k·vdd1 < vdd2 ≤ vdd1, so that the first chip dieA operates in the normal operating mode after the second chip dieB is powered on; the buffer path 220 is used to convert the vdd2 voltage domain input signal into a vdd1 voltage domain output signal when vdd1 ≤ vdd2, so that the first chip dieA operates in the normal operating mode; k is a positive number less than 1.

[0121] The input driver 200 is also provided with an internal pull-down mode or an internal pull-up mode, which is used to output a pull-down low-level signal or a pull-up high-level signal when vdd1 and vdd2 in the working voltage comparison result satisfy vdd2 ≤ k·vdd1, so that the first chip dieA operates in the default working mode where the second chip dieB is not normally powered on.

[0122] Specifically, when vdd1 and vdd2 in the working voltage comparison result satisfy k·vdd1 < vdd2 ≤ vdd1, this step directly uses the levelshifter path 210 in the input driver 200 to convert the input signal in the vdd2 voltage domain, and limits the voltage of the input signal between 0 and vdd1. The levelshifter path 210 can be implemented by using an existing levelshifter circuit, which will not be elaborated here.

[0123] Specifically, when vdd1 and vdd2 in the working voltage comparison result satisfy vdd1 < vdd2, this step directly uses the buffer path 220 in the input driver 200 to convert the input signal in the vdd2 voltage domain, and limits the voltage of the input signal between 0 and vdd1. The buffer path 220 can be implemented by using an existing buffer circuit, which will not be elaborated here.

[0124] Specifically, the value of the k is related to the specific resistance values of the voltage-dividing resistors in the first voltage-dividing circuit 103 and the second voltage-dividing circuit 104, and can be flexibly set according to actual needs.

[0125] Figure 6 In the levelshifter path 210: The signal input terminal of the input driver 200 is sequentially connected to the gate of the first MOS transistor M1 through the first inverter 211 and the second inverter 212; The second MOS transistor M2 and the third MOS transistor M3 are connected in parallel between vdd1 and the source of the first MOS transistor M1; The drain of the first MOS transistor M1 is grounded.

[0126] The fourth MOS transistor M4 and the fifth MOS transistor M5 are connected in parallel between the drain of the sixth MOS transistor M6 and the ground; The source of the sixth MOS transistor M6 is connected to vdd1; The gate of the sixth MOS transistor M6 is connected to the source of the first MOS transistor M1; The gate of the third MOS transistor M3 is connected to the drain of the sixth MOS transistor M6; The gate of the fourth MOS transistor M4 is connected to the output terminal of the first inverter 211.

[0127] The seventh MOS transistor M7, the eighth MOS transistor M8, the ninth MOS transistor M9 and the tenth MOS transistor M10 are connected in series between vdd1 and the ground; The drain of the sixth MOS transistor M6 is respectively connected to the gate of the eighth MOS transistor M8 and the gate of the ninth MOS transistor M9.

[0128] The gate of the second MOS transistor M2 is connected to the en_in input terminal of the input driver 200; the en_in input terminal is also connected to the gate of the fifth MOS transistor M5 through the third inverter 213.

[0129] The gate of the seventh MOS transistor M7 is connected to the en_ls input terminal of the input driver 200; the en_ls input terminal is also connected to the gate of the tenth MOS transistor M10 through the fourth inverter 214.

[0130] The drain of the eighth MOS transistor M8 is connected to the signal output terminal of the input driver 200 through the fifth inverter 215.

[0131] Among them, the channel types of the first MOS transistor M1, the fourth MOS transistor M4, the fifth MOS transistor M5, the ninth MOS transistor M9, and the tenth MOS transistor M10 are the same; the channel types of the second MOS transistor M2, the third MOS transistor M3, the sixth MOS transistor M6, the seventh MOS transistor M7, and the eighth MOS transistor M8 are the same; the channel types of the first MOS transistor M1 and the second MOS transistor M2 are different. That is: when the first MOS transistor M1, the fourth MOS transistor M4, the fifth MOS transistor M5, the ninth MOS transistor M9, and the tenth MOS transistor M10 are PMOS transistors, the second MOS transistor M2, the third MOS transistor M3, the sixth MOS transistor M6, the seventh MOS transistor M7, and the eighth MOS transistor M8 are NMOS transistors; when the first MOS transistor M1, the fourth MOS transistor M4, the fifth MOS transistor M5, the ninth MOS transistor M9, and the tenth MOS transistor M10 are NMOS transistors, the second MOS transistor M2, the third MOS transistor M3, the sixth MOS transistor M6, the seventh MOS transistor M7, and the eighth MOS transistor M8 are PMOS transistors.

[0132] Figure 6 In the buffer path 220 of: the eleventh MOS transistor M11, the twelfth MOS transistor M12, the thirteenth MOS transistor M13, and the fourteenth MOS transistor M14 are connected in series between vdd1 and ground; the signal input terminal of the input driver 200 is respectively connected to the gate of the twelfth MOS transistor M12 and the gate of the thirteenth MOS transistor M13; the en_ls input terminal is also connected to the gate of the eleventh MOS transistor M11; the en_ls input terminal is also connected to the gate of the fourteenth MOS transistor M14 through the fourth inverter 214; the drain of the twelfth MOS transistor M12 is connected to the signal output terminal of the input driver 200 through the fifth inverter 215; among them, the channel types of the eleventh MOS transistor M11 and the twelfth MOS transistor M12 are the same as the channel type of the second MOS transistor M2; the channel types of the thirteenth MOS transistor M13 and the fourteenth MOS transistor M14 are the same as the channel type of the first MOS transistor M1.

[0133] The first chip dieA is connected to the second chip dieB through the output driver 300.

[0134] Specifically, the output driver 300 can be implemented using a buffer circuit.

[0135] Here, a typical buffer circuit is provided to implement the output driver 300. As Figure 8 shown in Figure 5 the connection schematic diagram of the output driver in the multi-chip package structure shown, specifically:

[0136] The output driver 300 includes a sixth inverter 301 and a seventh inverter 302; the signal input terminal of the output driver 300 is connected to the signal output terminal of the output driver 300 through the sixth inverter 301 and the seventh inverter 302 in sequence.

[0137] To more clearly illustrate the working process of the multi-chip package structure provided in this embodiment, here, taking Figure 5 the multi-chip package structure shown as an example, the working process of this embodiment is described.

[0138] Specifically, dieA operates in the vdd1 power domain, and dieA_core implements its corresponding functions (such as control, calculation, etc.); the IO circuit IOA of dieA includes several output drivers 300, several input drivers 200, and a vdd2 operating voltage monitor 100; the input terminal in of the output driver 300 is connected to dieA_core, and the output terminal out is connected to the interconnection line 31, and after enhancing the driving ability of the signal processed by dieA_core, it is output to the input driver of dieB through the interconnection line 31; the in input terminal of the input driver 200 of dieA is connected to the interconnection line 3n, the en_in input terminal and the en_ls input terminal are respectively connected to the flag_vdd2on output terminal and the en_lvsft output terminal of the vdd2 operating voltage monitor 100, and the output terminal out is connected to dieA_core, and the input vdd2 power domain signal IO_n is converted to the vdd1 power domain and then transmitted to dieA_core; the pwrdet input terminal of the vdd2 operating voltage monitor 100 is connected to the power supply vdd2 of dieB through the power supply interconnection line 3AB2, and the output signals flag_vdd2on and en_lvsft are respectively connected to the en_in input terminal and the en_ls input terminal of the input driver 200, and by monitoring the state of vdd2, the input driver 200 is controlled to operate in different modes. The structure of dieB is similar to that of dieA and will not be elaborated here.

[0139] The VDD2 working voltage monitor 100 is composed of two groups of resistor voltage divider strings and two comparators. Among them, VDD1 is divided by the resistor voltage divider string to obtain a reference voltage, which is compared with the divided voltage value of VDD2 through a comparator to judge the power supply state of VDD2. Its output signals, the flag_VDD2on signal and the en_LVSFT signal, control the input driver 200 to work in an appropriate mode. The input driver 200 is divided into a level shifter path 210 and a buffer path 220. The output driver 300 is a typical buffer composed of inverters.

[0140] As described above, the voltage monitor controls the input driver 200 to work in different modes by monitoring the power supply state of the other party, such as Figure 9 shown as Figure 5 the schematic diagram of the working principle of the multi-chip package structure shown below, which mainly includes the following three modes: (The signals output from die B to die A are similar to those output from die A to die B. Here, the signals output from die B to die A are taken as an example to illustrate the working process of this embodiment)

[0141] Mode 1: When the power supply voltage VDD2 of die B is lower than k times the power supply voltage VDD1 of die A (where k is a constant, for example, k = 1 / 2), the output signal flag_VDD2on of the VDD2 voltage monitor is low and en_LVSFT is high, indicating that die B is not connected to die A (i.e., before multi-chip packaging) or die B is not powered on or the power-on is not completed. Then, the input drive circuit defaults to pull-down (or pull-up) internally, and die A enters its default working mode.

[0142] Mode 2: When the power supply voltage VDD2 of die B is higher than k times the power supply voltage VDD1 of die A and still lower than VDD1, flag_VDD2on is high and en_LVSFT is high, indicating that die B has been connected to die A (i.e., after multi-chip packaging) or the power-on of die B is completed. Then, the input signal IO_n in the VDD2 power supply domain is converted into a signal in the VDD1 power supply domain through the level shfiter path in the input driver 200 and then sent to die A_core, and the system enters the normal working mode.

[0143] Mode 3: When the power supply voltage VDD2 of die B is higher than the power supply voltage VDD1 of die A, flag_VDD2on is high and en_LVSFT is low. Then, the input signal IO_n in the VDD2 power supply domain is converted into a signal in the VDD1 power supply domain through the buffer path 220 in the input driver 200 and then sent to die A_core, and the system enters the normal working mode.

[0144] Compared with the prior art, this embodiment has the following advantages and beneficial effects:

[0145] 1. The working power supplies of each die are connected to the other die through interconnection lines (such as power interconnection lines 3AB1 and 3AB2) to monitor the power supply status of the other die; according to the status of each power supply, the input driver 200 is automatically controlled to work in an appropriate mode to ensure that the IO works in the correct state;

[0146] 2. Before multi-chip packaging, the internal input drive circuit in the IO circuit is default pulled down (or pulled up), and the chip works in a default determined state without leakage, which is convenient for screening defective chips through chip probing testing of the chip;

[0147] 3. After multi-chip packaging, even if a certain die is not powered on or the power-on is not completed, the IO working state of the other die is also determined, and the debugging of the entire system function can continue;

[0148] 4. Each die works in a different voltage domain. For some dies, the power supply voltage range is relatively wide in different working modes. The power supply monitor controls the input driver 200 to select the level shifter path 210 or the buffer path 220 according to the power supply status, which can meet the requirements of both function and performance at the same time;

[0149] 5. In the same way, it can be extended to the control scheme of the second chip;

[0150] 6. In the same way, it can be extended to the packaging scheme of multiple dies, that is, the same or similar connection and IO signal processing methods can be adopted between every two dies.

[0151] Based on the same inventive concept as the method, the embodiment of the present invention also provides a control device for the working mode of a chip in multi-chip packaging, such as Figure 10 shown in the structural schematic diagram of the device, which specifically includes:

[0152] The first acquisition module 41 is used to acquire the working voltage comparison result of the first working voltage vdd1 and the second working voltage vdd2; wherein, vdd1 is the working voltage of the first chip dieA; vdd2 is the working voltage of the second chip dieB;

[0153] The first control module 42 is used to control the working mode of the input driver 200 according to the working voltage comparison result, so that the first chip dieA works in a working mode adapted to the working mode of the input driver 200; wherein, the second chip dieB is connected to the first chip dieA through the input driver 200.

[0154] In a possible embodiment, the first acquisition module includes:

[0155] A second acquisition module, configured to acquire the working voltage comparison result according to the output signal of the working voltage monitor 100.

[0156] In a possible embodiment, the first control module includes:

[0157] A second control module, configured to adjust the input driver 200 to an internal pull - down mode or an internal pull - up mode when vdd1 and vdd2 in the working voltage comparison result satisfy vdd2 ≤ k·vdd1, so that the first chip dieA operates in a default working mode in which the second chip dieB is not normally powered on; where k is a positive number less than 1;

[0158] A third control module, configured to control the input driver 200 to convert the vdd2 voltage domain input signal into a vdd1 voltage domain output signal through the levelshifter path 210 when vdd1 and vdd2 in the working voltage comparison result satisfy k·vdd1 < vdd2 ≤ vdd1, so that the first chip dieA operates in a normal working mode in which the second chip dieB is powered on;

[0159] A fourth control module, configured to control the input driver 200 to convert the vdd2 voltage domain input signal into a vdd1 voltage domain output signal through the buffer path 220 when vdd1 and vdd2 in the working voltage comparison result satisfy vdd1 < vdd2, so that the first chip dieA operates in the normal working mode.

[0160] Based on the same inventive concept as the method, an embodiment of the present invention further provides a multi - chip - packaged microsystem, including: the multi - chip - packaging structure described in any one of the above.

[0161] Based on the same inventive concept as the method, an embodiment of the present invention further provides a computer system, including a multi - chip - packaged microsystem, and the multi - chip - packaged microsystem executes the steps of the method described in any one of the above.

[0162] The technical solution provided in the embodiment of the present invention has at least the following technical effects or advantages:

[0163] According to the working voltage comparison result of the first working voltage vdd1 and the second working voltage vdd2, the embodiment of the present invention controls the working mode of the input driver, so that the first chip operates in a working mode adapted to the working mode of the input driver, reducing the interference of incorrect working states, leakage, etc. of the first chip on the chip probe test, and improving the system function debugging efficiency of the multi - chip package.

[0164] Those skilled in the art should understand that the embodiments of the present invention can be provided as a method, a system, or a computer program product. Therefore, the present invention can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0165] The present invention is described with reference to the flowcharts and / or block diagrams of methods, apparatuses (modules, systems), and computer program products according to the embodiments of the present invention. It should be understood that each flow and / or block in the flowchart and / or block diagram, as well as the combination of flows and / or blocks in the flowchart and / or block diagram, can be realized by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded computer, or other programmable data processing devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices generate means for realizing the functions specified in Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0166] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing devices to work in a specific manner, so that the instructions stored in the computer-readable memory generate a manufactured article including instruction means, and the instruction means realizes the functions specified in Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0167] These computer program instructions can also be loaded onto a computer or other programmable data processing devices, so that a series of operation steps are executed on the computer or other programmable devices to generate a computer-implemented process. Thus, the instructions executed on the computer or other programmable devices provide steps for realizing the functions specified in Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0168] Although the preferred embodiments of the present invention have been described, those skilled in the art can make additional changes and modifications to these embodiments once they know the basic creative concepts. Therefore, the appended claims are intended to be construed as including the preferred embodiments and all changes and modifications falling within the scope of the present invention.

[0169] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention is also intended to include these modifications and variations.

Claims

1. A method for controlling the operating mode of chips in a multi-chip package, characterized in that, the method includes: Obtaining the operating voltage comparison result of the first operating voltage vdd1 and the second operating voltage vdd2; wherein, vdd1 is the operating voltage of the first chip; vdd2 is the operating voltage of the second chip; According to the operating voltage comparison result, controlling the operating mode of the input driver so that the first chip operates in an operating mode adapted to the operating mode of the input driver; wherein, the second chip is connected to the first chip through the input driver; The controlling the operating mode of the input driver according to the operating voltage comparison result includes: If vdd1 and vdd2 in the operating voltage comparison result satisfy vdd2 ≤ k·vdd1, then adjust the input driver to the internal pull-down mode or the internal pull-up mode so that the first chip operates in the default operating mode when the second chip is not powered on normally; where k is a positive number less than 1; If vdd1 and vdd2 in the operating voltage comparison result satisfy k·vdd1 < vdd2 ≤ vdd1, then control the input driver to convert the vdd2 voltage domain input signal into a vdd1 voltage domain output signal through the levelshifter path so that the first chip operates in the normal operating mode when the second chip is powered on; If vdd1 and vdd2 in the operating voltage comparison result satisfy vdd1 < vdd2, then control the input driver to convert the vdd2 voltage domain input signal into a vdd1 voltage domain output signal through the buffer path so that the first chip operates in the normal operating mode.

2. The method for controlling the operating mode of a chip according to claim 1, characterized in that, the obtaining the operating voltage comparison result of the first operating voltage vdd1 and the second operating voltage vdd2 includes: Obtaining the operating voltage comparison result according to the output signal of the operating voltage monitor.

3. A multi-chip package structure, the interior of the structure includes a first chip and a second chip, characterized in that, the structure further includes: An operating voltage monitor, whose input terminals are respectively connected to the operating voltage vdd1 of the first chip and the operating voltage vdd2 of the second chip, for outputting the operating voltage comparison result of vdd1 and vdd2; An input driver, whose input terminal is connected to the output terminal of the operating voltage monitor, for controlling the operating mode of the input driver according to the operating voltage comparison result so that the first chip operates in an operating mode adapted to the operating mode of the input driver; wherein, the second chip is connected to the first chip through the input driver; The controlling the operating mode of the input driver according to the operating voltage comparison result includes: If vdd1 and vdd2 in the comparison result of the operating voltages satisfy vdd2 ≤ k·vdd1, the input driver is adjusted to the internal pull - down mode or the internal pull - up mode, so that the first chip operates in the default operating mode where the second chip is not powered on properly; where k is a positive number less than 1. If vdd1 and vdd2 in the comparison result of the operating voltages satisfy k·vdd1 < vdd2 ≤ vdd1, the input driver is controlled to convert the vdd2 voltage domain input signal into a vdd1 voltage domain output signal through the levelshifter path, so that the first chip operates in the normal operating mode where the second chip is powered on. If vdd1 and vdd2 in the comparison result of the operating voltages satisfy vdd1 < vdd2, the input driver is controlled to convert the vdd2 voltage domain input signal into a vdd1 voltage domain output signal through the buffer path, so that the first chip operates in the normal operating mode.

4. The multi - chip package structure according to claim 3, characterized in that, the operating voltage monitor includes a first voltage - dividing circuit, a second voltage - dividing circuit, a first comparator, a second comparator, an en_lvsft output terminal, and a flag_vdd2on output terminal; the first voltage - dividing circuit is connected between vdd2 and ground and includes a first voltage - dividing point; the second voltage - dividing circuit is connected between vdd1 and ground and includes a high - voltage voltage - dividing point and a low - voltage voltage - dividing point; the first voltage - dividing point is respectively connected to the inverting input terminal of the first comparator and the non - inverting input terminal of the second comparator; the high - voltage voltage - dividing point is connected to the non - inverting input terminal of the first comparator; the low - voltage voltage - dividing point is connected to the inverting input terminal of the second comparator; the output terminal of the first comparator is connected to the en_lvsft output terminal; where the en_lvsft output terminal is connected to the en_ls input terminal of the input driver; the output terminal of the second comparator is connected to the flag_vdd2on output terminal; where the flag_vdd2on output terminal is connected to the en_in input terminal of the input driver.

5. The multi - chip package structure according to claim 4, characterized in that, the input driver includes a levelshifter path and a buffer path; wherein, the levelshifter path is used to convert the vdd2 voltage domain input signal into a vdd1 voltage domain output signal when k·vdd1 < vdd2 ≤ vdd1, so that the first chip operates in the normal operating mode where the second chip is powered on; the buffer path is used to convert the vdd2 voltage domain input signal into a vdd1 voltage domain output signal when vdd1 < vdd2, so that the first chip operates in the normal operating mode; k is a positive number less than 1.

6. The multi - chip package structure according to claim 5, characterized in that, in the levelshifter path: The signal input terminal of the input driver is sequentially connected to the gate of the first MOS transistor through a first inverter and a second inverter; the second MOS transistor and the third MOS transistor are connected in parallel between vdd1 and the source of the first MOS transistor; the drain of the first MOS transistor is grounded; The fourth MOS transistor and the fifth MOS transistor are connected in parallel between the drain of the sixth MOS transistor and the ground; the source of the sixth MOS transistor is connected to vdd1; the gate of the sixth MOS transistor is connected to the source of the first MOS transistor; the gate of the third MOS transistor is connected to the drain of the sixth MOS transistor; the gate of the fourth MOS transistor is connected to the output terminal of the first inverter; The seventh MOS transistor, the eighth MOS transistor, the ninth MOS transistor and the tenth MOS transistor are connected in series between vdd1 and the ground; the drain of the sixth MOS transistor is respectively connected to the gate of the eighth MOS transistor and the gate of the ninth MOS transistor; The en_in input terminal of the input driver is connected to the gate of the second MOS transistor; the en_in input terminal is also connected to the gate of the fifth MOS transistor through a third inverter; The en_ls input terminal of the input driver is connected to the gate of the seventh MOS transistor; the en_ls input terminal is also connected to the gate of the tenth MOS transistor through a fourth inverter; The drain of the eighth MOS transistor is connected to the signal output terminal of the input driver through a fifth inverter; Wherein, the channel types of the first MOS transistor, the fourth MOS transistor, the fifth MOS transistor, the ninth MOS transistor and the tenth MOS transistor are the same; the channel types of the second MOS transistor, the third MOS transistor, the sixth MOS transistor, the seventh MOS transistor and the eighth MOS transistor are the same; the channel types of the first MOS transistor and the second MOS transistor are different.

7. The multi-chip package structure according to claim 6, characterized in that, In the buffer path: The eleventh MOS transistor, the twelfth MOS transistor, the thirteenth MOS transistor and the fourteenth MOS transistor are connected in series between vdd2 and the ground; the signal input terminal of the input driver is respectively connected to the gate of the twelfth MOS transistor and the gate of the thirteenth MOS transistor; The en_ls input terminal is also connected to the gate of the eleventh MOS transistor; the en_ls input terminal is also connected to the gate of the fourteenth MOS transistor through a fourth inverter; The drain of the twelfth MOS transistor is connected to the signal output terminal of the input driver through a fifth inverter; Wherein, the channel types of the eleventh MOS transistor and the twelfth MOS transistor are the same as the channel type of the second MOS transistor; the channel types of the thirteenth MOS transistor and the fourteenth MOS transistor are the same as the channel type of the first MOS transistor.

8. The multi-chip package structure according to claim 5, characterized in that, The input driver is further provided with an internal pull-down mode or an internal pull-up mode, which is used to output a pull-down low-level signal or a pull-up high-level signal when vdd2 ≤ k·vdd1, so that the first chip operates in the default operating mode when the second chip is not normally powered on.

9. The multi-chip package structure according to any one of claims 3 to 8, characterized in that, The first chip is connected to the second chip through an output driver.

10. The multi-chip package structure according to claim 9, characterized in that, The output driver includes a sixth inverter and a seventh inverter; The signal input terminal of the output driver is connected to the signal output terminal of the output driver through the sixth inverter and the seventh inverter in sequence.

11. A control device for the working mode of a chip in a multi-chip package, characterized in that the device includes: a first acquisition module, configured to acquire the working voltage comparison result of a first working voltage vdd1 and a second working voltage vdd2; wherein, vdd1 is the working voltage of a first chip; vdd2 is the working voltage of a second chip; a first control module, configured to control the working mode of the input driver according to the working voltage comparison result, so that the first chip works in a working mode adapted to the working mode of the input driver; wherein, the second chip is connected to the first chip through the input driver; The first control module includes: a second control module, configured to adjust the input driver to an internal pull-down mode or an internal pull-up mode when vdd1 and vdd2 in the working voltage comparison result satisfy vdd2 ≤ k·vdd1, so that the first chip works in a default working mode when the second chip is not powered on normally; wherein, k is a positive number less than 1; a third control module, configured to control the input driver to convert the vdd2 voltage domain input signal into a vdd1 voltage domain output signal through the levelshifter path when vdd1 and vdd2 in the working voltage comparison result satisfy k·vdd1 < vdd2 ≤ vdd1, so that the first chip works in a normal working mode when the second chip is powered on; a fourth control module, configured to control the input driver to convert the vdd2 voltage domain input signal into a vdd1 voltage domain output signal through the buffer path when vdd1 and vdd2 in the working voltage comparison result satisfy vdd1 < vdd2, so that the first chip works in the normal working mode.

12. The control device for the chip working mode according to claim 11, characterized in that the first acquisition module includes: a second acquisition module, configured to acquire the working voltage comparison result according to the output signal of a working voltage monitor.

13. A microsystem of a multi-chip package, characterized in that it includes: the multi-chip package structure according to any one of claims 3 to 10.

14. A computer system, characterized in that it includes a microsystem of a multi-chip package, and the microsystem of the multi-chip package executes the steps of the method according to any one of claims 1 to 2.

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