Method for improving wafer dicing performance and wafer structure

Abstract

The present invention provides a method and wafer structure for improving wafer cutting performance. The method comprises providing a wafer provided with a plurality of semiconductor chips, wherein the adjacent semiconductor chips have a cutting path, and the cutting path has at least one of a metal structure for alignment, a metal pad for electrical testing, and a metal pad for film thickness measurement. Part or all of the metal of the metal structure or the metal pad is removed along the cutting path to form a gap, thereby reducing the difficulty of the cutting process, improving the cutting quality, and improving the product performance of the semiconductor chip.

Description

Technical Field

[0001] This invention relates to a method for improving wafer dicing performance and a wafer structure. Background Technology

[0002] like Figure 1 As shown, in the integrated circuit manufacturing process, multiple semiconductor chips 2 are integrated onto the same wafer 1. Figure 2 , Figure 3 for Figure 1 A magnified view of a portion of region P shows two adjacent semiconductor chips 21 and 22, and a dicing track AA located between semiconductor chips 21 and 22. During the wafer dicing process, the wafer is diced along the dicing track AA to form individual semiconductor chips 21 and 22.

[0003] according to Figure 2 In a preferred embodiment of the prior art shown, there is a metal structure 23 for alignment on the dicing track AA. The illumination laser is reflected and perpendicularly incident on the metal structure 23 on the wafer, then diffracts and returns. The positive and negative first-order diffracted light is retained by a specially constructed filter. The diffracted light returns to the projection lens and interferes with the mask mark. The photodetector receives the two-dimensional alignment grating intensity information containing the mask mark and the metal structure 23 on the wafer. Finally, the photodetector can receive the moiré signal function (sinusoidal relationship) of the light intensity with the wafer displacement behind the mask grating.

[0004] according to Figure 3 In another preferred embodiment of the prior art shown, there is a metal pad 24 on the cutting track AA for electrical testing or film thickness measurement. The current method for film thickness measurement is mainly elliptic polarization testing. Its basic principle is that a laser beam is converted into linearly polarized light by a polarizer, and then into ellipticly polarized light by a quarter-wave plate. After being reflected by the film surface to be tested, the polarization state (amplitude and phase) of the light will change. For a certain sample, the polarization azimuth angle P can always be found so that the reflected light changes from ellipticly polarized light to linearly polarized light. Then, the analyzer is rotated to obtain the extinction state at the corresponding azimuth angle A. The film thickness can be calculated by converting the two azimuth angles A and P.

[0005] In the prior art, the metal structure 23 used for alignment and the metal pad 24 used for electrical testing or film thickness measurement are both solid pieces of metal. Due to the large thickness of the wafer 1 and the high hardness of the metal structure 23 or the metal pad 24, the subsequent cutting process is more difficult and the cutting quality is hard to guarantee, which in turn affects the product performance of the semiconductor chip. Summary of the Invention

[0006] The purpose of this invention is to provide a method and wafer structure for improving wafer dicing performance, reducing the difficulty of the dicing process, improving dicing quality, and enhancing the performance of semiconductor chips.

[0007] Based on the above considerations, one aspect of the present invention provides a method for improving wafer dicing performance, comprising: providing a wafer having a plurality of semiconductor chips disposed thereon, wherein adjacent semiconductor chips have dicing tracks, and the dicing tracks have at least one of a metal structure for alignment, a metal pad for electrical testing, and a metal pad for film thickness measurement; removing part or all of the metal of the metal structure or the metal pad along the dicing track direction to form a gap, thereby reducing the difficulty of subsequent dicing.

[0008] Preferably, the metal is completely etched along the gap depth direction.

[0009] Preferably, the metal is partially etched along the gap depth direction.

[0010] Preferably, the position, size, and shape of the gap are pre-designed to ensure the effectiveness of wafer alignment, electrical testing, or film thickness measurement.

[0011] Preferably, for metal pads used for film thickness measurement, the measurement performance is guaranteed to have a confidence level greater than or equal to 0.9.

[0012] Preferably, a light spot is provided to illuminate the wafer, and the light spot corresponds to the metal pad for wafer measurement.

[0013] Preferably, when the ratio of the gap width to the metal pad width is greater than or equal to a threshold, the pad gap can be set in the non-middle area of ​​the metal pad.

[0014] Preferably, the gap is achieved through layout design, and the direction of the gap is consistent with the direction of the cutting path.

[0015] Preferably, the wafer is cut along the middle region of the metal structure or metal pad using a laser stealth cutting process.

[0016] Preferably, the wafer is cut along the middle region of the metal structure or metal pads using a mechanical cutting method.

[0017] Preferably, the wafer is cut to its entire or part thickness, and the wafer is expanded to form a single semiconductor chip.

[0018] Another aspect of the present invention provides a wafer structure for improving wafer dicing performance, comprising: a plurality of semiconductor chips disposed on the wafer, the adjacent semiconductor chips having dicing tracks, the dicing tracks having at least one of a metal structure for alignment, a metal pad for electrical testing, and a metal pad for film thickness measurement; the metal structure or the metal pads having gaps along the dicing track direction to reduce the difficulty of subsequent dicing.

[0019] Preferably, the gap depth is equal to the thickness of the metal structure or the metal pad.

[0020] Preferably, the gap depth is less than the thickness of the metal structure or the metal pad.

[0021] Preferably, the position, size, and shape of the gap ensure the effectiveness of wafer alignment, electrical testing, or film thickness measurement.

[0022] Preferably, for metal pads used for film thickness measurement, the measurement performance is guaranteed to have a confidence level greater than or equal to 0.9.

[0023] Preferably, when the ratio of the gap width to the metal pad width is greater than or equal to a threshold, the pad gap can be set in the non-middle area of ​​the metal pad.

[0024] Preferably, the direction of the gap is consistent with the direction of the cutting channel.

[0025] The present invention provides a method and wafer structure for improving wafer dicing performance. By providing a wafer on which a plurality of semiconductor chips are disposed, wherein adjacent semiconductor chips have dicing channels, and the dicing channels have at least one of the following: metal structures for alignment, metal pads for electrical testing, and metal pads for film thickness measurement; removing part or all of the metal of the metal structures or metal pads along the dicing channel direction to form gaps, thereby reducing the difficulty of the dicing process, improving the dicing quality, and improving the product performance of the semiconductor chips. Attached Figure Description

[0026] Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings.

[0027] Figure 1 This is a schematic diagram of a semiconductor chip integrated on the same wafer.

[0028] Figure 2 According to a preferred embodiment of the prior art Figure 1 A magnified view of a portion of region P in the middle;

[0029] Figure 3 According to another preferred embodiment of the prior art Figure 1 A magnified view of a portion of region P in the middle;

[0030] Figure 4 According to a preferred embodiment of the present invention Figure 1 A magnified view of a portion of region P in the middle;

[0031] Figure 5 According to a preferred embodiment of the present invention Figure 4 A partial sectional view of the middle BB line;

[0032] Figure 6 According to another preferred embodiment of the present invention Figure 4 A partial sectional view of the middle BB line;

[0033] Figure 7 According to another preferred embodiment of the present invention Figure 1 A magnified view of a portion of region P in the middle;

[0034] Figure 8 According to another preferred embodiment of the present invention Figure 1 A magnified view of a portion of region P in the middle;

[0035] Figure 9 According to another preferred embodiment of the present invention Figure 1 A magnified view of a portion of region P in the middle;

[0036] Figure 10 According to yet another preferred embodiment of the present invention Figure 1 A magnified view of a portion of region P in the middle.

[0037] Throughout the figures, the same or similar reference numerals denote the same or similar devices (modules) or steps. Detailed Implementation

[0038] To address the problems in the prior art, the present invention provides a method and wafer structure for improving wafer dicing performance. The method involves providing a wafer with a plurality of semiconductor chips, wherein adjacent semiconductor chips have dicing channels. Each dicing channel has at least one of the following: a metal structure for alignment, metal pads for electrical testing, and metal pads for film thickness measurement. Part or all of the metal from the metal structure or metal pads is removed along the dicing channel direction to form gaps, thereby reducing the difficulty of the dicing process, improving dicing quality, and enhancing the product performance of the semiconductor chips.

[0039] In the following detailed description of preferred embodiments, reference will be made to the accompanying drawings, which form part of this invention. The accompanying drawings illustrate specific embodiments by way of example that enable the implementation of the invention. The exemplary embodiments are not intended to be exhaustive of all embodiments according to the invention. It will be understood that other embodiments may be utilized, and structural or logical modifications may be made, without departing from the scope of the invention. Therefore, the following detailed description is not restrictive, and the scope of the invention is defined by the appended claims.

[0040] The present invention will now be described in detail with reference to specific embodiments.

[0041] The present invention provides a method for improving wafer dicing performance, comprising: providing a wafer having a plurality of semiconductor chips, wherein adjacent semiconductor chips have dicing tracks, and the dicing tracks have at least one of a metal structure for alignment, a metal pad for electrical testing, and a metal pad for film thickness measurement; removing part or all of the metal of the metal structure or the metal pad along the dicing track direction to form a gap, thereby reducing the difficulty of subsequent dicing.

[0042] like Figure 4 As shown, adjacent semiconductor chips 121 and 122 have cleaving paths AA, and metal pads 124 for electrical testing or film thickness measurement are provided on the cleaving paths AA as an example. Part or all of the metal of the metal pads 124 is removed along the direction of the cleaving paths AA to form gaps 125, thereby reducing the difficulty of subsequent cutting, improving cutting quality, and improving the product performance of semiconductor chips.

[0043] Figure 5 According to a preferred embodiment of the present invention Figure 4 A partial cross-sectional view of the BB line, in which the metal is completely etched along the depth direction of the gap 125, i.e. the gap depth Ds is equal to the thickness Dp of the metal pad 124. Figure 6 According to another preferred embodiment of the present invention Figure 4 A partial cross-sectional view of the BB line, in which the metal is partially etched along the depth direction of the gap 125, i.e., the gap depth Ds is less than the thickness Dp of the metal pad 124.

[0044] In addition, Figure 4 In the preferred embodiment shown, all metal of the metal pad 124 is removed along the cutting path AA, that is, the gap 125 penetrates the entire metal pad 124; in such a way... Figure 7 In another preferred embodiment shown, a portion of the metal in the metal pad 124 is removed along the dicing AA direction, and the portion of the metal removed from the metal pad 124 is continuous; in such a way... Figure 8 In another preferred embodiment shown, a portion of the metal in the metal pad 124 is removed along the AA direction, and the portion of the metal removed from the metal pad 124 is discontinuous.

[0045] Those skilled in the art will understand that the above-described optional embodiments can effectively reduce the difficulty of subsequent cutting. Therefore, the effectiveness of electrical testing or film thickness measurement can be ensured by pre-designing the position, size, and shape of the gap 125. Specifically, for the metal pads 124 used for film thickness measurement, light spots are provided to illuminate the wafer, and the light spots correspond to the metal pads 124 for wafer measurement. By designing the position, size, and shape of the gap 125, the measurement performance can be guaranteed to have a confidence level greater than or equal to 0.9.

[0046] like Figure 9 As shown, when the ratio of the gap width Ws to the metal pad width Wp is greater than or equal to a threshold, the influence of the gap 125 on the film thickness measurement may become significant. In this case, the pad gap 125 can be set in the non-middle area of ​​the metal pad 124 in order to minimize the influence of the light spot irradiating the gap 125 on the film thickness measurement performance.

[0047] Figure 10 A preferred embodiment is shown with a metal structure 123 for alignment on the dicing ray AA, wherein part or all of the metal of the metal structure 123 is removed along the direction of the dicing ray AA to form a gap 125, thereby reducing the difficulty of subsequent cutting. Those skilled in the art will understand that the effectiveness of wafer alignment can also be ensured by pre-designing the position, size, and shape of the gap 125, in a manner similar to the gap setting in the metal pad 124 described above, and will not be repeated here.

[0048] The method for improving wafer dicing performance using the present invention allows for the following wafer dicing processes: For cases where the gap 125 is located in the middle or non-middle region of the metal structure 123 or metal pad 124, laser stealth dicing can be used to dicing the wafer along the middle region of the metal structure 123 or metal pad 124; alternatively, mechanical dicing can be used. Preferably, by cutting away all or part of the wafer's thickness, the wafer is expanded to form a single semiconductor chip.

[0049] Another aspect of the present invention provides a wafer structure for improving wafer dicing performance, comprising: a plurality of semiconductor chips 121, 122 disposed on the wafer, the adjacent semiconductor chips 121, 122 having dicing paths AA, the dicing paths AA having at least one of a metal structure 123 for alignment, a metal pad 124 for electrical testing, and a metal pad 124 for film thickness measurement; the metal structure 123 or the metal pad 124 having a gap 125 along the direction of the dicing path AA, so as to reduce the difficulty of subsequent dicing, improve dicing quality, and improve the product performance of the semiconductor chips.

[0050] According to a preferred embodiment of the present invention, the gap depth Ds is equal to the thickness Dp of the metal structure 123 or the metal pad 124. According to another preferred embodiment of the present invention, the gap depth Ds is less than the thickness Dp of the metal structure 123 or the metal pad 124.

[0051] Preferably, the direction of the gap 125 is consistent with the direction of the dicing AA, and the position, size, and shape of the gap 125 ensure the effectiveness of wafer alignment, electrical testing, or film thickness measurement.

[0052] Preferably, for the metal pad 124 used for film thickness measurement, the measurement performance is guaranteed to have a confidence level greater than or equal to 0.9. Specifically, when the ratio of the gap width Ws to the metal pad width Wp is greater than or equal to a threshold, the pad gap 125 can be located in the non-middle region of the metal pad 124.

[0053] In summary, the method and wafer structure for improving wafer dicing performance of the present invention provide a wafer on which a plurality of semiconductor chips are disposed, wherein adjacent semiconductor chips have dicing channels, and the dicing channels have at least one of the following: metal structures for alignment, metal pads for electrical testing, and metal pads for film thickness measurement; and remove part or all of the metal of the metal structures or metal pads along the dicing channel direction to form gaps, thereby reducing the difficulty of the dicing process, improving the dicing quality, and improving the product performance of the semiconductor chips.

[0054] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered exemplary and not restrictive in any way. Furthermore, it is clear that the word "comprising" does not exclude other elements and steps, and the word "a" does not exclude a plurality. Multiple elements recited in the apparatus claims may also be implemented by a single element. The terms "first," "second," etc., are used to denote names and do not indicate any particular order.

Claims

1. A method for improving wafer dicing performance, characterized in that, include: A wafer is provided having a plurality of semiconductor chips, adjacent semiconductor chips having cleaving paths, the cleaving paths having at least one of the following: metal structures for alignment, metal pads for electrical testing, and metal pads for film thickness measurement. Remove part of the metal from the metal structure or metal pads along the cutting path to create a gap, thereby reducing the difficulty of subsequent cutting. The gap width and the width of the metal structure or metal pad have a certain ratio; The wafer is cut along the middle region of the metal structure or metal pads using a mechanical cutting method.

2. The method for improving wafer dicing performance as claimed in claim 1, characterized in that, The location, size, and shape of the gaps are pre-designed to ensure the effectiveness of wafer alignment, electrical testing, or film thickness measurement.

3. The method for improving wafer dicing performance as described in claim 2, characterized in that, For metal pads used for film thickness measurement, the measurement performance is guaranteed to have a confidence level greater than or equal to 0.

9.

4. The method for improving wafer dicing performance as described in claim 3, characterized in that, A light spot is provided to illuminate the wafer, and the light spot corresponds to the metal pad for wafer measurement.

5. The method for improving wafer dicing performance as described in claim 3, characterized in that, When the ratio of the gap width to the metal pad width is greater than or equal to a threshold, the pad gap can be set in the non-middle area of ​​the metal pad.

6. The method for improving wafer dicing performance as claimed in claim 1, characterized in that, The gap is achieved through layout design, and the direction of the gap is consistent with the direction of the cutting path.

7. The method for improving wafer dicing performance as claimed in claim 1, characterized in that, The wafer is cut to its full or partial thickness, and then expanded to form a single semiconductor chip.

8. A wafer structure for improving wafer dicing performance using the method described in any one of claims 1 to 7, characterized in that, include: The wafer is provided with a plurality of semiconductor chips, and adjacent semiconductor chips have dicing channels. The dicing channels have at least one of the following: metal structures for alignment, metal pads for electrical testing, and metal pads for film thickness measurement. The metal structure or metal pads are provided with gaps along the cutting path to reduce the difficulty of subsequent cutting.

9. The wafer structure for improving wafer dicing performance as claimed in claim 8, characterized in that, The gap depth is less than the thickness of the metal structure or metal pad.

10. The wafer structure for improving wafer dicing performance as claimed in claim 8, characterized in that, The position, size, and shape of the gap ensure the effectiveness of wafer alignment, electrical testing, or film thickness measurement.

11. The wafer structure for improving wafer dicing performance as claimed in claim 10, characterized in that, For metal pads used for film thickness measurement, the measurement performance is guaranteed to have a confidence level greater than or equal to 0.

9.

12. The wafer structure for improving wafer dicing performance as claimed in claim 11, characterized in that, When the ratio of the gap width to the metal pad width is greater than or equal to a threshold, the pad gap can be set in the non-middle area of ​​the metal pad.

13. The wafer structure for improving wafer dicing performance as claimed in claim 8, characterized in that, The direction of the gap is consistent with the direction of the cutting channel.

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