Method for passivating full front deep trench isolation structure

Abstract

This application relates to a method for passivating a full front deep trench isolation structure. The method includes providing a trench extending from a first face to a second face of a semiconductor substrate. The trench has an opening on the first face and a bottom and sides. A conformal layer of doped B-oxide is deposited on the bottom and sides of the trench and the thickness of the conformal layer of doped B-oxide is less than half the trench width leaving a deep recess in the trench. A second material is deposited on the conformal layer of doped B-oxide in the trench filling the recess in the trench to the first face. The conformal layer of doped B-oxide is annealed driving boron from the conformal layer of doped B-oxide into the semiconductor substrate forming a doped B region as a passivation layer juxtaposed with the conformal layer of doped B-oxide having a negative fixed charge.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to image sensors, and in particular, but not exclusively, to isolation structures in image sensors. BACKGROUND

[0002] CMOS image sensors (CIS) have become ubiquitous. They are widely used in digital still cameras, cellular telephones, surveillance cameras, and in medical, automotive, and other applications. A typical image sensor operates optically in response to image light reflected from an external scene being incident on the image sensor. The image sensor includes an array of pixels having a light-sensitive element (e.g., a photodiode) that absorbs a portion of the incident image light and generates image charge upon absorbing the image light. The image charge of each of the pixels can be measured as an output voltage of each light-sensitive element that varies with the incident image light. In other words, the amount of image charge generated is proportional to the intensity of the image light, which is used to generate a digital image (i.e., image data) representative of the external scene.

[0003] Techniques for fabricating image sensors continue to advance rapidly. The requirements of high resolution and low power consumption drive these devices to be further miniaturized and integrated. As the demand for image sensors continues to increase, the packing density with isolation and low noise performance of the pixel cells in image sensors are increasingly challenging. SUMMARY

[0004] In one aspect, the present application relates to a method for forming a deep trench isolation structure of a CMOS image sensor, the method comprising: providing a semiconductor substrate having a trench, wherein the trench extends from a first face of the semiconductor substrate toward a second face of the semiconductor substrate, wherein the trench has an opening on the first face and a bottom and a side of the trench are formed by the semiconductor substrate; depositing a conformal layer of boron (B) doped oxide at least on the bottom and the side of the trench, wherein a thickness of the conformal layer of B doped oxide is less than half of the trench width to leave a deep recess in the trench; depositing a second material at least on the conformal layer of B doped oxide in the trench, wherein the second material fills the recess in the trench to at least the first face; and annealing the conformal layer of B doped oxide to push boron from the conformal layer of B doped oxide to the semiconductor substrate, which forms a B doped region as a passivation layer in parallel with the conformal layer of B doped oxide, and the conformal layer of B doped oxide has a negative fixed charge.

[0005] In another aspect, the present application is directed to a semiconductor structure for a CMOS image sensor, comprising: a semiconductor substrate having a first face and a second face; and a deep trench isolation structure extending from the first face toward the second face of the semiconductor substrate, wherein the deep trench isolation structure includes: a trench having a bottom and sides formed by the semiconductor substrate; a boron (B) doped oxide layer on the bottom and sides of the trench; and a second material filling the trench at least to the first face of the semiconductor substrate, wherein there is boron as a passivation layer in a region of the semiconductor substrate on the bottom and sides of the trench, wherein the B doped oxide layer has a negative fixed charge forming a hole accumulation layer around the trench, and wherein the second material is in juxtaposition with the B doped oxide layer and extends in a central depth of the trench. BRIEF DESCRIPTION OF DRAWINGS

[0006] Non-limiting and non-exhaustive embodiments of the present application are described with reference to the following figures, wherein like numerals refer to like parts throughout the several views.

[0007] Figures 1 to 7 is a cross-sectional illustration of a semiconductor structure showing an example of a process for passivating a full front deep trench isolation (DTI) structure of a CMOS image sensor in accordance with the teachings of the present application.

[0008] Figure 8 is a plan view of one example of a pixel cell having a passivated full front deep trench isolation structure in a pixel array arranged in a layer of semiconductor material in accordance with the teachings of the present application.

[0009] Figure 9A is a plan view of one example of a pixel cell having a passivated full front deep trench isolation structure in a pixel array arranged in a layer of semiconductor material in accordance with the teachings of the present application.

[0010] Figures 9B to 9C is a cross-sectional illustration of a semiconductor structure showing an example pixel structure of a CMOS image sensor in accordance with the teachings of the present application.

[0011] Figure 10 is a block diagram illustrating an example of an imaging system using a pixel array having a passivated full front deep trench isolation structure in accordance with the teachings of the present application.

[0012] Corresponding reference characters indicate corresponding components throughout the drawings. Understanding that the drawings are diagrammatic and are not necessarily drawn to scale, the skilled artisan will further appreciate that elements in the figures are illustrated for the purpose of providing illustration and description and can not appear as they would in a commercial embodiment of the application. For example, dimensions of some of the elements can be exaggerated relative to others for clarity. Similarly, well-known elements of the devices are generally not depicted in order to facilitate explanation of the various embodiments. DETAILED DESCRIPTION

[0013] Apparatuses and methods related to passivated full front deep trench isolation structures for CMOS image sensors are disclosed, for example. In the following description, numerous specific details are set forth to provide a thorough understanding of the embodiments. One skilled in the relevant art will recognize, however, that the technology described herein can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail in order to avoid obscuring aspects of certain aspects.

[0014] Reference throughout this specification to "one example" or "an example" means that a particular feature, structure, or characteristic described in connection with the example is included in at least one example of the present application. Thus, the appearances of the phrase "in one example" or "in one embodiment" in various places throughout this specification are not necessarily all referring to the same example and embodiment. Furthermore, the particular features, structures, or characteristics can be combined in any suitable manner in one or more examples and embodiments.

[0015] Spatially relative terms (for example, "beneath", "below", "lower", "under", "above", "upper", and the like) can be used herein for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if a device is inverted in the figure, a dependent element or feature described as "below" or "beneath" another element or feature would then be oriented "above" the other element or feature. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Additionally, it will be understood that, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers can also be present.

[0016] In the present disclosure, the term "semiconductor substrate" or "substrate" refers to any type of substrate used in the formation of semiconductor devices thereon, including single crystalline substrates, semiconductor-on-insulator (SOI) substrates, doped bulk silicon substrates, and semiconductor-on-epitaxial film (EPI) substrates, among others. Moreover, while various embodiments will be described primarily with respect to materials and processes compatible with silicon-based semiconductor materials (e.g., silicon and alloys of silicon and germanium and / or carbon), the present technology is not limited in this regard. Rather, any type of semiconductor material can be used to implement various embodiments.

[0017] Throughout this specification, several technical terms are used. These terms have their ordinary meanings in the field of the technology from which this disclosure arises unless specifically defined otherwise or the context of their use clearly dictates otherwise. It should be noted that chemical element names and their symbols (e.g., Si for silicon) can be used interchangeably throughout this document; however, both have the same meaning.

[0018] CMOS image sensors employ deep trench isolation technology to improve the modulation transfer function (MTF). The MTF refers to the degree to which an image sensor can convert the details of an object into an image, also referred to as the sharpness of the image. In one example, the MTF is improved by reducing cross-talk using a deep trench isolation structure.

[0019] There are various methods of fabricating deep trench isolation structures. One method is to fabricate a deep trench isolation structure from the backside of a semiconductor substrate. Another method is to fabricate a partial deep trench isolation structure that does not extend completely from the backside to the frontside of a semiconductor substrate. Both the backside fabrication and the partial deep trench isolation structure have advantages that recommend their use for CMOS image sensors.

[0020] As will be discussed, examples in accordance with the teachings of the present disclosure relate to image sensors having frontside fabricated, full deep trench isolation structures with a passivation layer. In various examples, full frontside deep trench isolation structures for CMOS image sensors are formed from the frontside of a semiconductor substrate (e.g., a P-type silicon substrate), and in the finished pixel, the deep trench isolation structure will extend vertically from the frontside surface to the semiconductor substrate to reach the backside of the semiconductor substrate, thereby providing a "full" deep trench isolation structure.

[0021] In various examples, frontside fabricated, full deep trench isolation structures with a passivation layer are advantageous due to the etching process used for the trench without the need to concern about ending the etching step precisely. Moreover, during the fabrication of full frontside fabricated deep trench isolation structures, high temperatures can be employed due to the formation of the frontside fabricated deep trench isolation structure prior to photodiode formation.

[0022] However, despite these advantages, the trenches manufactured on the front side should be passivated on the sidewall surface after etching to avoid white pixels and dark current effects. The use of typical high dielectric constant films with negative fixed charge (e.g., AlOx and others) for passivation is not suitable for trenches manufactured on the front side because the negative charge of such high dielectric constant films will not be retained under the high heat treatment of downstream processing. Due to the high aspect ratio of deep trenches, the use of gas phase passivation is also not suitable or sufficient for deep trench passivation, resulting in insufficient passivation at or near the bottom of the trench. In addition, plasma implantation is non-uniform and causes damage due to the higher plasma density near the trench opening, which causes more doping near the trench and a gradual decrease in doping through the trench.

[0023] Therefore, in one embodiment, a doping method for passivating the sidewalls and bottom of a deep trench isolation structure is provided, wherein the method realizes a passivated full-deep trench isolation structure for front-side fabrication of a CMOS image sensor.

[0024] To illustrate the example process, Figure 1 A cross-section of a semiconductor substrate 100 is shown having a front side 102 and a back side 104. In the present disclosure, the "front side" may also be referred to as the first side, and the "back side" may also be referred to as the second side opposite the first side. In some embodiments, the back side 104 (the second side) may also refer to the illuminated side, and the front side 102 (the first side) may also refer to the non-illuminated side. The illustrated semiconductor substrate 100 has been etched by any suitable etching process to form a trench 106 having an opening on the first side 102 that extends toward, but does not penetrate, the second side 104.

[0025] In one example, trench 106 is fabricated in a series of steps that include creating a photomask, etching, and then removing the photomask. In the illustrated embodiment, trench 106 is a trench used to form a deep trench isolation structure. In one example, the critical dimension (trench width) of trench 106 can be approximately 100 nm to approximately 150 nm. Trench 106 is an opening whose bottom and sides are formed in semiconductor substrate 100.

[0026] exist Figure 1 , trench 106 is illustrated as not extending completely from first side 102 to second side 104. Etching can be performed such that the depth of trench 106 is greater than or equal to the final thickness (or depth) of semiconductor substrate 100. In one example, the trench depth is approximately 3 μm. As further described herein, material is removed from second side 104 of semiconductor substrate 100 to thin semiconductor substrate 100, resulting in a final thickness or depth of semiconductor substrate 100 that is less than the depth of trench 106 after fabrication of the full front side deep trench isolation structure.

[0027] In one example, the full front deep trench isolation structure is fabricated from a series of trenches, such as trenches 106. In particular, in one example, the full front deep trench isolation structure is fabricated by forming a plurality of trenches (e.g., trenches 106) aligned in a first direction intersecting a plurality of trenches (e.g., trenches 106) aligned in a second direction, where the first direction is perpendicular to the second direction. In this way, the full front deep trench isolation structure forms, for example, a square grid in which photodiodes can be fabricated within the squares to electrically isolate the photodiodes from adjacent photodiodes. (See also Figure 8 and 9A ). However, it should be appreciated that in other embodiments, the full front deep trench isolation structure can form a grid of other geometric shapes, such as triangles, pentagons, that define photodiode regions.

[0028] In one example, after etching and cleaning the trenches 106, a conformal layer of boron (B) doped oxide 108 is deposited at least on the bottom and sides of the trenches 106, where the thickness of the conformal layer of B doped oxide 108 is less than half the width of the trenches 106 to leave a deep recess in the trenches 106. In one example, the conformal layer of B doped oxide 108 is deposited on the first face 102 of the semiconductor substrate 100 while also being deposited on the bottom and sides of the trenches 106. In one example, the thickness of the conformal layer of B doped oxide is approximately 3 nm to 30 nm. In one example, the conformal layer of B doped oxide 108 is formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD). In one example, the conformal layer of B doped oxide 108 is conformal around the trenches 106 on the top, sides, and bottom, which is achieved by using chemical vapor deposition or atomic layer deposition. In one example, the conformal layer of B doped oxide 108 is deposited at a deposition temperature of about 300 °C to about 500 °C and a deposition pressure of about 1 to 760 Torr. Figure 2 The results of depositing the conformal layer of B doped oxide 108 are shown in the depicted example.

[0029] In one example, the conformal layer of B doped oxide 108 is formed by chemical vapor deposition at a deposition temperature of about 300 °C to about 500 °C and a deposition pressure of about 1 to 760 Torr.

[0030] In one example, the boron doping in the conformal layer of B doped oxide 108 is in-situ doping, where a boron dopant is introduced to the oxide film during the oxide deposition process. In one example, the boron atomic concentration of the conformal layer of B doped oxide 108 is about 5% to 20% when deposited, but after the application of a thermal anneal, the boron atomic concentration will decrease, as the thermal anneal pushes the boron from the conformal layer of B doped oxide 108 into the nearby region within the semiconductor substrate 100.

[0031] In one example, the conformal layer of B-doped oxide 108 will remain in the trench 106 throughout the process. The conformal layer of B-doped oxide 108 has at least a negative fixed charge that will help to passivate the surface of the trench 106. The negative fixed charge is theorized to be a property of the B-doped oxide related to the boron-oxygen network and remains after thermal annealing. The amount of negative fixed charge contained in the conformal layer of B-doped oxide 108 can be related to the thickness of the conformal layer of B-doped oxide 108. For example, the thicker the conformal layer of B-doped oxide 108, the higher the amount of negative fixed charge contained in the conformal layer of B-doped oxide 108.

[0032] In one example, the conformal layer of B-doped oxide 108 is borosilicate glass (BSG). Borosilicate glass includes any borosilicate glass that contains at least silica (silicon dioxide, Si02) and boron oxide (B203). In one example, the amount of boron oxide can be varied to give the borosilicate glass different properties. In one example, the borosilicate glass can contain alkaline earth and aluminum oxide (AI2O3). In one example, borosilicate glass containing up to 13% by weight of boron oxide and more than 80% by weight of silica can have high chemical resistance and low thermal expansion. Higher boron oxide content generally results in a softer glass.

[0033] In one example, the deposition of borosilicate glass is performed by atmospheric pressure chemical vapor deposition (AP-CVD) using SiH4, O2, B2H6gases at a deposition temperature of about 430°C. The borosilicate glass layer thickness and boron concentration can be controlled by the gas flow ratio of B2H6to SiH4, respectively.

[0034] In one example, the conformal layer of B-doped oxide 108 is a B-doped dielectric, such as boron-doped zinc oxide ZnO:B, etc.

[0035] After depositing the conformal layer of B-doped oxide (first material), a second material 110 is deposited on at least the conformal layer of B-doped oxide 108 in the trench 106, where the second material 110 completely fills the recess remaining in the trench 106 after the deposition of the conformal layer of B-doped oxide 108. In one example, the second material 110 is also deposited over the conformal layer of B-doped oxide 108 on the first face 102 of the semiconductor substrate 100, as illustrated in the depicted example. In either case, the second material 110 completely fills the trench 106 at least to the level of the first face 102. For example, the second material 110 can fill the trench 106 to the surface of the first face 102 such that the surface of the first face 102 is planarized for subsequent lithography processes of ion implantation and gate formation processes. Figure 3

[0036] ​In one example, the second material 110 is a dielectric. Dielectrics include, but are not limited to, silicon oxide (SiO2), hafnium oxide (HfO2), silicon nitride (Si3N4), silicon oxide (SiO x N y ), tantalum oxide (Ta2O5), titanium oxide (TiO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), praseodymium oxide (Pr2O3), cerium oxide (CeO2), neodymium oxide (Nd2O3), promethium oxide (Pm2O3), samarium oxide (Sm2O3), europium oxide (Eu2O3), gadolinium oxide (Gd2O3), terbium oxide (Tb2O3), dysprosium oxide (Dy2O3), holmium oxide (Ho2O3), erbium oxide (Er2O3), thulium oxide (Tm2O3), ytterbium oxide (Yb2O3), lutetium oxide (Lu2O3), yttrium oxide (Y2O3), or other suitable dielectric material. In one example, the second material 110 can be the borosilicate glass or boron-doped zinc oxide ZnO:B described above.

[0037] In one example, the second material 110 is doped polysilicon. In one example, the doped polysilicon is deposited by chemical vapor deposition (CVD) at a deposition temperature of about 500°C. In one example, the doped polysilicon can be n-type doped (e.g., phosphorous) polysilicon or p-type doped (e.g., boron) polysilicon. In one example, the doping process is an in-situ doping process, in which a dopant is introduced into the polysilicon during the deposition process.

[0038] After deposition of the second material 110, chemical mechanical polishing is performed, if necessary, to remove excess doped polysilicon 110 and the conformal layer of doped boron oxide 108 on top of the trench 106. The chemical mechanical polishing stops on the first face 102 of the semiconductor substrate 100, as illustrated in the example depicted in Figure 4

[0039] In one example, doped polysilicon is preferred for the second material 110 because doped polysilicon is a conductor through which a bias can be applied. In one embodiment, the doped polysilicon can be negatively biased to form an additional hole accumulation layer around the trench 106, passivating the trench sidewalls and bottom surface to reduce dark current. However, biasing in the second material 110 is not mandatory.

[0040] In one example, after deposition of the second material 110, a thermal anneal is applied to push boron from the conformal layer of doped B oxide 108 into the silicon semiconductor substrate 100, for example, by a diffusion process, to form a doped boron silicon region 112 as a passivation layer around the trench 106 on the sidewalls and bottom, as illustrated in the example depicted in Figure 5 , preventing defect / trap sites on the sidewalls and bottom from capturing electrons and generating dark current.​Figure 5 The structure is considered a complete front-side fabricated, deep trench isolation structure 114 with a passivation layer. After the material is removed from the second side 104 of the semiconductor substrate 100, the front-side deep trench isolation structure 114 will be considered "complete," meaning that the structure 114 extends from the first side 102 to the second side 104 of the semiconductor substrate 100.

[0041] In one example, the anneal temperature for annealing the conformal layer of doped B oxide 108 in the anneal step is about 800 °C to about 1000 °C, and the time at the anneal temperature can be about 1 min to about 60 min. The time will be inversely proportional to the anneal temperature, such that a lower anneal temperature requires a longer anneal time. In one example, the thermal anneal step is performed in an inert atmosphere (e.g., N2, Ar, etc.). In one example, the pressure during the anneal step is about 0.1 Torr to about 760 Torr. The anneal process can be performed in a furnace or a rapid thermal anneal (RTA) chamber. According to one embodiment, a high temperature can be employed because the anneal process occurs before the photodiode is formed in the semiconductor substrate 100.

[0042] In one example, when the second material 110 is doped polysilicon, the anneal step that pushes boron from the conformal layer of doped B oxide 108 into the silicon semiconductor substrate 100 also electrically activates the second material 110 to enable the bias function. In one example, the thermal anneal step can accomplish two things, the first being to push the boron dopant into the silicon semiconductor substrate 100 to form the doped boron silicon region 112 as a passivation layer on the sides and bottom of the front-side deep trench isolation structure 114, and the second being to electrically activate the doped polysilicon fill (second material 110).

[0043] However, the process flow sequence is not limited to performing the anneal step after both the conformal layer of doped B oxide 108 and the second material 110 are deposited. In one example, instead of depositing the second material 110 after depositing the conformal layer of doped B oxide 108, a first anneal process is performed. The first anneal process pushes boron from the conformal layer of doped B oxide 108 into the silicon semiconductor substrate 100 to form the doped boron silicon region 112 as a passivation layer on the sides and bottom of the trench 106 around the front-side deep trench isolation structure 114 (as still illustrated in Figure 5

[0044] Furthermore, a first chemical mechanical polishing step can also be performed prior to or after the first anneal process to reduce the excess conformal layer of doped B oxide 108 on the top of the trench 106 prior to depositing the second material 110. The first chemical mechanical polishing stops on the first side 102 of the semiconductor substrate 100, as Figure 4 ​1 , but there is no second material 110 inside the trench 106. However, the chemical mechanical polishing of the conformal layer of B-doped oxide 108 can also be delayed until after the deposition of the second material 110.

[0045] After the first annealing process, the process flow sequence can continue as described above by depositing the second material 110. After depositing the second material 110, a first or second chemical mechanical polishing can be performed to remove excess second material 110 with or without the conformal layer of the B-doped oxide 108, depending on whether the excess conformal layer of the B-doped oxide 108 on the front surface of the semiconductor substrate 100 has been removed.

[0046] After depositing the second material 110 , and if the second material 110 is doped polysilicon, a second annealing process may be performed to electrically activate the doped polysilicon to enable biasing functionality.

[0047] While other variations with fewer or additional steps or process flow sequences in a different order result in similar passivated deep trench isolation structures 114 or structures 114 with similar functionality, such variations are also within the scope of the present invention.

[0048] In completion Figure 5 After the passivated front deep trench isolation structure 114 is formed, in which the boron-doped silicon region 112 of the semiconductor substrate 100 on the bottom and side of the trench 106 acts as a passivation layer, the conformal layer of the doped B oxide 108 having a negative fixed charge can form an additional hole accumulation layer to provide additional passivation to the interface between the front deep trench isolation structure 114 and the semiconductor substrate 100. The hole accumulation layer can surround the trench of the front deep trench isolation structure 114 and passivate the defect / trap sites on the interface between the front deep trench isolation structure 114 and the semiconductor substrate 100 originating from the etching process to further reduce dark current. In one embodiment, the hole accumulation layer formed by the conformal layer of the doped B oxide 108 can overlap with the boron region diffused from the conformal layer of the doped B oxide 108. Thereafter, the process flow can use conventional processes to construct the remaining structure to complete the pixel structure.

[0049] exist Figure 6In the depicted example, the photodiode region 120, the pinned layer, the floating diffusion region 122, the implant isolation well 136 (e.g., P-type isolation implant region), and the source / drain pixel transistors are formed by masking and ion implantation processes on the first side 102 of the semiconductor substrate 100. According to embodiments, the photodiode region 120 is formed proximate to the first side 102 of the semiconductor substrate 100 and proximate to the frontside deep trench isolation structure 114 after annealing the conformal layer of doped B oxide 108 due to the high temperature used in the anneal. The floating diffusion region 122 can be formed in the implant isolation well 136 with a concentration and junction depth configured such that the photodiode region 120 is not directly connected to the floating diffusion region 122. The gate electrodes of the pixel transistors, such as the transfer gate, the source follower transistor, the reset transistor, and the row select can be subsequently formed. An interlayer dielectric layer 124 is formed on the surface of the first side 102 of the semiconductor substrate 100 to encapsulate the gate electrodes, the pixel transistor source and drain contacts (e.g., the drain of the source follower transistor, the drain of the reset transistor), and the metal interconnect structures for the pixel circuitry. In one embodiment, the contact for biasing the frontside deep trench isolation structure 114 having the second material 110 as doped polysilicon can also be embedded in the interlayer dielectric layer 124. The interlayer dielectric layer 124 further includes the transfer gate 118 and the gate electrodes for the pixel transistors. Additionally, the metal interconnect structures can be formed in a single or multiple metal layers and include the metal conductor 116A and the via 116B. In embodiments, the floating diffusion region is connected to the gate of the source follower transistor (e.g., source follower gate 944G) and the drain of the reset transistor through the metal interconnect structures. The metal interconnect structures are also formed in the interlayer dielectric layer 124. The foregoing structures are fabricated in a typical sequence.

[0050] In Figure 7 In the depicted example, an example of a completed backside illuminated pixel 202 is illustrated. According to the structure of Figure 6 The semiconductor substrate 100 has been flipped such that the first side 102 is on top and the interlayer dielectric layer 124 is bonded to an application specific integrated circuit (ASIC) wafer 126, e.g., through a hybrid or oxide bonding process.

[0051] Figure 7 The second side 104, as illustrated in the foregoing, has been thinned to the level of the doped polysilicon, the second material 110. Thinning the semiconductor substrate 100 includes bulk grinding to quickly remove the bulk of the silicon material. The bulk grinding is timed. After the bulk grinding, a wet chemical etch is applied to remove the silicon material in a slower and better controlled manner. The wet chemical etch is also timed. Then, a chemical mechanical polish is applied to remove silicon defects, planarize the silicon surface, and define the final thickness. The chemical mechanical polish can also be timed.

[0052] A second side 104 or backside process is performed to form a buffer oxide layer 128 on the thinned second side 104 of the semiconductor substrate 100. A metal gate 130 is formed on the buffer oxide layer 128, and the metal gate 130 includes a plurality of metal structures. An array of color filters 132 is formed on the buffer oxide layer 128, and each color filter 132 is formed between openings in the metal gate 130 and isolated by a corresponding metal structure. An array of microlenses 134 is formed on the array of color filters 132. Each microlens 134 is formed on a respective color filter 132 to direct incoming light through the respective color filter 132 to the respective photodiode region 120. The microlenses 134 can be aligned with centerlines of adjacent metal structures of the metal gate 130. These structures are fabricated in a typical sequence.

[0053] In exemplary operations, in response to incident light received through the second side 104 during an integration operation of the image sensor, the photodiode region 120 generates and accumulates charge in the photodiode region 120 in response to the incident light directed to the photodiode region 120 through the respective microlens 134 and filtered by the respective color filter 132. During a charge transfer operation of the image sensor, when the transfer gate 118 of the transfer transistor receives a supply voltage (e.g., a positive bias voltage) that turns on the associated transfer transistor, the photo-generated charge is transferred to the floating diffusion region 122 through a conduction channel formed by the respective transfer transistor. The floating diffusion region 122 modulates a gate voltage of the source follower transistor based on an amount of photo-generated charge received from the corresponding photodiode region 120 to cause the source follower transistor to output an image signal based on the gate voltage.

[0054] Figure 8 The example illustrated in FIG. 2B depicts a plan view illustration of an example of a pixel 202 including a photodiode region 120, a floating diffusion region 122, and a transfer gate 118 of a transfer transistor placed proximate to a passivated full frontside deep trench isolation structure 114 fabricated according to the present disclosure to prevent electrical crosstalk. Figure 7 may exhibit a pitch along the x-axis that is different than a pitch along the y-axis. Figure 8cross-section along the tangent line A-A' of the semiconductor structure. In the illustrated example, the passivated full front deep trench isolation structure 114 includes a grid structure formed from a plurality of deep trench structures formed by first etching a plurality of trenches in a first direction intersecting a plurality of trenches in a second direction on the first face 102 of the semiconductor substrate 100, thereby defining a plurality of photodiode regions of a plurality of pixels 202. Thus, in the completed process, each photodiode region 120 of a pixel 202 is enclosed within a four-sided passivated full front deep trench isolation structure 114, such that the photodiode region 120 of the associated pixel 202 is electrically isolated from adjacent photodiode regions 120 in all directions. In other words, each pixel 202 is surrounded or enclosed by the grid structure formed from the passivated full front deep trench isolation structure 114 and is isolated from the photodiode regions 120 of adjacent pixels 202, such that each individual pixel 202 is electrically isolated from any of the adjacent pixels 202. Reiterate that the pixel region (e.g., area of the photodiode region 120) of each individual pixel 202 can be defined by a plurality of intersecting full front deep trench structures of the passivated full front deep trench isolation structure 114.

[0055] In one embodiment, the pixel 202 can have at least a pixel transistor, e.g., a reset transistor, a source follower transistor (or amplification transistor), a row select transistor can be formed over the corresponding photodiode region 120 to take full advantage of the area within each pixel 202 to further minimize the pixel without affecting the light sensing of the photodiode region 120. By further minimizing the pixel area, a higher spatial resolution of the image sensor can be achieved. The one or more pixel transistors associated with the pixel 202 can be placed proximate to the trenches of the passivated full front deep trench isolation structure 114 with sufficient spacing between the individual trenches of the passivated full front deep trench isolation structure 114 and the pixel transistors. Those skilled in the art will appreciate that the sufficient spacing can be determined based on the minimum separation required for device fabrication.

[0056] Figure 9A is a plan view of one example of a pixel cell 902 having a passivated full front deep trench isolation structure 114 arranged in a pixel array in a layer of semiconductor material in accordance with the teachings of this disclosure. Figure 9B is a cross-sectional illustration of a semiconductor structure along the tangent line B-B' of Figure 9A in accordance with the teachings of this disclosure showing an example pixel 902 structure of a CMOS image sensor. Figure 9C is a cross-sectional illustration of a semiconductor structure along the tangent line C-C' of Figure 9A in accordance with the teachings of this disclosure showing an example pixel 902 structure of a CMOS image sensor.

[0057] For example, as Figure 9A, the pixel transistor region 940 of the pixel 902 may be defined above the photodiode region 120 within the pixel 202, wherein at least one of the pixel transistors 942, 944, 946 is formed above the photodiode region 120 with respect to the front side 102. The area or region of the pixel 202 is defined by a grid structure formed by a plurality of passivated full front side deep trenches of the passivated full front side deep trench isolation structure 114. Specifically, as Figures 9B to 9C 1. As shown, the pixel transistor region 940 of the pixel 202 can be electrically isolated from the corresponding photodiode region 120 by an implanted isolation well 930. The implanted isolation well 930 can be formed, for example, by ion implantation on the surface of the first side 102. In one example, the implanted isolation well 930 can be formed simultaneously with the formation of the implanted isolation well 136, for example, at Figure 6 In other words, the pixel transistors 942 , 944 , 946 formed above the photodiode region 120 are electrically isolated from the photodiode region 120 by the implanted isolation well 930 .

[0058] In one example, Figure 9C As shown, reset gate 942G of reset transistor 942 is formed on the surface of front side 102, wherein the source and drain (S / D) (e.g., 942D) are formed in implanted isolation well 930 above photodiode region 120 with respect to front side 102, wherein the source and drain for reset transistor 942 can be formed in a direction into and out of the page above photodiode region 120. Source follower gate 944G of source follower transistor 944 is formed on the surface of front side 102, wherein the source and drain are formed in implanted isolation well 930 above photodiode region 120 with respect to front side 102, wherein the source and drain for source follower transistor 944 can be formed in a direction into and out of the page above photodiode region 120. Source follower gate 944G of source follower transistor 944 is connected to a contact (not shown) of floating diffusion region 122. A row select gate 946G of the row select transistor 946 is formed on the surface of the front side 102, wherein the source and drain are formed in an implanted isolation well 930 above the photodiode region 120 with respect to the front side 102, wherein the source and drain for the row select transistor 946 can be formed above the photodiode region 120 in a direction into and out of the page.

[0059] In the illustrated embodiment, the pixel 202 is a four-transistor configuration having a pixel transistor region 940 that includes a reset transistor 942, a source follower transistor 944, and a row select transistor 946. However, it should be appreciated that the pixel 202 can be configured as a three-transistor, five-transistor, or six-transistor configuration, e.g., further including a double-floated diffusion (DFD) transistor, an overflow transistor, and / or a storage transistor, depending on the pixel circuitry configuration, and the pixel transistor region 940 can include three, four, five, or six transistors, forming corresponding spacing between the pixel transistors, without departing from the teachings of the present disclosure.

[0060] It should be appreciated that, for simplicity, and in order not to obscure the understanding of the embodiments, some features regarding the gate structures, e.g., spacers, gate oxide readings, are omitted in Figure 6 , 7 , 9B, and 9C. For example, under the gate electrodes, e.g., between the transfer gate 118, the reset gate 942G, the source follower gate 944G, the row select gate 946G, and the frontside 102 surface, there is a gate oxide layer. For example, there are single or multiple layers of oxide and / or nitride based spacers on the gate electrode sides, providing implant alignment during a self-aligned ion implant process for forming the associated source / drain, e.g., the edges of the spacers for the transfer gate 118 can be aligned with the edges of the floating diffusion region 122 in Figure 6 .

[0061] Figure 10 is a block diagram illustrating one example of an imaging system 300. The imaging system 300 includes a pixel array 200 (as described in Figure 8 or as described in Figure 9A ), control circuitry 304, readout circuitry 306, and functional logic 308. In one example, the pixel array 200 is a two-dimensional (2D) array of photodiode or image sensor pixels 202 (e.g., PI, P2,..., Pn). Each of the image sensor photodiodes / pixels 202 is electrically and / or optically isolated from adjacent image sensor photodiodes / pixels 202 by a plurality of passivated full frontside deep trench isolation structures 114. As illustrated, the photodiodes are arranged in rows (e.g., rows R1 to Ry) and columns (e.g., columns C1 to Cx) to acquire image data of a person, place, object, etc., which can then be used to render a 2D image of the person, place, object, etc. However, in other examples, it should be appreciated that the photodiodes need not be arranged in rows and columns, and other configurations can be employed.

[0062] In one example, after the image sensor photodiodes / pixels 202 in the pixel array 200 have acquired their image data or image charge, the image data is read out by the readout circuitry 306 through the bit lines 310 and then transferred to the functional logic 308. In various examples, the readout circuitry 306 can include amplification circuitry, analog-to-digital (ADC) conversion circuitry, or others. The functional logic 308 can merely store the image data or even manipulate the image data by applying image post effects (e.g., cropping, rotation, red-eye removal, adjusting brightness, adjusting contrast, or others). In an embodiment, the functional logic 308 can be implemented by an image sensor processor (ISP) formed in an application-specific integrated circuit (ASIC) die 126. In one example, the readout circuitry 306 can read out one row of image data at a time along the readout column lines (illustrated) or can read out the image data using various other techniques (not illustrated) (e.g., serially reading out all the pixels or reading out all the pixels in parallel all at once).

[0063] In one example, the control circuitry 304 is coupled to the pixel array 200 to control the operation of the plurality of photodiodes in the pixel array 200. For example, the control circuitry 304 can generate a shutter signal for controlling image acquisition. In one example, the shutter signal is a global shutter signal for simultaneously enabling all the pixels within the pixel array 200 to capture their respective image data at the same time during a single acquisition window. In another example, the shutter signal is a rolling shutter signal such that each row, each column, or each group of pixels are sequentially enabled during successive acquisition windows. In another example, the image acquisition is synchronized with an illumination effect (e.g., a flash).

[0064] In one example, the imaging system 300 can be included in a digital camera, a cellular phone, a laptop computer, a car, etc. Additionally, the imaging system 300 can be coupled to other hardware such as a processor (general purpose or other purpose), a memory element, an output (USB port, wireless transmitter, HDMI port, etc.), an illumination / flash, an electrical input (keyboard, touch display, trackpad, mouse, microphone, etc.), and / or a display. The other hardware can deliver instructions to the imaging system 300, extract image data from the imaging system 300, or manipulate image data provided by the imaging system 300.

[0065] The above description of the illustrated examples of the present application (including that in the Abstract) is not intended to be a limitation on the present application. While specific examples of the present application are described in this specification, each of these can be modified, combined, substituted, deleted, augmented, improved, or changed in various ways, and the resulting examples are also intended to be within the scope of the present application. In fact, it will be understood that any specific example described herein is intended to be illustrative only and not limiting of the present application.

[0066] These modifications can be made in light of the above detailed description. The terms used in the following claims should not be construed to limit the application to the specific embodiments disclosed in the specification and drawings. Rather, the scope of the application is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation. The description and drawings are, therefore, to be regarded as illustrative rather than restrictive.

Claims

1. A method for forming a deep trench isolation structure for a CMOS image sensor, the method comprising: forming a trench in a semiconductor substrate, wherein the trench extends from a first face of the semiconductor substrate toward a second face of the semiconductor substrate, wherein the trench has an opening on the first face and a bottom and sides of the trench are formed by the semiconductor substrate; depositing a conformal layer of boron-doped dielectric at least on the bottom and the sides of the trench, wherein a thickness of the conformal layer of boron-doped dielectric is less than half of a width of the trench to leave a longitudinal recess in the trench; depositing a second material at least on the conformal layer of boron-doped dielectric in the trench, wherein the second material fills the recess in the trench to at least the first face; and annealing the conformal layer of boron-doped dielectric to push boron from the conformal layer of boron-doped dielectric to the semiconductor substrate and form a boron-doped region of the semiconductor substrate, the boron-doped region of the semiconductor substrate corresponding to a passivation layer disposed immediately adjacent to the conformal layer of boron-doped dielectric, wherein the second material comprises doped polysilicon and the annealing of the conformal layer of boron-doped dielectric further electrically activates the doped polysilicon.

2. The method of claim 1, wherein the depositing the conformal layer of boron-doped dielectric includes atomic layer deposition or chemical vapor deposition at a deposition temperature between 300 °C and 500 °C.

3. The method of claim 1, wherein the depositing the second material includes depositing the doped polysilicon by chemical vapor deposition at a deposition temperature between 450 °C and 550 °C.

4. The method of claim 1, wherein the conformal layer of boron-doped dielectric is borosilicate glass.

5. The method of claim 1, wherein the conformal layer of boron-doped dielectric has a negative fixed charge as a result of the annealing.

6. The method of claim 5, wherein the conformal layer of boron-doped dielectric forms a hole accumulation layer to provide additional passivation at least partially due to the negative fixed charge.

7. The method of claim 6, wherein the hole accumulation layer formed by the conformal layer of boron-doped dielectric overlaps the boron-doped region of the semiconductor substrate forming the passivation layer.

8. The method of claim 1, wherein a thickness of the conformal layer of boron-doped dielectric is 10 nm to 30 nm.

9. The method of claim 1, wherein the deposited conformal layer of boron-doped dielectric has a boron atomic concentration of 5% to 20% prior to the annealing.

10. The method of claim 1, wherein the conformal layer of boron-doped dielectric directly contacts the second material and the passivation layer.

11. The method of claim 1, wherein the annealing occurs after depositing the second material.

12. The method of claim 1, wherein the second material is blanket deposited, and wherein the method further comprises chemical mechanical polishing the second material to the semiconductor substrate.

13. The method of claim 1, wherein the annealing of the conformal layer of boron-doped dielectric is performed in an inert ambient atmosphere at a temperature from 800 °C to 1000 °C and at a pressure from 0.1 Torr to 760 Torr for a time from 1 min to 60 min.

14. The method of claim 1, wherein the annealing of the conformal layer of boron-doped dielectric occurs prior to formation of photodiodes in the semiconductor substrate.

15. The method of claim 1, further comprising: forming photodiodes proximate the first face of the semiconductor substrate and proximate the deep trench isolation structure after the annealing of the conformal layer of boron-doped dielectric; thinning the second face of the semiconductor substrate to a level of the passivation layer at the bottom of the trench to form a full deep trench isolation structure extending from the first face to the second face of the semiconductor substrate; and forming an isolation well proximate the first face of the semiconductor substrate, wherein the isolation well defines a pixel transistor region disposed over the photodiodes, such that the isolation well is disposed between the first face of the semiconductor substrate and the photodiodes.

16. The method of claim 15, further comprising: forming an interlayer dielectric layer on the first face of the semiconductor substrate, including metal conductors and vias disposed in the interlayer dielectric layer; forming a buffer oxide layer on the second face of the semiconductor substrate; forming a metal mesh on the buffer oxide layer; forming a color filter on the buffer oxide layer; and forming a microlens on the color filter.

17. The method of claim 16, further comprising bonding the interlayer dielectric layer to a system on a chip wafer.

18. The method of claim 15, further comprising forming a pixel transistor at least partially within the isolation well, the pixel transistor disposed over the photodiodes proximate the first face, the pixel transistor having a gate electrode formed on a surface of the first face.

19. A semiconductor structure for a CMOS image sensor, comprising: a semiconductor substrate having a first face and a second face; and a deep trench isolation structure extending from the first face toward the second face of the semiconductor substrate, wherein the deep trench isolation structure includes: a trench having a bottom and sides formed by the semiconductor substrate; a boron-doped dielectric layer on the bottom and sides of the trench; and a second material filling the trench at least to the first face of the semiconductor substrate, wherein the second material comprises a doped polysilicon extending in a central depth of the trench, wherein the doped polysilicon is electrically activated, wherein a boron-doped region is present in the semiconductor substrate on the bottom and sides of the trench as a passivation layer, and wherein the boron-doped region and the second material are on opposite sides of the boron-doped dielectric layer.

20. The semiconductor structure of claim 19, wherein the boron-doped dielectric layer is borosilicate glass. ​ ​ ​ 21. The semiconductor structure of claim 19, wherein the boron-doped dielectric layer has a thickness of 3 nm to 30 nm.

22. The semiconductor structure of claim 19, wherein the boron-doped dielectric layer has a boron atomic concentration of 5% to 20% when deposited.

23. The semiconductor structure of claim 19, further comprising a photodiode proximate the first face of the semiconductor substrate and proximate the deep trench isolation structure.

24. The semiconductor structure of claim 23, further comprising at least a pixel transistor disposed proximate the first face over the photodiode, the pixel transistor having a gate electrode formed on a surface of the first face.

25. The semiconductor structure of claim 24, further comprising an interlayer dielectric layer on the first face of the semiconductor substrate, including a metal conductor and a via disposed in the interlayer dielectric layer.

26. The semiconductor structure of claim 25, wherein the deep trench isolation structure extends from the first face to the second face of the semiconductor substrate.

27. The semiconductor structure of claim 26, further comprising: a buffer oxide layer disposed on the second face of the semiconductor structure and on the passivation layer at the bottom of the deep trench isolation structure; a metal mesh disposed on the buffer oxide layer; a color filter disposed on the buffer oxide layer; a microlens disposed on the color filter; and an application specific integrated circuit die bonded to the interlayer dielectric layer.

28. The semiconductor structure of claim 19, wherein the deep trench isolation structure is a grid of intersecting deep trench isolation structures enclosing a plurality of photodiodes within the intersecting deep trench isolation structures and electrically isolating individual photodiodes from adjacent photodiodes. ​

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