Memory device, method of operating the same, and method of operating a memory controller

Abstract

A memory device includes memory banks including a plurality of memory banks each including an array of memory cells, compute logic including a plurality of memory-in-processor (PIM) circuits arranged correspondingly to the memory banks, each of the plurality of PIM circuits performing a compute process using at least one selected from data provided from a host and information read from a corresponding one of the memory banks, and control logic configured to control memory operations to the memory banks in response to commands and / or addresses received from the host each or control the compute logic to perform the compute process, wherein read operations are performed in parallel for the compute process to the memory banks respectively, the memory banks are configured with offsets having different values respectively, and information is read from different locations in the respective array of memory cells of the memory banks and provided to the PIM circuits.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0005604, filed on January 15, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to a memory device, and more specifically, to a memory device that performs parallel computing processing, a method of operating the memory device, and a method of operating a memory controller that controls the memory device. Background Technology

[0004] The capacity and speed of semiconductor memory devices, widely used in high-performance electronic systems, have increased. Memory devices can be used to store various types of information, such as data. For example, memory devices can be used to store data for various computational processes (such as neural network calculations) or to store computation results. A method has been proposed for using the processor-in-memory (PIM) circuitry of memory devices to perform at least some computational operations in order to efficiently perform large amounts of computation.

[0005] PIM circuits can perform various computational processes using data provided from external sources and information stored in memory devices, and require appropriate data and information related to various neural network functions to be provided to PIM circuits. Summary of the Invention

[0006] Example embodiments provide a memory device that allows the data and information required for various neural network computations to be appropriately provided to the memory-in-memory processor (PIM) circuitry of the memory device, a method of operating the memory device, and a method of operating a memory controller for controlling the memory device.

[0007] According to one aspect of an example embodiment, a memory device is provided, comprising: a memory bank including a plurality of memory banks, each of the plurality of memory banks including a memory cell array, and the plurality of memory banks including at least a first memory bank and a second memory bank, the first memory bank including a first memory cell array, and the second memory bank including a second memory cell array; computing logic including a plurality of memory-in-processor (PIM) circuits arranged corresponding to the plurality of memory banks, the plurality of PIM circuits including at least a first PIM circuit arranged corresponding to the first memory bank and a second PIM circuit arranged corresponding to the second memory bank, and each of the plurality of PIM circuits being configured to perform computational processing using at least one selected from data provided from a host or memory information read from a corresponding memory bank of the plurality of memory banks. The control logic is configured to control memory operations on a memory bank based on at least one of a command or address received from a host, and to control computation logic to perform computational processing. The control logic is further configured to control, at least in parallel, a first read operation from a first memory bank and a second read operation from a second memory bank for computational processing. At least a first offset of the first memory bank and a second offset of the second memory bank are configured with different values ​​for the first memory bank and the second memory bank, respectively. The memory operations are configured to: read first memory information from a first location in the first memory cell array and read second memory information from a second location in the second memory cell array; and provide at least the first memory information to a first PIM circuit and the second memory information to a second PIM circuit.

[0008] According to one aspect of an example embodiment, a method of operating a memory device is provided. The memory device includes a plurality of memory banks and a plurality of memory-in-processor (PIM) circuits arranged corresponding to the plurality of memory banks. Each of the plurality of memory banks includes a memory cell array. The plurality of memory banks include at least a first memory bank arranged corresponding to a first PIM circuit and a second memory bank arranged corresponding to a second PIM circuit. The first memory bank includes a first memory cell array, the second memory bank includes a second memory cell array, the first memory cell array includes a first plurality of rows, and the second memory cell array includes a second plurality of rows. The method of operating the device includes configuring a plurality of offsets under the control of a host, the plurality of offsets including a first offset and a second offset of the first memory bank. The second offset of the memory bank, and the first offset and the second offset have different values; receiving at least one of a command or address from the host, the command or address being associated with the execution of computational processing; generating a plurality of internal addresses based on computation using the address and the plurality of offsets, the plurality of internal addresses being configured to access a plurality of memory banks, the plurality of internal addresses including a first internal address of a first memory cell array and a second internal address of a second memory cell array; reading first memory information from a first row of a first plurality of rows using the first internal address; reading second memory information from a second row of a second plurality of rows using the second internal address; and performing computational processing in parallel using at least a first PIM circuit and a second PIM circuit, respectively, utilizing the first memory information and the second memory information.

[0009] According to one aspect of an example embodiment, a method of operating a memory controller is provided, the memory controller controlling a memory device including a plurality of memory banks and a plurality of memory-in-processor (PIM) circuits arranged corresponding to the plurality of memory banks. The method of operating includes: controlling a memory operation configured to store a plurality of items of table information in the plurality of memory banks, the plurality of items of table information being obtained by classifying information for neural network computation; calculating a plurality of offsets based on the positions of the plurality of items of table information stored in the plurality of memory banks, the plurality of offsets having different values ​​for the plurality of memory banks; configuring the plurality of offsets in the memory device, the plurality of offsets being calculated corresponding to the plurality of memory banks; and controlling the computation operation by providing the memory device with at least one of a command or an address for computation processing, the computation processing being configured to perform computation processing using information read from different positions in the plurality of memory banks based on the address and the plurality of offsets. Attached Figure Description

[0010] Embodiments of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1This is a block diagram of a memory system including a memory device according to an example embodiment;

[0012] Figure 2 It shows from Figure 1 A conceptual diagram illustrating an example of reading information from multiple banks in a system;

[0013] Figure 3 This is a flowchart of an operation method of a memory device according to an example embodiment;

[0014] Figure 4 This is a block diagram illustrating an implementation of a memory device and a memory system according to an embodiment;

[0015] Figure 5 This is a conceptual diagram of a process for generating internal addresses according to an example embodiment;

[0016] Figure 6 This is a diagram illustrating an example of a computational operation performed according to an example embodiment;

[0017] Figure 7A and Figure 7B This is a diagram illustrating a method of operating a memory system according to an example embodiment;

[0018] Figure 8A , Figure 8B , Figure 9A and Figure 9B This is a block diagram illustrating examples of recording offsets in a memory device according to various embodiments;

[0019] Figure 10 This is a timing diagram illustrating the overall computational processing according to an example embodiment;

[0020] Figure 11 This is a block diagram illustrating an implementation of a memory device according to an example embodiment;

[0021] Figure 12 This is a conceptual diagram illustrating examples of various loops executed by a memory device during computational processing according to an embodiment;

[0022] Figure 13 This is a block diagram illustrating an example of a memory device including high bandwidth memory (HBM) according to an example embodiment; and

[0023] Figure 14 This is a block diagram of a server system including a data processing system according to an embodiment. Detailed Implementation

[0024] In the following description, exemplary embodiments will be described in detail with reference to the accompanying drawings.

[0025] Figure 1 This is a block diagram of a memory system including a memory device according to an example embodiment.

[0026] refer to Figure 1 The memory system 10 may include a memory controller 100 and a memory device 200. The memory controller 100 may include a memory interface and provide various signals to the memory device 200 through the memory interface to control memory operations such as writing and reading. For example, the memory controller 100 may provide the memory device 200 with commands CMD and addresses ADD, and access the data of the memory device 200.

[0027] The memory controller 100 can access the memory device 200 upon request from the host. The memory controller 100 can communicate with the host using various protocols. For example, the memory controller 100 can communicate with the host using interface protocols such as Peripheral Component Interconnect-High Speed ​​(PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), or Serial Attached Small Computer Interface (SCSI) (SAS). In addition to those, various other interface protocols (such as Universal Serial Bus (USB), Multimedia Card (MMC), Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE)) can also be used as protocols between the host and the memory controller 100.

[0028] According to the example embodiment, the memory controller 100 may correspond to a host or a configuration included in a host. The host and the memory device 200 may form a data processing system; therefore, the memory system 10 may correspond to the data processing system, or may be defined as a configuration included in the data processing system.

[0029] The memory device 200 may include a memory bank 210, computing logic 220, and control logic 230. The memory bank 210 may include multiple memory banks, for example, a first memory bank BANK 1 to an Nth memory bank BANK N, each memory bank may include a memory cell array, the memory cell array including multiple memory cells. The computing logic 220 may include at least one memory-in-memory processor (PIM) circuitry. Although the computing logic 220 includes... Figure 1The memory storage bank 210 contains N PIM circuits corresponding to N storage banks, such as first PIM circuit 221_1 to Nth PIM circuit 221_N. However, the computation logic 220 may include various numbers of PIM circuits. For example, when multiple PIM circuits are provided for a single storage bank, the number of PIM circuits may be greater than the number of storage banks. Conversely, when at least two storage banks share a single PIM circuit, the number of PIM circuits may be less than the number of storage banks. Each PIM circuit can perform computational processing using one or more bits of data from the host and one or more bits of information read from the memory device 200.

[0030] Control logic 230 may include command / address decoder 231. Command / address decoder 231 can decode commands (CMD) and / or addresses (ADD) from memory controller 100, and control logic 230 can perform internal control operations on memory device 200 to perform memory operations based on the decoding results. When computational processing in memory device 200 is controlled by memory controller 100, control logic 230 can perform internal control operations on memory device 200 to perform computational processing operations based on the decoding results.

[0031] Memory device 200 may include dynamic random access memory (DRAM), such as double data rate synchronous DRAM (DDR SDRAM), low power DDR (LPDDR) SDRAM, graphics DDR (GDDR) SDRAM, or Rambus DRAM (RDRAM). However, embodiments are not limited to this. For example, memory device 200 may include non-volatile memory, such as flash memory, magnetic RAM (MRAM), ferroelectric RAM (FeRAM), phase-change RAM (PRAM), or resistive RAM (ReRAM).

[0032] The memory device 200 may correspond to a single semiconductor chip or to a single channel in a memory device comprising multiple channels with independent interfaces. Alternatively, when the memory module comprises multiple memory chips, the memory device 200 may correspond to the memory module or to a single memory chip mounted on a module board.

[0033] Hereinafter, examples of computational processing operations performed in memory device 200 will be described with reference to exemplary embodiments. Various computational processing operations can be performed in memory device 200. For example, at least some of neural network computations related to artificial intelligence can be performed in memory device 200. For example, a host can control memory device 200 through memory controller 100, such that at least some of the neural network computations are performed by memory device 200. Although in the embodiments described below, memory controller 100 controls memory device 200, the embodiments are not necessarily limited thereto. For example, memory controller 100 may correspond to a configuration included in a host, and the host may control memory device 200.

[0034] Assuming the number of first PIM circuits 221_1 to Nth PIM circuits 221_N in the computational logic 220 is the same as the number of memory banks in the memory bank 210, each PIM circuit of the computational logic 220 can perform computational processing using information read from the corresponding memory bank. Each of the first PIM circuits 221_1 to Nth PIM circuits 221_N in the computational logic 220 may include a calculator and storage circuitry for storing certain information. For example, each of the first PIM circuits 221_1 to Nth PIM circuits 221_N may include a register for storing information used for computation and / or computation results.

[0035] In the example operation, data from the memory controller 100 can be provided jointly to the first PIM circuit 221_1 through the Nth PIM circuit 221_N, and the first PIM circuit 221_1 through the Nth PIM circuit 221_N can use the data to perform computational processing. Alternatively, different information can be read from the first memory bank BANK 1 through the Nth memory bank BANK N and provided to the first PIM circuit 221_1 through the Nth PIM circuit 221_N, and correspondingly, the first PIM circuit 221_1 through the Nth PIM circuit 221_N can use the same data and different information to perform computational processing.

[0036] According to the example embodiment, the first PIM circuit 221_1 to the Nth PIM circuit 221_N can perform parallel computing processing, and correspondingly, read operations performed on the first memory bank BANK 1 to the Nth memory bank BANK N can be performed in parallel. For example, the memory cell array of each memory bank may include multiple rows, and various information required for computing processing can be stored in a distributed manner in the rows of the first memory bank BANK 1 to the Nth memory bank BANK N, and information provided to the computing logic 220 can be read from different rows in the corresponding memory cell arrays of the first memory bank BANK 1 to the Nth memory bank BANK N.

[0037] According to an example embodiment, the calculation logic 220 may include an offset storage circuit that stores offsets, for example, first offsets offset_1 to Nth offsets offset_N corresponding to the first memory bank BANK 1 to the Nth memory bank BANK N, respectively. Figure 1 As shown, offset storage circuits can be arranged in each of the first PIM circuits 221_1 to the Nth PIM circuit 221_N, and store the offset of the corresponding memory bank. For example, the first PIM circuit 221_1 may include an offset storage circuit 222 that stores a first offset offset_1 corresponding to the first memory bank BANK 1. The offset storage circuit may include various types of storage circuits, such as registers.

[0038] Command / address decoder 231 can decode command (CMD) and / or address (ADD) from memory controller 100. For example, address (ADD) can be provided from control logic 230 to calculation logic 220, and each of the first PIM circuits 221_1 to Nth PIM circuits 221_N can generate an internal address using the address (ADD) from memory controller 100 and an offset stored therein, wherein the internal address indicates a read location in the memory cell array of a corresponding memory bank BANK 1 to Nth memory bank BANK N. For example, each of the first PIM circuits 221_1 to Nth PIM circuits 221_N may include an internal address generator that performs calculations using address (ADD) and offset to generate the internal address. Because the offset is configured differently for each memory bank, internal addresses can be generated to indicate different locations (e.g., different rows) in the corresponding memory cell arrays of the first memory banks BANK 1 to Nth memory banks BANK N.

[0039] In the example operation, the starting position of a read operation on the memory cell array of each bank can be defined based on an internal address generated using an offset. Neural network computation may involve a large amount of computation. Multiple rows of the memory cell array can be read sequentially in response to commands CMD and / or addresses ADD, each command CMD and / or address ADD instructing the execution of computational processing. Each PIM circuit can perform computational processing based on at least one of data from the memory controller 100 and information read from the corresponding bank. For example, information can be read sequentially from at least one row of each of the first bank BANK 1 and the second bank BANK 2, starting from different rows of the first bank BANK 1 and the second bank BANK 2, and the information read from the first bank BANK can be provided to the first PIM circuit 221_1, and the information read from the second bank BANK 2 can be provided to the second PIM circuit 221_2.

[0040] According to the above example embodiment, in the memory device 200 that performs multiple matrix-vector-based computations in parallel, offsets can be configured to process a large number of random vectors simultaneously in parallel. For example, for matrix-vector-based computations, when the matrix corresponding to the data is constant and the information corresponding to the vector is stored in a distributed manner in multiple rows of the corresponding memory cell arrays in the first memory bank BANK 1 to the Nth memory bank BANK N, the information corresponding to the vector can be read in parallel from the appropriate position in each of the first memory bank BANK 1 to the Nth memory bank BANK N and provided to the computation logic 220.

[0041] Offset configuration in memory device 200 can be controlled by memory controller 100. Memory controller 100 can provide various signals for offset configuration to memory device 200. In example operation, memory controller 100 can exchange data with memory device 200 via a data bus and can provide offset information offset[1:N] corresponding to the first memory bank BANK1 to the Nth memory bank BANK N via the data bus to memory device 200. Command CMD and / or address ADD indicating the execution of offset configuration can be defined in various ways. For example, offset configuration can be performed by defining commands separately from normal memory operations or by defining addresses with values ​​different from the address range of normal memory operations. Alternatively, memory device 200 can include a mode register set (MRS) for setting modes of various circuits in memory device 200, and commands for offset configuration can be defined using mode register commands from memory controller 100.

[0042] The command CMD and / or address ADD instructing the execution of computational processing can also be defined in various ways. For example, computational processing can be performed using each existing memory operation such as data writing and / or reading, or computational commands can be defined independently of normal memory operations. The memory device 200 can selectively perform memory operations or computational processing operations based on the decoding operation of the command CMD and / or address ADD.

[0043] Computational logic 220 can be defined in various ways, and accordingly, the PIM circuitry corresponding to each memory bank can include various elements. The PIM circuitry can include a calculator. Examples of calculators can include a Single Instruction Multiple Data (SIMD) unit and an Arithmetic Logic Unit (ALU). As mentioned above, the PIM circuitry can also include registers or internal address generators. Computational logic 220 can include various other elements related to computational processing. For example, computational logic 220 can include various elements such as a controller that controls all operations of the computational processing, an instruction memory (or instruction queue) that stores computation-related instructions, and a decoder that decodes the instructions.

[0044] The memory system 10 can process various types of data. According to an embodiment, when the memory device 200 performs neuromorphic computation, the memory device 200 may be referred to as a neuromorphic device or neuromorphic chip. Typically, neuromorphic computation can refer to the implementation of a model of the human nervous system using circuitry and / or software. When the memory device 200 corresponds to a neuromorphic device, the memory device 200 may include neuronal circuits and synaptic circuits, respectively corresponding to neurons and synapses in the human nervous system, as hardware components. For example, elements of the memory bank 210 and elements of the computational logic 220 may form neuronal circuits and synaptic circuits. According to an example implementation, the synaptic circuits may store weight information and perform weighted multiplication using a memristor-based design, and the memory bank 210 may include a memristor-based memory array.

[0045] The memory system 10 or the data processing system including the memory system 10 may include a personal computer (PC), a data server, a cloud system, an artificial intelligence server, network attached storage (NAS), an Internet of Things (IoT) device, or a portable electronic device. When the data processing system is a portable electronic device, it may include a laptop computer, a cellular phone, a smartphone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital camcorder, an audio device, a portable multimedia player (PMP), a personal navigation device (PND), an MP3 player, a handheld game console, an e-reader, or a wearable device.

[0046] Figure 2 It shows from Figure 1 A conceptual diagram illustrating an example of reading information from multiple storage units. Figure 2 An example of a read operation performed on the first memory bank BANK 1 and the second memory bank BANK 2 is shown.

[0047] refer to Figure 1 and Figure 2 The address ADD from the memory controller 100 can be provided jointly to the first memory bank BANK 1 and the second memory bank BANK 2, and the internal address generator of the memory device 200 can generate an internal address for each memory bank by applying different offsets to the address ADD. For example, the memory device 200 can generate a first internal address ADD_I1 for accessing the first memory bank BANK 1 by applying a first offset offset1 to the address ADD, and can generate a second internal address ADD_I2 for accessing the second memory bank BANK 2 by applying a second offset offset2 to the address ADD.

[0048] Based on the offsets applied to the first bank BANK 1 and the second bank BANK 2, information can be read from different rows of the first bank BANK 1 and the second bank BANK 2, respectively. For example, the internal address can be generated based on the sum of the address ADD and the offset configured for each bank. Figure 2 An example is shown where information “Info 1” is read from the second row (Row 2) of the first memory bank BANK 1 based on a first internal address ADD I1 and provided to the first PIM circuit PIM 1, and information “Info 2” is read from the Kth row (Row K) of the second memory bank BANK 2 based on a second internal address ADD I2 and provided to the second PIM circuit PIM 2. Therefore, the first PIM circuit PIM 1 and the second PIM circuit PIM 2 can perform computational processing on the same data (e.g., the same matrix) using different information (e.g., different vectors). According to the example embodiment, each of the first PIM circuit PIM 1 and the second PIM circuit PIM 2 may include a calculator (e.g., an ALU) and registers, and the results of the computational processing can be stored in the registers.

[0049] The configuration for generating internal addresses using offsets and address ADDs from memory controller 100 can be implemented in various ways. For example, an internal address generator can be provided jointly for multiple memory banks, and the internal address generator can use address ADDs and multiple offsets corresponding to the memory banks to generate internal addresses respectively. Alternatively, an internal address generator can be provided for each of the multiple memory banks, and the internal address generator can use address ADDs from memory controller 100 and offsets configured for the corresponding memory bank to generate internal addresses.

[0050] Figure 3 This is a flowchart of an operation method of a memory device according to an example embodiment.

[0051] refer to Figure 3 The memory device can be subject to various controls from a host (or memory controller) related to computational processing. For example, the memory device can receive instructions for various computational processes in advance and store the instructions in a storage circuit (e.g., instruction memory). For example, various computations can be performed sequentially for neural network functions analyzing image files or audio files, and instructions for predefined computations can be provided from the host to the memory device. The memory device can perform computational processing either by its own determination or in response to requests from the memory controller. For example, the memory device can sequentially read the stored instructions during each computational processing operation and sequentially execute computational processing operations according to a preset sequence based on the results of decoding the instructions.

[0052] Assuming computation is performed based on commands and / or addresses from the host, the memory device can receive each command and / or address in operation S11 that instructs the execution of computation, and can access multiple memory banks based on addresses. For example, multiple offsets can be defined for each memory bank, and at least two of the offsets can have different values ​​from each other.

[0053] In operation S12, the memory device can apply different offsets to the address for each memory bank, thereby generating multiple internal addresses for accessing the memory bank. For example, when multiple rows of each memory bank are accessed sequentially in response to commands and / or addresses from the host, in operation S13, starting addresses with different values ​​can be generated for the corresponding memory bank as internal addresses.

[0054] To read data from memory banks in parallel, multi-memory bank activation can be performed based on internal addresses in operation S14, and information can be read from the activated memory banks in operation S15. For example, rows at different locations in the memory banks can be activated, and information can be read from at least one row starting from the activated row in each memory bank, where the address of the activated row is the starting address. Typically, row activation in DRAM provides access to information stored in a specific row of the DRAM. Specifically, in some embodiments, row activation moves charge from a DRAM charge storage location (e.g., an effective capacitor) to a sense amplifier associated with that row. When multiple PIM circuits are provided for each memory bank, information read from each memory bank can be provided to the corresponding PIM circuit, and in operation S16, the PIM circuit can perform parallel computation processing using the received information. For example, the PIM circuits can simultaneously receive the same data from the memory controller (or host), and each PIM circuit can receive different information read from a corresponding memory bank. Therefore, the PIM circuits can receive the same data and generate outputs with different values ​​respectively.

[0055] Figure 4 This is a block diagram illustrating an implementation of a memory device and memory system according to an embodiment.

[0056] refer to Figure 4 The memory system or data processing system 300 may include a memory controller 310 and a memory device 320. The memory device 320 may include first memory banks 321_1 to Nth memory banks 321_N, each of which may include memory cell arrays 322_1 to 322_N. Each of the memory cell arrays 322_1 to 322_N may include multiple rows.

[0057] According to the example embodiment, the memory may include various components. Although the computational logic, including PIM circuitry, is provided outside the memory in the above embodiment, at least some components of each PIM circuit may be included within the memory. For example, besides Figure 4 In addition to the memory cell array 322_1, the first memory bank 321_1 also includes a calculator for computational processing (e.g., a first ALU 323_1) and an internal address generator 324_1 for generating the internal address ADD_I. However, other elements may also be included in the memory bank. Although in Figure 4 The diagram shows storage circuitry in the internal address generator that stores offsets configured for the memory bank; alternatively, the storage circuitry may be provided externally to the internal address generator.

[0058] The memory controller 310 can provide the memory device 320 with data and commands (CMD) and / or addresses (ADD) for computational processing. The memory device 320 may include a shared region 325, which includes at least one circuit configuration shared by the first memory bank 321_1 to the Nth memory bank 321_N. For example, the aforementioned control logic, command / address buffers, etc., may be included in the shared region 325. The shared region 325 may also include path selection circuitry for communication between the first memory bank 321_1 to the Nth memory bank 321_N and the memory controller 310.

[0059] Various signals related to computational processing can be provided to the first memory bank 321_1 to the Nth memory bank 321_N through the shared area 325. For example, data from the memory controller 310 can be provided to the first ALU 323_1 to the Nth ALU 323_N respectively included in the first memory bank 321_1 to the Nth memory bank 321_N, and the address ADD from the memory controller 310 can be provided to the internal address generators 324_1 to 324_N respectively included in the first memory bank 321_1 to the Nth memory bank 321_N.

[0060] Each of the first memory bank 321_1 to the Nth memory bank 321_N can use the address ADD and its offset to select a read location in its memory cell array. For example, assuming the offset configured in the first memory bank 321_1 has a value of 0, the offset set in the second memory bank 321_2 has a value of 3, and the address ADD has a value indicating the location of the first row "0" in the memory cell array, the information stored in the first row "0" of the memory cell array 322_1 of the first memory bank 321_1 can be read and provided to the first ALU 323_1, and the information stored in the fourth row "3" of the memory cell array 322_2 of the second memory bank 321_2 can be read and provided to the second ALU 323_2. Therefore, the first ALU 323_1 and the second ALU 323_2 can receive the same data and perform computational processing using information stored in different rows in the first memory bank 321_1 and the second memory bank 321_2, respectively.

[0061] When information is read sequentially from multiple rows in each storage bank for computational processing, information can be read sequentially from a certain number of rows starting from the first row "0" in the first storage bank 321_1, and information can be read sequentially from a certain number of rows starting from the fourth row "3" in the second storage bank 321_2.

[0062] exist Figure 4In the illustrated embodiment, the shared region 325 may further include a command / address decoder. During normal memory operation, based on the command / address decoding result, the memory controller 310 reads data from the row indicated by address ADD without applying an offset to address ADD.

[0063] Figure 5 This is a conceptual diagram of a process for generating internal addresses according to an example embodiment. The memory device may include at least one die. For example, the memory device may include a die that manages or controls memory operations (e.g., a buffer die) and at least one die (e.g., a core die) that includes an array of memory cells (or a memory bank).

[0064] refer to Figure 5 The memory device 400 may include a buffer die 410 and a core die 420. The buffer die 410 may include an address generator 411 and an offset configuration unit 412. The buffer die 410 can communicate with an external host or memory controller and can control the memory operations and computational processing operations of the core die 420 based on the results of decoding commands and / or addresses from the host. The core die 420 may include first to Nth memory banks 420_1 to 420_N. The buffer die 410 can receive control signals related to offset configuration from the host, and the offset configuration unit 412 can control the offset configuration of the first memory bank 420_1 to the Nth memory bank 420_N based on the control signals. Figure 5 In the example, exemplary offsets of 0x00, 0x30, and 0x10 are shown for three of the N memory banks.

[0065] In the example operation, address generator 411 can provide addresses from the host to the first memory bank 420_1 through the Nth memory bank 420_N of the core die 420. For example, the row address RowAddr included in the address from the host can be provided to the first memory bank 420_1 through the Nth memory bank 420_N for the generation of the aforementioned internal address. Each of the first memory bank 420_1 through the Nth memory bank 420_N can include an internal address generator ADDI_Gen, which can generate an internal address ADD_I by performing a calculation (e.g., addition) using an offset and the row address RowAddr generated from the address from the host. Because different offsets are configured for the first memory bank 420_1 through the Nth memory bank 420_N, the internal addresses ADD_I generated from the first memory bank 420_1 through the Nth memory bank 420_N can have different values ​​from each other. Therefore, information can be read from different rows in the corresponding memory arrays of the first memory bank 420_1 through the Nth memory bank 420_N.

[0066] Figure 6This is a diagram illustrating an example of a computational operation performed according to an example embodiment.

[0067] For neural network computations such as deep learning, artificial neural networks can be constructed, and multiplication and accumulation (MAC) operations are primarily performed within them. This involves multiplying a vector (or input vector) by a weight matrix and summing the results. For example, a matrix-vector operation can be written as Ax = b, where A is the weight matrix; x is the input vector with the number of elements equal to the number of columns in A; and b is the output vector with the number of elements equal to the number of rows in A. Figure 6 An example is shown in which each of the first storage bank 1 and the second storage bank 2 performs matrix-vector computation using vectors and weight matrices.

[0068] For example, data DATA1 to DATA H corresponding to the weight matrix can be provided from the host to the storage device, and information read from the corresponding memory cell arrays of multiple storage banks based on offsets can be formed into vectors. For example, when performing a function to analyze a file such as an image file or an audio file according to a neural network computation, the vectors read from multiple storage banks can include information about the file. In other words, to determine the features of a file, the information about the file can be classified into tabular information items based on various features and stored in the storage banks. When an output (e.g., the result of a neural network computation) is generated by performing weighted multiplication on the input, the information stored in the storage banks can correspond to the input.

[0069] like Figure 6 As shown, according to an embodiment, calculations can be performed in parallel by multiple PIM circuits corresponding to multiple memory banks. For example, data DATA1 to DATAH forming a weight matrix from the host can be provided to the first memory bank BANK1 and the second memory bank BANK2. Vectors can be read from different rows of the corresponding memory cell arrays of the first memory bank BANK1 and the second memory bank BANK2, and matrix-vector calculations can be performed. Figure 6 An example is shown where a vector is read from the first row 1 of the first memory bank BANK 1 and from the third row 3 of the second memory bank BANK 2, depending on the offset.

[0070] Based on the matrix-vector calculations described above, different calculation results can be generated from multiple memory banks using the same weight matrix. For example, a first calculation result Result 1 generated from the first memory bank BANK 1 (or the PIM circuit of the first memory bank BANK 1) can be different from a second calculation result Result 2 generated from the second memory bank BANK 2 (or the PIM circuit of the second memory bank BANK 2).

[0071] Figure 7A and Figure 7B This is a diagram illustrating an operation method of a memory system according to an example embodiment. (Reference) Figure 7A and Figure 7B This describes an example operation of a memory controller (or host) within a memory system. As mentioned above, the memory system can be referred to as a data processing system. The host can control a memory device, which includes multiple memory banks and multiple PIM circuits corresponding to those memory banks.

[0072] refer to Figure 7A It can perform various artificial intelligence functions, including the analysis of files such as image files or audio files, based on neural network calculations, and in operation S21, it can send information (e.g., calculation information) including file information used for neural network calculations from the memory controller to the memory device. For file analysis, the calculation information can be categorized into multiple feature tables, and calculations can be performed using weight information and the calculation information included in the feature tables. The host can control the operation of storing the calculation information categorized into the feature tables in the memory device. In the example operation, the host can store the calculation information categorized into the feature tables in different memory banks.

[0073] In operation S22, when computational information is stored in the memory device, the memory controller can determine an offset for each feature table. For example, for neural network computation, computational processing can be performed using weight information and computational information for each feature table, and the computational information can be stored in rows of multiple memory banks in a distributed manner. In this case, computational information can be stored at different locations in the memory bank for computational processing, and the memory controller can determine the offset based on the location where the computational information is stored.

[0074] In operation S23, the memory controller can perform a control operation to reset the registers of each PIM circuit in the memory device to perform computation processing, and in operation S24, it can configure an offset determined for each memory bank in the memory device. For example, the memory device may include multiple PIM circuits arranged corresponding to the memory banks, and an offset storage circuit for storing the offset may be provided in each PIM circuit. The memory controller can perform a control operation to store the determined offset in the offset storage circuit of each PIM circuit.

[0075] Subsequently, the memory controller can perform control operations to cause at least some of the computations included in the neural network computation to be performed in the memory device. For example, in operation S25, the memory controller can send a command and / or address indicating the execution of the computation operation, as well as data for the computation operation, to the memory device. For example, data from the memory controller can be provided jointly to the memory bank of the memory device. According to the above embodiment, the PIM circuits can perform computation processing using the same data and different computation information, and each PIM circuit can store the computation result in its register. In operation S26, the memory controller can receive the computation processing result from the memory device.

[0076] Figure 7B It is a conceptual diagram illustrating the overall flow of computational processing performed by the memory system.

[0077] Operation S31, which stores all inputs in a memory device, can refer to the operation of storing the aforementioned calculation information in multiple memory banks of the memory device. As described above, the memory controller can determine the storage location of the calculation information classified into the feature table in the memory device when storing the calculation information in the memory device, and can perform the aforementioned offset determination operation based on the storage location. Operation S32 refers to the process of reading the calculation information classified into the feature table for offset calculation, and refers to the functions of "reading table A", "reading table B", ... and "reading table N". In operation S33, an offset is determined for each feature table ("determine offset for table 1", "determine offset for table 2", ... "determine offset for table N"). In operation S34, the offset determined for each feature table is stored in the memory controller ("store offset for table 1", "store offset for table 2", and "store offset for table N").

[0078] Operation S35 refers to resetting the registers included in each PIM circuit of the memory device to perform the calculation processing according to the above embodiment. Operation S36 refers to storing or configuring the offset for each feature table in the memory device. The memory controller can provide commands and / or addresses for calculation processing to the memory device, and can also provide data to the memory device. Operation S37 refers to sending (or broadcasting) weight information as data to all memory banks of the memory device. The memory controller can provide a command and / or address to the memory device and receive the calculation result. Operation S38 refers to receiving the sum of multiple results of multiplying the data by the calculation information.

[0079] Figure 8A , Figure 8B , Figure 9A and Figure 9BThis is a block diagram illustrating examples of recording offsets in a memory device according to various embodiments. According to the above embodiments, the memory device may include a plurality of memory banks and a plurality of PIM circuits corresponding to the memory banks.

[0080] refer to Figure 8A and Figure 8B The memory system 400A may include a host 410A and a memory device 420A. For example, the host 410A may include an application processor (AP).

[0081] Various commands and / or addresses can be defined to store offsets in memory device 420A. For example, memory regions of the memory cell array included in memory system 400A can be indicated by a certain address range, such as... Figure 8B As shown. For example, memory operations on a memory region can be controlled using a certain address range from ADD 1 to ADD L, and another address range, such as ADD(L+1) to ADD(L+N), can be defined to indicate memory offsets. In other words, the memory system 400A can indicate memory offsets based on commands related to normal memory operations, and can perform memory operations or offset recording operations based on the results of decoding the command CMD and / or address ADD from the host 410A.

[0082] The host 410A can send offsets to the memory device 420A through various transmission paths. For example, the host 410A can exchange data for memory operations with the memory device 420A via the data bus. When the host 410A provides the memory device 420A with the command CMD and / or address ADD for storing offsets, the host 410A can provide the offsets to the memory device 420A via the data bus.

[0083] Figure 9A and Figure 9B An example of storing offsets using control commands for MRS (e.g., mode register commands) is shown. References Figure 9A and Figure 9B Control commands for the MRS may include a mode register write command (MRW) and a mode register read command (MRR) for controlling operations related to memory offsets. For example, the memory system 400B may include a host 410B and a memory device 420B. The host 410B can control the MRS by providing the memory device 420B with either the mode register write command (MRW) or the mode register read command (MRR).

[0084] An MRS region can be defined, into which various information related to the configuration of memory device 420B is written or read. The MRS region can be defined by a range of addresses from ADD 1 to ADD P. According to an example embodiment, another address range beyond this range can be further defined to store offsets. For example, host 410B can control the storage of offsets in memory device 420B by providing a mode register write command MRW and a specific address range to memory device 420B, or by providing a mode register read command MRR and another specific address range to memory device 420B.

[0085] Figure 10 This is a timing diagram illustrating the overall computational processing according to an example embodiment.

[0086] refer to Figure 10 The host (or memory controller) can control memory operations and computational processing operations by providing various command prompts (CMDs) to the memory devices. These commands can be defined in relation to computational processing operations at times T1, T2, T3, T4, T5, T6, T7, and T8.

[0087] For example, according to the above embodiment, the offset of each of a plurality of memory banks (e.g., the first memory bank BANK1 to the Nth memory bank BANK N) can be calculated and stored in the memory device, and for computation processing, a reset command MRST can be provided to the memory device to reset the registers of the PIM circuit at T0. Parallel computation processing can be performed using the plurality of PIM circuits included in the memory device. For this operation, an activation command ACT for simultaneously activating the memory banks of the memory device can be provided from the host to the memory device at T1. At this time, according to the above embodiment, the memory device can perform computation using the address ADD from the host and the offset configured for each memory bank, thereby generating an internal address for each memory bank. In addition, at least one row of each memory bank can be activated based on the internal address, and according to the above embodiment, rows at different locations in the memory bank can be activated.

[0088] At T2, the host can provide the memory device with a command ABRO to provide data for computational processing, and at T3, a command MAC can be provided to the memory device to instruct it to perform computations using data from the host and information read from each memory bank. In response to the command MAC, the memory device can perform computations in parallel using PIM circuitry. Information for neural network computations can be efficiently read and used from different rows of memory banks.

[0089] Computational processing using data and information stored in the memory bank can be performed repeatedly and sequentially. The host can repeatedly provide the command ABRO at T4 and T6 to provide data, and repeatedly provide the command MAC at T5 and T7 to instruct computation to be performed on the memory device. In the example operation, the size of a row in the memory cell array of each memory bank can be larger than the size of the data provided from the host, and accordingly, computation can be performed using information from a single active row and multiple data from the host. For example, when the command ABRO and command MAC are provided from the host, computation can be performed using data from the host and a portion of the information from the active row. Subsequently, when the host provides new commands ABRO and command MAC, computation can be performed using data from the host and another portion of the information from the active row.

[0090] When the PIM circuit performs a series of computational processing operations as described above, the host can provide the command SUM to the memory device at T8 to receive the computational processing result. In the example operation, in response to the command SUM, the memory device can provide the host with the summation result as the final computation result based on the MAC operation.

[0091] Figure 10 The series of operations shown can be repeated multiple times. For example, when performing heterogeneous neural network computation, or when performing computation using different feature tables in homogeneous neural network computation, this can be performed after offset determination and configuration according to the above embodiments. Figure 10 The series of operations shown in the figure.

[0092] Figure 11 This is a block diagram illustrating an implementation of a memory device according to an example embodiment. Figure 11 An example is shown in which each of the multiple memory banks includes multiple subarrays for the memory cell array, and provides PIM circuitry for each memory bank.

[0093] refer to Figure 11 The memory device 500 may include multiple memory banks, each of which may include at least one subarray and various elements relating to memory operations on the subarray (e.g., bit line sense amplifiers BL S / A, local input / output lines LIO, and global input / output lines GIO). For example, the first memory bank BANK 1 may include at least two subarrays 510 and 512.

[0094] The memory device 500 may further include computing logic 520, which may include multiple PIM circuits, such as a first PIM circuit 521_1 and a second PIM circuit 521_2 corresponding to the memory bank, respectively. The first PIM circuit 521_1 corresponding to the first memory bank BANK 1 may include a MAC unit as a calculator. Each of the first PIM circuit 521_1 and the second PIM circuit 521_2 may also include a register that stores information for calculation and / or calculation results.

[0095] The first PIM circuit 521_1 can perform computational processing using data from the host and information read from the first memory bank BANK 1, and can provide a computational result Result 1. In example operation, the host and / or memory device 500 generates various control signals, and the first PIM circuit 521_1 can perform computational operations in response to these control signals. For example, the first PIM circuit 521_1 can perform a reset operation on its registers in response to a reset signal Reset, and can output the computational result Result 1 stored in the registers to the host in response to a result output request E_Out.

[0096] Figure 12 This is a conceptual diagram illustrating examples of various loops executed by a memory device during computational processing according to an embodiment. Figure 12 Examples of operations performed based on various cyclical processes are shown.

[0097] Before the computational processing, according to the above embodiment, the registers of the memory device can be reset in operation S41, and word lines in each of the multiple memory banks can be activated in operation S42 based on the address from the host and the offset configured for each memory bank. According to the above embodiment, rows at different locations in the memory bank can be activated. In operation S43, data corresponding to the weight information can be sent (or broadcast) from the host to the memory bank. In operation S44, data can be read (or retrieved) from memory cells (e.g., DRAM cells) of each activated row. As in the above embodiment, data can be read from some memory cells of the activated row in operation S44. Some memory cells of the activated row can be selected by column address.

[0098] When performing computation using the first loop (Loop 1), after performing a MAC operation in operation S45 using data from the host and information read from some memory units, new data can be broadcast from the host. Thereafter, MAC operations can be performed using the new data from the host and data read from other memory units of the active row. When the computation using a row of data is completed through the above process, the row can be precharged in operation S46, and the computation result can be output in operation S47.

[0099] When performing computation using the second loop (Loop2), operations S41 to S45 can be executed sequentially according to the above embodiment, and the activated row can be pre-charged in operation S46. Subsequently, in order to perform computation using information from another row, the row address (or internal address) can be changed, and the row corresponding to the changed row address can be activated in operation S42. Afterwards, operations S43 to S46 can be executed sequentially, and the computation result using information from multiple rows can be output in operation S47.

[0100] When performing computation using the third loop (Loop3), operations S46 and S47 can be executed when computation is completed for a line. After outputting the computation result, the memory device registers can be reset in operation S41, and operations S42 to S47 can be executed sequentially for another line. In other words, when using the third loop (Loop3), the computation result can be provided to the host each time computation is performed using information from a line.

[0101] Figure 13 This is a block diagram illustrating an example of a memory device including high-bandwidth memory (HBM) according to an example embodiment.

[0102] By including multiple channels with independent interfaces, the HBM 600 can achieve increased bandwidth. (Reference) Figure 13 The HBM600 can include multiple dies, such as a buffer die (or logic die) 610 and one or more core dies 620 stacked on the buffer die 610. Figure 14 In the example shown, HBM 600 includes the first through fourth core dies, but the number of core dies 620 can vary.

[0103] Each of the core die 620 can include at least one channel. Figure 13In the example shown, each of the core dies 620 includes two channels, and therefore, the HBM 600 has eight channels CH1 to CH8. For example, the first core die may include a first channel CH1 and a third channel CH3, the second core die may include a second channel CH2 and a fourth channel CH4, the third core die may include a fifth channel CH5 and a seventh channel CH7, and the fourth core die may include a sixth channel CH6 and an eighth channel CH8.

[0104] Buffer die 610 may include interface (IF) circuitry 611 for communicating with a host (or memory controller) and may receive commands and / or addresses and data from the host via interface circuitry 611. The host may send commands and / or addresses and data via a bus provided for the channel. Buses may be provided separately for each channel, or some buses may be shared by at least two channels. Interface circuitry 611 may send commands and / or addresses and data to a channel requesting the host to perform a memory operation or computational processing operation. According to an example embodiment, each of the core dies 620 or each of the channels may include PIM circuitry 621 and offset memory circuitry 622. Although in Figure 13 The diagram shows a PIM circuit 621, but multiple PIM circuits can be provided corresponding to multiple memory banks for each channel.

[0105] The host can provide commands and / or addresses and data, enabling at least some calculations to be performed by the HBM 600, and computational processing can be performed by the PIM circuitry 621 of the channel indicated by the host. According to an example embodiment, each channel may include multiple memory banks, and the offset storage circuitry 622 can store the offset of each of the memory banks. For example, according to the above embodiment, offsets with different values ​​for corresponding memory banks can be stored. When performing parallel data reads on the memory banks, data at different locations within the memory banks can be read based on the offsets.

[0106] The buffer chip 610 may also include a through-silicon via (TSV) region 612, a physical (PHY) region 613, and a direct access (DA) region 614. A processor controlling all operations of the HBM 600, such as data transfer path control, may also be provided in the buffer die 610.

[0107] TSV region 612 is the region in which a TSV for communication with the core die 620 is formed. PHY region 613 may include multiple input / output circuits for communication with an external host. For example, PHY region 613 may include at least one port for communication with a host. DA region 614 can communicate directly with an external test instrument in the test mode of HBM 600 by providing conductive components on the outer surface of HBM 600.

[0108] Figure 14 This is a block diagram of a server system including a data processing system according to an embodiment.

[0109] refer to Figure 14 The server system 700 may include a manager 710 and multiple servers 720_1, 720_2 to 720_K. Each of servers 720_1 to 720_K may correspond to the data processing system described in the above embodiments. Servers 720_1 to 720_K may be interconnected via a bus supporting predetermined protocols (e.g., PCI, PCI-E, etc.). For example, servers 720_1 to 720_K may communicate with each other via a peer-to-peer (P2P) connection architecture under the control of manager 710.

[0110] Referring to a server, such as server 720_1, server 720_1 may include a host, and according to the above embodiments, at least one memory device MEM can perform various computational processes according to its functions and can store the process results. According to embodiments, the memory device MEM may include a plurality of memory banks and PIM circuitry arranged corresponding to the memory banks. According to the above embodiments, the host can control the offset calculation and storage operations of the memory banks of the memory device MEM. In various embodiments, server system 700 may correspond to a neural network server system, and server 720_1 can control the memory device MEM such that at least some of a large number of neural network computations can be performed by the memory device MEM.

[0111] While exemplary embodiments of this disclosure have been specifically shown and described, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A memory device, comprising: A memory storage unit includes a plurality of memory units, each of the plurality of memory units including a memory cell array, and the plurality of memory units including at least a first memory unit and a second memory unit, the first memory unit including a first memory cell array, and the second memory unit including a second memory cell array; The computational logic includes a plurality of memory-in-processor (PIM) circuits arranged corresponding to the plurality of memory banks, the plurality of PIM circuits including at least a first PIM circuit arranged corresponding to a first memory bank and a second PIM circuit arranged corresponding to a second memory bank, the first memory bank including first memory information and configured to provide the first memory information only to the first PIM circuit, and each of the plurality of PIM circuits being configured to perform computational processing using at least one selected from data provided from a host or memory information read from a corresponding memory bank of the plurality of memory banks; as well as The control logic is configured to control memory operations on the memory bank based on at least one of commands or addresses received from the host, and to control the computation logic to perform computational processing. The control logic is further configured to control, at least in parallel, a first read operation from the first memory bank and a second read operation from the second memory bank for computational processing. Wherein, at least a first offset of the first memory bank and a second offset of the second memory bank are respectively configured with different values ​​for the first memory bank and the second memory bank, and The memory operation is configured as follows: Read the first memory information from a first location in the first memory cell array, and read the second memory information from a second location in the second memory cell array. At least the first memory information is provided to the first PIM circuit and the second memory information is provided to the second PIM circuit.

2. The memory device according to claim 1, further comprising: The offset storage circuit is configured to store at least a first offset and a second offset.

3. The memory device according to claim 1, wherein, The first memory cell array of the first storage bank includes a first plurality of rows containing a first row, and the second memory cell array of the second storage bank includes a second plurality of rows containing a second row. The first memory information from the first row and the second memory information from the second row are read in parallel according to the first offset and the second offset, respectively.

4. The memory device according to claim 3, wherein, The memory operation is further configured to sequentially read first memory information from a first plurality of rows in a first memory bank in response to at least one of a command or address received from a host. as well as Wherein, according to the first offset and the second offset, the first starting position of the first read operation from the first plurality of rows is different from the second starting position of the second read operation from the second plurality of rows.

5. The memory device of claim 1, further comprising an internal address generator configured to: Based on a first calculation using an address from the host and a first offset, a first internal address is generated indicating a first read location in the first memory cell array of the first memory bank, and Based on a second calculation using the address from the host and a second offset, a second internal address is generated that indicates the second read location in the second memory cell array of the second storage bank.

6. The memory device according to claim 5, wherein, The internal address generator includes a first internal address generator corresponding to the first memory bank and a second internal address generator corresponding to the second memory bank. The address from the host is common across multiple PIM circuits.

7. The memory device according to claim 1, wherein, Data from the host is jointly provided to the multiple PIM circuits; and The plurality of PIM circuits are configured to use memory information and data to perform computational processing.

8. The memory device according to claim 1, wherein, The computational processing includes neural network computation using a weight matrix and at least a first vector and a second vector, the weight matrix including data from the host, the first vector including first memory information read from a first storage bank, and the second vector including second memory information read from a second storage bank.

9. The memory device according to claim 8, wherein, The weight matrix is ​​provided jointly to the plurality of PIM circuits; as well as The plurality of PIM circuits use a weight matrix and at least a first vector and a second vector to perform computational processing. The weight matrix includes data from the host provided jointly by the host. The at least first vector and the second vector include a third vector, which includes third memory information read from a third memory bank among the plurality of memory banks.

10. The memory device of claim 8, further comprising a memristor array, wherein, The memristor array is configured as follows: Store the weight matrix. Input the first vector into the weight matrix, and Output the result of the weight matrix operation on the first vector.

11. The memory device according to claim 1, wherein, The memory device includes a high-bandwidth memory (HBM), which includes multiple channels, including a first channel and a second channel. The first channel includes multiple memory cells and multiple PIM circuits, and The second channel includes a second plurality of memory cells and a second plurality of PIM circuits, and the second channel is configured in a similar manner to the first channel.

12. A method of operating a memory device, the memory device comprising a plurality of memory banks and a plurality of memory-in-processor (PIM) circuits arranged corresponding to the plurality of memory banks, each of the plurality of memory banks comprising a memory cell array, the plurality of memory banks comprising at least a first memory bank arranged corresponding to a first PIM circuit and a second memory bank arranged corresponding to a second PIM circuit, the first memory bank comprising first memory information and configured to provide the first memory information only to the first PIM circuit, the first memory bank comprising a first memory cell array, the second memory bank comprising a second memory cell array, the first memory cell array comprising a first plurality of rows, and the second memory cell array comprising a second plurality of rows. The operation method includes: Multiple offsets are configured under the control of the host, including a first offset of a first memory bank and a second offset of a second memory bank, and the first offset and the second offset have different values; Receive at least one of a command or address from the host, wherein the at least one command or address is associated with the execution of computational processing; Multiple internal addresses are generated based on calculations using the address and the multiple offsets, the multiple internal addresses being configured to access the multiple memory banks, the multiple internal addresses including a first internal address of a first memory cell array and a second internal address of a second memory cell array; The first memory information is read from the first row of the first plurality of rows using the first internal address; Use the second internal address to read the second row of the second plurality of rows; as well as At least a first PIM circuit and a second PIM circuit are used to perform computational processing in parallel using the first memory information and the second memory information, respectively.

13. The operating method according to claim 12, further comprising: Receive data from the host; as well as The data is provided to multiple PIM circuits. Parallel execution of computational processing includes using multiple PIM circuits to perform computational processing using data and memory information, wherein the data is provided jointly by the host.

14. The operating method according to claim 12, wherein, Configuring the multiple offsets includes: Receive at least one of a command or an address from the host, the command and address being associated with a configuration of multiple offsets; Multiple offsets are received from the host via a data bus, each offset having a different value for the multiple memory banks; and Multiple offsets are stored in the corresponding storage circuits of multiple PIM circuits respectively.

15. The operating method according to claim 12, further comprising receiving a second address, in, The address has a first value within a first range, and the second address has a second value within a second range different from the first range. The first value within the first range is associated with the execution of memory operations on a plurality of memory banks. The configuration of the multiple offsets is performed based on the second address.

16. A method of operating a memory controller, the memory controller controlling a memory device, the memory device including a plurality of memory banks and a plurality of memory-in-processor (PIM) circuits, the plurality of memory banks including at least a first memory bank and a second memory bank, the plurality of PIM circuits including at least a first PIM circuit and a second PIM circuit, the plurality of PIM circuits being arranged corresponding to the plurality of memory banks, and the first memory bank including first memory information and configured to provide the first memory information only to the first PIM circuit. The operation method includes: Controlling memory operations, the memory operations being configured to store multiple items of table information in multiple storage banks, the multiple items of the table information being obtained by classifying information for neural network computation; Based on the table information, multiple items are stored in multiple storage bodies at their respective locations, and multiple offsets are calculated, with each offset having a different value for the multiple storage bodies. The plurality of offsets are configured in the memory device, and the plurality of offsets are calculated corresponding to the plurality of memory banks; as well as Computational operations are controlled by providing at least one of a command or address to a memory device for computational processing, which is configured to perform computational processing using information read from different locations in multiple memory banks based on the address and multiple offsets.

17. The operating method according to claim 16, wherein, The control calculation operation includes providing data to the plurality of PIM circuits, the data corresponding to matrices in matrix-vector calculations.

18. The operating method according to claim 17, wherein, The data includes a weight matrix, and the input vector includes memory information read from the plurality of storage units, the memory information including file information of the target to be analyzed.

19. The method of operation of claim 16, further comprising resetting a register before configuring the plurality of offsets, the register being included in at least the first PIM circuit of the plurality of PIM circuits.

20. The operating method according to claim 16, wherein, Controlling memory operations includes: controlling memory operations to store different items in the plurality of items of table information in different storage banks of the plurality of storage banks.

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