Method for improving identification of bottom metal and pad and semiconductor structure

Abstract

The present invention provides a method and a semiconductor structure for improving the identification of bottom metal and pad, the method comprising: providing a substrate, forming a first mask layer with a first window and a bottom metal, removing the first mask layer, forming a repair metal layer, forming a second mask layer with a second window, forming a pad, removing the second mask layer and part of the repair metal layer, and then forming a metal wire on the pad. The present invention forms a repair metal layer on the bottom metal and the substrate around it after removing the first mask layer, and the repair metal layer has a higher surface flatness than the bottom metal, thereby improving the flatness of the surface of the pad formed subsequently, and increasing the roughness difference between the surface of the pad and the surface of the bottom metal around the pad, making the two easier to identify and distinguish, thereby facilitating accurate and effective preparation of metal wires on the pad, and improving the yield of metal wire preparation.

Description

Technical Field

[0001] The invention belongs to the field of packaging, and in particular relates to a method for improving the identification of bottom metal and welding pad and a semiconductor structure. Background Art

[0002] The general definition of wafer level packaging (WLP) is: most or all packaging and testing procedures are performed directly on the wafer, and then cut (Singulation) into a single chip (Chip). Due to WLP's high packaging density, fast packaging speed and low packaging cost, it has become one of the more advanced packaging methods and has been widely used.

[0003] In the existing packaging process, there are problems such as rough pads, uneven surfaces and defects on the pad surfaces. In addition, it is necessary to identify and distinguish the metal layer and the lead pads formed on the metal layer, and there is a problem that it is difficult to effectively distinguish between the two. For example, in the packaging process, after the pad metal is formed on the grounding metal (such as GND Cu), the two often need to be identified so that metal wires can be prepared on the pad metal. If there are defects on the surface of the exposed grounding metal and the surface of the pad metal, or the morphology, roughness and other factors that affect the identification between the two are similar, it is difficult to effectively distinguish between the two, which is bound to affect the yield of subsequent metal wire preparation and the yield of the product.

[0004] Therefore, it is necessary to provide a method for improving the identification of the bottom metal and the bonding pad and a semiconductor structure to solve the above problems. Summary of the invention

[0005] In view of the shortcomings of the prior art described above, an object of the present invention is to provide a method and a semiconductor structure for improving the identification of the bottom metal and the welding pad, so as to solve the problems in the prior art such as uneven welding pad surface, surface defects, and poor identification between the welding pad and the bottom metal around it that is difficult to effectively distinguish.

[0006] To achieve the above objectives and other related objectives, the present invention provides a method for improving the identification of bottom metal and pad, the method comprising:

[0007] providing a substrate;

[0008] forming a first mask layer on the substrate, wherein the first mask layer includes a first window defining a bottom metal position;

[0009] forming the bottom metal in the first window;

[0010] removing the first mask layer;

[0011] forming a repair metal layer on the bottom metal and the surrounding substrate;

[0012] forming a second mask layer on the repair metal layer, wherein the second mask layer comprises a second window defining a pad, and the second window is correspondingly located on the bottom metal and exposes the repair metal layer;

[0013] forming a welding pad in the second window;

[0014] The second mask layer and the repair metal layer around the bonding pad are removed, and a metal wire is prepared on the bonding pad.

[0015] Optionally, the pad includes a buffer barrier layer and a metal layer sequentially formed on the bottom metal surface in the second window.

[0016] Optionally, the buffer barrier layer includes a Ni layer; the metal layer includes an Au layer; and the bottom metal material includes Cu.

[0017] Optionally, the thickness of the buffer barrier layer is between 1.8 μm and 2.2 μm; the thickness of the metal layer is between 0.1 μm and 1 μm; and the thickness of the bottom metal is between 3 μm and 6 μm.

[0018] Optionally, a seed layer is further formed on the substrate, the first window exposes the seed layer, the first mask layer and the bottom metal are both formed on the seed layer, and the seed layer is removed after the first mask layer is removed.

[0019] Optionally, the seed layer includes an adhesion layer and an upper metal layer sequentially formed on the substrate, wherein a material of the upper metal layer is the same as a material of the bottom metal, and the adhesion layer includes a Ti layer.

[0020] Optionally, the substrate includes a supporting layer, a peeling layer formed on the supporting layer, and a dielectric layer formed on the peeling layer, wherein the bottom metal is formed on the dielectric layer based on the first window.

[0021] Optionally, the process of forming the metal wire includes a wire bonding process.

[0022] Optionally, the repair metal layer is formed by a sputtering process.

[0023] Optionally, the material of the repair metal layer is the same as that of the bottom metal; the thickness of the repair metal layer is between 1000 angstroms and 8000 angstroms.

[0024] The present invention further provides a semiconductor structure for improving the identification of the bottom metal and the pad. The formation of the semiconductor structure is preferably based on the method for improving the identification of the bottom metal and the pad provided by the present invention. Of course, it can also be prepared by other methods, wherein the semiconductor structure includes:

[0025] substrate;

[0026] A plurality of bottom metals are spaced apart and distributed on the substrate;

[0027] A plurality of welding pads are formed on each of the bottom metals;

[0028] A plurality of repair metal parts are formed between the bottom metal and the pads respectively;

[0029] A metal wire is formed on the bonding pad.

[0030] Optionally, the repair metal part comprises a metal layer based on a sputtering process, and the material of the repair metal part is the same as that of the bottom metal; the thickness of the repair metal part is between 1000 angstroms and 8000 angstroms.

[0031] As described above, the method and semiconductor structure of improving the identification of the bottom metal and the welding pad of the present invention forms a repair metal layer on the bottom metal and the substrate around it after removing the first mask layer. The repair metal layer has a higher surface flatness than the bottom metal, thereby improving the flatness of the surface of the subsequently formed welding pad, and can increase the difference in roughness between the surface of the welding pad and the surface of the bottom metal around the welding pad, making the two easier to identify and distinguish, thereby facilitating the accurate and effective preparation of metal wires on the welding pads and improving the yield of metal wire preparation. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 Shown is a flow chart of a method for improving the identification of bottom metal and bonding pads according to the present invention.

[0033] Figure 2 It is a schematic diagram showing the structure of a substrate provided in the process of the method for improving the identification of the bottom metal and the bonding pad of the present invention.

[0034] Figure 3 It is a schematic diagram showing the formation of a first mask layer during the method for improving the identification of bottom metal and bonding pad according to the present invention.

[0035] Figure 4 It is a schematic diagram showing the formation of bottom metal in the process of the method for improving the identification between bottom metal and bonding pad according to the present invention.

[0036] Figure 5 It is a schematic diagram showing the removal of the first mask layer during the method for improving the identification of the bottom metal and the bonding pad according to the present invention.

[0037] Figure 6 It is a schematic diagram showing the formation of a repair metal layer during the method for improving the identification between the bottom metal and the bonding pad according to the present invention.

[0038] Figure 7 It is a schematic diagram showing the formation of a second mask layer during the method for improving the identification of the bottom metal and the bonding pad according to the present invention.

[0039] Figure 8 It is a schematic diagram showing the formation of a bonding pad during the method for improving the identification between the bottom metal and the bonding pad according to the present invention.

[0040] Fig. 9 It is a schematic diagram showing the removal of the second mask layer and a portion of the repaired metal layer during the method for improving the identification of the bottom metal and the bonding pad according to the present invention.

[0041] Fig.10 It is a schematic diagram showing the formation of metal lines during the method for improving the identification of bottom metal and bonding pads according to the present invention.

[0042] Component number description

[0043] 101 Base

[0044] 101a Support layer

[0045] 101b Peeling layer

[0046] 101c Dielectric Layer

[0047] 102 first mask layer

[0048] 102a First Window

[0049] 103 Bottom Metal

[0050] 104 Repair metal layer

[0051] 105 Second mask layer

[0052] 105a Second Window

[0053] 106 Solder pad

[0054] 106a Buffer barrier layer

[0055] 106b Metal layer

[0056] 107 Repair of metal parts

[0057] 108 Metal Wire

[0058] Steps S1 to S8 DETAILED DESCRIPTION

[0059] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0060] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0061] For ease of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0062] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0063] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0064] like Figure 1-10 As shown, the present invention provides a method for improving the identification of bottom metal and pad, the method comprising:

[0065] providing a substrate;

[0066] forming a first mask layer on the substrate, wherein the first mask layer includes a first window defining a bottom metal position;

[0067] forming the bottom metal in the first window;

[0068] removing the first mask layer;

[0069] forming a repair metal layer on the bottom metal and the surrounding substrate;

[0070] forming a second mask layer on the repair metal layer, wherein the second mask layer comprises a second window defining a pad, and the second window is correspondingly located on the bottom metal and exposes the repair metal layer;

[0071] forming a welding pad in the second window;

[0072] The second mask layer and the repair metal layer around the bonding pad are removed, and a metal line is formed on the bonding pad.

[0073] The scheme of the present invention will be described in detail below with reference to the accompanying drawings.

[0074] like Figure 1 S1 and Figure 2 As shown, a substrate 101 is provided. The substrate 101 may be any structure on which a subsequent bottom metal 103 is formed. The substrate 101 may be a single material layer or a stacked structure composed of multiple material layers.

[0075] In one example, the substrate 101 includes a supporting layer 101a, a peeling layer 101b formed on the supporting layer 101a, and a dielectric layer 101c formed on the peeling layer 101b, wherein the supporting layer 101a can be selected to be glass, and the peeling layer 101b can separate the supporting layer 101a and the structure above the peeling layer 101b in a subsequent process. Optionally, the peeling layer 101b can be selected to be a light-to-heat conversion layer (LTHC), which is formed on the supporting layer 101a by a spin coating process and is cured and formed by a curing process. The light-to-heat conversion layer (LTHC) has stable performance and a smooth surface, which is conducive to obtaining a flat surface. In the subsequent peeling process, the peeling difficulty is relatively low. The dielectric layer 101c includes but is not limited to a silicon oxide layer. The subsequent bottom metal 103 is formed on the dielectric layer 101c. Of course, the substrate 101 may also include other structures, such as a structure electrically connected to the bottom metal 103 via the dielectric layer 101c.

[0076] like Figure 1 S2 and Figure 3 As shown, a first mask layer 102 is formed on the substrate 101, and the first mask layer includes a first window 102a for defining the position of the bottom metal 103, wherein the number and arrangement of the first windows 102a are selected according to actual requirements for the bottom metal 103, and optionally, the material of the first mask layer 102 can be photoresist, which can be prepared by photoresist coating, exposure and development processes.

[0077] like Figure 1 S3 and Figure 4 As shown, the bottom metal 103 is formed in the first window 102a. The bottom metal 103 is formed on the substrate 101 defined by the first window 102a. The material of the bottom metal 103 may be Cu, which may be prepared by an electroplating process. In one example, it may be a metal Cu (GND Cu) used as a ground connection. Optionally, the thickness of the bottom metal is between 3μm and 6μm, such as 4μm and 5μm. In one example, the thickness of the grounding metal Cu may be 3μm or 6μm. The thickness of the bottom metal 103 is set according to actual conditions.

[0078] like Figure 1 S4 and Figure 5 As shown, the first mask layer 102 is removed. In one example, the material of the first mask layer 102 can be selected as photoresist, and a degumming solution can be used to remove the first mask layer 102, thereby facilitating the subsequent preparation of a patterned second mask layer 105 to form a solder pad 106 on the bottom metal 103 based thereon.

[0079] like Figure 1 S5 and Figure 6 As shown, a repair metal layer 104 is formed on the bottom metal 103 and the substrate 101 around it, wherein the repair metal layer 104 has a higher surface flatness than the bottom metal 103. The formation of the repair metal layer 104 can be used to improve the flatness of the surface of the bottom metal 103, thereby facilitating the improvement of the flatness of the surface of the subsequently formed pad 106. The repair metal layer 104 around the pad 106 will be removed later, so that the roughness difference between the pad 106 and the bottom metal 103 around it can be improved through the solution of the present invention. As an example, a sputtering process is used. The repair metal layer 104 is formed. The flatness of the material layer formed by sputtering is better than that of the material layer formed by electroplating. Therefore, the repair metal layer 104 can improve the flatness of the surface of the subsequently formed pad 106. In addition, other processes may also cause damage to the surface of the bottom metal 103. For example, the process of removing the first mask layer 102 may cause etching to the surface of the bottom metal 103 or there may be residue of the removal liquid. The formation of the repair metal layer 104 can also repair the above defects, thereby improving the flatness of the surface of the bottom metal 103 and the flatness of the pad 106.

[0080] As an example, the material of the repair metal layer 104 is the same as that of the bottom metal 103, for example, both can be selected as Cu. In another example, the thickness of the repair metal layer 104 is between 1000 angstroms and 8000 angstroms, and can be 2000 angstroms, 5000 angstroms, etc., thereby effectively improving the roughness of the surface of the bottom metal 103 while ensuring the consistency and stability of the semiconductor structure material, that is, effectively improving the surface flatness of the pad 106.

[0081] like Figure 1 S6 and Figure 7 As shown, a second mask layer 105 is formed on the repair metal layer 104, and the second mask layer 105 includes a second window 105a defining a pad 106, and the second window 105a is located on the bottom metal 103 and exposes the repair metal layer 104. In one example, the second window 104a corresponds to the bottom metal 103 one by one, so as to prepare a pad on the bottom metal 103 defined by the second window 105a, so as to electrically lead out the bottom metal 103. Optionally, the material of the second mask layer 105 can be photoresist, which can be prepared by photoresist coating, exposure and development processes. In the present invention, after the bottom metal 103 is formed, the first mask layer 102 is removed, and then the second mask layer 105 is directly formed on the repair metal layer 104 after it is formed, and the second window 105a required for forming the pad 106 is obtained.

[0082] like Figure 1 S7 and Figure 8As shown, a pad 106 is formed in the second window 105a, wherein the pad 106 is formed on the bottom metal 103 corresponding to the second window 105a, and can be formed by electroplating. As an example, the pad 106 includes a buffer barrier layer 106a and a metal layer 106b sequentially formed on the surface of the repair metal layer 104 in the second window 105a. The buffer barrier layer 106a has the functions of buffering and blocking. In an example, the buffer barrier layer is selected as a Ni layer, and the metal layer is selected as an Au layer. Of course, the materials of the two can also be selected and set according to actual conditions. In a further optional example, the thickness of the buffer barrier layer is between 1.8μm-2.2μm, such as 2μm; the thickness of the metal layer is between 0.1μm-1μm, such as 0.5μm; the thickness of the bottom metal is between 3μm-6μm, such as 3μm, 4μm, 5μm, 6μm. This is beneficial for further improving the surface flatness of the pad 106 under the premise of forming the repair metal layer 104 of the present invention, thereby helping to further increase the difference in roughness between the pad 106 and the bottom metal 103 surrounding it, thereby improving the recognition between the two.

[0083] like Figure 1 S8 and Figure 9-10 As shown, the second mask layer 105 is removed. As an example, the material of the second mask layer includes photoresist. Optionally, the second mask layer 105 is removed using a photoresist remover.

[0084] After removing the second mask layer 105, the step also includes removing the repair metal layer 104 around the pad 106 to expose the bottom metal 103 covered by the repair metal layer 104, wherein the repair metal layer 104 constitutes a repair metal part 107 corresponding one-to-one to the bottom metal 103 and the pad 106, wherein the repair metal layer 104 can be removed by a dry etching process.

[0085] After removing the second mask layer 105 and part of the repair metal layer 104, a metal wire 108 is formed on the pad 106 and the repair metal portion 107. Optionally, the process for forming the metal wire 108 includes a wirebonding process, and the material thereof can be selected according to actual conditions. It can be seen from the above description that the process of the present invention can make the surface of the pad 106 flat, thereby increasing the difference in roughness between the surface of the pad 106 and the surface of the bottom metal 103 around the pad 106, making the two easier to identify and distinguish. For example, in the process of forming the metal wire 108, the wirebonding machine needs to automatically identify the pad 106 (Pad) when automatically bonding. If it cannot be identified, manual adjustment is required, which affects the efficiency. The solution of the present invention can provide a difference in roughness between the pad 106 and the bottom metal 103 around it, so that it can be identified during the preparation process of the metal wire 108, thereby facilitating accurate and effective preparation of the metal wire 108 on the pad 106, thereby improving the yield of metal wire preparation.

[0086] As an example, a seed layer (not shown in the figure) is also formed on the substrate 101, the first window 102a exposes the seed layer, the first mask layer 102 and the bottom metal 103 are both formed on the seed layer, wherein the seed layer is also removed after the second mask layer 105 and the first mask layer 102 are removed. In an optional example, the seed layer includes an adhesion layer and an upper metal layer sequentially formed on the substrate, wherein the adhesion layer includes a Ti layer, but is not limited thereto, optionally, considering the consistency of the materials, the material of the upper metal layer is the same as the material of the bottom metal 103 and the material of the repair metal layer 104, and in addition, it can also be beneficial to remove the repair metal layer 104 and the upper metal layer based on the same process, for example, by increasing the etching time to remove both together, wherein the repaired metal layer 104 and the upper metal layer in the seed layer can be removed by an etching process.

[0087] In addition, the present invention further provides a semiconductor structure for improving the identification of the bottom metal and the pad. The formation of the semiconductor structure is preferably based on the method for improving the identification of the bottom metal and the pad provided by the present invention. Of course, it can also be prepared by other methods. The relevant structure and description can refer to the above description, wherein the semiconductor structure includes:

[0088] Base 101;

[0089] A plurality of bottom metals 103 are spaced and distributed on the substrate 101;

[0090] A plurality of bonding pads 106 are formed on each of the bottom metals 103;

[0091] A plurality of repair metal parts 107 are formed between the bottom metal 103 and the pad 106 ;

[0092] The metal line 108 is formed on the bonding pad 106 .

[0093] As an example, the repair metal part 107 includes a metal layer based on a sputtering process, and the material of the repair metal part 107 is the same as that of the bottom metal; the thickness of the repair metal part 107 is between 1000 angstroms and 8000 angstroms.

[0094] In summary, the method and semiconductor structure of improving the identification of the bottom metal and the pad of the present invention, after removing the first mask layer, forms a repair metal layer on the bottom metal and the substrate around it, the repair metal layer has a higher surface flatness than the bottom metal, thereby improving the flatness of the surface of the pad formed subsequently, and can make the roughness difference between the surface of the pad and the surface of the bottom metal around the pad larger, making the two easier to identify and distinguish, thereby facilitating accurate and effective preparation of metal wires on the pad, and improving the yield of metal wire preparation. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0095] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for improving the identification of bottom metal and pad, characterized in that: The method comprises: providing a substrate; forming a first mask layer on the substrate, wherein the first mask layer includes a first window defining a bottom metal position; forming the bottom metal in the first window; removing the first mask layer; forming a repair metal layer on the bottom metal and the substrate around it, wherein the repair metal layer has a higher surface flatness than the bottom metal; forming a second mask layer on the repair metal layer, wherein the second mask layer comprises a second window defining a pad, and the second window is correspondingly located on the bottom metal and exposes the repair metal layer; forming a pad in the second window, wherein a planar size of the pad is smaller than a planar size of the bottom metal; and The second mask layer and the repair metal layer around the bonding pad are removed, and a metal wire is prepared on the bonding pad.

2. The method for improving the identification of bottom metal and pad according to claim 1, characterized in that: The pad includes a buffer barrier layer and a metal layer sequentially formed on the bottom metal surface in the second window.

3. The method for improving the identification of bottom metal and pad according to claim 2, characterized in that: The buffer barrier layer includes a Ni layer; the metal layer includes an Au layer; and the material of the bottom metal includes Cu.

4. The method for improving the identification of bottom metal and pad according to claim 2, characterized in that: The thickness of the buffer barrier layer is between 1.8 μm and 2.2 μm; the thickness of the metal layer is between 0.1 μm and 1 μm; and the thickness of the bottom metal is between 3 μm and 6 μm.

5. The method for improving the identification of bottom metal and pad according to claim 1, characterized in that: A seed layer is also formed on the substrate, the first window exposes the seed layer, the first mask layer and the bottom metal are both formed on the seed layer, wherein the seed layer is removed after the first mask layer is removed.

6. The method for improving the identification of bottom metal and pad according to claim 5, characterized in that: The seed layer includes an adhesion layer and an upper metal layer which are sequentially formed on the substrate, wherein a material of the upper metal layer is the same as a material of the bottom metal, and the adhesion layer includes a Ti layer.

7. The method for improving the identification of bottom metal and pad according to claim 1, characterized in that: The substrate includes a supporting layer, a peeling layer formed on the supporting layer, and a dielectric layer formed on the peeling layer, wherein the bottom metal is formed on the dielectric layer based on the first window.

8. The method for improving the identification of bottom metal and pad according to claim 1, characterized in that: The process of forming the metal wire includes a wire bonding process.

9. The method for improving the identification of bottom metal and pad according to any one of claims 1 to 8, characterized in that: The repair metal layer is formed by a sputtering process.

10. The method for improving the identification of bottom metal and pad according to claim 9, characterized in that: The material of the repair metal layer is the same as that of the bottom metal; the thickness of the repair metal layer is between 1000 angstroms and 8000 angstroms.

11. A semiconductor structure for improving the identification of bottom metal and pad, characterized in that: The semiconductor structure comprises: substrate; A plurality of bottom metals are spaced apart and distributed on the substrate; A plurality of welding pads are formed on each of the bottom metals, and the plane size of the welding pads is smaller than the plane size of the bottom metal; A plurality of repair metal parts are formed between the bottom metal and the pad, and the repair metal parts have a higher surface flatness than the bottom metal; A metal wire is formed on the bonding pad.

12. The semiconductor structure for improving the identification of bottom metal and pad according to claim 11, characterized in that: The repair metal part includes a metal layer based on a sputtering process, and the material of the repair metal part is the same as that of the bottom metal; the thickness of the repair metal part is between 1000 angstroms and 8000 angstroms.

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