Semiconductor device and method for manufacturing the same

Abstract

Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same. The semiconductor device includes: a gate electrode; a source / drain structure; a lower contact contacting the gate electrode or the source / drain structure; and an upper contact disposed in an opening formed in an interlayer dielectric layer and in direct contact with the lower contact. The upper contact directly contacts the interlayer dielectric layer without interposing a conductive barrier layer, and the upper contact includes ruthenium.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same. Background Art

[0002] As semiconductor device dimensions decrease, self-aligned contacts (SACs) have been widely used to manufacture, for example, source / drain contacts arranged closer to gate structures in field effect transistors (FETs). Source / drain contacts are generally required to have lower resistivity. Summary of the invention

[0003] According to one aspect of the present invention, a method for manufacturing a semiconductor device is provided, the method comprising: forming a source / drain structure above a substrate; forming a first interlayer dielectric layer including one or more first insulating layers above the source / drain structure; forming a first opening in the first interlayer dielectric layer to at least partially expose the source / drain structure; filling the first opening with a first conductive material to form a source / drain contact in contact with the source / drain structure; forming a second interlayer dielectric layer including a first layer and a second layer disposed on the first layer above the source / drain contact and the first interlayer dielectric layer; forming a second opening in the second interlayer dielectric layer to at least partially expose the source / drain contact; and filling the second opening with a second conductive material to form an upper contact in direct contact with the source / drain contact and in direct contact with the second interlayer dielectric layer without intervening a conductive barrier layer, wherein the second conductive material comprises ruthenium.

[0004] According to another aspect of the present invention, a method for manufacturing a semiconductor device is provided, the method comprising: forming a source / drain structure above a substrate; forming a first interlayer dielectric layer including one or more first insulating layers above the source / drain structure; forming a first opening in the first interlayer dielectric layer to at least partially expose the source / drain structure; filling the first opening with a first conductive material to form a source / drain contact in contact with the source / drain structure; forming a second interlayer dielectric layer including a first layer and a second layer disposed on the first layer above the source / drain contact and the first interlayer dielectric layer; forming a second opening in the second interlayer dielectric layer to at least partially expose the source / drain contact; partially recessing the source / drain contact to form a groove extending below the first layer; performing a cleaning operation on the groove and the first layer; and filling the second opening and the groove with ruthenium to form an upper contact that is in direct contact with the source / drain contact and in direct contact with the second interlayer dielectric layer without intervening a conductive barrier layer.

[0005] According to another aspect of the present invention, a semiconductor device is provided, comprising: a gate electrode; a source / drain structure; a lower contact contacting the gate electrode or the source / drain structure; and an upper contact disposed in an opening formed in an interlayer dielectric layer and in direct contact with the lower contact; wherein the upper contact is in direct contact with the interlayer dielectric layer without the insertion of a conductive barrier layer, and the upper contact comprises ruthenium. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustration purposes only. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A , Figure 1B , Figure 1C and Figure 1D Various views of a semiconductor device according to an embodiment of the present disclosure are shown.

[0008] Figure 2A A plan view (viewed from above) showing one of the various stages in a sequential manufacturing process of a semiconductor device according to an embodiment of the present disclosure. Figure 2B Shown along Figure 2A A cross-sectional view along line X1-X1. Figure 2C and Figure 2D This is an enlarged view of the gate structure. Figure 2E A perspective view is shown of one of the various stages of a sequential manufacturing process of a semiconductor device according to an embodiment of the present disclosure.

[0009] Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E Cross-sectional views illustrating various stages of a sequential manufacturing process of a semiconductor device according to an embodiment of the present disclosure are shown.

[0010] Figure 4A and Figure 4B Cross-sectional views illustrating various stages of a sequential manufacturing process of a semiconductor device according to an embodiment of the present disclosure are shown.

[0011] Figure 5A , Figure 5B and Figure 5C Cross-sectional views illustrating various stages of a sequential manufacturing process of a semiconductor device according to an embodiment of the present disclosure are shown.

[0012] Figure 6 Cross-sectional views illustrating various stages of a sequential manufacturing process of a semiconductor device according to an embodiment of the present disclosure are shown.

[0013] Fig. 7A and Figure 7B Cross-sectional views illustrating various stages of a sequential manufacturing process of a semiconductor device according to an embodiment of the present disclosure are shown.

[0014] Fig. 8A and Figure 8B Cross-sectional views illustrating various stages of a sequential manufacturing process of a semiconductor device according to an embodiment of the present disclosure are shown.

[0015] Fig. 9A and Fig. 9B Cross-sectional views illustrating various stages of a sequential manufacturing process of a semiconductor device according to an embodiment of the present disclosure are shown.

[0016] Fig.10 A cross-sectional view of a semiconductor device according to an embodiment of the present disclosure is shown.

[0017] Fig.11 A cross-sectional view of a semiconductor device according to an embodiment of the present disclosure is shown.

[0018] Fig. 12A and Fig. 12B A cross-sectional view of a semiconductor device according to an embodiment of the present disclosure is shown.

[0019] Fig.13 The deposition rate of Ru under various conditions is shown. DETAILED DESCRIPTION

[0020] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, the size of the element is not limited to the disclosed range or value, but may depend on the process conditions and / or the desired characteristics of the device. In addition, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component, so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. For simplicity and clarity, various components may be arbitrarily drawn in different proportions.

[0021] In addition, for ease of description, spacing relationship terms such as "below", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figure. In addition to the orientation shown in the figure, the spacing relationship terms are intended to include different orientations of the device in use or operation process. The device can be positioned in other ways (rotated 90 degrees or in other orientations), and the spacing relationship descriptors used in this article can be interpreted accordingly. In addition, the term "made of" can mean "including" or "consisting of". In the present disclosure, the phrase "one of A, B and C" means "A, B and / or C" (A, B, C, A and B, A and C, B and C or A, B and / or C), unless otherwise specified, it does not mean one element from A, one element from B and one element from C. The materials, configurations, dimensions, processes and / or operations described in relation to one embodiment may be adopted in other embodiments, and their detailed description may be omitted.

[0022] Figure 1A , Figure 1B , Figure 1C and Figure 1D Various views of a semiconductor device according to an embodiment of the present disclosure are shown. Figure 1A It is a floor plan. Figure 1B is the cross-section (Y-tangent line), Figure 1C is a cross-sectional view (X-tangent line 1), Figure 1D is a cross-sectional view (X-cut line 2). In some embodiments, Figures 1A to 1D The semiconductor device shown in FIG. 1 is a fin field effect transistor (Fin FET).

[0023] exist Figure 1A In the embodiment, three gate structures 10 extending in the Y direction are arranged above four fin structures 5 extending in the X direction. The portion between the gate structures 10 is the source / drain region 50 (see Figure 1B and Figure 1C ), and the source / drain contact 70 is disposed above the source / drain region 50. In some embodiments, the source / drain region 50 includes one or more epitaxially formed semiconductor layers (epitaxial layers). In some embodiments, the source / drain contact 70 is a contact strip extending beyond the source / drain region 50 in the Y direction. Therefore, the width of the source / drain epitaxial layer (source / drain region) 50 is smaller than the width of the source / drain contact 70 in the Y direction. Figure 1A and Figure 1BAs shown, in some embodiments, the width of the source / drain contact 70 is greater than the width of the upper contact 100 in the Y direction. In some embodiments, one or more gate contacts 102 are disposed on one or more gate electrodes of the gate structure 10. In addition, in some embodiments, the upper contact 100 is disposed above the source / drain contact 70.

[0024] like Figures 1B to 1D As shown, source / drain regions 50 are formed in the recesses formed in the fin structure 5. The gate structure 10 includes an interfacial layer 11 made of chemically formed silicon oxide, a gate dielectric layer 12 formed over the fin structure 5, a metal gate electrode 15, and a gate sidewall spacer 30. The gate structure 10 is embedded in a first interlayer dielectric (ILD) layer 45. The first ILD layer 45 includes one or more dielectric layers. In some embodiments, a first etch stop layer 60 is disposed over the first ILD layer 45, and a second ILD layer 65 is formed over the first etch stop layer 60. In addition, a second etch stop layer 75 is disposed over the second ILD layer 65, and a third ILD layer 80 is formed over the second etch stop layer 75.

[0025] The first to third ILD layers 45, 65, 80 include one or more layers of insulating materials, for example, silicon oxide-based materials such as silicon dioxide (SiO2), SiOC and SiOCN. In some embodiments, low-k materials or organic materials are used for the ILD layers. The first and second etch stop layers 60, 75 are made of a material different from the ILD layer and include one or more layers of insulating materials, for example, silicon nitride-based materials such as silicon nitride and SiON.

[0026] In some embodiments, the third ILD layer 80 does not include Group IV elements except Si and C. In other embodiments, the third ILD layer 80 includes Ge and / or Sn to introduce compressive stress in the third ILD layer 80. In some embodiments, the concentration of Ge and / or Sn is in a range of about 0.01 atomic % to 1 atomic %.

[0027] Source / drain contacts 70 are formed in contact openings (holes) through the first and second ILD layers 45, 65 and the first and second etch stop layers 60, 75. In some embodiments, a first contact liner 68 is formed on the inner surface of the contact opening. In some embodiments, the first contact liner 68 includes one or more conductive material layers such as Ti, TiN, Ta, and TaN. In some embodiments, a TiN layer is used as the first contact liner 68.

[0028] The source / drain contact 70 includes one or more layers of conductive materials, such as W, Co, Ni, Mo, and alloys thereof. In some embodiments, the source / drain contact 70 is made of Co.

[0029] The upper contact 100 is formed in a contact opening (hole) through the third ILD layer 80 and the second etch stop layer 75, and the upper contact 102 (gate contact) is formed in a contact opening through the third ILD layer 80, the second etch stop layer 75, the second ILD layer 65, and the first etch stop layer 60. The upper contacts 100, 102 include ruthenium (Ru) or a Ru alloy.

[0030] In some embodiments, the purity of ruthenium in the upper contact 100, 102 is equal to or greater than about 99.9% and less than 100%. In some embodiments, the upper contact 100, 102 includes impurities other than ruthenium. In some embodiments, the amount of impurities is 0.00001 atomic % to 0.1 atomic %. In some embodiments, the impurities include one or more selected from alkali metals and alkaline earth metals. In certain embodiments, the impurities are one or more of Ca, K, and Na. In other embodiments, the impurities include carbon.

[0031] like Figure 1B and Figure 1C As shown, in some embodiments, the upper contact 100 is in direct contact with the third ILD layer 80 without interposing any conductive barrier layer (such as Ti, TiN, Ta and / or TaN layer). In some embodiments, the upper contact 100 is in direct contact with the second etch stop layer 75 without interposing any conductive barrier layer. Similarly, the upper contact 102 is in direct contact with the third ILD layer 80, the second etch stop layer 75, the second ILD layer 65 and the first etch stop layer 60 without interposing any conductive barrier layer, such as Figure 1D shown.

[0032] Furthermore, if Figure 1B and Figure 1C As shown, in some embodiments, a portion of the upper contact 100 penetrates into the source / drain contact 70. In addition, in some embodiments, a portion of the upper contact 100 is disposed below the second etch stop layer 75 and contacts the bottom surface of the second etch stop layer 75. In some embodiments, the portion of the upper contact 100 that penetrates into the source / drain contact 70 contacts the first contact liner 68, as shown in FIG. Figure 1C As shown. Figure 1B and Figure 1C As shown, in some embodiments, the upper contact 100 has a rivet shape with a convex rounded head. In other embodiments, the head of the rivet shape is a triangle or trapezoid with or without rounded corners.

[0033] In some embodiments, the bottom corner of the second etch stop layer 75 has a rounded corner. In some embodiments, the upper corner of the second etch stop layer 75 has a rounded corner, and the radius of curvature of the rounded corner (greater than 0 nm) is smaller than the radius of curvature of the bottom corner. In other embodiments, the upper corner of the second etch stop layer 75 is not rounded.

[0034] FIG. 2A to FIG. 2E The embodiment according to the present disclosure is shown Figures 1A to 1D The structures shown correspond to the various stages of the sequential manufacturing process of the semiconductor device. It should be understood that FIG. 2A to FIG. 2E Additional operations are provided before, during, and after the processes shown, and for other embodiments of the method, some of the operations described below may be replaced or eliminated. The order of operations / processes may be interchanged.

[0035] Figure 2A and Figure 2B One of the stages of a sequential manufacturing process of a semiconductor device according to an embodiment of the present disclosure is shown. Figure 2A A plan view (top view) is shown, and Figure 2B A top view is shown. Figure 2B Shown along Figure 2A A cross-sectional view along line X1-X1.

[0036] Figure 2A and Figure 2B FIG. 2 shows the structure of a semiconductor device after forming a metal gate structure 10. The metal gate structure 10 includes a metal gate electrode 15 and a gate dielectric layer 12. Figure 2A and Figure 2B , a metal gate structure 10 is formed over a channel region (e.g., a portion of a fin structure) of a fin structure 5, and a capping insulating layer 20 is disposed over the metal gate structure 10. In some embodiments, the thickness of the metal gate structure 10 is in a range of 15 nm to 50 nm. In some embodiments, the thickness of the capping insulating layer 20 is in a range of about 10 nm to about 30 nm, and in other embodiments in a range of about 15 nm to about 20 nm. A sidewall spacer 30 is provided on the sidewalls of the metal gate structure 10 and the capping insulating layer 20. In some embodiments, the film thickness of the sidewall spacer 30 at the bottom of the sidewall spacer is in a range of about 3 nm to about 15 nm, and in other embodiments, in a range of about 4 nm to about 8 nm. The combination of the metal gate structure 10, the capping insulating layer 20, and the sidewall spacer 30 may be collectively referred to as a gate structure. In addition, a source / drain region 50 is formed adjacent to the gate structure, and the space between the gate structures is filled with an interlayer dielectric (ILD) layer 40.

[0037] Figure 2Cis an enlarged view of the gate structure. The metal gate electrode 15 includes one or more layers of metal material 16, such as Al, Cu, W, Ti, Ta, TiN, TiAl, TiAlC, TiAlN, TaN, NiSi, CoSi or other conductive materials. The gate dielectric layer 12 disposed between the channel region of the fin structure 5 and the metal gate includes one or more layers of metal oxide, such as a high-k metal oxide. Examples of metal oxides for high-k dielectrics include oxides of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu and / or mixtures thereof.

[0038] In some embodiments, one or more work function adjustment layers 14 are inserted between the gate dielectric layer 12 and the metal material 16. The work function adjustment layer 14 is made of a single layer of a conductive material such as TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi or TiAlC, or a multilayer of two or more of these materials. For n-channel FETs, one or more of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi and TaSi are used as the work function adjustment layer, and for p-channel FETs, one or more of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC and Co are used as the work function adjustment layer.

[0039] The capping insulating layer 20 includes one or more layers of insulating materials, such as silicon nitride-based materials including SiN, SiCN, and SiOCN. The gate sidewall spacer 30 is made of a material different from the capping insulating layer 20 and includes one or more layers of insulating materials, such as silicon nitride-based materials including SiN, SiON, SiCN, and SiOCN. The ILD layer 40 includes one or more layers of insulating materials, such as silicon oxide-based materials including silicon dioxide (SiO2) and SiON.

[0040] In some embodiments, Figure 2D As shown, no gate cap insulating layer is formed.

[0041] The materials of the sidewall spacer 30, the capping insulating layer 20, and the ILD layer 40 are different from each other so that each of these layers can be selectively etched. In one embodiment, the gate sidewall spacer 30 is made of SiOCN, SiCN, or SiON, the capping insulating layer 20 is made of SiN, and the ILD 40 layer is made of SiO2.

[0042] In this embodiment, a fin field effect transistor (FinFET) manufactured by a gate replacement process is used.

[0043] Figure 2E An exemplary perspective view of a FinFET structure is shown.

[0044] First, a fin structure 310 is fabricated on a substrate 300. The fin structure includes a bottom region and an upper region as a channel region 315. The substrate is, for example, a p-type silicon substrate having a thickness of about 1×10 15 cm -3 To about 1×10 18 cm -3 In other embodiments, the substrate is an n-type silicon substrate having an impurity concentration ranging from about 1×10 15 cm -3 About 1×10 18 cm -3 Alternatively, the substrate may include: another elemental semiconductor, such as germanium; a compound semiconductor, including a Group IV-IV semiconductor, such as SiC and SiGe; a Group III-V compound semiconductor, such as GaAs, GaP, GaN, InP, InAs, InSb, GaAsP, AlGaN, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or a combination thereof. In one embodiment, the substrate is a silicon layer of a SOI (silicon on insulator) substrate.

[0045] After forming the fin structure 310, an isolation insulating layer 320 is formed over the fin structure 310. The isolation insulating layer 320 includes one or more layers of insulating materials, such as silicon oxide, silicon oxynitride, or silicon nitride formed by LPCVD (low pressure chemical vapor deposition), plasma CVD, or flowable CVD. The isolation insulating layer may be formed of one or more layers of spin-on glass (SOG), SiO, SiON, SiOCN, and / or fluorine-doped silicate glass (FSG).

[0046] After forming the isolation insulating layer 320 over the fin structure, a planarization operation is performed to remove a portion of the isolation insulating layer 320. The planarization operation may include a chemical mechanical polishing (CMP) and / or an etch-back process. Then, the isolation insulating layer 320 is further removed (recessed) to expose the upper region of the fin structure.

[0047] A dummy gate structure is formed over the exposed fin structure. The dummy gate structure includes a dummy gate electrode layer and a dummy gate dielectric layer made of polysilicon. A gate sidewall spacer 350 including one or more layers of insulating material is also formed on the sidewall of the dummy gate electrode layer. After the dummy gate structure is formed, the fin structure 310 not covered by the dummy gate structure is recessed below the upper surface of the isolation insulating layer 320. Then, a source / drain region 360 is formed over the recessed fin structure by using an epitaxial growth method. The source / drain region may include a strained material to apply stress to the channel region 315.

[0048] Then, an interlayer dielectric (ILD) layer 370 is formed over the dummy gate structure and the source / drain regions. After the planarization operation, the dummy gate structure is removed to form a gate space. Then, a metal gate structure 330 including a metal gate electrode and a gate dielectric layer such as a high-k dielectric layer is formed in the gate space. In addition, a capping insulating layer 340 is formed over the metal gate structure 330 to obtain Figure 2E The Fin FET structure shown in Figure 1 is a fin FET structure. Figure 2E In FIG. 3 , portions of the metal gate structure 330 , the capping isolation layer 340 , the gate sidewall spacer 350 , and the ILD layer 370 are cut away to show the underlying structures.

[0049] Figure 2E The fin structure 310, the metal gate structure 330, the capping isolation layer 340, the gate sidewall spacer 350, the source / drain 360 and the ILD layer 370 substantially correspond to Figures 1A to 1D The fin structure 5, the metal gate structure 10, the capping insulating layer 20, the gate sidewall spacer 30, the source / drain region 50 and the interlayer dielectric (ILD) layer 40 are formed. In some embodiments, one or more ILD layers are additionally formed over the ILD layer 40 to form a first ILD layer 45.

[0050] Figure 3A-3E to Figure 9A-9B The embodiment according to the present disclosure is shown Figures 1A to 1D The structures shown correspond to the various stages of the sequential manufacturing process of the semiconductor device. It should be understood that FIG. 3A to FIG. 9B Additional operations are provided before, during, and after the processes shown. FIG. 3A to FIG. 9B In other embodiments of the method, some operations described below may be replaced or eliminated. The order of processes / procedures may be interchanged. The materials, configurations, dimensions, processes and / or operations described in the previous embodiments may be adopted in the following embodiments, and their detailed descriptions may be omitted. FIG. 3A to FIG. 9B , four fin structures 5 are shown, but the number of the fin structures 5 is not limited to four and may be one, two, three, or five or more.

[0051] After forming the metal gate structure, a first insulating layer is formed on the first ILD layer 45 (or 40) as a first etch stop layer 60, and a second insulating layer is formed on the first etch stop layer 60 as a second ILD layer 65. Figure 3A The etch stop layer 60 and the second ILD layer 65 are formed by a suitable film forming method such as CVD, physical vapor deposition (PVD) or atomic layer deposition (ALD).

[0052] By using one or more photolithography and etching operations, first contact holes (openings) 67 for lower contacts (source / drain contacts) 70 are formed in the first and second ILD layers 45, 65, as shown in FIG. Figure 3B shown.

[0053] Then, a first contact liner 68 is conformally formed in the first contact hole 67 and on the upper surface of the second ILD layer 65, and a conductive material is formed on the first contact liner 68. The contact liner 68 and the conductive material layer are formed by a suitable film forming method such as CVD, PVD, ALD, or plating. Figure 3C As shown, a planarization operation such as an etch-back operation or a chemical mechanical polishing (CMP) operation is performed to form source / drain contacts 70 .

[0054] Then, if FIG. 3D to FIG. 3E As shown, a third insulating layer as a second etch stop layer 75 and a fourth insulating layer as a third ILD layer 80 are formed. Figure 3D 1 shows a cross-sectional view of the source / drain contact 70 cut along the Y direction, Figure 3E FIG. 1 shows a cross-sectional view of the gate electrode 15 cut along the Y direction. FIG. 3A to FIG. 9B In the figure, the gate dielectric layer 12 is omitted for simplicity.

[0055] like Figure 4A and Figure 4B As shown, by using one or more photolithography and etching operations, a second contact hole (opening) 82 for the upper contact 100 is formed in the third ILD layer 80 and the second etch stop layer 75, and a third contact hole (opening) 84 for the upper contact (gate contact) 102 is formed in the third ILD layer 80, the second etch stop layer 75, and the second ILD layer 65. In some embodiments, the thickness of the second etch stop layer 75 is in the range of about 5 nm to about 20 nm, and in other embodiments, in the range of about 10 nm to about 15 nm. In some embodiments, as Figure 4B As shown, by this etching, at least a portion of the upper surface of the metal gate electrode 15 is exposed at the bottom of the third contact hole 84. In some embodiments, the contact holes 82 and 84 are formed in the same etching operation using the same mask pattern, while in other embodiments, the contact holes 82 and 84 are formed by different etching operations using different mask patterns.

[0056] In some embodiments, Figure 5A As shown, the exposed portion of the source / drain contact 70 is partially etched (recessed) to form a groove 85. In some embodiments, the exposed upper portion of the source / drain contact 70 is etched vertically and laterally (horizontally) to form the groove 85.

[0057] In some embodiments, etching is one or more of isotropic etching operations. In some embodiments, etching is wet etching using an acid. In some embodiments, the acid is an organic acid. In certain embodiments, when the source / drain contact 70 is made of Co, the organic acid is 4-methyl-2-(phenylamino)-1,3-thiazole-5-carboxylic acid. In some embodiments, after the acid etching, a wet cleaning operation using isopropanol is performed. In other embodiments, etching is chemical dry etching using a gas containing, for example, HCl. In some embodiments, the wet etchant includes benzotriazole.

[0058] In some embodiments, the bottom of the groove 85 has an arc shape, such as Figure 5A and Figure 5C shown. Figure 5C yes Figure 5A In other embodiments, the groove has a triangular or trapezoidal shape. Figure 5C As shown, the recess 85 horizontally penetrates below the second etch stop layer 75 .

[0059] In some embodiments, during the recess etching at the second contact hole 82, the upper surface of the metal gate electrode 15 exposed at the bottom of the third contact hole 84 is covered by the first etch stop layer 60 and is therefore not etched. Figure 5B As shown, even if the first etch stop layer does not cover the upper surface of the metal gate electrode 15 exposed at the bottom of the third contact hole 84, the metal gate electrode 15 is not substantially etched due to the etching selectivity. In other words, the etching etchant selectively etches the material (e.g., Co) of the source / drain contact 70 compared to the material (e.g., W) of the gate electrode 10.

[0060] Next, if Figure 6 As shown, a pre-deposition cleaning operation is performed on the second contact hole 82 and the recessed source / drain contacts 70 .

[0061] In some embodiments, the pre-deposition cleaning operation includes a plasma treatment. In some embodiments, the plasma treatment includes a hydrogen plasma and / or an argon plasma. In certain embodiments, the plasma treatment includes a hydrogen plasma treatment followed by an argon plasma treatment. In some embodiments, the duration of the hydrogen plasma treatment is longer than the duration of the argon plasma treatment. In some embodiments, depending on the design and / or process requirements / conditions, the duration of the hydrogen plasma treatment is in the range of about 60 seconds to about 300 seconds, and in other embodiments, in the range of about 90 seconds to about 250 seconds. In some embodiments, depending on the design and / or process requirements / conditions, the duration of the argon plasma treatment is in the range of about 1 second to about 10 seconds, and in other embodiments, in the range of about 2 seconds to about 8 seconds.

[0062] Through the pre-deposition cleaning operation, the second etch stop layer 75 is etched. Figure 6 As shown, the bottom corner of the second etch stop layer 75 has a rounded corner. In some embodiments, depending on the design and / or process requirements / conditions, the radius of curvature of the rounded corner is in the range of about 0.2nm to 0.4nm, and in other embodiments, in the range of about 0.25nm to about 0.35nm.

[0063] In some embodiments, depending on design and / or process requirements / conditions, the ratio (D2 / D1) of the width D2 of the groove 85 to the narrowest width D1 (diameter) of the second contact hole 82 is in the range of about 1.2 to about 2.5, and in other embodiments, in the range of about 1.5 to about 2.0. In some embodiments, depending on design and / or process requirements / conditions, the depth D3 of the groove 85 in the vertical direction is in the range of about 2 nm to about 20 nm, and in other embodiments, in the range of about 5 nm to about 12 nm.

[0064] After the pre-deposition cleaning operation, a conductive material layer 99 is formed in the second contact hole 82 and the third contact hole 84 and on the third ILD layer 80. Fig. 7A and Figure 7B In some embodiments, the conductive material layer 99 is made of Ru. Fig. 7A and Figure 7B As shown, Ru layer 99 is formed without any conductive barrier or liner layer. In some embodiments, Ru layer 99 is formed without breaking vacuum (without exposure to air or any oxidizing atmosphere) after a pre-deposition cleaning operation.

[0065] In some embodiments, the Ru layer is formed by a thermal CVD method (without plasma) at a temperature range of about 100° C. to about 250° C. at a pressure of about 0.5 mTorr to about 1000 mTorr, depending on the design and / or process requirements / conditions. In some embodiments, the source gas of ruthenium includes triruthenium dodecacarbon (Ru3(CO) 12 ) and one or more of an organic Ru compound such as Ru[C5H5(CO)2]2 or cyclopentadienyl-propylcyclopentadienylruthenium(II) (RuCp(i-PrCp)). In some embodiments, the Ru CVD process is a selective CVD process for growth from the Co surface of the source / drain contact 70.

[0066] Then, if Fig. 8A and Figure 8B As shown, a planarization operation such as an etch-back operation or a CMP operation is performed to form the upper contact 100 and the gate contact 102. Fig. 9A and Fig. 9B As shown, an additional upper ILD layer 90 is formed over the third ILD layer 80, and via contacts 110 and 112 are formed on the upper contact 100 and the gate contact 102, respectively. In some embodiments, the upper contact comprises one or more of TiN, Ti, Ta, TaN, W, Co, Ni, Mo, Cu, and Al, and alloys thereof. Fig. 9A and Fig. 9B As shown, the upper contact 100 above the lower contact (source / drain contact) 70 has a rivet shape, while the gate contact 102 has a substantially flat bottom above the gate electrode 10 (without a recess in the gate electrode).

[0067] In some embodiments, no dopant implantation operations (eg, Ge doping) are performed on any ILD layer.

[0068] It should be understood that Fig. 9A and Fig. 9B The device shown in is subjected to further CMOS processing to form various components, such as interconnect metal layers, dielectric layers, passivation layers, and the like.

[0069] Fig.10 and Fig.11 A cross-sectional view of an upper contact 100 manufactured according to the above-described embodiment is shown.

[0070] like Fig.10 As shown, the upper contact 100 has a plug portion 105 above the source / drain contact 70 and a rivet portion 107 embedded in the source / drain contact 70. Fig.10 and Fig.11 As shown, the interface between the rivet portion 107 of the upper contact 100 and the source / drain contact 70 is clearly observed. This means that there is substantially no mixing of ruthenium (layer 107) and cobalt (layer 70). In some embodiments, there is a mixing region, and the width of the mixing region is greater than 0.2 nm and less than 0.5 nm. As described above, a pre-deposition cleaning operation is performed before ruthenium is deposited in the recess 85. The pre-deposition cleaning operation removes oxides formed on the surface of the Co layer of the source / drain contact 70 and removes or terminates surface dangling bonds of the Co layer, which is believed to prevent mixing of Ru and Co.

[0071] In some embodiments, the plug portion 105 has a tapered shape having a taper angle θ1 in the range of about 1.0 degrees to about 4.0 degrees relative to the normal direction of the substrate, and in other embodiments, the taper angle is in the range of about 1.4 degrees to about 3.1 degrees. The taper angle θ1 corresponds to the taper angle of the sidewall of the second contact hole 82. When the taper angle θ1 is below these ranges, the ruthenium layer may not be completely filled in the second contact hole 82, resulting in a void or a slit. When the taper angle θ1 exceeds these ranges, the bottom area of ​​the plug portion becomes too small or the top area of ​​the plug portion becomes too large, which will result in undesirable high resistance and / or current leakage.

[0072] In some embodiments, Fig.10 As shown, the bottom corner of the second etch stop layer 75 has a rounded corner, and the Ru contact 100 is conformally formed along the rounded corner. In some embodiments, the radius of curvature R1 of the rounded corner of the bottom edge of the second etch stop layer 75 is in the range of about 0.25 nm to about 0.35 nm, and in other embodiments, in the range of about 0.28 nm to about 0.32 nm. The rounded corners within these ranges reduce the shear stress in the Ru layer.

[0073] In some embodiments, the lateral ends of the rivet portion 107 have the following configurations. In some embodiments, an angle θ2 in the source / drain contact 70 between the interface of the rivet portion 107 and the source / drain contact 70 and the bottom surface of the second etch stop layer 75 is in a range of about 110 degrees to about 130 degrees, and in other embodiments, in a range of about 112 degrees to about 128 degrees. An angle θ3 in the rivet portion 107 between the interface of the rivet portion 107 and the source / drain contact 70 and the bottom surface of the second etch stop layer 75 is (180°-θ2).

[0074] In some embodiments, the upper processed region 120 is formed in the Co source / drain contact 70 below the rivet portion 107, such as Fig.10 and Fig.11 The upper processed portion 120 is a portion of the Co layer formed by the pre-deposition process, and has a disordered structure of Co atoms compared to the bulk of the source / drain contact 70 .

[0075] In some embodiments, the angle θ4 in the source / drain contact 70 between the rivet portion 107 and the upper processing portion 120 is in a range of about 130 degrees to about 150 degrees, and in other embodiments, in a range of about 132 degrees to about 146 degrees. In some embodiments, the angle θ5 in the rivet portion 107 between the rivet portion 107 and the upper processing portion 120 is in a range of about 30 degrees to about 40 degrees, and in other embodiments, in a range of about 36 degrees to about 38 degrees.

[0076] When the angles θ2 - θ5 are within these ranges, the shear stress in the Ru layer can be reduced, and the Co corrosion under the rivet portion 107 can be suppressed.

[0077] Reference Fig.11 In some embodiments, the width (diameter) D11 at the bottom of the plug portion 105 (at the level of the interface between the second etch stop layer 75 and the source / drain contact 70) is in the range of about 5 nm to about 20 nm, and depending on the design and / or process requirements / conditions, in the range of about 8 nm to about 20 nm. In some embodiments, the maximum lateral width (diameter) D12 of the rivet portion 107 at the level of the interface between the second etch stop layer 75 and the source / drain contact 70 is in the range of about 10 nm to about 30 nm, and depending on the design and / or process requirements, in the range of about 13 nm to about 23 nm. In some embodiments, the ratio D12 / D11 is in the range of about 1.2 to about 2.5, and in other embodiments, in the range of about 1.5 to about 2.0, depending on the design and / or process requirements / conditions. In some embodiments, depending on design and / or process requirements / conditions, the depth D13 of the rivet portion 107 starting from the interface between the second etch stop layer 75 and the source / drain contact 70 in the vertical direction is in the range of about 2 nm to about 20 nm, and in other embodiments, in the range of about 5 nm to about 12 nm.

[0078] also, Fig.11 The vertical line Z1 shown corresponds to the minimum width of the plug portion 105 and contacts the sidewall of the second etch stop layer 75. Depending on the design and / or process requirements / conditions, in the vertical direction, the depth D14 of the rivet portion at the point where the line Z1 intersects the bottom of the rivet portion is in the range of about 7 nm to about 10 nm, and in other embodiments, in the range of about 8 nm to about 9 nm. Depending on the design and / or process requirements / conditions, the depth D15 of the over-processed region 120 from the interface between the second etch stop layer 75 and the source / drain contact 70 is in the range of about 2.5 nm to about 20 nm in the vertical direction, and in other embodiments, in the range of about 4 nm to about 16 nm.

[0079] When the above-mentioned dimensions are within these ranges, the shear stress in the Ru layer can be reduced, and the Co corrosion under the rivet portion 107 can be suppressed.

[0080] Fig. 12A and Fig. 12B A cross-sectional view of a pre-deposition cleaning operation is shown. Fig.13 The effect of the pre-deposition cleaning operation on the deposition rate of Ru under various conditions is shown.

[0081] exist Fig. 12A In the embodiment of the present invention, the pre-deposition cleaning operation includes a hydrogen plasma treatment without an argon plasma treatment, and Fig. 12B In the present invention, the pre-deposition cleaning operation includes a hydrogen plasma treatment followed by an argon plasma treatment. Fig. 12A As shown, the bottom corner of the second etch stop layer 75 does not have a clear rounded corner, and when the bottom corner has a clear rounded corner, the radius of curvature is less than about 0.1 nm. In some embodiments, a slight mixing of Ru and Co is observed. Fig. 12B As shown, when the argon plasma treatment is additionally applied, the bottom corner of the second etch stop layer 75 has a clear rounded corner as described above. In addition, substantially no mixing of Ru and Co is observed.

[0082] Fig.13 The deposition rate of Ru under various conditions is shown, and the effect of the pre-deposition cleaning operation is also shown. The line "Ru on Ox(H2)" represents the deposition thickness of Ru on the silicon oxide surface that has undergone a hydrogen pre-deposition cleaning operation, the line "Ru on Co(H2+Ar)" represents the deposition thickness of Ru on the cobalt surface that has undergone a hydrogen and argon pre-deposition cleaning, the line "Ru on Co(H2)" represents the deposition thickness of Ru on the Co surface that has undergone a hydrogen pre-deposition cleaning, and the line "Ru on Co (without pre-deposition cleaning)" represents the deposition thickness of Ru on the Co surface that has not undergone a pre-deposition cleaning. Fig.13 As shown, since the deposition rate on the silicon oxide surface is much smaller than that on the Co surface, Ru can be selectively formed on the Co surface (i.e., the source / drain contact 70). In addition, the pre-deposition cleaning operation can increase the deposition rate on the Co surface. In particular, when the pre-deposition cleaning operation includes hydrogen plasma treatment followed by argon plasma treatment, the deposition rate is the highest, which means that the selectivity between the Co surface and the silicon oxide surface is the highest.

[0083] In the foregoing embodiments, Ru contacts are formed on Co source / drain contacts, and no conductive contact liner or barrier layer is interposed between the Ru contacts and the interlayer dielectric layer. Ru contacts have multiple advantages over W contacts. When W is used as an upper contact, cracking of the W layer and / or corrosion of the Co layer are common problems, which require more stringent process control to mitigate these problems. In contrast, the Ru contacts in conjunction with the pre-deposition cleaning operation of the present embodiment are substantially free of cracking due to shear stress and Co corrosion.

[0084] The various embodiments or examples described herein provide several advantages over the prior art. It will be understood that not all advantages must be discussed herein, specific advantages are not required for all embodiments or examples, and other embodiments or examples may provide different advantages.

[0085] According to one aspect of the present disclosure, in a method for manufacturing a semiconductor device, a source / drain structure is formed above a substrate, a first interlayer dielectric layer including one or more first insulating layers is formed above the source / drain structure, a first opening is formed in the first interlayer dielectric layer to at least partially expose the source / drain structure, the first opening is filled with a first conductive material to form a source / drain contact in contact with the source / drain structure, a second interlayer dielectric layer including a first layer and a second layer disposed on the first layer is formed above the source / drain contact and the first interlayer dielectric layer, a second opening is formed in the second interlayer dielectric layer to at least partially expose the source / drain contact, and the second opening is filled with a second conductive material to form an upper contact that is in direct contact with the source / drain contact and in direct contact with the second interlayer dielectric layer without intervening a conductive barrier layer. In one or more of the foregoing and following embodiments, the second conductive material includes ruthenium. In one or more of the foregoing and following embodiments, the upper contact includes impurities other than ruthenium. In one or more of the foregoing and following embodiments, the amount of impurity is in the range of 0.00001 atomic % to 0.1 atomic %. In one or more of the foregoing and following embodiments, the impurity is one or more selected from the group consisting of alkali metals and alkaline earth metals. In one or more of the foregoing and following embodiments, the impurity is carbon. In one or more of the foregoing and following embodiments, the first conductive material is Co. In one or more of the foregoing and following embodiments, the first layer is made of a silicon nitride-based material and the second layer is made of a silicon oxide-based material. In one or more of the foregoing and following embodiments, the portion of the source / drain contact below the upper contact has a disordered structure of Co atoms.

[0086] According to another aspect of the present disclosure, in a method for manufacturing a semiconductor device, a source / drain structure is formed over a substrate, a first interlayer dielectric layer including one or more first insulating layers is formed over the source / drain structure, a first opening is formed in the first interlayer dielectric layer to at least partially expose the source / drain structure, the first opening is filled with a first conductive material to form a source / drain contact in contact with the source / drain structure, a second interlayer dielectric layer including a first layer and a second layer disposed on the first layer is formed over the source / drain contact and the first interlayer dielectric layer, a second opening is formed in the second interlayer dielectric layer to at least partially expose the source / drain contact, the source / drain contact is partially recessed to form a groove extending below the first layer, a cleaning operation is performed on the groove and the first layer, and the second opening and the groove are filled with ruthenium to form an upper contact that is in direct contact with the source / drain contact and with the second interlayer dielectric layer without the interposition of a conductive barrier layer. In one or more of the foregoing and following embodiments, the recessing includes wet etching. In one or more of the foregoing and following embodiments, the etchant of the wet etching includes an organic acid. In one or more of the foregoing and following embodiments, after the recessing, a plasma treatment is performed on the groove and the first layer. In one or more of the foregoing and following embodiments, the plasma treatment includes a first plasma treatment using hydrogen plasma and a second plasma treatment using argon plasma after the first plasma treatment. In one or more of the foregoing and following embodiments, after the plasma treatment, the bottom corner of the first layer constituting the second opening has a rounded corner. In one or more of the foregoing and following embodiments, the first layer is made of a silicon nitride-based material, and the second layer is made of a silicon oxide-based material. In one or more of the foregoing and following embodiments, the purity of the ruthenium in the upper contact is equal to or greater than 99.9% and less than 100%. In one or more of the foregoing and following embodiments, the ruthenium of the upper contact is formed by thermal CVD at a temperature in the range of 100°C to 250°C.

[0087] According to another aspect of the present disclosure, in a method of manufacturing a semiconductor device, a source / drain structure is formed over a substrate, a gate electrode is formed adjacent to the source / drain structure, a first interlayer dielectric (ILD) layer including one or more first insulating layers is formed over the first source / drain structure and the gate electrode, a first opening is formed in the first ILD layer to at least partially expose the source / drain structure, the first opening is filled with a first conductive material to form a first lower contact in contact with the first source / drain structure, a second ILD layer including a first layer and a second layer disposed on the first layer is formed over the first lower contact and the first ILD layer, a second opening is formed to at least partially expose the first lower contact and a third opening to at least partially expose the gate electrode, and the second opening and the third opening are filled with a second conductive material to form a first upper contact in direct contact with the first lower contact and in direct contact with the second ILD layer, and a second upper contact in direct contact with the gate electrode and in direct contact with the second ILD layer and at least one insulating layer of the first ILD layer. In one or more of the foregoing and following embodiments, the second conductive material comprises ruthenium. In one or more of the foregoing and following embodiments, in forming the second opening and the third opening, the second ILD layer is etched to at least partially expose the first lower contact and the second ILD layer and a portion of the first ILD on the gate electrode, wherein one of the first ILD layers remains on the gate electrode, a portion of the first lower contact is etched to form a recess, and one of the first ILD layers remaining on the gate electrode is etched to at least partially expose the gate electrode, and plasma treatment is performed on the recess and the first layer.

[0088] According to one aspect of the present disclosure, a semiconductor device includes: a gate electrode; a source / drain structure; a lower contact, contacting the gate electrode or the source / drain structure; and an upper contact, disposed in an opening formed in an interlayer dielectric layer and in direct contact with the lower contact. The upper contact is in direct contact with the interlayer dielectric layer without interposing a conductive barrier layer, and the upper contact includes ruthenium. In one or more of the foregoing and following embodiments, the upper contact includes impurities other than ruthenium. In one or more of the foregoing and following embodiments, the amount of impurities is in the range of 0.00001 atomic % to 0.1 atomic %. In one or more of the foregoing and following embodiments, the impurity is one or more selected from the group consisting of alkali metals and alkaline earth metals. In one or more of the foregoing and following embodiments, the impurity is carbon. In one or more of the foregoing and following embodiments, the lower contact contacts the source / drain structure, is disposed in an opening formed in one or more insulating material layers, and includes Co. In one or more of the foregoing and following embodiments, the lower contact comprises a conductive liner disposed between the Co layer and one or more insulating material layers. In one or more of the foregoing and following embodiments, the conductive liner is made of one or more of Ti, TiN, Ta, and TaN.

[0089] According to another aspect of the present disclosure, a semiconductor device includes: a gate electrode; a source / drain structure; a lower contact contacting the source / drain structure and disposed in a first opening formed in a first dielectric layer including an insulating layer; at least one insulating material, and an upper contact, the upper contact being disposed in a second opening formed in a second dielectric layer and in direct contact with the lower contact. The upper contact is in direct contact with the ILD layer without interposing a conductive barrier layer, and includes ruthenium, the second dielectric layer includes a first layer and a second layer disposed on the first layer, and a portion of the upper contact penetrates into the insulating layer. The lower contact is disposed below the first layer of the second dielectric layer and in contact with the bottom surface of the first layer. In one or more of the foregoing and following embodiments, the first layer is made of silicon nitride or silicon oxynitride. In one or more of the foregoing and following embodiments, the upper contact has a rivet shape. In one or more of the foregoing and following embodiments, the bottom corner of the first layer constituting the second opening has a rounded corner. In one or more of the foregoing and following embodiments, the radius of curvature of the rounded corner is in the range of 0.25 nm to 0.35 nm. In one or more of the foregoing and following embodiments, the penetration amount of the upper contact into the lower contact in the vertical direction is in the range of 2nm to 20nm. In one or more of the foregoing and following embodiments, the second opening has a tapered shape, and the bottom dimension of the tapered shape is smaller than the top dimension. In one or more of the foregoing and following embodiments, the taper angle of the taper is in the range of 1.4 degrees to 3.1 degrees.

[0090] According to another aspect of the present disclosure, a semiconductor device includes: a gate electrode; a source / drain structure; a source / drain contact in contact with the source / drain structure and arranged in a first opening formed in a first insulating layer. A second insulating layer is arranged on the first insulating layer, a gate contact contacts the gate electrode and is arranged in a second opening, the second opening is formed in the second insulating layer, a third insulating layer is arranged above the second insulating layer, and an upper contact is arranged in the first insulating layer. The third opening is formed in the third insulating layer and is in direct contact with the source / drain contact. The upper contact is in direct contact with the third insulating layer without interposing a conductive barrier layer, and includes ruthenium, a fourth insulating layer is arranged between the second insulating layer and the third insulating layer, and a portion of the upper contact penetrates into the insulating layer. The source / drain contact is arranged below the fourth insulating layer and in contact with the bottom surface of the fourth insulating layer. In one or more of the foregoing embodiments and the following embodiments, the gate contact is in direct contact with the third insulating layer, the fourth insulating layer, and the second insulating layer without interposing a conductive barrier layer, and includes ruthenium. In one or more of the foregoing and following embodiments, the gate electrode extends in a first direction, the source-drain structure includes a source / drain epitaxial layer, and the width of the source / drain epitaxial layer is less than the width of the source / drain contact in the first direction. In one or more of the foregoing and following embodiments, the purity of ruthenium in the upper contact and the gate contact is equal to or greater than 99.9% and less than 100%. In one or more of the foregoing and following embodiments, the upper contact has a rivet shape, and the gate contact does not have a rivet shape.

[0091] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or achieve the same advantages of the embodiments described herein. Those skilled in the art will also appreciate that such equivalent structures do not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications in the present invention without departing from the spirit and scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: forming a source / drain structure over the substrate; forming a first interlayer dielectric layer including one or more first insulating layers over the source / drain structure; forming a first opening in the first interlayer dielectric layer to at least partially expose the source / drain structure; filling the first opening with a first conductive material to form a source / drain contact in contact with the source / drain structure; forming a second interlayer dielectric layer including a first layer and a second layer disposed on the first layer over the source / drain contacts and the first interlayer dielectric layer; forming a second opening in the second interlayer dielectric layer to at least partially expose the source / drain contact; as well as filling the second opening with a second conductive material to form an upper contact that is in direct contact with the source / drain contacts and with the second interlayer dielectric layer without intervening a conductive barrier layer, Wherein, the second conductive material includes ruthenium.

2. The method according to claim 1, wherein: The upper contact includes impurities other than ruthenium.

3. The method according to claim 2, wherein: The amount of impurities is 0.00001 atomic % to 0.1 atomic %.

4. The method according to claim 2, wherein: The impurities are one or more selected from alkali metals and alkaline earth metals.

5. The method according to claim 2, wherein: The impurity is carbon.

6. The method according to claim 1, wherein: The first conductive material is Co.

7. The method according to claim 6, wherein: A portion of the source / drain contact below the upper contact has a disordered structure of Co atoms.

8. The method according to claim 1, wherein: The first layer is made of a silicon nitride-based material, and the second layer is made of a silicon oxide-based material.

9. A method for manufacturing a semiconductor device, the method comprising: forming a source / drain structure over the substrate; forming a first interlayer dielectric layer including one or more first insulating layers over the source / drain structure; forming a first opening in the first interlayer dielectric layer to at least partially expose the source / drain structure; filling the first opening with a first conductive material to form a source / drain contact in contact with the source / drain structure; forming a second interlayer dielectric layer including a first layer and a second layer disposed on the first layer over the source / drain contacts and the first interlayer dielectric layer; forming a second opening in the second interlayer dielectric layer to at least partially expose the source / drain contact; partially recessing the source / drain contact to form a recess, the recess extending below the first layer; performing a cleaning operation on the recess and the first layer, the cleaning operation comprising performing a plasma treatment on the recess and the first layer; as well as The second opening and the groove are filled with ruthenium to form an upper contact in direct contact with the source / drain contacts and in direct contact with the second interlayer dielectric layer without intervening a conductive barrier layer.

10. The method according to claim 9, wherein: The recessing includes wet etching.

11. The method according to claim 10, wherein: The wet etching etchant includes an organic acid.

12. The method according to claim 9, wherein: The plasma treatment includes hydrogen plasma and / or argon plasma.

13. The method according to claim 12, wherein: The plasma treatment includes a first plasma treatment using hydrogen plasma and a second plasma treatment using argon plasma after the first plasma treatment.

14. The method according to claim 12, wherein: After the plasma treatment, a bottom corner of the first layer constituting the second opening has a rounded corner.

15. The method according to claim 9, wherein: The first layer is made of a silicon nitride-based material, and the second layer is made of a silicon oxide-based material.

16. The method according to claim 9, wherein: The purity of ruthenium in the upper contact is equal to or greater than 99.9% and less than 100%.

17. The method according to claim 9, wherein: The ruthenium of the top contact is formed by thermal CVD at a temperature in the range of 100°C to 250°C.

18. A semiconductor device comprising: a gate electrode; Source / drain structure; a lower contact, contacting the gate electrode or the source / drain structure; as well as an upper contact disposed in an opening formed in the interlayer dielectric layer and in direct contact with the lower contact; wherein the upper contact is in direct contact with the interlayer dielectric layer without interposing a conductive barrier layer, and The upper contact includes ruthenium.

19. The semiconductor device according to claim 18, wherein: The upper contact includes impurities other than ruthenium.

20. The semiconductor device according to claim 19, wherein The amount of impurities is in the range of 0.00001 atomic % to 0.1 atomic %.

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