Metal Oxide Semiconductor Field Effect Transistor and Method of Manufacturing the Same

Abstract

The present invention discloses a metal oxide semiconductor field effect transistor and a manufacturing method thereof. The metal oxide semiconductor field effect transistor includes a substrate structure, a plurality of doped regions, an oxide layer structure, a plurality of semiconductor layer structures, a dielectric layer structure, and a metal structure. The substrate structure includes a base layer and an epitaxial layer. The epitaxial layer forms a plurality of trenches along a first direction. A pitch is formed between any two adjacent trenches. The pitch between the plurality of trenches increases along the first direction. The plurality of doped regions are respectively formed at the bottoms of the plurality of trenches. The oxide layer structure is formed on the inner walls of the plurality of trenches and the surface of the epitaxial layer. The plurality of semiconductor layer structures are respectively formed in the plurality of trenches to form a plurality of trench-type structures. The dielectric layer structure is formed on the oxide layer structure. The metal structure is formed on the dielectric layer structure and electrically connected to at least one of the trench-type structures. Thereby, competitive advantages in products such as low production cost, high production yield, small size, and simple structure can be achieved.

Description

Technical Field

[0001] The present invention relates to a metal oxide semiconductor field effect transistor, and more particularly to a metal oxide semiconductor field effect transistor suitable for use in a power supply and a manufacturing method thereof. Background Art

[0002] With the progress of electronic technology and the miniaturization trend of electronic products, more and more electronic components are produced by means of integrated circuit manufacturing processes. However, electronic components in the form of integrated circuits need to consider many aspects, such as problems like high voltage resistance, mutual interference or noise immunity, especially for electronic components used in power supplies. Since the power supply needs to receive a high voltage input, and the high voltage input can cause the integrated circuit type of electronic components to burn out, which in turn leads to the failure of the power supply, this is the main reason why the size of the power supply cannot be reduced.

[0003] Among them, metal oxide semiconductor field effect transistors are also often used in power supplies. Because the operation speed of metal oxide semiconductor field effect transistors is quite fast and their performance in voltage signal processing is quite excellent, metal oxide semiconductor field effect transistors are used as converters. In response to the miniaturization trend of electronic products, metal oxide semiconductor field effect transistors are also gradually developing towards the direction of integration. However, when the power supply bears a high voltage, the integrated circuit type of metal oxide semiconductor field effect transistors will also burn out due to their inability to withstand high voltages. Moreover, existing metal oxide semiconductor field effect transistors still have deficiencies such as too high production costs, too low production yields, and too large volumes.

[0004] Therefore, the inventor of the present invention felt that the above deficiencies could be improved, and thus specifically devoted himself to research and combined with the application of theory, and finally proposed the present invention with a reasonable design and effectively improving the above deficiencies. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a metal oxide semiconductor field effect transistor and a manufacturing method thereof in view of the deficiencies of the prior art.

[0006] To solve the above technical problems, one of the technical solutions adopted by the present invention is to provide a metal-oxide-semiconductor field-effect transistor, which includes: a substrate structure, which includes: a base layer; and an epitaxial layer formed on the base layer, and multiple trenches are formed in the epitaxial layer, wherein multiple trenches are recessed at intervals along a first direction on a surface of the epitaxial layer opposite to the base layer, and a spacing is formed between any two adjacent trenches, and the spacing between multiple trenches increases along the first direction; multiple doping regions are respectively formed at bottoms of multiple trenches and partially diffuse toward the epitaxial layer; an oxide layer structure, which includes: multiple trench oxide layers respectively formed on inner walls of multiple trenches and respectively abutting against multiple doping regions; wherein each trench oxide layer surrounds and forms a groove; and a cladding oxide layer formed on a surface of the epitaxial layer opposite to the base layer and extending and connecting between multiple trench oxide layers; multiple semiconductor layer structures are respectively formed in multiple grooves to respectively form multiple trench-type structures together with multiple trench oxide layers; a dielectric layer structure is formed and covers the oxide layer structure and multiple semiconductor layer structures; and a metal structure is formed on a surface of the dielectric layer structure opposite to the base layer and electrically connected to at least one of multiple trench-type structures.

[0007] Preferably, the number of multiple trenches is N, and N is a positive integer greater than 3; an increase amount of a spacing between any two adjacent ones of them is between 5% and 25%.

[0008] Preferably, the number of multiple trenches is N, and N is a positive integer greater than 3; wherein a difference between a spacing between any two adjacent ones of them is between 0.3 micrometer and 1.2 micrometers.

[0009] Preferably, the number of multiple trenches is N, and N is a positive integer greater than 3; wherein the spacing of N trenches increases in an arithmetic progression along the first direction.

[0010] Preferably, the number of multiple trench-type structures corresponds to the number of multiple trenches and is N, the number of multiple spacings is N - 1, and N trench-type structures are sequentially defined as a first trench-type structure to an Nth trench-type structure along the first direction, and N - 1 spacings are sequentially defined as a first spacing to an (N - 1)th spacing along the first direction; wherein N is a positive integer between 7 and 30.

[0011] Preferably, the metal structure includes a conductive portion and a contact plug; wherein, the conductive portion is formed on a surface of the dielectric layer structure opposite to the base layer, and the contact plug penetrates through the dielectric layer structure, so that the conductive portion can be electrically connected to one of the plurality of trench structures through the contact plug.

[0012] Preferably, the number of the contact plugs is two, and the two contact plugs are respectively formed to penetrate through the dielectric layer structure and partially extend into the semiconductor layer structures of a first trench structure and a second trench structure among the plurality of trench structures, so that the conductive portion can be electrically connected to the first trench structure and the second trench structure among the plurality of trench structures respectively through the two contact plugs.

[0013] Preferably, a trench depth of each trench is between 4 micrometers and 20 micrometers.

[0014] Preferably, the metal oxide semiconductor field effect transistor forms a depletion region boundary, and the depletion region boundary extends from the top surface of the epitaxial layer to the bottom surface of the epitaxial layer to divide the epitaxial layer into a first region and a second region; wherein, the first region and the second region are arranged in sequence along the first direction, and the plurality of trench structures are all located on one side of the depletion region boundary and completely fall inside the first region.

[0015] To solve the above technical problems, another technical solution adopted by the present invention is to provide a manufacturing method of a metal oxide semiconductor field effect transistor, including: providing a substrate structure; wherein, the substrate structure includes a base layer and an epitaxial layer formed on the base layer; forming a plurality of trenches by recessing on the epitaxial layer; wherein, the plurality of trenches are recessed at intervals along a first direction on the surface of the epitaxial layer opposite to the base layer, and a spacing is formed between any two adjacent trenches, and the spacing between the plurality of trenches increases along the first direction; forming a plurality of doping regions at the bottoms of the plurality of trenches respectively; wherein, the plurality of doping regions respectively diffuse from the bottoms of the plurality of trenches towards a part of the epitaxial layer; forming an oxide layer structure on the epitaxial layer; wherein, the oxide layer structure includes a plurality of trench oxide layers and a coating oxide layer, the plurality of trench oxide layers are respectively formed on the inner walls of the plurality of trenches and respectively abut against the plurality of doping regions, and a groove is formed by surrounding each trench oxide layer; wherein, the coating oxide layer is formed on the surface of the epitaxial layer opposite to the base layer and extends to connect between the plurality of trench oxide layers; forming a plurality of semiconductor layer structures in the plurality of grooves respectively, so that the plurality of semiconductor layer structures and the plurality of trench oxide layers can jointly form a plurality of trench structures; forming a dielectric layer structure on the oxide layer structure and the plurality of semiconductor layer structures, so that the oxide layer structure and the plurality of semiconductor layer structures are covered by the dielectric layer structure; and forming a metal structure on the surface of the dielectric layer structure opposite to the base layer; wherein, the metal structure is electrically connected to at least one of the plurality of trench structures.

[0016] One beneficial effect of the present invention is that the metal oxide semiconductor field effect transistor and its manufacturing method provided by the present invention can, through the technical solution of "the plurality of trenches are recessed at intervals along a first direction on the surface of the epitaxial layer opposite to the base layer, and a spacing is formed between any two adjacent trenches, and the spacing between the plurality of trenches increases along the first direction", enable the metal oxide semiconductor field effect transistor of this embodiment to have competitive advantages in terms of low production cost, high production yield, small volume, and simple structure.

[0017] To further understand the features and technical content of the present invention, please refer to the following detailed description and drawings of the present invention. However, the provided drawings are only for reference and illustration, and are not used to limit the present invention. Description of the Drawings

[0018] Figure 1Schematic diagram of the metal-oxide-semiconductor field-effect transistor according to an embodiment of the present invention.

[0019] Figure 2A Manufacturing flowchart (I) of the metal-oxide-semiconductor field-effect transistor.

[0020] Figure 2B Manufacturing flowchart (II) of the metal-oxide-semiconductor field-effect transistor.

[0021] Figure 2C Manufacturing flowchart (III) of the metal-oxide-semiconductor field-effect transistor.

[0022] Figure 2D Manufacturing flowchart (IV) of the metal-oxide-semiconductor field-effect transistor.

[0023] Figure 2E Manufacturing flowchart (V) of the metal-oxide-semiconductor field-effect transistor.

[0024] Figure 2F Manufacturing flowchart (VI) of the metal-oxide-semiconductor field-effect transistor.

[0025] Figure 2G Manufacturing flowchart (VII) of the metal-oxide-semiconductor field-effect transistor. Detailed implementation manners

[0026] The following are specific embodiments to illustrate the disclosed embodiments of the present invention. Those skilled in the art can understand the advantages and effects of the present invention from the content disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of the present invention. In addition, the drawings of the present invention are only simple schematic illustrations and are not drawn according to actual sizes. The following embodiments will further detail the related technical content of the present invention, but the disclosed content is not used to limit the protection scope of the present invention.

[0027] It should be understood that although terms such as "first", "second", and "third" may be used herein to describe various components or signals, these components or signals should not be limited by these terms. These terms are mainly used to distinguish one component from another, or one signal from another. In addition, the term "or" used herein should, depending on the actual situation, possibly include any one or a combination of more of the associated listed items.

[0028] [Manufacturing method of metal-oxide-semiconductor field-effect transistor]

[0029] Please refer to Figure 1 、and Figures 2A through 2GAs shown in the figure, an embodiment of the present invention provides a method for manufacturing a metal oxide semiconductor field effect transistor, which includes steps S110 to S170. Among them, in this embodiment, the metal oxide semiconductor field effect transistor is a power component, such as a power supply or a transformer, but the present invention is not limited thereto. It should be noted that the order of the steps described in this embodiment and the actual operation method can be adjusted according to needs, and is not limited to those described in this embodiment.

[0030] In the following, this embodiment first describes the manufacturing method of the metal oxide semiconductor field effect transistor. For the convenience of understanding, this embodiment takes a unit area of the metal oxide semiconductor field effect transistor as an example and makes an explanation with a cross-sectional view. Mainly refer to the drawings corresponding to each step, and refer to the drawings of other steps as needed. The specific steps of the manufacturing method of the metal oxide semiconductor field effect transistor are described as follows.

[0031] As Figure 2A shown, step S110 includes: providing a substrate structure 1. The substrate structure 1 includes: a base layer 11 and an epitaxial layer 12 formed on the base layer 11. The two surfaces of the substrate structure 1 on opposite sides are respectively defined as a top surface and a bottom surface (not labeled in the figure). Among them, the surface of the epitaxial layer 12 opposite to the base layer 11 is the top surface, and the surface of the base layer 11 opposite to the epitaxial layer 12 is the bottom surface.

[0032] More specifically, the material of the base layer 11 can be, for example, an N-type doped semiconductor or a P-type doped semiconductor. The epitaxial layer 12 can be, for example, formed on the base layer 11 by an epitaxy process, and the conductivity type of the epitaxial layer 12 can be, for example, the same as that of the base layer 11 (such as N-type doping or P-type doping). In this embodiment, the base layer 11 is an N-type doped semiconductor, and the epitaxial layer 12 is also an N-type doped semiconductor, and the doping concentration of the base layer 11 is higher than that of the epitaxial layer 12, but the present invention is not limited thereto.

[0033] As Figure 2B shown, step S120 includes: forming a plurality of trenches 13 recessed on the epitaxial layer 12. Among them, the plurality of trenches 13 can be, for example, formed by an etching method, but the present invention is not limited thereto.

[0034] More specifically, a plurality of the grooves 13 are recessed at intervals along a first direction D1 on a surface of the epitaxial layer 12 opposite to the base layer 11, and bottoms of the plurality of grooves 13 do not contact the base layer 11 and are spaced apart from the base layer 11 by a certain distance. In other words, the plurality of grooves 13 are recessed from the top surface of the substrate structure 1 and do not contact the base layer 11 of the substrate structure 1.

[0035] Furthermore, a spacing is formed between any two adjacent grooves 13, and the spacings G1 to GN-1 between the plurality of grooves 13 increase along the first direction D1. Wherein, the number of the plurality of grooves 13 is N, and N is a positive integer greater than 3.

[0036] It is worth mentioning that in order to make the finally formed metal oxide semiconductor field effect transistor 100 suitable for applying a relatively high operating voltage (such as an operating voltage between 300 volts and 800 volts), the number of the plurality of grooves 13 is usually between 7 and 30, preferably between 7 and 20, and particularly preferably between 7 and 15. That is to say, the above-mentioned value N is usually a positive integer between 7 and 30, preferably a positive integer between 7 and 20, and particularly preferably a positive integer between 7 and 15, but the present invention is not limited thereto.

[0037] As described above, the spacings G1 to GN-1 between the plurality of grooves 13 increase along the first direction D1. Wherein, in an embodiment of the present invention, an increase amount of any two adjacent spacings G1 to GN-1 is usually between 5% and 25%, and preferably between 5% and 15%. That is to say, in any two adjacent spacings G1 to GN-1 described above, an increase amount of the latter spacing compared to the former spacing is usually between 5% and 25%. For example, in Figure 2B the increase amount of the second spacing G2 compared to the first spacing G1 is between 5% and 25%, and the increase amount of the third spacing G3 compared to the second spacing G2 is also between 5% and 25%.

[0038] In other words, in an embodiment of the present invention, a difference (or absolute value of the difference) between any two adjacent spacings G1 to GN-1 is usually between 0.3 micrometers and 1.2 micrometers, and preferably between 0.4 micrometers and 0.8 micrometers. That is to say, in any two adjacent spacings G1 to GN-1 described above, a difference between the latter spacing and the former spacing is usually between 0.3 micrometers and 1.2 micrometers. For example, in Figure 2BAmong them, the difference between the second spacing G2 and the first spacing G1 is between 0.3 micrometers and 1.2 micrometers, and the difference between the third spacing G3 and the second spacing G2 is also between 0.3 micrometers and 1.2 micrometers.

[0039] It should be noted that the increase amount or difference between any two adjacent spacings G1 to GN-1 above can be, for example, the same or different, and the present invention is not limited thereto. However, in a preferred embodiment of the present invention, the difference between any two adjacent spacings G1 to GN-1 above is the same. That is to say, the spacings G1 to GN-1 formed between the above N grooves 13 increase in an arithmetic progression along the first direction D1.

[0040] Please continue to refer to Figure 2B , in a specific embodiment of the present invention, the number of the grooves 13 is eight, and a total of seven spacings are formed between the eight grooves 13. Among them, among the above seven spacings, the first spacing G1 along the first direction D1 is 2.65 micrometers, the second spacing G2 is 3.25 micrometers, and the third spacing G3 is 3.85 micrometers. That is to say, the difference between the second spacing G2 and the first spacing G1 is 0.6 micrometers, and the difference between the third spacing G3 and the second spacing G2 is also 0.6 micrometers, and so on. That is to say, the above seven spacings increase in an arithmetic progression along the first direction D1.

[0041] It should be noted that the above first spacing G1 is described by taking 2.65 micrometers as an example, but the present invention is not limited thereto. For example, the first spacing G1 of the above multiple spacings along the first direction D1 is usually between 2 micrometers and 8 micrometers, and preferably between 3 micrometers and 6 micrometers.

[0042] Furthermore, the distance between the bottom and the top of each groove 13 is defined as a groove depth H. That is to say, the distance from the bottom of each groove 13 to the top surface of the substrate structure 1 is defined as the groove depth H. Among them, the groove depth H of each groove 13 is usually between 4 micrometers and 20 micrometers, and preferably between 4 micrometers and 16 micrometers.

[0043] It should be noted that in Figure 2B , the groove depths H of the multiple grooves 13 are described by taking the same depth as an example, but the present invention is not limited thereto. For example, in an embodiment not shown in the present invention, the groove depths H of the multiple grooves 13 can also be different from each other.

[0044] Furthermore, it should be noted that the above-mentioned multiple trenches 13 are described from the perspective of a cross-sectional view for the trenches 13 at different parts within the epitaxial layer 12. Viewed as a whole, these trenches 13 may be of a connected structure or a separated structure, and the present invention does not impose any limitations thereon.

[0045] As Figure 2C shown, step S130 includes: respectively forming a plurality of doping regions 2 at the bottoms of the multiple trenches 13, and the multiple doping regions 2 all diffuse towards a part of the epitaxial layer 12. Among them, the multiple doping regions 2 can be formed, for example, by an ion implantation process, but the present invention is not limited thereto.

[0046] That is to say, a doping region 2 is respectively formed at the bottom of each trench 13, and each doping region 2 diffuses from the bottom of its corresponding trench 13 towards a part of the epitaxial layer 12. Accordingly, each doping region 2 surrounds the periphery of the bottom of its corresponding trench 13. Furthermore, in this embodiment, each doping region 2 only slightly diffuses from the bottom of its corresponding trench 13 towards a part of the epitaxial layer 12 and presents a semi-circular structure, and each doping region 2 does not contact the base layer 11 and is spaced apart from the base layer 11 by a certain distance.

[0047] Furthermore, in this embodiment, the conduction types of the multiple doping regions 2 are different from the conduction type of the above-mentioned base layer 11 and also different from the conduction type of the above-mentioned epitaxial layer 12. That is to say, the multiple doping regions 2 in this embodiment are P-type doped semiconductors, and the implanted ion species can be, for example, boron ions (B+).

[0048] In addition, it is worth mentioning that the above-mentioned multiple doping regions 2 (P-type doped semiconductors) can jointly form a P-N junction diode with the epitaxial layer 12 (N-type doped semiconductor). Since the holes in the P-type semiconductor material and the electrons in the N-type semiconductor material will combine at the junction surface, resulting in a lack of carriers in the region near the junction surface, thereby forming a depletion region as shown in Figure 1 region R1 shown, and the boundary of this depletion region is defined as a depletion boundary DB.

[0049] As Figure 2DAs shown, step S140 includes: forming an oxide layer structure 3 extending on the surface of the epitaxial layer 12 opposite to the base layer 11 and on the inner walls of the plurality of trenches 13. The oxide layer structure 3 can be formed, for example, by a low temperature oxide deposition (LTO deposition) process, but the present invention is not limited thereto.

[0050] More specifically, the oxide layer structure 3 includes a plurality of trench oxide layers 31 and a coating oxide layer 32. Among them, the plurality of trench oxide layers 31 are respectively formed on the inner walls of the plurality of trenches 13 and respectively abut against the plurality of doped regions 2, and each trench oxide layer 31 surrounds and forms a groove 33. Furthermore, the coating oxide layer 32 is formed on the surface of the epitaxial layer 12 opposite to the base layer 11 (i.e., the top surface of the epitaxial layer 12) and extends and connects between the plurality of trench oxide layers 31.

[0051] Among them, the thickness of the above-mentioned oxide layer structure 3 in this embodiment is generally between 0.5 micrometers and 1.5 micrometers More specifically, the thickness of each trench oxide layer 31 is generally between 0.5 micrometers and 1.5 micrometers. Furthermore, the material of the oxide layer structure 3 can be composed of, for example, a silicon compound or other dielectric materials. For example, the above-mentioned silicon compound can be, for example, silicon dioxide or silicate, and preferably silicon dioxide, but the present invention is not limited thereto.

[0052] As Figure 2E shown, and please also refer to Figure 1 shown, step S150 includes: forming a plurality of semiconductor layer structures 4 in the grooves 33 surrounded by the plurality of trench oxide layers 31, so that the plurality of semiconductor layer structures 4 and the plurality of trench oxide layers 31 together form a plurality of trench structures T.

[0053] Furthermore, the above-mentioned plurality of semiconductor layer structures 4 can, for example, have their exposed surfaces (i.e., Figure 2E the top surface of the semiconductor layer structure 4 in Figure 2E lower than the outer surface of the coating oxide layer 32 (i.e.,

[0054] As Figure 2FAs shown, step S160 includes: forming and covering an inter layer dielectric (ILD) dielectric layer structure 5 on the oxide layer structure 3 and the plurality of semiconductor layer structures 4, so that the oxide layer structure 3 and the plurality of semiconductor layer structures 4 are buried in the dielectric layer structure 5. Among them, the dielectric layer structure 5 can be formed, for example, by chemical vapor deposition, but the present invention is not limited thereto. For example, the dielectric layer structure 5 can also be formed, for example, by physical vapor deposition or other suitable deposition processes. Furthermore, the material of the dielectric layer structure 5 can be composed of, for example, a compound of silicon or other dielectric materials.

[0055] Furthermore, the outer surface of the dielectric layer structure 5 can be surface planarized, for example, through a Chemical Mechanical Polishing (CMP) process, but the present invention is not limited thereto.

[0056] As Figure 2G shown, and please refer to Figure 1 As shown, step S170 includes: forming a metal structure 6 on the surface of the dielectric layer structure 5 opposite to the base layer 11, and the metal structure 6 partially penetrates the dielectric layer structure 5 to electrically connect to at least one of the plurality of trench structures T1 to TN. Among them, the metal structure 6 can be formed, for example, by deposition, and the metal structure 6 is an integral structure formed of an aluminum-silicon-copper alloy in this embodiment, but in actual applications, it is not limited thereto.

[0057] Furthermore, the metal structure 6 includes: a conductive part 62 and two contact plugs 61 integrally formed with the conductive part 62. Among them, the conductive part 62 is formed on the surface of the dielectric layer structure 5 opposite to the base layer 11, the two contact plugs 61 are arranged at intervals from each other, and the two contact plugs 61 respectively penetrate the dielectric layer structure 5, so that the conductive part 62 can be electrically connected to two adjacent trench structures T among the plurality of trench structures T through the two contact plugs 61 respectively. In addition, the width of each contact plug 61 is smaller than the width of the corresponding trench structure T and also smaller than the width of the corresponding groove 13.

[0058] More specifically, the two contact plugs 61 are respectively formed through the dielectric layer structure 5, and the two contact plugs 61 respectively partially extend into the semiconductor layer structure 4 of the first trench structure T1 and the semiconductor layer structure 4 of the second trench structure T2, so that the conductive portions 62 can be electrically connected to the first trench structure T1 and the second trench structure T2 in the plurality of trench structures T1 to TN respectively through the two contact plugs 61 (as Figure 1 ). Thereby, the semiconductor layer structure 4 of the first trench structure T1 and the semiconductor layer structure 4 of the second trench structure T2 are set at the same potential compared to the two contact plugs 61 to which they are electrically connected.

[0059] It is worth mentioning that although two of the contact plugs 61 are taken as examples in this embodiment, the present invention is not limited thereto. For example, in another embodiment of the present invention, the number of the contact plugs 61 can also be one or more than three according to the design requirements of the product.

[0060] Furthermore, in this embodiment, the above-mentioned conductive portion 62 only covers a part of the outer surface of the dielectric layer structure 5 and exposes another part of the outer surface of the dielectric layer structure 5 to the outside.

[0061] It is worth mentioning that before forming the metal structure 6, the manufacturing method of this embodiment further includes: forming two contact grooves (not labeled in the figure) in the dielectric layer structure 5 by etching to provide the above two contact plugs 61 to be respectively formed therein.

[0062] After implementing the above steps S110 to S170, the metal oxide semiconductor field effect transistor 100 (or, trench power component) as shown in Figure 1 can be completed. However, in actual application, each step does not exclude being replaced by a reasonable variant form. Furthermore, it must be emphasized that the above steps are described from the perspective of a sectional view. On the premise of conforming to the above steps, the possibility of implementing the present invention with various design layouts is not excluded. In other words, when viewed from above, the metal oxide semiconductor field effect transistor of this embodiment can have different design layout forms.

[0063] [Metal Oxide Semiconductor Field Effect Transistor]

[0064] The above is the description of the manufacturing method of the metal oxide semiconductor field effect transistor according to the embodiment of the present invention. Next, the specific structure of the metal oxide semiconductor field effect transistor of this embodiment will be described. It must be noted that although the metal oxide semiconductor field effect transistor of this embodiment is manufactured by the above manufacturing method, the present invention is not limited thereto. That is to say, the metal oxide semiconductor field effect transistor of the present invention can also be manufactured by other transistor manufacturing methods.

[0065] As shown Figure 1 in the figure, this embodiment further discloses a metal-oxide semiconductor field-effect transistor 100, which includes a substrate structure 1, a plurality of doping regions 2, an oxide layer structure 3, a plurality of semiconductor layer structures 4, a dielectric layer structure 5, and a metal structure 6.

[0066] Among them, the substrate structure 1 includes a base layer 11 and an epitaxial layer 12. The epitaxial layer 12 is formed on the base layer 11, and a plurality of trenches 13 are formed in the epitaxial layer 12. The plurality of trenches 13 are recessed at intervals along a first direction D1 on a surface of the epitaxial layer 12 opposite to the base layer 11, and a spacing G is formed between any two adjacent trenches 13, and the spacing G between the plurality of trenches 13 increases along the first direction D1.

[0067] Among them, the plurality of doping regions 2 are respectively formed at the bottoms of the plurality of trenches 13 and partially diffuse toward the epitaxial layer 12.

[0068] Among them, the oxide layer structure 3 includes a plurality of trench oxide layers 31 and a coating oxide layer 32. The plurality of trench oxide layers 31 are respectively formed on the inner walls of the plurality of trenches 13 and respectively abut against the plurality of doping regions 2, and each trench oxide layer 31 surrounds and forms a groove 33. Furthermore, the coating oxide layer 32 is formed on a surface of the epitaxial layer 12 opposite to the base layer 11 and extends and connects between the plurality of trench oxide layers 31.

[0069] Among them, the plurality of semiconductor layer structures 4 are respectively formed in the plurality of grooves 33, and the plurality of semiconductor layer structures 4 can respectively form a plurality of trench structures T together with the plurality of trench oxide layers 31.

[0070] Among them, the dielectric layer structure 5 is formed and covers the oxide layer structure 3 and the plurality of semiconductor layer structures 4.

[0071] Among them, the metal structure 6 is formed on a surface of the dielectric layer structure 5 opposite to the base layer 11 and partially penetrates through the dielectric layer structure 5, so that the metal structure 6 can be electrically connected to at least one of the plurality of trench structures T.

[0072] It is worth mentioning that, as described in the above embodiment, the number of the plurality of trenches 13 is N, and the number of the plurality of trench structures T corresponds to the number of the plurality of trenches 13 and is also N. In addition, the number of the spacings G1 to GN-1 formed between the plurality of trenches 13 is N - 1. That is to say, the number of the plurality of spacings G1 to GN-1 is N - 1.

[0073] Among them, the N trench structures T are sequentially defined as a first trench structure T1, a second trench structure T2, a third trench structure T3, a fourth trench structure T4, …, an (N - 1)th trench structure TN-1, and an Nth trench structure TN along the first direction D1. Furthermore, the N - 1 spacings are sequentially defined as a first spacing G1, a second spacing G2, a third spacing G3, …, and an (N - 1)th spacing GN-1 along the first direction D1. Among them, the above value N is usually a positive integer between 7 and 30, preferably a positive integer between 7 and 20, and particularly preferably a positive integer between 7 and 15. In this embodiment, the above value N is 8, but the present invention is not limited thereto.

[0074] More specifically, the first spacing G1 is the spacing formed between the first trench structure T1 and the second trench structure T2. The second spacing G2 is the spacing formed between the second trench structure T2 and the third trench structure T3. The third spacing G3 is the spacing formed between the third trench structure T3 and the fourth trench structure T4. And the (N - 1)th spacing GN-1 is the spacing formed between the (N - 1)th trench structure TN-1 and the Nth trench structure TN, and so on.

[0075] According to the spacing design between the above-mentioned multiple trench structures, the metal oxide semiconductor field effect transistor 100 can form a depletion boundary DB, and the depletion boundary DB extends from the top surface of the epitaxial layer 12 to the bottom surface of the epitaxial layer 12 to divide the epitaxial layer 12 into a first region R1 and a second region R2. Among them, the first region R1 and the second region R2 are sequentially arranged along the first direction D1, and the multiple trench structures T1 to TN are all located on one side of the depletion boundary DB and are completely inside the first region R1. In other words, the depletion boundary DB is closed at the rear side of the last trench structure TN among the multiple trench structures T1 to TN along the first direction D1. Thereby, when the metal oxide semiconductor field effect transistor 100 of this embodiment is cut, it can be cut from a part of the above second region R2.

[0076] It is worth mentioning that the above depletion boundary DB is Figure 1 an arc curve. Furthermore, the above first region R1 can be called a depletion region, the above second region R2 can be called a neutral region, and the area of the above depletion region is larger than the area of the neutral region.

[0077] Accordingly, the metal-oxide-semiconductor field-effect transistor 100 of this embodiment can be supplied with an operating voltage between 300 volts and 800 volts, and can operate normally without significant risk of burnout. Among them, the above operating voltage is preferably between 500 volts and 700 volts.

[0078] According to the above configuration, the metal-oxide-semiconductor field-effect transistor 100 of this embodiment has competitive advantages in terms of low production cost, high production yield, small size, and simple structure. The metal-oxide-semiconductor field-effect transistor 100 of this embodiment is particularly suitable for use in power supplies or transformers with voltages between 300 volts and 650 volts. Moreover, the width of the metal-oxide-semiconductor field-effect transistor 100 of this embodiment in the first direction D1 can be reduced to a size not greater than 120 micrometers (preferably not greater than 100 micrometers), which represents a 30% to 50% reduction in volume compared to traditional products of the same specifications.

[0079] [Advantages of the Embodiment]

[0080] One of the advantages of the present invention is that the metal-oxide-semiconductor field-effect transistor and its manufacturing method provided by the present invention can, through the technical solution of "a plurality of the trenches are recessed at intervals along a first direction on the surface of the epitaxial layer opposite to the base layer, and a spacing is formed between any two adjacent trenches, and the spacing between the plurality of trenches increases along the first direction", enable the metal-oxide-semiconductor field-effect transistor of this embodiment to have competitive advantages in terms of low production cost, high production yield, small size, and simple structure.

[0081] The content disclosed above is only the preferred feasible embodiment of the present invention, and does not limit the scope of the patent application of the present invention. Therefore, any equivalent technical changes made by using the content of the specification and drawings of the present invention are included in the scope of the patent application of the present invention.

Claims

1. A metal oxide semiconductor field effect transistor, characterized in that, The metal oxide semiconductor field effect transistor includes: A substrate structure, which includes: A base layer; and An epitaxial layer, which is formed on the base layer, and multiple trenches are formed in the epitaxial layer; Wherein, the multiple trenches are recessed at intervals along a first direction on the surface of the epitaxial layer opposite to the base layer, and a spacing is formed between any two adjacent trenches, and the spacing between the multiple trenches increases along the first direction; wherein, the number of the multiple trenches is N, N is a positive integer greater than 3, and an increase amount of any two adjacent spacings is between 5% and 25%; Multiple doped regions, which are respectively formed at the bottoms of the multiple trenches and diffuse towards a part of the epitaxial layer; An oxide layer structure, which includes: Multiple trench oxide layers, which are respectively formed on the inner walls of the multiple trenches and respectively abut against the multiple doped regions; wherein, each trench oxide layer surrounds and forms a groove; and A coating oxide layer, which is formed on the surface of the epitaxial layer opposite to the base layer and extends and connects between the multiple trench oxide layers; Multiple semiconductor layer structures, which are respectively formed in the multiple grooves to respectively form multiple trench-type structures together with the multiple trench oxide layers; A dielectric layer structure, which is formed and covers the oxide layer structure and the multiple semiconductor layer structures; and A metal structure, which is formed on the surface of the dielectric layer structure opposite to the base layer and is electrically connected to at least one of the multiple trench-type structures.

2. The metal oxide semiconductor field effect transistor according to claim 1, characterized in that, N is a positive integer between 7 and 30, and the increase amount of any two adjacent spacings is between 5% and 15%.

3. The metal oxide semiconductor field effect transistor according to claim 1, characterized in that, A difference between any two adjacent spacings is between 0.3 micrometers and 1.2 micrometers.

4. The metal oxide semiconductor field effect transistor according to claim 1, characterized in that, The spacings of the N trenches increase in an arithmetic progression along the first direction.

5. The metal oxide semiconductor field effect transistor according to claim 1, characterized in that, The number of the multiple trench-type structures corresponds to the number of the multiple trenches and is N, the number of the multiple spacings is N - 1, and the N trench-type structures are sequentially defined as the first trench-type structure to the Nth trench-type structure along the first direction, and the N - 1 spacings are sequentially defined as the first spacing to the (N - 1)th spacing along the first direction; wherein, N is a positive integer between 7 and 30.

6. The metal oxide semiconductor field effect transistor according to claim 5, characterized in that, The metal structure includes: a conductive part and a contact plug; wherein, the conductive part is formed on the surface of the dielectric layer structure opposite to the base layer, and the contact plug penetrates through the dielectric layer structure so that the conductive part can be electrically connected to one of the multiple trench-type structures through the contact plug.

7. The metal oxide semiconductor field effect transistor according to claim 6, characterized in that, The number of the contact plugs is two. The two contact plugs are respectively formed through the dielectric layer structure and respectively partially extend into the semiconductor layer structures of a first trench structure and a second trench structure among the plurality of trench structures, so that the conductive part can be electrically connected to the first trench structure and the second trench structure among the plurality of trench structures through the two contact plugs respectively.

8. The metal oxide semiconductor field effect transistor according to claim 1, characterized in that, The trench depth of each trench is between 4 micrometers and 20 micrometers.

9. The metal oxide semiconductor field effect transistor according to any one of claims 1 to 8, characterized in that, The metal oxide semiconductor field effect transistor is formed with a depletion region boundary, and the depletion region boundary extends from the top surface of the epitaxial layer to the bottom surface of the epitaxial layer to divide the epitaxial layer into a first region and a second region; wherein, the first region and the second region are arranged in sequence along the first direction, and the plurality of trench structures are all located on one side of the depletion region boundary and completely fall inside the first region.

10. A method for manufacturing a metal oxide semiconductor field effect transistor, characterized in that, The manufacturing method of the metal oxide semiconductor field effect transistor includes: providing a substrate structure; wherein, the substrate structure includes a base layer and an epitaxial layer formed on the base layer; forming a plurality of trenches by recessing on the epitaxial layer; wherein, the plurality of trenches are recessed at intervals along a first direction on the surface of the epitaxial layer opposite to the base layer, and a spacing is formed between any two adjacent trenches, and the spacing between the plurality of trenches increases along the first direction; wherein, the number of the plurality of trenches is N, N is a positive integer greater than 3, and the increase amount of any two adjacent spacings is between 5% and 25%; forming a plurality of doped regions at the bottoms of the plurality of trenches respectively; wherein, the plurality of doped regions respectively diffuse from the bottoms of the plurality of trenches towards a part of the epitaxial layer; forming an oxide layer structure on the epitaxial layer; wherein, the oxide layer structure includes a plurality of trench oxide layers and a coating oxide layer, the plurality of trench oxide layers are respectively formed on the inner walls of the plurality of trenches and respectively abut against the plurality of doped regions, and each trench oxide layer surrounds and forms a groove; wherein, the coating oxide layer is formed on the surface of the epitaxial layer opposite to the base layer and extends and connects between the plurality of trench oxide layers; forming a plurality of semiconductor layer structures in the plurality of grooves respectively, so that the plurality of semiconductor layer structures and the plurality of trench oxide layers can jointly form a plurality of trench structures; forming a dielectric layer structure on the oxide layer structure and the plurality of semiconductor layer structures, so that the oxide layer structure and the plurality of semiconductor layer structures are covered by the dielectric layer structure; and forming a metal structure on the surface of the dielectric layer structure opposite to the base layer; wherein, the metal structure is electrically connected to at least one of the plurality of trench structures.

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