Storage device and storage system

Abstract

The storage device includes a detector and a storage unit capable of storing a plurality of semiconductor wafers, wherein the plurality of semiconductor wafers respectively include a plurality of non-volatile memory chips. The controller in the detector writes the first identification information and the first check code into the first semiconductor wafer when the first semiconductor wafer transported from the storage unit to the workbench in the detector does not store a group of identification information and a check code with a correct corresponding relationship, and obtains a first logical-physical address conversion table associated with the identification information of the first semiconductor wafer from a host computer or the first semiconductor wafer when the group of identification information and the check code with a correct corresponding relationship is stored in the first semiconductor wafer.

Description

Technical Field

[0001] Embodiments of the present invention relate to a memory device and a memory system for controlling a nonvolatile memory. Background Art

[0002] In recent years, storage devices that control nonvolatile memories have become widely used.

[0003] As such a storage device, a solid state drive (SSD) having a NAND flash memory is known. SSD is used in various computers.

[0004] Recently, there is a demand for memory devices with larger storage capacity. Therefore, it is necessary to realize new technology for increasing the storage capacity of memory devices.

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent Application Laid-Open No. 01-028863

[0008] Patent Document 2: U.S. Patent No. 6,228,684

[0009] Patent Document 3: Japanese Patent No. 3980807 Summary of the invention

[0010] Technical problem that the invention will solve

[0011] The technical problem to be solved by the present invention is to provide a storage device and a storage system capable of increasing storage capacity.

[0012] Means for solving technical problems

[0013] According to an embodiment, a storage device includes a probe and a storage unit capable of storing a plurality of semiconductor wafers, each of which includes a plurality of nonvolatile memory chips. Each of the plurality of semiconductor wafers includes a plurality of electrodes that can be connected to the outside. The probe includes: a workbench on which a semiconductor wafer is mounted; a probe card having a first surface opposite to the one semiconductor wafer and a second surface opposite to the first surface, and including a plurality of probe pins arranged on the first surface; a controller configured to be arranged on the second surface of the probe card, and to perform data writing and reading on the one semiconductor wafer according to the reception of a write request and a read request from a host computer; and a driving unit that moves the probe card or the workbench so that the electrodes of the one semiconductor wafer contact the probe pins. The one semiconductor wafer can be replaced with one of the plurality of semiconductor wafers in the storage unit through a storage device conveying mechanism. Each of the plurality of semiconductor wafers includes a first memory area for storing data, and a second memory area for storing identification information for identifying the semiconductor wafer and a check code for checking the integrity of the identification information. The controller, when the second memory area of ​​the first semiconductor wafer transported from the storage unit to the workbench by the storage member transport mechanism does not store a group of identification information and a check code with a correct corresponding relationship, writes the first identification information for identifying the first semiconductor wafer and the first check code for checking the integrity of the first identification information into the second memory area of ​​the first semiconductor wafer based on a request from the host computer. The controller, when the second memory area of ​​the first semiconductor wafer stores a group of identification information and a check code with a correct corresponding relationship, obtains a first logical-physical address conversion table associated with the identification information stored in the second memory area of ​​the first semiconductor wafer from the host computer or the first memory area of ​​the first semiconductor wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is a block diagram showing a configuration example of a storage system including a storage device according to an embodiment of the present invention.

[0015] Figure 2 This is a diagram showing a configuration example of a semiconductor wafer used as a memory element in a memory device.

[0016] Figure 3 The diagram shows a configuration example of each of a plurality of nonvolatile memory chips (memory dies) included in a semiconductor wafer.

[0017] Figure 4 The diagram shows a plurality of probes arranged on a first surface of a probe card.

[0018] Figure 5 This is a diagram showing a plurality of memory controllers constituting a controller disposed on the second surface of a probe card.

[0019] Figure 6 This diagram shows the relationship between a reader / writer (probe) included in a storage device and a storage stocker.

[0020] Figure 7 This is a block diagram showing an example of the configuration of a controller included in a detector.

[0021] Figure 8 This is a flowchart showing the procedure of identification information writing processing executed in the controller.

[0022] Fig. 9 This is a flowchart showing the procedure of data writing / reading processing executed in the controller.

[0023] Fig.10 This is a flowchart showing the procedure of a process executed in a controller to erase all data in a semiconductor wafer.

[0024] Fig.11 This is a block diagram showing an example of the configuration of a host computer.

[0025] Fig.12 This is a flowchart showing conditions under which each of the new writing process, the additional writing process, the reading process, the wafer adding process, and the wafer removing process controlled by the host computer should be executed.

[0026] Fig.13 This is a block diagram of a storage system showing an initial state in which no semiconductor wafer having identification information exists.

[0027] Fig.14 This is a diagram for explaining a new write process executed in the storage system.

[0028] Fig.15 This is a flowchart showing the procedure of a new writing process controlled by a host computer.

[0029] Fig.16 This is a diagram for explaining the additional writing process performed in the storage system.

[0030] Fig.17 This is a flowchart showing a part of the procedure of the additional writing process controlled by the host computer.

[0031] Fig.18 This is a flowchart showing the sequence of the subsequent part of the additional writing process.

[0032] Fig.19This is a diagram for explaining a read process executed in the storage system.

[0033] Fig. 20 This is a flowchart showing a part of the procedure of the readout process.

[0034] Fig.21 It is a flowchart showing the sequence of the subsequent part of the readout process.

[0035] Fig. 22 This is a diagram for explaining a wafer adding process executed in the storage system.

[0036] Fig.23 This is a flowchart showing the procedure of wafer addition processing.

[0037] Fig.24 It is a diagram for explaining a wafer removal process performed in a storage system.

[0038] Fig.25 : is a flowchart showing the sequence of wafer removal processing. DETAILED DESCRIPTION

[0039] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0040] First, the configuration of a storage system according to an embodiment of the present invention will be described. Figure 1 This is a block diagram showing a configuration example of a storage system including a storage device according to an embodiment of the present invention.

[0041] The storage system 1 includes a host computer 2 and a storage device 3. The host computer 2 is an information processing device that controls the operation of the storage device 3. The host computer 2 manages the wafer storage position where the semiconductor wafer 40 is stored.

[0042] The memory device 3 uses a semiconductor wafer 40 including a plurality of nonvolatile memory chips as a memory device. The memory device 3 is configured to write data to the nonvolatile memory chips in the semiconductor wafer 40 and read data from the nonvolatile memory chips in the semiconductor wafer 40 .

[0043] Generally, nonvolatile memory chips formed on a semiconductor wafer are cut out as chips by dicing and used as storage devices (also called storage media). In contrast, the semiconductor wafer 40 includes a plurality of nonvolatile memory chips, and the semiconductor wafer 40 itself is used as a storage device. The semiconductor wafer 40 may also be in the form of nonvolatile memory chips formed without being cut out. In addition, the semiconductor wafer 40 may also be in a reassembled form formed by gathering the cut nonvolatile memory chips.

[0044] The semiconductor wafer 40 includes a plurality of electrodes (hereinafter referred to as pads) 41 that can be connected to the outside. In more detail, the plurality of pads 41 are pad groups contained in each of the plurality of non-volatile memory chips in the semiconductor wafer 40. The plurality of pads 41 are respectively used for supplying power supply voltage and inputting and outputting signals. The signals include, for example, a chip enable signal, a write enable signal, a read enable signal, an instruction latch enable signal, an address latch enable signal, a write protection signal, a multi-bit width I / O signal, a ready / busy signal RBn, and the like.

[0045] Each of the plurality of semiconductor wafers 40 includes a memory (first memory area) for storing user data and a memory (second memory area) for storing identification information for identifying the semiconductor wafer 40. The identification information for identifying the semiconductor wafer 40 and a check code for checking the integrity of the identification information are stored in the second memory area.

[0046] The identification information may be any identifier (also referred to as wafer ID) that can uniquely identify each semiconductor wafer. The identification information is issued by the host computer 2 .

[0047] The check code is, for example, a cyclic redundancy code (CRC), another type of parity check different from CRC, a hash value calculated based on the identification information, etc. The check code can be used to check the integrity of the value read from the second memory area as the identification information. Thus, it is possible to prevent the random value stored in the second memory area of ​​the new semiconductor wafer 40 just after leaving the factory from being mistakenly processed as the identification information of another semiconductor wafer 40.

[0048] In each semiconductor wafer 40, a part of the storage area of ​​some nonvolatile memory chips among the plurality of nonvolatile memory chips may be used as the second memory area. In this case, a collection of other storage areas other than the storage area used as a part of the second memory area may be used as the first memory area.

[0049] The storage device 3 includes a reader and writer (also referred to as a probe) 10 , a storage element transport mechanism 20 , and a storage element storage unit 30 .

[0050] The reader / writer (also referred to as a prober) 10 writes and reads data on a semiconductor wafer 40 transported from a storage medium storage unit 30 to the reader / writer (also referred to as a prober) 10 by a storage medium transport mechanism 20 .

[0051] The reader / writer (probe) 10 includes a probe card 11 , a stage 12 , and a driving unit 13 .

[0052] The probe card 11 has a surface 11A (here, the lower surface) and a surface 11B (here, the upper surface) on the opposite side to the surface 11A. The surface 11A faces the semiconductor wafer 40 placed on the stage 12 .

[0053] A plurality of probe pins 51 are arranged on the surface 11A. Each probe pin 51 is used to supply an electrical signal to a pad 41 of a semiconductor wafer 40 placed on the workbench 12, or to receive an electrical signal from the pad 41. The probe pin 51 is also called a probe or a probe needle. The total number of probe pins 51 arranged on the surface 11A may be the same as the total number of pads 41 in the semiconductor wafer 40. In this case, the reader and writer (detector) 10 can be connected to the pads 41 in the semiconductor wafer 40 via the probe card 11. Thus, the number of non-volatile memory chips that can be accessed in parallel can be increased.

[0054] A controller 61 is disposed on the surface 11B. The controller 61 is a storage controller configured to control a plurality of nonvolatile memory chips in the semiconductor wafer 40 placed on the worktable 12. The controller 61 can be implemented by an LSI such as a System-on-a-chip (SoC). Figure 1 In the embodiment, a configuration example is shown in which a plurality of controllers 61 are arranged on the surface 11B of the probe card 11 . However, the number of controllers 61 arranged on the surface 11B may be one or more.

[0055] The controller 61 can function as a flash translation layer (FTL) configured to perform data management and lock management of each non-volatile memory chip in the semiconductor wafer 40. The data management performed by the FTL includes the management of mapping information representing the correspondence between each logical address and each physical address. The logical address is an address used by the host computer 2 to specify the address of the location in the logical address space of the semiconductor wafer 40 to be accessed. The physical address corresponding to a certain logical address is used to indicate the physical storage location in the non-volatile memory chip to which the data corresponding to the logical address is written. As a logical address, in general, LBA (logical block address (addressing)) can be used. The logical address of the semiconductor wafer 40 to be accessed is represented by a combination of LBA and identification information of the semiconductor wafer 40 to be accessed, for example.

[0056] The workbench 12 has a mechanism for holding a semiconductor wafer 40. The semiconductor wafer 40 transported from the storage unit 30 to the reader / writer (probe) 10 by the storage unit transport mechanism 20 is placed on the workbench 12. The semiconductor wafer 40 placed on the workbench 12 can be replaced with one of the plurality of semiconductor wafers 40 stored in the storage unit 30 by the storage unit transport mechanism 20.

[0057] The driving unit 13 moves the probe card 11 or the worktable 12 so that the pads 41 of the semiconductor wafer 40 placed on the worktable 12 come into contact with the probe pins 51 of the probe card 11. The pads 41 of the semiconductor wafer 40 come into contact with the probe pins 51, so that the controller 61 and the semiconductor wafer 40 (a plurality of non-volatile memory chips) are electrically connected. For example, the driving unit 13 may also be implemented as an actuator capable of moving the worktable 12 in three mutually orthogonal directions (X direction, Y direction, and Z direction).

[0058] The storage element conveying mechanism 20 can convey the semiconductor wafer 40 between the storage element storage unit 30 and the worktable 12 under the control of the host computer 2 .

[0059] The storage element conveying mechanism 20 includes a supporting body 21 and a tray 22 .

[0060] The support body 21 can move in the horizontal direction and the vertical direction respectively. In addition, the support body 21 can rotate around the central axis along the longitudinal direction of the support body 21.

[0061] The tray 22 is attached to the upper end portion of the support body 21 and is used to transport the semiconductor wafer 40 to be transferred.

[0062] The storage unit storage unit 30 stores a plurality of semiconductor wafers 40. The storage unit storage unit 30 includes a plurality of wafer storage positions. A user can add a new semiconductor wafer 40 to an empty wafer storage position of the storage unit storage unit 30 as needed. Therefore, the storage capacity handled by the storage system 1 can be easily increased in units of semiconductor wafers.

[0063] The semiconductor wafer 40 stored in the storage unit 30 functions as an off-line storage electrically disconnected from the controller 61. The semiconductor wafer 40 transported from the storage unit 30 to the stage 12 by the storage unit transport mechanism 20 functions as an on-line storage electrically connected to the controller 61 via the probe 51.

[0064] Next, the operation of the storage system 1 according to the embodiment of the present invention will be described.

[0065] The storage device 3 writes or reads data to or from the semiconductor wafer 40 (online storage device) to be accessed under the control of the host computer 2 .

[0066] The host computer 2 sends a transport request to the storage device 3 to designate a wafer storage position storing the semiconductor wafer 40 to be accessed. Upon receiving the transport request, the storage device transport mechanism 20 of the storage device 3 transports the semiconductor wafer 40 at the designated wafer storage position in the storage device storage unit 30 to the reader / writer (probe) 10 and places it on the workbench 12. The reader / writer (probe) 10 writes or reads data on the semiconductor wafer 40 to be accessed placed on the workbench 12.

[0067] If the data writing or reading is completed for the semiconductor wafer 40 to be accessed, the storage device 3 can store the semiconductor wafer 40 on the workbench 12 in the wafer storage position in the storage device storage unit 30. Alternatively, the storage device 3 can also continue to place the semiconductor wafer 40 on the workbench 12 until receiving a transfer request for other semiconductor wafers 40.

[0068] When the semiconductor wafer 40 on the workbench 12 is stored in the wafer storage position in the storage device storage unit 30, the host computer 2 sends a return request to the storage device 3, which specifies the wafer storage position in the storage device storage unit 30 where the semiconductor wafer 40 on the workbench 12 is stored. When the host computer 2 completes writing or reading data on the semiconductor wafer 40 to be accessed, or when, for example, user data can no longer be written to the first memory area, the return request is sent to the storage device 3. If the return request is received, the storage device conveying mechanism 20 of the storage device 3 conveys the semiconductor wafer 40 on the workbench 12 of the reader and writer (detector) 10 to the storage device storage unit 30, and stores it in the designated wafer storage position.

[0069] Next, a more detailed description will be given of the operation of writing or reading data to or from the semiconductor wafer 40 to be accessed.

[0070] In the storage device storage unit 30, there may be a mixture of semiconductor wafers 40 to which data has been written and semiconductor wafers 40 to which data has not been written. Under the control of the host computer 2, the storage device 3 uses the identification information stored in the semiconductor wafer 40 to distinguish the semiconductor wafers 40 to which data has been written and the semiconductor wafers 40 to which data has not been written, and performs processing.

[0071] If the second memory area of ​​the semiconductor wafer 40 placed on the workbench 12 does not store a set of identification information and a check code having a correct corresponding relationship, the semiconductor wafer 40 is a semiconductor wafer into which data has not yet been written. If the second memory area of ​​the semiconductor wafer 40 placed on the workbench 12 stores a set of identification information and a check code having a correct corresponding relationship, the semiconductor wafer 40 is a semiconductor wafer into which data has been written.

[0072] In the case where the second memory area of ​​the semiconductor wafer 40 placed on the workbench 12 does not store a set of identification information and a check code having a correct correspondence relationship, the controller 61 writes the identification information for identifying the semiconductor wafer 40 and the check code for checking the integrity of the identification information to the second memory area of ​​the semiconductor wafer 40 based on a request from the host computer 2. Then, the controller 61 creates a logical-to-physical address translation table associated with the identification information. The logical-to-physical address translation table is used to manage the correspondence relationship between logical addresses and physical addresses. Hereinafter, the logical-to-physical address translation table is also referred to as the L2P table.

[0073] When the second memory area of ​​the semiconductor wafer 40 placed on the workbench 12 stores a group of identification information and a check code having a correct corresponding relationship, the controller 61 obtains a logical-physical address conversion table associated with the identification information from the host computer 2. Alternatively, the logical-physical address conversion table may be divided into two levels, namely, an upper table and a lower table. Furthermore, the controller 61 may obtain an upper table in the logical-physical address conversion table from the host computer 2 and obtain a lower table from the semiconductor wafer 40.

[0074] The controller 61 controls the nonvolatile memory chip in the semiconductor wafer 40 mounted on the stage 12 , and writes or reads data to or from the semiconductor wafer 40 in response to receiving a write request (write command) or a read request (read command) from the host computer 2 .

[0075] When receiving a write request from the host computer 2, the controller 61 writes the user data included in the write request to a physical storage location in the first memory area of ​​the semiconductor wafer 40. Then, the controller 61 updates the acquired L2P table in such a way that the physical address indicating the physical storage location is associated with the logical address specified by the write request.

[0076] When receiving a read request from the host computer 2, the controller 61 identifies the physical address corresponding to the logical address specified by the read request by referring to the acquired L2P table. Then, the controller 61 reads the user data from the first memory area of ​​the semiconductor wafer 40 indicated by the identified physical address.

[0077] Next, the detailed structure of the semiconductor wafer 40 according to the embodiment of the present invention will be described. Figure 2 FIG. 4 is a diagram showing a configuration example of a semiconductor wafer 40 used as a memory element in the memory device 3 .

[0078] The semiconductor wafer 40 includes a plurality of nonvolatile memory chips 70. The size of the semiconductor wafer 40 is not limited, but may be a 300 mm wafer. When the number of nonvolatile memory chips 70 included in one semiconductor wafer is 1024 and the storage capacity of each nonvolatile memory chip 70 is 32 GB, the storage capacity of each semiconductor wafer is 32 TB. The nonvolatile memory chip 70 is, for example, rectangular in shape, and a plurality of pads 41 that can be connected to the outside are arranged on one side thereof.

[0079] A portion of the storage area of ​​one or more of the nonvolatile memory chips 70 included in the semiconductor wafer 40 is used as the second memory area 102. The second memory area 102 is used as a storage area for storing identification information sent by the host computer 2 to identify the semiconductor wafer 40 and a check code for checking the integrity of the identification information. The check code for checking the integrity of a certain identification information can be calculated from the identification information by mathematical calculation.

[0080] For example, the size of the identification information and the size of the check code corresponding to the identification information are predetermined. In the verification process for determining whether the set of identification information and the check code having a correct correspondence relationship is stored in the second memory area 102, for example, a part of the bit string read from the second memory area 102 is processed as the identification information, and the remaining part is processed as the check code. In addition, the example of the data structure for storing the identification information and the check code in the second memory area 102 is not limited to this example, and various other data structures can be used.

[0081] In the semiconductor wafer 40, other storage areas other than the second memory area 102 function as the first memory area 101 for storing user data or management data. The management data includes, for example, wafer control information required for writing and reading data to the semiconductor wafer 40. Examples of the wafer control information include, for example, a logical-physical address conversion table corresponding to the semiconductor wafer 40, defect information corresponding to the semiconductor wafer 40, and the like.

[0082] The first memory area 101 is used to store user data. Furthermore, the first memory area 101 may be used to store both user data and management data for the semiconductor wafer 40. In addition, the semiconductor wafer 40 may include a dedicated memory for storing a set of identification information and a check code as the second memory area 102.

[0083] Next, the detailed structure of the nonvolatile memory chip 70 according to the embodiment of the present invention will be described. Figure 3 1 is a diagram showing a configuration example of a plurality of nonvolatile memory chips 70 included in a semiconductor wafer 40 .

[0084] Each of the plurality of nonvolatile memory chips 70 included in the semiconductor wafer 40 is, for example, a NAND flash memory chip. The nonvolatile memory chip 70 may be implemented as a two-dimensional NAND flash memory or a three-dimensional NAND flash memory.

[0085] In NAND flash memory, data can only be written to a page once per erase cycle. That is, new data cannot be directly overwritten in an area within a block where data has been written. Therefore, in the case of updating (changing) written data, the controller 61 writes new data (updated data) to an unused area (unwritten area) within the block (or another block), and then treats the previous data as invalid data. In other words, the controller 61 writes the updated data corresponding to a certain logical address to another physical storage location, rather than the physical storage location corresponding to the logical address where the previous data is stored. Then, the controller 61 updates the L2P table, associates the logical address with the other physical storage location, and invalidates the previous data.

[0086] The memory cell array of the nonvolatile memory chip 70 includes a plurality of blocks (physical blocks) B0 to Bj-1. The blocks B0 to Bj-1 function as units of an erase operation.

[0087] Blocks B0 to Bj-1 include multiple pages (physical pages). That is, each of blocks B0 to Bj-1 includes pages P0, P1, ..., Pk-1. Each page includes multiple memory cells connected to the same word line. In each nonvolatile memory chip, data reading and data writing are performed in units of pages.

[0088] Next, use Figure 4 as well as Figure 5 , the detailed structure of the probe card 11 according to the embodiment of the present invention is described. Figure 4 The diagram shows a plurality of probes 51 arranged on the first surface 11A of the probe card 11 .

[0089] exist Figure 4 , a case where the same number of probes 51 as the number of pads 41 of all nonvolatile memory chips 70 of the semiconductor wafer 40 is arranged on the first surface 11A of the probe card 11 is exemplified.

[0090] In this case, the probes 51 of the probe card 11 are brought into contact with all the pads 41 of all the nonvolatile memory chips 70 in the semiconductor wafer 40 , and all the nonvolatile memory chips 70 can be controlled by the controller 61 .

[0091] Figure 5 This is a diagram showing a plurality of memory controllers constituting the controller 61 disposed on the second surface 11B of the probe card 11 .

[0092] exist Figure 5 , the controller 61 is implemented by 16 memory controllers 61 - 1, 61 - 2, ..., 61 - 16. When one semiconductor wafer 40 includes 1024 nonvolatile memory chips 70 and 16 memory controllers 61 - 1, 61 - 2, ..., 61 - 16 are arranged on the second surface 11B of the probe card 11, each memory controller only needs to control 64 nonvolatile memory chips via the probe 51.

[0093] The memory controllers 61 - 1 , 61 - 2 , . . . , and 61 - 16 may be connected to the host computer 2 via a switch circuit shared by the memory controllers 61 - 1 , 61 - 2 , . . . , and 61 - 16 .

[0094] Here, a specific example of the operation of the storage system 1 according to the embodiment of the present invention will be described. Figure 6 The diagram shows the relationship between the reader / writer (probe) 10 included in the storage device 3 and the storage device storage unit 30 .

[0095] exist Figure 6 In the example, the storage element #1 is placed on the workbench 12 of the reader / writer (probe) 10 as an online storage element, and the storage elements #2 and #3 are stored in the storage element storage unit 30 as offline storage elements. The storage element #2 is one of the semiconductor wafers with identification information, and the storage element #3 is one of the semiconductor wafers without identification information.

[0096] The controller 61 reads the identification information and the check code from the second memory area of ​​the semiconductor wafer conveyed to the reader and writer (probe) 10. Then, the host computer 2 or the controller 61 performs a verification process to determine whether the correspondence between the read identification information and the check code is correct.

[0097] When a semiconductor wafer with identification information (here, storage device #2) is transported to the reader and writer (detector) 10, it is determined that the correspondence between the read identification information and the check code is correct. In this case, the controller 61 obtains from the host computer 2 an L2P table associated with the identification information stored in the second memory area of ​​the semiconductor wafer with identification information (storage device #2). Alternatively, the controller 61 obtains from the storage device #2 an L2P table associated with the identification information stored in the second memory area of ​​the storage device #2. Alternatively, in the case where the L2P table associated with the identification information stored in the second memory area of ​​the storage device #2 is divided into an upper table and a lower table, the controller 61 may also obtain the upper table from the host computer 2 and obtain the lower table from the storage device #2. Then, the controller 61 uses the obtained L2P table to manage the mapping between each logical address and each physical address in units of a specified management size.

[0098] When a semiconductor wafer without identification information (here, storage element #3) is transported to the workbench 12 of the reader and writer (detector) 10, it is determined that the correspondence between the read identification information and the check code is incorrect. In this case, the controller 61 writes the identification information sent from the host computer 2 and the check code for checking the integrity of the identification information to the second memory area of ​​the storage element #3 based on a request from the host computer 2. Hereinafter, the check code for checking the integrity of the identification information is also referred to as the check code corresponding to the identification information.

[0099] The host computer 2 manages a plurality of defect information corresponding to a plurality of semiconductor wafers 40 having identification information. The defect information associated with a certain semiconductor wafer 40 indicates bad blocks contained in a plurality of nonvolatile memory chips in the semiconductor wafer 40. The controller 61 can obtain not only the L2P table associated with the identification information of the semiconductor wafer transported to the workbench 12, but also the defect information associated with the identification information of the semiconductor wafer from the host computer 2 or the first storage area in the semiconductor wafer 40 that does not contain bad blocks. Then, the controller 61 determines the write destination block to which the data from the host computer 2 should be written based on the acquired defect information to avoid the bad block from being selected as the write destination block.

[0100] Next, the detailed configuration of the controller 61 according to the embodiment of the present invention will be described. Figure 7 1 is a block diagram showing a configuration example of the controller 61 included in the reader / writer (probe) 10 .

[0101] The controller 61 includes a main interface circuit (main I / F) 111, a CPU 112, a NAND interface circuit (NAND I / F) 113, a dynamic RAM interface circuit (DRAM I / F) 114, a direct memory access controller (DMAC) 115, a static RAM (SRAM) 116, and an ECC encoding / decoding unit 117. The main interface circuit 111, the CPU 112, the NAND interface circuit 113, the dynamic RAM interface circuit 114, the direct memory access controller 115, the static RAM 116, and the ECC encoding / decoding unit 117 are connected via a bus 110.

[0102] The host interface circuit 111 is configured to perform communication with the host computer 2. The host interface circuit 111 receives various commands from the host computer 2. These commands include a write command (write request), a read command (read request), an erase command (erase), and other various commands.

[0103] A write instruction is an instruction (write request) for writing the data to be written (write data) to the non-volatile memory chip in the semiconductor wafer, and includes the logical address (starting LBA) where the write data should be written, the size of the write data (data length), a data pointer (buffer address) indicating the location in the memory of the host computer 2 where the write data is stored, etc.

[0104] A read instruction is an instruction (read request) for reading data from a non-volatile memory chip in a semiconductor wafer, and includes a logical address (starting LBA) corresponding to the data to be read, the size of the data (data length), a data pointer (buffer address) indicating the location in a read buffer in the memory of the host computer 2 to which the data should be transmitted, etc.

[0105] The erase command is a command (erase request) for erasing data written in each nonvolatile memory chip in a semiconductor wafer, and is used to put a memory cell group in each erase target block in the nonvolatile memory chip into an erased state.

[0106] The CPU 112 is a processor configured to control the host interface circuit 111, the NAND interface circuit 113, the dynamic RAM interface circuit 114, the direct memory access controller 115, the static RAM 116, and the ECC encoding / decoding unit 117. The CPU 112 loads a control program (firmware) from a ROM (not shown) to the static RAM 116 in response to power-on of the storage device 3, and then executes the firmware to perform various processes. The CPU 112 can perform instruction processing for processing various instructions from the host computer 2, the processing corresponding to the above-mentioned FTL, and the like.

[0107] The NAND interface circuit 113 is a memory control circuit configured to control each nonvolatile memory chip under the control of the CPU 112 .

[0108] The DRAM interface circuit 114 is a DRAM control circuit configured to control the DRAM under the control of the CPU 112. In addition, when the DRAM is connected to the controller 61, the firmware can also be loaded into the DRAM. In addition, a part of the storage area of ​​the DRAM can be used as a write buffer, and another part of the storage area of ​​the DRAM can be used to store the L2P table associated with the identification information of the semiconductor wafer 40.

[0109] The DMAC 115 executes data transfer between the memory of the host computer 2 and the static RAM 116 (or DRAM) under the control of the CPU 112 .

[0110] A portion of the storage area of ​​the static RAM 116 may also be used as a write buffer for temporarily storing data to be written to the semiconductor wafer 40. In addition, another portion of the storage area of ​​the static RAM 116 may also be used to store an L2P table associated with the identification information of the semiconductor wafer 40. A portion of the L2P table associated with the identification information of the semiconductor wafer 40 may also be stored in the static RAM 116 as an L2P table cache.

[0111] When data is to be written to a nonvolatile memory chip in the semiconductor wafer 40, the ECC encoding / decoding unit 117 encodes (ECC encoding) the data (data to be written) and adds an error correction code (ECC) to the data as a redundant code. When data is read from a nonvolatile memory chip in the semiconductor wafer 40, the ECC encoding / decoding unit 117 uses the ECC added to the read data to perform error correction (ECC decoding) on ​​the data.

[0112] Figure 8 1 is a flowchart showing the procedure of the identification information writing process executed in the controller 61 .

[0113] If the semiconductor wafer 40 to be accessed is placed on the workbench 12 in the reader and writer (probe) 10 (start), the controller 61 reads the identification information and the check code of the second memory area of ​​the semiconductor wafer 40 to be accessed. Then, a verification process is performed to determine whether the read identification information and the check code are in a correct corresponding relationship (step S11). The verification process can be performed by the controller 61 or by the host computer 2.

[0114] When the read identification information and the check code are not in a correct correspondence relationship (i.e., when the target wafer is not an identified wafer) (No in step S11), the controller 61 writes the identification information for identifying the semiconductor wafer 40 to be accessed and the check code corresponding to the identification information to the second memory area of ​​the semiconductor wafer 40 to be accessed based on the request from the host computer 2 (step S12). The identification information is issued by the host computer 2. The check code corresponding to the identification information may also be issued by the host computer 2, or may be calculated by the controller 61 based on the identification information.

[0115] Then, the controller 61 creates an L2P table associated with the identification information of the semiconductor wafer 40 to be accessed (step S13 ), and ends the processing (end).

[0116] When the read identification information and the check code are in a correct correspondence relationship (i.e., when the target wafer is an identified wafer) (yes in step S11), the controller 61 obtains the L2P table associated with the read identification information from the host computer 2 or the first memory area of ​​the semiconductor wafer 40 to be accessed (step S14), and ends the processing (end). In step S14, the controller 61 may also obtain the upper table of the L2P table associated with the read identification information from the host computer 2, and obtain the lower table from the first memory area of ​​the semiconductor wafer 40 to be accessed. Alternatively, in step S14, the controller 61 may also obtain both the L2P table associated with the read identification information and the defect information associated with the read identification information from the host computer 2. Alternatively, in step S14, the controller 61 may also obtain both the L2P table associated with the read identification information and the defect information associated with the read identification information from the first memory area of ​​the semiconductor wafer 40 to be accessed. Alternatively, in step S14, when the L2P table associated with the read identification information includes an upper table and a lower table, the controller 61 may obtain the upper table from the host computer 2, and obtain both the lower table and the defect information associated with the read identification information from the first memory area of ​​the semiconductor wafer 40 being accessed.

[0117] Fig. 9 1 is a flowchart showing the procedure of a data writing process and a data reading process executed in the controller 61 .

[0118] When receiving a request (start) from the host computer 2, the controller 61 determines whether the received request is a write request or a read request (step S15).

[0119] When the received request is a write request ("write request" in step S15), the controller 61 writes the write data (data from the host computer 2) to the physical storage location of the first memory area of ​​the semiconductor wafer 40 to be accessed (step S16). In step S16, the controller 61 determines the physical storage location to which the data should be written in such a manner that the bad block indicated by the acquired defect information is not selected as the write destination block.

[0120] Then, the controller 61 updates the L2P table associated with the identification information of the semiconductor wafer 40 to be accessed so that the physical address indicating the physical storage location where the write data is written is associated with the logical address specified by the write request (step S17 ), and ends the processing (end).

[0121] When the received request is a read request ("read request" in step S15), the controller 61 determines the physical address corresponding to the logical address specified by the read request by referring to the L2P table associated with the identification information of the semiconductor wafer 40 to be accessed (step S18). The physical address indicates the physical storage location in the first memory area where the read target data is stored.

[0122] The controller 61 reads the read target data from the physical storage position in the first memory area based on the determined physical address (step S19), sends it to the host computer 2, and ends the processing (end).

[0123] In this embodiment, a semiconductor wafer whose identification information and check code stored in the second memory area do not correspond correctly is identified as a wafer without identification information, thereby preventing a new semiconductor wafer just shipped from a factory from being mistakenly treated as a semiconductor wafer with identification information.

[0124] Thus, by writing the identification information and the check code corresponding to the identification information into the second memory area of ​​the semiconductor wafer, it is possible to correctly distinguish between a semiconductor wafer that has been written with data and a new semiconductor wafer that has just been shipped from the factory. If the identification information and the check code corresponding to the identification information are written into the second memory area of ​​a new semiconductor wafer that has just been shipped from the factory, data can be written and read from the semiconductor wafer.

[0125] Thus, the user can easily increase the storage capacity that can be handled by the storage system 1 simply by adding new semiconductor wafers immediately after being shipped from the factory to the storage device warehouse 30 .

[0126] In addition, when the second memory area of ​​the semiconductor wafer of the access object transported to the workbench 12 has stored a group of identification information and check codes with a correct correspondence, the semiconductor wafer of the access object is determined to be a wafer with data written (a semiconductor wafer with identification information), and then, the L2P table associated with the identification information of the semiconductor wafer of the access object is obtained from the host computer 2 or the semiconductor wafer of the access object. Thus, the controller 61 can refer to or update the correct L2P table corresponding to the identification information of the semiconductor wafer of the access object, so that the correspondence between each logical address used to access the semiconductor wafer of the access object and each physical address of the target wafer can be correctly managed, and in addition, the read object data specified by the host computer 2 can be correctly read from the semiconductor wafer of the access object.

[0127] In addition, when an L2P table associated with identification information of a semiconductor wafer to be accessed is obtained from the host computer 2, the L2P table can be quickly prepared on the SRAM 116 (or DRAM) of the controller 61, compared to a case where the L2P table is read from the semiconductor wafer to be accessed, thereby improving data read / write performance.

[0128] In addition, the host computer 2 manages multiple identification information corresponding to multiple semiconductor wafers on which identification information and check codes are written, and allows data to be written to the first memory area of ​​the semiconductor wafer transported to the workbench 12 and read from the first memory area of ​​the semiconductor wafer transported to the workbench 12 when the following conditions are met. The condition is that a group of identification information and check codes with a correct correspondence is stored in the second memory area of ​​the semiconductor wafer transported from the storage component storage unit 30 to the workbench 12 by the storage component transport mechanism 20, and the identification information stored in the second memory area of ​​the semiconductor wafer transported to the workbench 12 is consistent with the identification information of the semiconductor wafer of the access object specified by the host computer 2.

[0129] Thus, even when an unintended semiconductor wafer different from the semiconductor wafer to be accessed designated by the host computer 2 is transported from the storage stocker 30 to the stage 12 , data can be prevented from being written or read from the unintended semiconductor wafer.

[0130] Fig.10 1 is a flowchart showing the procedure of a process executed by the controller 61 to erase all data in a semiconductor wafer.

[0131] When the second memory area of ​​the semiconductor wafer (target wafer) transported to the workbench 12 already stores a set of identification information and a check code having a correct corresponding relationship, the controller 61 erases both the content of the first memory area of ​​the target wafer and the content of the second memory area of ​​the target wafer when erasing the data in the target wafer as a whole based on a request (erase request) from the host computer 2. Thus, the semiconductor wafer with identification information can be reused as a semiconductor wafer without identification information.

[0132] For example, the host computer 2 may send an erase request to the controller 61 to erase all data on the target wafer.

[0133] When the controller 61 receives an erase request for erasing all data of the target wafer from the host computer 2 (Yes in step S21 ), the controller 61 erases both the contents of the first memory area of ​​the target wafer and the contents of the second memory area of ​​the target wafer (step S22 ).

[0134] In this way, the host computer 2 can cause the controller 61 to erase both the contents of the first memory area of ​​the target wafer and the contents of the second memory area of ​​the target wafer by sending an erase request for erasing all data of the target wafer to the controller 61 .

[0135] Fig.11 It is a block diagram showing a configuration example of the host computer 2.

[0136] The host computer 2 includes a processor 201 , a main memory 202 , a system controller 203 , and the like.

[0137] The processor 201 executes various software loaded into the main memory 202 (e.g., DRAM). Such software may include, for example, an application 211, an operating system (OS) 212, a file system 213, a device driver 214 for controlling the storage device 3, a storage device management tool 216 for enabling a user to manage settings of the storage device 3, and the like.

[0138] In addition, the host computer 2 can manage the wafer identification information management table 301, the wafer position information 302, and the wafer control information 400 corresponding to each semiconductor wafer having identification information as management data for the plurality of semiconductor wafers 40 in the storage unit 30. Fig.11 As shown, the wafer identification information management table 301, the wafer location information 302, and the wafer control information 400 may be stored in the main memory 202. At least a portion of the wafer control information 400 corresponding to a semiconductor wafer 40 may also be stored in the first storage area of ​​the semiconductor wafer 40.

[0139] The host computer 2 is configured to send unique identification information to each semiconductor wafer 40. The host computer 2 manages the identification information of each storage element using the wafer identification information management table 301. Fig.11 In the example, storage element #1, storage element #2, and storage element #3 are semiconductor wafers with identification information, and storage element #4 is a semiconductor wafer without identification information. In this case, in the wafer identification information management table 301, the identification information (wafer ID #11) written in the second memory area of ​​storage element #1, the identification information (wafer ID #12) written in the second memory area of ​​storage element #2, and the identification information (wafer ID #13) written in the second memory area of ​​storage element #3 are managed.

[0140] In addition, the host computer 2 is configured to manage position information indicating the physical position (current physical position) of each semiconductor wafer stored in the storage unit storage section 30 using the wafer position information 302. The physical position of each semiconductor wafer indicates one of a plurality of wafer storage positions in the storage unit storage section 30 or a position on the workbench 12.

[0141] For example, when storage component #1 is present at the first wafer storage position in the storage component storage section 30, storage component #2 is present at the second wafer storage position in the storage component storage section 30, storage component #3 is present at the workbench 12 by being transported from the third wafer storage position in the storage component storage section 30 to the workbench 12, and storage component #4 is present at the fourth wafer storage position in the storage component storage section 30, in the wafer position information 302, a physical position L1 representing the first wafer storage position in the storage component storage section 30 is stored as the physical position of storage component #1, a physical position L2 representing the second wafer storage position in the storage component storage section 30 is stored as the physical position of storage component #2, a physical position S representing the position on the workbench 12 is stored as the physical position of storage component #3, and a physical position L4 representing the fourth wafer storage position in the storage component storage section 30 is stored as the physical position of storage component #4.

[0142] When storage device #1, storage device #2, and storage device #3 are semiconductor wafers with identification information, in the host computer 2, wafer control information #1 required for writing and reading data to storage device #1, wafer control information #2 required for writing and reading data to storage device #2, and wafer control information #3 required for writing and reading data to storage device #3 are managed.

[0143] Wafer control information #1 is associated with identification information (wafer ID #11) of the semiconductor wafer used as storage element #1. Wafer control information #2 is associated with identification information (wafer ID #12) of the semiconductor wafer used as storage element #2. Wafer control information #3 is associated with identification information (wafer ID #13) of the semiconductor wafer used as storage element #3.

[0144] Wafer control information #1 may also include L2P table #1 associated with wafer ID #11 and defect information #1 associated with wafer ID #11. L2P table #1 is a logical-physical address conversion table for managing the mapping between each logical address used by host computer 2 and each physical address of storage element #1 in order to access storage element #1. Defect information #1 shows bad blocks contained in multiple nonvolatile memory wafers in storage element #1.

[0145] Wafer control information #2 may also include L2P table #2 associated with wafer ID #12 and defect information #2 associated with wafer ID #12. L2P table #2 is a logical-physical address conversion table for managing the mapping between each logical address used by host computer 2 and each physical address of storage element #2 in order to access storage element #2. Defect information #2 respectively indicates bad blocks contained in a plurality of nonvolatile memory chips in storage element #2.

[0146] Wafer control information #3 may include L2P table #3 associated with wafer ID #13 and defect information #3 associated with wafer ID #13. L2P table #3 is a logical-physical address conversion table for managing the mapping between each logical address used by host computer 2 and each physical address of storage element #3 in order to access storage element #3. Defect information #3 respectively indicates bad blocks contained in a plurality of nonvolatile memory wafers in storage element #3.

[0147] In addition, the wafer control information corresponding to each storage device (semiconductor wafer) may also include information representing the following voltages, namely, the write voltage to be used in the write operation of each non-volatile memory chip of the corresponding semiconductor wafer, and the read voltage to be used in the read operation of each non-volatile memory chip of the corresponding semiconductor wafer.

[0148] Fig.12 This is a flowchart showing conditions under which “new writing process”, “additional writing process”, “reading process”, “wafer adding process”, and “wafer removing process” controlled by the host computer 2 should be executed.

[0149] "New write processing" refers to the initial write processing for writing data for the first time to a semiconductor wafer without identification information. A semiconductor wafer without identification information is, for example, a new semiconductor wafer that has just been shipped from a factory. No meaningful data has been written in the first memory area of ​​the new semiconductor wafer that has just been shipped from the factory, and no meaningful data (identification information, etc.) has been written in the second memory area.

[0150] The “additional writing process” refers to the second and subsequent writing processes for re-transporting the semiconductor wafer having the identification information from the storage medium stocker 30 to the stage 12 and re-writing data to the semiconductor wafer having the identification information.

[0151] The “reading process” refers to a process of reading data from a semiconductor wafer having identification information.

[0152] The “wafer addition process” refers to a process for adding management information required for managing new semiconductor wafers added by a user to the storage warehouse 30 just after shipment from a factory.

[0153] The “wafer removal process” refers to a process for deleting the management information corresponding to the semiconductor wafer removed from the storage warehouse 30 by the user.

[0154] Below, refer to Fig.12 The conditions under which each of “new writing process”, “additional writing process”, “reading process”, “wafer addition process” and “wafer removal process” should be executed are described with reference to the flowchart of FIG.

[0155] For example, when the request from the user (or application) is a read / write request for the storage device 3 ("read / write" in step S31), the host computer 2 determines whether the read / write request is a write request or a read request (step S32).

[0156] When the read / write request is a write request ("write" in step S32), the host computer 2 determines whether the write request is to write to a semiconductor wafer without identification information (new write) or to write to a semiconductor wafer with identification information (additional write) (step S33).

[0157] When the write request is a new write (“new write” in step S33 ), the host computer 2 executes a procedure for performing a “new write process” (step S34 ).

[0158] When the write request is for additional writing (“additional writing” in step S33 ), the host computer 2 executes a procedure for performing “additional writing processing” (step S35 ).

[0159] When the read / write request is a read request ("read" in step S32), the host computer 2 executes a procedure for performing a "reading process" (step S36).

[0160] When the request from the user (or application) is a wafer addition / removal request (“wafer addition / removal” in step S31 ), the host computer 2 determines whether the wafer addition / removal request is a wafer addition request or a wafer removal request (step S37 ).

[0161] When the wafer addition / removal request is a wafer addition request (“add” in step S37 ), the host computer 2 executes a procedure for performing a “wafer addition process” (step S38 ).

[0162] When the wafer addition / removal request is a wafer removal request (“remove” in step S37 ), the host computer 2 executes a procedure for performing “wafer removal processing” (step S39 ).

[0163] Fig.13 1 is a block diagram showing the storage system 1 in an initial state where no semiconductor wafer having identification information exists.

[0164] exist Fig.13 In the example, each of storage element #1, storage element #2, storage element #3, and storage element #4 is a semiconductor wafer without identification information (a new semiconductor wafer just after leaving the factory). No identification information is stored in the second memory area of ​​each of storage element #1, storage element #2, storage element #3, and storage element #4, and no check code is stored. No user data is written in the first memory area of ​​each of storage element #1, storage element #2, storage element #3, and storage element #4.

[0165] Storage element #1, storage element #2, and storage element #4 are respectively located at a first wafer storage position, a second wafer storage position, and a fourth wafer storage position in the storage element storage section 30 , and storage element #3 is located on the workbench 12 .

[0166] In the wafer position information 302 managed by the host computer 2, the physical positions of the storage unit #1, the storage unit #2, the storage unit #3, and the storage unit #4 are managed.

[0167] There is no wafer control information (L2P table, etc.) corresponding to each of the storage element #1, the storage element #2, the storage element #3, and the storage element #4.

[0168] Fig.14 This is a diagram for explaining “new write processing” executed in the storage system 1 .

[0169] exist Fig.14, the case where, after executing the “new write process” for the storage element #2 and the “new write process” for the storage element #1, the “new write process” for the storage element #3 is started is illustrated.

[0170] Each of the storage element #1 and the storage element #2 that have been subjected to the "new write process" becomes a semiconductor wafer with identification information. The identification information and the check code corresponding to the identification information are stored in the second memory area of ​​each of the storage element #1 and the storage element #2. In addition, user data is written in the first memory area of ​​each of the storage element #1 and the storage element #2 through the "new write process".

[0171] Each of the storage elements #3 and #4 is a semiconductor wafer without identification information. No identification information is stored in the second memory area of ​​each of the storage elements #3 and #4, and no check code is stored. No user data is written in the first memory area of ​​each of the storage elements #3 and #4.

[0172] After the execution of the "new write process" is completed, the storage component #1 is returned from the workbench 12 in the reader and writer (detector) 10 to the first wafer storage position in the storage component storage unit 30 where the storage component #1 originally existed. Instead, the storage component #3 is transported from the storage component storage unit 30 to the workbench 12 as the semiconductor wafer on which the "new write process" should be executed.

[0173] In this case, the physical positions of storage element #1 and storage element #3 are updated in wafer position information 302. The physical position of storage element #1 indicated by wafer position information 302 is updated from the position on stage 12 to the first wafer storage position in storage element warehouse 30.

[0174] The physical position of the storage element # 3 indicated by the wafer position information 302 is updated from the third wafer storage position in the storage element storage unit 30 to the position on the stage 12 .

[0175] Under the control of the host computer 2, the controller 61 reads the identification information and the check code from the second memory area of ​​the storage element #3. Then, a verification process is performed to determine whether the correspondence between the read identification information and the read check code is correct. The verification process can also be performed by either the host computer 2 or the controller 61, but the following example shows a case where the verification process is performed by the host computer 2.

[0176] The host computer 2 executes verification processing to determine whether the correspondence between the read identification information and the read check code is correct.

[0177] When the correspondence between the read identification information and the read check code is correct, it is determined that the read identification information is correct.

[0178] When the correspondence between the read identification information and the read check code is incorrect, it is determined that the read identification information is incorrect.

[0179] When the read identification information is incorrect, in other words, when it is confirmed that the second memory area of ​​storage element #3 does not store a group of identification information and check code with a correct corresponding relationship, the host computer 2 issues identification information for identifying storage element #3.

[0180] Then, the host computer 2 uses the controller 61 to write the sent identification information and the check code corresponding to the sent identification information into the second memory area of ​​the storage element #3. As a result, the host computer 2 is allowed to write data (user data) into the first memory area of ​​the storage element #3, thereby creating wafer control information associated with the identification information of the storage element #3.

[0181] The produced wafer control information includes the L2P table corresponding to the storage element #3, etc. The host computer 2 loads the wafer control information corresponding to the storage element #3 (the L2P table corresponding to the storage element #3, etc.) to the controller 61, or the controller 61 obtains the wafer control information corresponding to the storage element #3 (the L2P table corresponding to the storage element #3, etc.) from the host computer 2 or the first memory area of ​​the storage element #3, so that the wafer control information corresponding to the storage element #3 (the L2P table corresponding to the storage element #3, etc.) is stored in the SRAM 116 (or DRAM) of the controller 61.

[0182] Next, the controller 61 writes the data from the host computer 2 to the first memory area of ​​the storage device #3 in response to receiving the write request from the host computer 2. Then, the controller 61 updates the L2P table corresponding to the storage device #3.

[0183] Fig.15 This is a flowchart showing the procedure of a new write process controlled by a host computer.

[0184] The host computer 2 determines whether there is a target wafer without wafer control information and with wafer position information (step S41 ). Here, the target wafer without wafer control information and with wafer position information refers to a semiconductor wafer for which there is no corresponding wafer control information 400 and whose physical position is managed by the wafer position information 302 .

[0185] When the target wafer without wafer control information and with wafer position information does not exist ("does not exist" in step S41), since the target wafer capable of new writing processing does not exist, the host computer 2 determines that the processing cannot be performed (step S42) and ends the processing (end).

[0186] When a target wafer having no wafer control information and wafer position information exists (“exists” in step S41 ), the host computer 2 determines whether the target wafer is connected to the probe 51 based on the physical position of the target wafer indicated by the wafer position information 302 (step S43 ).

[0187] When the physical position of the target wafer indicates the position on the stage 12 , it is determined that the target wafer is connected to the probe 51 . On the other hand, when the physical position of the target wafer indicates a certain wafer storage position in the storage unit 30 , it is determined that the target wafer is not connected to the probe 51 .

[0188] When the target wafer is not connected to the probe 51 ("Not Connected" in step S43), the host computer 2 replaces the storage element on the workbench 12 with the target wafer in the storage element storage unit 30 by controlling the storage element 3 (storage element conveying mechanism 20), thereby connecting the target wafer to the probe 51 (step S44). In step S44, the host computer 2 may also send a conveying request to the storage element 3 for specifying the wafer storage position in the storage element storage unit 30 where the target wafer is stored. In step S44, the host computer 2 further updates the position information of each wafer after the replacement. When the target wafer is connected to the probe 51 ("Connected" in step S43), the host computer 2 skips the execution of the processing of step S44.

[0189] Next, the host computer 2 uses the controller 61 to read the identification information and the check code from the second memory area of ​​the target wafer, and confirms whether the read identification information is correct (step S45). In step S45, the host computer 2 performs a verification process to determine whether the correspondence between the identification information and the check code read from the second memory area is correct. If it is confirmed that the correspondence between the identification information and the check code is correct, it is determined that the read identification information is correct, in other words, the target wafer is a wafer with identification information. On the other hand, if it is confirmed that the correspondence between the identification information and the check code is incorrect, it is determined that the read identification information is incorrect, in other words, the target wafer is a wafer without identification information. Generally speaking, in the case where the target wafer is a new semiconductor wafer just after manufacturing, the values ​​read from the second memory area as identification information and check code are random values. In this case, the read identification information and the read check code have no relationship with each other, so it can be determined that the read identification information is incorrect, in other words, the target wafer is a wafer without identification information.

[0190] When it is determined that the identification information is correct (“correct = identification information exists” in step S45 ), since an irregular state occurs in which identification information is stored in a wafer without wafer control information, the host computer 2 determines it as an error (step S46 ) and ends the processing (end).

[0191] On the other hand, when it is determined that the identification information is incorrect ("incorrect = no identification information" in step S45), the host computer 2 issues identification information for identifying the target wafer, and then sends a prescribed request for writing the identification information to the controller 61, and writes the issued identification information and the check code corresponding to the issued identification information into the second memory area of ​​the target wafer (step S47). In step S47, the controller 61 writes the identification information and the check code corresponding to the identification information into the second memory area of ​​the target wafer in response to receiving the prescribed request from the host computer 2.

[0192] The host computer 2 writes data (user data) to the first memory area of ​​the target wafer by sending a write request to the controller 61 (step S48). In step S48, the controller 61 writes the data (user data) from the host computer 2 to the physical storage location in the first memory area of ​​the target wafer according to the reception of the write request from the host computer 2.

[0193] The host computer 2 adds the produced control information to the wafer control information 400 (step S49) in such a manner that the produced control information is associated with the identification information of the target wafer, and ends the processing (end). In step S49, the controller 61 obtains the wafer control information (L2P table, etc.) corresponding to the target wafer from the host computer 2 or the first memory area of ​​the target wafer, and updates the L2P table corresponding to the target wafer in such a manner that the physical address representing the physical storage location in the first memory area where the user data is written is associated with the logical address specified by the write request. Moreover, at a predetermined timing, the controller 61 also performs a process of writing back the contents of the updated L2P table to the main memory of the host computer 2 or the first memory area of ​​the target wafer.

[0194] Fig.16 This is a diagram for explaining the additional writing process executed in the storage system 1 .

[0195] exist Fig.16 , the case where additional writing processing is performed on the storage material #3 having identification information stored in the storage material storage unit 30 is exemplified.

[0196] When storage component #1 (storage component with identification information) exists on the workbench 12, storage component #1 is returned from the workbench 12 in the reader and writer (detector) 10 to the first wafer storage position in the storage component storage unit 30 where storage component #1 originally existed or to other vacant wafer storage positions in the storage component storage unit 30, and storage component #3 is transported from the storage component storage unit 30 to the workbench 12 as the semiconductor wafer to be accessed and to be subjected to "additional write processing".

[0197] In the wafer position information 302, the physical position of the storage element #1 and the physical position of the storage element #3 are updated. The physical position of the storage element #1 indicated by the wafer position information 302 is updated from the position on the worktable 12 to the first wafer storage position in the storage element storage section 30. The physical position of the storage element #3 indicated by the wafer position information 302 is updated from the third wafer storage position in the storage element storage section 30 to the position on the worktable 12.

[0198] Under the control of the host computer 2, the controller 61 reads the identification information and the check code from the second memory area of ​​the storage element #3. Then, a verification process is performed to determine whether the correspondence between the read identification information and the read check code is correct. The verification process may be performed by either the host computer 2 or the controller 61, but the following example shows a case where the verification process is performed by the host computer 2.

[0199] The host computer 2 executes a verification process to determine whether the correspondence between the read identification information and the read check code is correct.

[0200] When the correspondence between the read identification information and the read check code is correct, it is determined that the read identification information is correct.

[0201] When the correspondence between the read identification information and the read check code is incorrect, it is determined that the read identification information is incorrect.

[0202] When the correspondence between the read identification information and the read check code is correct, the host computer 2 determines whether the read identification information is consistent with the identification information (wafer ID #13) of the storage element #3 managed by the host computer 2 in order to confirm that the semiconductor wafer transported to the workbench 12 is the semiconductor wafer to be written (here, the storage element #3). When the read identification information is consistent with the identification information (wafer ID #13) of the storage element #3 managed by the host computer 2, it can be confirmed that the semiconductor wafer transported to the workbench 12 is the storage element #3. In this case, the host computer 2 performs "additional writing processing" on the storage element #3, in other words, allows data to be written to the first memory area of ​​the storage element #3 having the identification information.

[0203] The wafer control information corresponding to the storage component #3 (such as the L2P table corresponding to the storage component #3) is loaded into the controller 61 through the main computer 2, or the controller 61 obtains the wafer control information corresponding to the storage component #3 (such as the L2P table corresponding to the storage component #3) from the main computer 2 or the first memory area of ​​the storage component #3, thereby storing the wafer control information corresponding to the storage component #3 (such as the L2P table corresponding to the storage component #3) in the SRAM116 (or DRAM) of the controller 61.

[0204] Next, in response to receiving a write request from the host computer 2, the controller 61 writes the data from the host computer 2 into the first memory area of ​​the storage device #3. Then, the controller 61 updates the L2P table corresponding to the storage device #3.

[0205] Fig.17 This is a flowchart showing a part of the procedure of the additional writing process controlled by the host computer 2 .

[0206] The host computer 2 determines whether there is a target wafer having wafer control information and wafer position information (step S51). Here, the target wafer having wafer control information and wafer position information refers to a semiconductor wafer having corresponding wafer control information 400 and whose physical position is managed.

[0207] If there is no target wafer having wafer control information and wafer position information ("not present" in step S51), since there is no target wafer capable of additional writing, the host computer 2 determines that the processing cannot be performed (step S52) and ends the processing (end).

[0208] In the case where there is a target wafer with wafer control information and wafer position information ("existence" in step S51), the host computer 2 determines the identification information of the target wafer based on the wafer control information 400 and the wafer position information 302 (step S53). In step S53, based on the wafer control information 400 and the wafer position information 302, a wafer that satisfies the conditions that the corresponding wafer control information 400 exists and the physical position is managed may be searched as the target wafer, and then the identification information corresponding to the searched wafer is obtained from the wafer identification information management table 301.

[0209] Next, the host computer 2 determines whether the target wafer is connected to the probe 51 based on the physical position of the target wafer indicated by the wafer position information 302 (step S54 ).

[0210] When the physical position of the target wafer indicates the position on the stage 12 , the target wafer is determined to be connected to the probe 51 . On the other hand, when the physical position of the target wafer indicates a wafer storage position in the storage unit 30 , the target wafer is determined to be not connected to the probe 51 .

[0211] When the target wafer is not connected to the probe 51 ("Not Connected" in step S54), the host computer 2 replaces the target wafer in the storage unit storage section 30 with the storage unit on the workbench 12 by controlling the storage unit conveying mechanism 20 of the storage unit 3, thereby connecting the target wafer to the probe 51 (step S55). In step S55, the host computer 2 may also send a conveyance request to the storage unit 3 for specifying the wafer storage position in the storage unit storage section 30 where the target wafer is stored. In step S55, the host computer 2 further updates the position information of each replaced wafer. When the target wafer is connected to the probe 51 ("Connected" in step S54), the host computer 2 skips the execution of the processing of step S55.

[0212] Next, the host computer 2 uses the controller 61 to read the identification information and the check code from the second memory area of ​​the target wafer, and confirms whether the read identification information is correct (step S56). In step S56, the host computer 2 performs a verification process to determine whether the correspondence between the identification information read from the second memory area and the check code is correct. If it is confirmed that the correspondence between the identification information and the check code is correct, it is determined that the read identification information is correct, in other words, the target wafer is a wafer with identification information. On the other hand, if it is confirmed that the correspondence between the identification information and the check code is incorrect, it is determined that the read identification information is incorrect, in other words, the target wafer is a wafer without identification information.

[0213] When it is determined that the identification information is incorrect ("incorrect = no identification information" in step S56), since an irregular state occurs in which the wafer with wafer control information does not store the identification information, the host computer 2 determines it as an error (step S57) and ends the processing (end). For example, when a new semiconductor wafer just after manufacturing is mistakenly transported to the workbench 12, the values ​​read from the second memory area of ​​the semiconductor wafer as identification information and check code are random values. In this case, since the read identification information and the read check code have no relationship with each other, it can be determined that the read identification information is incorrect, in other words, the target wafer is a wafer without identification information. Therefore, by determining whether the correspondence between the identification information and the check code is correct, it is possible to prevent the random value stored in the second memory area of ​​the new semiconductor wafer just after leaving the factory from being mistakenly processed as identification information, thereby causing the new semiconductor wafer (wafer without identification information) just after leaving the factory to be mistakenly accessed.

[0214] On the other hand, when it is determined that the identification information is correct ("correct = identification information exists" in step S56), the host computer 2 determines whether the read identification information matches the identification information determined in advance in step S53 (step S58).

[0215] When the read identification information is inconsistent with the identification information predetermined in step S53 ("inconsistent" in step S58), since a wafer different from the desired wafer (another wafer with identification information) is transported to the workbench 12, the host computer 2 determines that it is an error (step S59) and ends the processing (end). In this case, the possibility that the wafer position information is destroyed is also considered.

[0216] If the read identification information matches the identification information determined in advance in step S53 ("matched" in step S58), the process proceeds to step S54. Fig.18 Step S60.

[0217] In step S60, the host computer 2 loads the wafer control information associated with the identification information of the target wafer (L2P table associated with the identification information of the target wafer, etc.) to the controller 61. In step S60, the controller 61 may also obtain the wafer control information associated with the identification information of the target wafer (L2P table associated with the identification information of the target wafer, etc.) from the host computer 2 or the first memory area of ​​the target wafer.

[0218] Then, the host computer 2 sends a write request to the controller 61, thereby writing data (user data) to the first memory area of ​​the target wafer (step S61). In step S61, the controller 61 writes the data (user data) from the host computer 2 to the physical storage location in the first memory area of ​​the target wafer according to the reception of the write request from the host computer 2.

[0219] Then, the controller 61 updates the L2P table corresponding to the target wafer in such a manner that the physical address indicating the physical storage location in the first memory area where the user data is written is associated with the logical address specified by the write request (step S62), and the process ends (end). Furthermore, at a predetermined timing, the controller 61 also performs a process of writing the updated L2P table content back to the main memory of the host computer 2 or the first memory area of ​​the target wafer.

[0220] Fig.19 This is a diagram for explaining a read process executed in the storage system 1 .

[0221] exist Fig.19 In FIG. 1 , a case where a storage element # 3 having identification information stored in the storage element storage unit 30 is read out is exemplified.

[0222] When storage component #1 (storage component with identification information) is present on the workbench 12, storage component #1 is returned from the workbench 12 in the reader and writer (detector) 10 to the first wafer storage position in the storage component storage unit 30 where storage component #1 originally existed, and storage component #3 is transported from the storage component storage unit 30 to the workbench 12 as the semiconductor wafer to be accessed and to be subjected to "read processing".

[0223] In the wafer position information 302, the physical position of the storage element #1 and the physical position of the storage element #3 are updated. The physical position of the storage element #1 indicated by the wafer position information 302 is updated from the position on the worktable 12 to the first wafer storage position in the storage element storage section 30. The physical position of the storage element #3 indicated by the wafer position information 302 is updated from the third wafer storage position in the storage element storage section 30 to the position on the worktable 12.

[0224] Under the control of the host computer 2, the controller 61 reads the identification information and the check code from the second memory area of ​​the storage element #3. Then, a verification process is performed to determine whether the correspondence between the read identification information and the read check code is correct. The verification process may be performed by either the host computer 2 or the controller 61, but the following example shows a case where the verification process is performed by the host computer 2.

[0225] The host computer 2 executes a verification process to determine whether the correspondence between the read identification information and the read check code is correct.

[0226] When the correspondence between the read identification information and the read check code is correct, it is determined that the read identification information is correct.

[0227] When the correspondence between the read identification information and the read check code is incorrect, it is determined that the read identification information is incorrect.

[0228] When the correspondence between the read identification information and the read check code is correct, the host computer 2 determines whether the read identification information is consistent with the identification information (wafer ID #13) of the storage element #3 managed by the host computer 2 in order to confirm that the semiconductor wafer transported to the workbench 12 is the semiconductor wafer to be read (here, the storage element #3). When the read identification information is consistent with the identification information (wafer ID #13) of the storage element #3 managed by the host computer 2, it can be confirmed that the semiconductor wafer transported to the workbench 12 is the storage element #3. In this case, the host computer 2 performs a "reading process" on the storage element #3, in other words, allows data to be read from the first memory area of ​​the storage element #3 having the identification information.

[0229] The wafer control information corresponding to the storage component #3 (such as the L2P table corresponding to the storage component #3) is loaded into the controller 61 through the main computer 2, or the controller 61 obtains the wafer control information corresponding to the storage component #3 (such as the L2P table corresponding to the storage component #3) from the main computer 2 or the first memory area of ​​the storage component #3, thereby storing the wafer control information corresponding to the storage component #3 (such as the L2P table corresponding to the storage component #3) in the SRAM116 (or DRAM) of the controller 61.

[0230] Next, in response to receiving the read request from the host computer 2, the controller 61 obtains the physical address corresponding to the logical address specified by the read request by referring to the L2P table corresponding to the storage element #3. The controller 61 reads data from the first memory area of ​​the storage element #3 based on the obtained physical address. Then, the controller 61 sends the read data to the host computer 2.

[0231] Fig. 20 This is a flowchart showing a part of the procedure of the readout process.

[0232] The host computer 2 determines whether there is a target wafer having wafer control information and wafer position information (step S71). Here, the target wafer having wafer control information and wafer position information refers to a semiconductor wafer having corresponding wafer control information 400 and whose physical position is managed.

[0233] If there is no target wafer having wafer control information and wafer position information ("not present" in step S71), since there is no target wafer storing data to be read, the host computer 2 determines that processing cannot be performed (step S72) and ends the processing (end).

[0234] When the target wafer with wafer control information and wafer position information exists ("exists" in step S71), the host computer 2 determines the identification information of the target wafer based on the wafer control information 400 and the wafer position information 302 (step S73). In step S73, the host computer 2 can also search for a wafer that satisfies the conditions that the corresponding wafer control information 400 exists and the physical position is managed based on the wafer control information 400 and the wafer position information 302 as the target wafer, and then obtain the identification information corresponding to the searched wafer from the wafer identification information management table 301.

[0235] Next, the host computer 2 determines whether the target wafer is connected to the probe 51 based on the physical position of the target wafer indicated by the wafer position information 302 (step S74 ).

[0236] When the physical position of the target wafer indicates the position on the stage 12 , the target wafer is determined to be connected to the probe 51 . On the other hand, when the physical position of the target wafer indicates a wafer storage position in the storage unit 30 , the target wafer is determined to be not connected to the probe 51 .

[0237] When the target wafer is not connected to the probe 51 ("Not Connected" in step S74), the host computer 2 replaces the target wafer in the storage storage unit 30 with the storage unit on the workbench 12 by controlling the storage unit conveying mechanism 20 of the storage unit 3, thereby connecting the target wafer to the probe 51 (step S75). In step S75, the host computer 2 may also send a conveying request to the storage unit 3 for specifying the wafer storage position in the storage unit storage unit 30 where the target wafer is stored. In step S75, the host computer 2 further updates the position information of each replaced wafer. When the target wafer is connected to the probe 51 ("Connected" in step S74), the host computer 2 skips the execution of the processing of step S75.

[0238] Next, the host computer 2 uses the controller 61 to read the identification information and the check code from the second memory area of ​​the target wafer, and confirms whether the read identification information is correct (step S76). In step S76, the host computer 2 performs a verification process to determine whether the correspondence between the identification information read from the second memory area and the check code is correct. If it is confirmed that the correspondence between the identification information and the check code is correct, it is determined that the read identification information is correct, in other words, the target wafer is a wafer with identification information. On the other hand, if it is confirmed that the correspondence between the identification information and the check code is incorrect, it is determined that the read identification information is incorrect, in other words, the target wafer is a wafer without identification information.

[0239] When it is determined that the identification information is incorrect ("incorrect = no identification information" in step S76), since an irregular state occurs in which the wafer with wafer control information does not store the identification information, the host computer 2 determines it as an error (step S77) and ends the processing (end). For example, in the case where a new semiconductor wafer just after manufacturing is mistakenly transported to the workbench 12, the values ​​read from the second memory area of ​​the semiconductor wafer as identification information and check codes are random values. In this case, since the read identification information and the read check code have no relationship with each other, it can be determined that the read identification information is incorrect, in other words, the target wafer is a wafer without identification information. Therefore, by determining whether the correspondence between the identification information and the check code is correct, it is possible to prevent a new semiconductor wafer (wafer without identification information) that has just been shipped from the factory from being mistakenly accessed as a semiconductor wafer with identification information that has been used for data writing.

[0240] On the other hand, when it is determined that the identification information is correct ("correct = identification information exists" in step S76), the host computer 2 determines whether the read identification information matches the identification information determined in advance in step S73 (step S78).

[0241] When the read identification information is inconsistent with the identification information predetermined in step S73 ("inconsistent" in step S78), since a wafer different from the desired wafer (another wafer with identification information) is transported to the workbench 12, the host computer 2 determines that it is an error (step S79) and ends the processing (end). In this case, the possibility that the wafer position information is destroyed is also considered.

[0242] If the read identification information matches the identification information determined in advance in step S73 ("matched" in step S78), the process proceeds to step S74. Fig.21 Step S80.

[0243] In step S80, the host computer 2 loads the wafer control information associated with the identification information of the target wafer (L2P table associated with the identification information of the target wafer, etc.) to the controller 61. In step S80, the controller 61 may also obtain the wafer control information associated with the identification information of the target wafer (L2P table associated with the identification information of the target wafer, etc.) from the host computer 2 or the first memory area of ​​the target wafer.

[0244] Then, the host computer 2 sends a read request to the controller 61 to read data (user data) from the first memory area of ​​the target wafer (step S81 ), and ends the process (end).

[0245] In step S81, the controller 61 refers to the L2P table associated with the identification information of the target wafer, and obtains from the L2P table the physical address corresponding to the logical address specified by the read request received from the host computer 2. The controller 61 reads data from the first memory area of ​​the target wafer based on the obtained physical address. Then, the controller 61 sends the read data to the host computer 2.

[0246] Fig. 22 This is a diagram for explaining a wafer adding process executed in the storage system 1 .

[0247] exist Fig. 22 3, the example shows a case where a storage element #5 is physically added by a user to, for example, the fifth wafer storage position in the storage element storage unit 30, while the physical positions of the storage elements #1 to #4 are managed by the wafer position information 302. The storage element #5 is, for example, a new semiconductor wafer (a wafer without identification information) that has just been shipped from a factory.

[0248] In this case, the host computer 2 adds the location information indicating the physical location of the storage element #5 to the wafer location information 302. The fact that a new storage element (semiconductor wafer) is physically added to the storage element storage section 30 and the wafer storage position in the storage element storage section 30 to which the new storage element (semiconductor wafer) is physically added can be automatically detected by sensors provided at each storage position in the storage element storage section 30. Alternatively, the fact that a new storage element is physically added to the storage element storage section 30 can be detected by the host computer 2 by inputting information indicating that a new storage element is physically added to the storage element storage section 30 by the user operating the storage element management tool 216 and information indicating the storage position to which the new storage element is physically added as a trigger.

[0249] Fig.23 This is a flowchart showing the procedure of wafer addition processing.

[0250] When the host computer 2 detects that a new storage component (semiconductor wafer) is physically added to the wafer storage position within the storage component storage unit 30 (yes in step S91), the host computer 2 adds the location information representing the physical location of the new storage component to the wafer position information 302 (step S92) and ends the processing (end).

[0251] The wafer control information corresponding to the added new storage element may also be produced when a new write process is performed on the added new storage element. In addition, the identification information corresponding to the added new storage element may also be issued when a new write process is performed on the added new storage element.

[0252] Fig.24 It is a diagram for explaining a wafer removal process executed in the storage system 1 .

[0253] exist Fig.24 3 shows an example in which the physical positions of storage elements #1 to #4 are managed by wafer position information 302, and storage element #4 is removed from storage element warehouse 30 by a user. Storage element #4 is a semiconductor wafer having identification information.

[0254] In this case, the host computer 2 deletes the position information indicating the physical position of the storage element #4 from the wafer position information 302. In addition, the host computer 2 may also delete the wafer control information associated with the identification information of the storage element #4.

[0255] The fact that a storage element has been removed from the storage element storage section 30 and the wafer storage position in the storage element storage section 30 from which the storage element has been removed can be automatically detected by sensors provided at each storage position in the storage element storage section 30. Alternatively, the fact that a storage element has been removed from the storage element storage section 30 can be detected by the host computer 2 by inputting information indicating that a user has removed a storage element by operating the storage element management tool 216 and information indicating the storage position from which the storage element has been removed into the host computer 2 as a trigger.

[0256] Fig.25 : is a flowchart showing the sequence of wafer removal processing.

[0257] When the host computer 2 detects that the storage component (semiconductor wafer) is physically removed from the storage component storage unit 30 (yes in step S101), the host computer 2 deletes the position information representing the physical position of the physically removed storage component from the wafer position information 302 (step S102) and ends the processing (end).

[0258] In the case where there is wafer control information corresponding to the physically removed storage element, the host computer 2 may also delete the wafer control information corresponding to the physically removed storage element.

[0259] As described above, according to this embodiment, the controller 61 writes the identification information and the check code for checking the integrity of the identification information into the second memory area of ​​the semiconductor wafer 40. Thus, the semiconductor wafers already written with data can be correctly distinguished from new semiconductor wafers just shipped from the factory.

[0260] When the second memory area of ​​the target wafer transported to the worktable 12 stores a group of identification information and a check code having a correct correspondence relationship, the controller 61 obtains the L2P table associated with the identification information of the target wafer from the host computer 2 or the first memory area of ​​the target wafer. Thus, the controller 61 can refer to or update the correct L2P table corresponding to the identification information of the target wafer, and thus can correctly manage the correspondence between each logical address used to access the target wafer and each physical address of the target wafer, and can also correctly read the read target data designated by the host computer 2 from the target wafer.

[0261] On the other hand, if the second memory area of ​​the target wafer transported to the workbench 12 does not store a set of identification information and a check code having a correct corresponding relationship, the controller 61 writes the identification information for identifying the target wafer and the check code for checking the integrity of the identification information into the second memory area of ​​the target wafer based on a request from the host computer 2. Thus, data can be written and read from the target wafer. Thus, for example, the user can easily increase the storage capacity that can be processed by the storage system 1 by simply adding a new semiconductor wafer that has just been shipped from the factory to the storage storage unit 30.

[0262] In addition, the host computer 2 manages a plurality of identification information corresponding to a plurality of semiconductor wafers in which the identification information and the check code are written. Furthermore, the host computer 2 stores a group of identification information and the check code having a correct corresponding relationship in the second memory area of ​​the semiconductor wafer transported from the storage storage unit 30 to the worktable 12 by the storage transport mechanism 20, and when the identification information stored in the second memory area of ​​the semiconductor wafer transported to the worktable 12 is consistent with the identification information of the semiconductor wafer of the access object specified by the host computer 2, the writing of data to the first memory area of ​​the semiconductor wafer transported to the worktable 12 and the reading of data from the first memory area of ​​the semiconductor wafer transported to the worktable 12 are allowed. Thus, even when an undesired semiconductor wafer different from the semiconductor wafer of the access object specified by the host computer 2 is transported from the storage storage unit 30 to the worktable 12, the writing or reading of data to the undesired semiconductor wafer can be prevented, and the reliability of the storage system 1 using the semiconductor wafer as a storage element can be improved.

[0263] In addition, the host computer 2 manages the wafer storage locations where the semiconductor wafers 40 are stored. The host computer 2 can instruct the storage device 3 (storage device transport mechanism 20) to transport the semiconductor wafer 40 to be accessed from the designated wafer storage location in the storage device storage unit 30 to the workbench 12 in the reader and writer (probe) 10 by sending a transport request to the storage device 3 to specify the wafer storage location where the semiconductor wafer 40 to be accessed is stored. Therefore, the host computer 2 can transport the desired semiconductor wafer 40 from the plurality of semiconductor wafers 40 in the storage device storage unit 30 to the workbench 12.

[0264] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the subject matter of the invention. These embodiments and their variations are included in the scope and subject matter of the invention, and are included in the invention described in the claims and the scope of their equivalents.

[0265] Description of Reference Numerals

[0266] 1 Storage System

[0267] 2 Host Computer

[0268] 3 Storage Devices

[0269] 10 Readers and writers (detectors)

[0270] 11 Probe Card

[0271] 12 Workbench

[0272] 13. Drive unit

[0273] 20 Storage unit conveying mechanism

[0274] 21 Support

[0275] 22 Pallets

[0276] 40 Semiconductor Wafer

[0277] 41 Electrode (pad)

[0278] 51 Probe pin (probe)

[0279] 61 Controller

[0280] 61-1, 61-2, 61-3, 61-4, 61-5, 61-6, 61-7, 61-8, 61-9, 61-10, 61-11, 61-12, 61-13, 61-14, 61-15, 61-16 Storage controller

[0281] 70 Non-volatile memory chip

[0282] 101 First memory area

[0283] 102 Second memory area

[0284] B0, B1, B2, Bj - 1 block

[0285] P0, P1, Pk-1 page

[0286] 110 Bus

[0287] 111 Main interface circuit (main I / F)

[0288] 112 CPU

[0289] 113 NAND interface circuit (NANDI / F)

[0290] 114 Dynamic RAM Interface Circuit (DRAMI / F)

[0291] 115 Direct Memory Access Controller (DMAC)

[0292] 116 Static RAM (SRAM)

[0293] 117 ECC encoding / decoding unit

[0294] 201 Processor

[0295] 202 Main memory

[0296] 203 System Controller

[0297] 211 Applications

[0298] 212 Operating System (OS)

[0299] 213 File System

[0300] 214 Device Driver

[0301] 216 Storage Management Tools

[0302] 301 Wafer Identification Information Management Table

[0303] 302 Wafer location information

[0304] 400 Wafer control information

Claims

1. A storage device comprising: A workbench capable of placing a semiconductor wafer capable of writing or reading data; A plurality of probe pins for writing or reading data; and A controller, connected with the probe pin, The semiconductor wafer comprises: an electrode capable of being connected to the probe pin; a first memory area capable of storing user data; as well as a second memory area capable of storing identification information for identifying the semiconductor wafer and a check code for checking integrity of the identification information, The controller can read the identification information and the check code from the second memory area.

2. The memory device according to claim 1, The controller writes the first identification information for identifying the semiconductor wafer and the first check code for checking the integrity of the first identification information into the second memory area when the second memory area does not store a group of identification information and check code with a correct corresponding relationship.

3. The memory device according to claim 1, When a group of identification information and a check code having a correct correspondence relationship is stored in the second memory area, the controller obtains a first logical-physical address conversion table associated with the identification information stored in the second memory area from the outside or the first memory area.

4. The memory device according to any one of claims 1 to 3, The semiconductor wafer also has a plurality of memory chips. The electrode, the first memory area, and the second memory area are included in the memory chip.

5. The memory device according to claim 1, It also has a probe card. The probe pins and the controller are included in the probe card.

6. The memory device according to claim 5, It also has a drive unit. The driving unit moves the probe card or the stage to bring the electrodes of the first semiconductor wafer placed on the stage into contact with the probe pins.

7. The memory device according to claim 1, It also has a storage unit capable of storing a plurality of semiconductor wafers.

8. The memory device according to claim 7, A conveying mechanism for conveying semiconductor wafers from the storage unit to the workbench is also provided. The transport mechanism can replace the semiconductor wafer placed on the worktable with any one of the plurality of semiconductor wafers in the storage unit.

9. The memory device according to claim 7 or 8, The controller writes different identification information into each of the plurality of semiconductor wafers.

10. The memory device according to claim 9, The controller checks whether the identification information written is correct for each semiconductor wafer based on the check code, and writes or reads from the memory chip of the semiconductor wafer only when the identification information written is correct.

11. The memory device according to claim 1, The controller is configured as follows: When a pair of identification information and a check code having a correct correspondence relationship is stored in the second memory area, Acquire a first logical-physical address conversion table associated with the identification information from the outside or the first memory area, In response to receiving a write request, writing data to a physical storage location in the first memory area, and updating the first logical-physical address translation table in such a way as to associate a physical address representing the physical storage location with a logical address specified by the write request, In response to reception of a read request, a physical address corresponding to a logical address specified by the read request is acquired by referring to the first logical-physical address conversion table, and data is read from the first memory area based on the acquired physical address.

12. The memory device according to claim 1, The controller is configured to obtain a first logical-physical address conversion table associated with the identification information of the semiconductor wafer and first defect information associated with the identification information of the semiconductor wafer from the outside or the first memory area when a group of identification information and a check code having a correct correspondence relationship is stored in the second memory area, The first defect information indicates bad blocks included in a plurality of nonvolatile memories in the semiconductor wafer.

13. The memory device according to claim 1, The controller is configured to erase both the content of the first memory area and the content of the second memory area when erasing the entire content of the first memory area.

14. A storage system comprising a host computer and a storage device, wherein: The storage device comprises: a reader and writer capable of mounting a probe card; and The storage department can store multiple semiconductor wafers. The reader and writer comprises: a workbench capable of being loaded with one of the plurality of semiconductor wafers; as well as Drive unit, The probe card comprises: a plurality of probe pins; and A controller, connected with the probe pin, Each semiconductor wafer of the plurality of semiconductor wafers comprises: an electrode capable of being connected to the probe pin; a first memory area capable of storing user data; as well as The second memory area is capable of storing identification information for identifying the semiconductor wafer and a check code for checking the integrity of the identification information. The driving unit moves the probe card or the stage so that the electrodes of the first semiconductor wafer placed on the stage come into contact with the probe pins. The controller is configured as follows: According to a write request or a read request from the host computer, data can be written or read from the first semiconductor wafer. In a case where a set of identification information and a check code having a correct corresponding relationship is not stored in the second memory area of ​​the first semiconductor wafer, based on a request from the host computer, first identification information for identifying the first semiconductor wafer and a first check code for checking the integrity of the first identification information are written into the second memory area of ​​the first semiconductor wafer, When a group of identification information and check codes having a correct correspondence is stored in the second memory area of ​​the first semiconductor wafer, a first logical-physical address conversion table associated with the identification information of the first semiconductor wafer is obtained from the host computer or the first memory area of ​​the first semiconductor wafer.

15. The storage system according to claim 14, In a case where a group of identification information and check codes with a correct correspondence is not stored in the second memory area of ​​the first semiconductor wafer, after the first identification information and the first check code are written into the second memory area of ​​the first semiconductor wafer through the controller, data is written to the first memory area of ​​the first semiconductor wafer through the controller.

16. The storage system according to claim 14, The controller is configured as follows: When a set of identification information and a check code having a correct correspondence relationship is stored in the second memory area of ​​the first semiconductor wafer, obtain the first logical-physical address conversion table from the host computer or the first memory area of ​​the first semiconductor wafer, writing data to a physical storage location in the first memory area of ​​the first semiconductor wafer in response to receiving a write request from the host computer, and updating the first logical-physical address conversion table in such a manner as to associate a physical address representing the physical storage location with a logical address specified by the write request, In response to receiving a read request from the host computer, the physical address corresponding to the logical address specified by the read request is obtained by referring to the first logical-physical address conversion table, and data is read from the first memory area of ​​the first semiconductor wafer based on the obtained physical address.

17. The storage system according to claim 14, The host computer is configured to manage a plurality of logical-physical address conversion tables and a plurality of defect information corresponding to a plurality of semiconductor wafers, each of which has identification information and a check code for checking integrity of the identification information written therein. Each defect information indicates a bad block included in a plurality of nonvolatile memories in a corresponding semiconductor wafer. The controller is configured to obtain the first logical-physical address conversion table associated with the identification information of the first semiconductor wafer and the first defect information associated with the identification information of the first semiconductor wafer from the host computer or the first memory area of ​​the first semiconductor wafer when a group of identification information and a check code having a correct corresponding relationship is stored in the second memory area of ​​the first semiconductor wafer. The first defect information indicates bad blocks included in a plurality of nonvolatile memories in the first semiconductor wafer.

18. The storage system according to claim 14, The host computer is configured to cause the controller to erase both the content of the first memory area of ​​the first semiconductor wafer and the content of the second memory area of ​​the first semiconductor wafer when erasing all the data in the first memory area of ​​the first semiconductor wafer.

19. The storage system according to claim 14, The host computer, managing a plurality of identification information corresponding to each of a plurality of semiconductor wafers into which the identification information and a check code for checking the integrity of the identification information are written, A group of identification information and check codes having a correct correspondence is stored in the second memory area of ​​the first semiconductor wafer, and when the identification information stored in the second memory area is consistent with the identification information of the semiconductor wafer of the access object specified by the host computer, writing of data to the first memory area of ​​the first semiconductor wafer and reading of data from the first memory area of ​​the first semiconductor wafer are allowed.

20. The storage system according to claim 14, The main computer is configured to determine whether a group of identification information and check codes with a correct correspondence is stored in the second memory area of ​​the first semiconductor wafer by performing a verification process to determine whether the correspondence between the identification information read from the second memory area of ​​the first semiconductor wafer and the check code is correct.

21. The storage system according to claim 14, The host computer is configured to manage position information indicating a physical position where each of the plurality of semiconductor wafers exists. The physical location indicates whether the items are stored at the workbench or at the storage section, or, if stored at the storage section, at which location in the storage section the items are stored.

Images