Stage circuit and scan driver including the stage circuit

Abstract

A stage circuit and a scan driver including the stage circuit are provided. The stage circuit includes a first sub-stage circuit unit connected to a first input terminal to a third input terminal for receiving a start signal, a first clock signal, and a second clock signal, respectively. The first sub-stage circuit unit generates a first operation signal and a second operation signal based on the start signal, the first clock signal, and the second clock signal, and supplies a first scan signal to a first output terminal based on the first operation signal and the second operation signal. The stage circuit also includes a second sub-stage circuit unit connected to a third input terminal and a fourth input terminal for receiving a third clock signal. The second sub-stage circuit unit supplies a second scan signal to a second output terminal based on the first operation signal, the second operation signal, the second clock signal, and the third clock signal. The first scan signal and the second scan signal include a pulse of a low voltage level and a pulse of a high voltage level, respectively.

Description

[0001] This application claims priority from Korean Patent Application No. 10-2020-0006108, filed on January 16, 2020, the disclosure of which is hereby incorporated by reference in its entirety. Technical Field

[0002] The disclosed exemplary embodiments relate to a stage circuit and a scan driver including the stage circuit. Background Art

[0003] As information technology advances, the importance of display devices increases. Therefore, the use of display devices, such as, for example, liquid crystal display (LCD) devices or organic light emitting diode (OLED) display devices, has been increasing.

[0004] The pixels included in the OLED display device can be implemented using NMOS transistors and PMOS transistors to minimize leakage current. Each of the NMOS transistors and PMOS transistors included in such a pixel can be driven by a scan signal. In this case, the scan driver may include a stage circuit that supplies a high-level scan signal corresponding to the NMOS transistor and a low-level scan signal corresponding to the PMOS transistor. Summary of the invention

[0005] When a scan signal of a high level is generated, power consumption may increase due to continuous charging and discharging of some capacitors included in the stage circuit.

[0006] An object of the disclosed exemplary embodiments is to provide a stage circuit for reducing power consumption that may occur due to a capacitor included in the stage circuit and a scan driver including the stage circuit.

[0007] Another object of the disclosed exemplary embodiments is to provide a stage circuit for simultaneously supplying a scan signal including a pulse of a low level and a scan signal including a pulse of a high level, and a scan driver including the stage circuit.

[0008] The objects of the disclosed exemplary embodiments are not limited to the above objects, and other technical objects not described above will be clearly understood by those skilled in the art through the following description.

[0009] The stage circuit according to the disclosed exemplary embodiment for solving the above-mentioned purpose includes: a first sub-stage circuit unit, connected to a first input terminal receiving a start signal, a second input terminal receiving a first clock signal, and a third input terminal receiving a second clock signal. The first sub-stage circuit unit generates a first operation signal and a second operation signal corresponding to the start signal, the first clock signal, and the second clock signal, and supplies a first scan signal to the first output terminal corresponding to the first operation signal and the second operation signal. The stage circuit also includes a second sub-stage circuit unit connected to a third input terminal and a fourth input terminal receiving a third clock signal. The second sub-stage circuit unit supplies a second scan signal to the second output terminal corresponding to the first operation signal, the second operation signal, the second clock signal, and the third clock signal. The first scan signal includes a pulse of a low voltage level, and the second scan signal includes a pulse of a high voltage level.

[0010] Each of the first and second sub-stage circuit units may be connected to a first power input terminal and a second power input terminal. The first power input terminal may receive a first power set as a gate-off voltage, and the second power input terminal may receive a second power set as a gate-on voltage.

[0011] The first sub-stage circuit unit may include a first output unit connected to the third input terminal and the first power input terminal, and may supply a first scan signal to the first output terminal in response to a voltage of the first node and a voltage of the second node. The first sub-stage circuit unit may also include a first driver connected to the first input terminal and the first power input terminal, and may control the voltage of the third node in response to a first clock signal and a second clock signal. The first sub-stage circuit unit may also include a second driver connected to the second input terminal, the first power input terminal, the second power input terminal, and the third node, and may control the voltage of the first node and the voltage of the second node.

[0012] The first driver may include a first transistor, a second transistor, and a third transistor, the first transistor being connected between the first input terminal and the third node and having a gate electrode connected to the second input terminal, the second transistor and the third transistor being connected in series between the first power input terminal and the third node. The gate electrode of the second transistor may be connected to the third input terminal, and the gate electrode of the third transistor may be connected to the first node.

[0013] The first output unit may include a fourth transistor and a fifth transistor, the fourth transistor being connected between the first power input terminal and the first output terminal and having a gate electrode connected to the first node, and the fifth transistor being connected between the third input terminal and the first output terminal and having a gate electrode connected to the second node.

[0014] The second driver may include: a sixth transistor connected between the second node and the third node and having a gate electrode connected to the second power input terminal; a seventh transistor connected between the first node and the second input terminal and having a gate electrode connected to the third node; an eighth transistor connected between the first node and the second power input terminal and having a gate electrode connected to the second input terminal; a first capacitor connected between the second node and the first output terminal; and a second capacitor connected between the first node and the first power input terminal.

[0015] The first operating signal may be a voltage of the first node, and the second operating signal may be a voltage of the third node.

[0016] The first operating signal may be a voltage of the first node, and the second operating signal may be a voltage of the second node.

[0017] The second sub-stage circuit unit may include a second output unit connected to a fourth input terminal and a second power input terminal, and may supply a second scan signal to the second output terminal in response to a voltage of the fourth node and a voltage of the fifth node. The second sub-stage circuit unit may also include a third driver connected to a third input terminal, a first power input terminal, a second power input terminal, a sixth node, and a seventh node, and may control the voltage of the fifth node in response to a second operation signal supplied to the sixth node and a first operation signal supplied to the seventh node. The second sub-stage circuit may also include a fourth driver connected to the third input terminal, the second power input terminal, and the sixth node, and may control the voltage of the fourth node. The sixth node and the third node may be the same node, and the seventh node and the first node may be the same node.

[0018] The third driver may include: a ninth transistor connected between the fifth node and the seventh node and having a gate electrode connected to the second power input terminal; a tenth transistor connected between the third input terminal and the eighth node and having a gate electrode connected to the fifth node; an eleventh transistor connected between the first power input terminal and the eighth node and having a gate electrode connected to the sixth node; and a third capacitor connected between the fifth node and the eighth node.

[0019] The fourth driver may include: a twelfth transistor connected between the sixth node and the ninth node and having a gate electrode connected to the second power input terminal; a thirteenth transistor connected between the third input terminal and the tenth node and having a gate electrode connected to the ninth node; a fourteenth transistor connected between the fourth node and the tenth node and having a gate electrode connected to the third input terminal; and a fourth capacitor connected between the ninth node and the tenth node.

[0020] The second output unit may include: a fifteenth transistor connected between the fourth node and the fourth input terminal and having a gate electrode connected to the fifth node; a sixteenth transistor connected between the fourth input terminal and the second output terminal and having a gate electrode connected to the fourth node; a seventeenth transistor connected between the second power input terminal and the second output terminal and having a gate electrode connected to the fifth node; and a fifth capacitor connected between the fourth input terminal and the fourth node.

[0021] The first clock signal and the second clock signal may have the same cycle, and in one cycle, the high voltage supply period may be set to be longer than the low voltage supply period. The second clock signal may be set to be a signal shifted from the first clock signal by half a cycle, and the third clock signal may be a signal having a phase inverted from the phase of the second clock signal.

[0022] The start signal may be a scan start signal or a first scan signal of a previous first sub-stage circuit unit.

[0023] The scan driver according to the disclosed exemplary embodiment for solving the above-mentioned purpose includes a plurality of stage circuits, and the plurality of stage circuits are configured to supply a first scan signal including a pulse of a low voltage level to a first scan line and a second scan signal including a pulse of a high voltage level to a second scan line. Each of the plurality of stage circuits includes a first sub-stage circuit unit connected to a first input terminal, a second input terminal, and a third input terminal receiving different clock signals, the first sub-stage circuit unit generates a first operation signal and a second operation signal corresponding to a voltage of the first input terminal, a voltage of the second input terminal, and a voltage of the third input terminal, and supplies a first scan signal to a first output terminal corresponding to the first operation signal and the second operation signal. Each of the plurality of stage circuits also includes a second sub-stage circuit unit connected to a third input terminal and a fourth input terminal receiving a clock signal, and the second sub-stage circuit unit supplies a second scan signal to a second output terminal corresponding to the first operation signal, the second operation signal, the voltage of the third input terminal, and the voltage of the fourth input terminal.

[0024] The first sub-stage circuit unit may include: a first output unit connected to the third input terminal and the first power input terminal, and supplying a first scan signal to the first output terminal in response to a voltage of the first node and a voltage of the second node; a first driver connected to the first input terminal, the second input terminal, the third input terminal, the first power input terminal, and the first power input terminal, and controlling a voltage of the third node; and a second driver connected to the second input terminal, the first power input terminal, the second power input terminal, and the third node, and controlling a voltage of the first node and a voltage of the second node. The first power input terminal may supply a gate-off voltage, and the second power input terminal may supply a gate-on voltage.

[0025] The second sub-stage circuit unit may include: a second output unit, connected to the fourth input terminal and the second power input terminal, and supplies a second scan signal to the second output terminal in response to the voltage of the fourth node and the voltage of the fifth node; a third driver, connected to the third input terminal, the first power input terminal, the second power input terminal, the sixth node and the seventh node, and controls the voltage of the fifth node in response to the second operation signal supplied to the sixth node and the first operation signal supplied to the seventh node; and a fourth driver, connected to the third input terminal, the second power input terminal and the sixth node, and controls the voltage of the fourth node.

[0026] In odd-numbered stages, the second input terminal may receive the first clock signal, the third input terminal may receive the second clock signal, and the fourth input terminal may receive the third clock signal. In even-numbered stages, the second input terminal may receive the second clock signal, the third input terminal may receive the first clock signal, and the fourth input terminal may receive the fourth clock signal.

[0027] The first clock signal and the second clock signal may have the same cycle, and in one cycle, the high voltage supply period may be set to be longer than the low voltage supply period. The second clock signal may be set to be a signal shifted from the first clock signal by half a cycle, the third clock signal and the fourth clock signal may have the same cycle, in one cycle, the high voltage supply period may be set to be shorter than the low voltage supply period, and the fourth clock signal may be set to be a signal shifted from the third clock signal by half a cycle.

[0028] The third clock signal may be a signal having a phase inverted from that of the second clock signal, and the fourth clock signal may be a signal having a phase inverted from that of the first clock signal.

[0029] The stage circuit and the scan driver including the stage circuit according to the disclosed exemplary embodiments may maintain a voltage across both ends of a capacitor included in the stage circuit at a high level to prevent continuous charging and discharging and improve power consumption characteristics.

[0030] In addition, the stage circuit and the scan driver including the stage circuit according to the disclosed exemplary embodiment can use one stage to simultaneously supply a high-level scan signal and a low-level scan signal. Therefore, the installation area of ​​the stage circuit can be minimized or reduced, and the manufacturing cost can be reduced.

[0031] The effects according to the exemplary embodiments are not limited to the details shown above, and various additional effects are included in the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other features of the disclosure will become more apparent by further describing exemplary embodiments of the disclosure in detail with reference to the accompanying drawings, in which:

[0033] Figure 1 is a diagram schematically illustrating a display device according to an exemplary embodiment;

[0034] Figure 2 It is shown that the Figure 1 A diagram of an example of a pixel in a display device of FIG. 1 ;

[0035] Figure 3 is a method for describing a driver according to an exemplary embodiment. Figure 2 A diagram of the method for pixels shown in ;

[0036] Figure 4 is a diagram schematically illustrating a scan driver according to an exemplary embodiment;

[0037] Figure 5 is a schematic diagram showing a Figure 4 A waveform diagram of a scanning signal of a scanning driver;

[0038] Figure 6 It is shown Figure 4 A diagram of an example of a stage circuit and a connection stage of the stage circuit shown in FIG.

[0039] Figure 7 is a diagram showing a method according to an exemplary embodiment Figure 4 A circuit diagram of one of the stage circuits shown in ;

[0040] Figure 8 is a method for describing a driver according to an exemplary embodiment. Figure 7 The waveform diagram of the method of the stage circuit shown in ;

[0041] Fig. 9 is a circuit diagram showing a stage circuit according to an exemplary embodiment; and

[0042] Fig.10 is a circuit diagram illustrating a stage circuit according to an exemplary embodiment. DETAILED DESCRIPTION

[0043] Hereinafter, the disclosed exemplary embodiments will be described more fully with reference to the accompanying drawings.Throughout the drawings, like reference numerals may refer to like elements.

[0044] It will be understood that when an element is referred to as being "on," "connected to," "coupled to," or "adjacent to" another element, the element can be directly on, directly connected to, directly coupled to, or directly adjacent to the other element, or intervening elements may be present. It will also be understood that when an element is referred to as being "between" two elements, the element can be the only element between the two elements, or one or more intervening elements may also be present. Other words used to describe the relationship between elements should be interpreted in a like manner.

[0045] It will also be understood that the terms "first", "second", "third", etc. are used herein to distinguish one element from another element, and the elements are not limited by these terms. Therefore, the "first" element in an exemplary embodiment may be described as the "second" element in another exemplary embodiment.

[0046] It will also be understood that descriptions of features or aspects within each exemplary embodiment should typically be considered as available for other similar features or aspects in other exemplary embodiments, unless the context clearly dictates otherwise.

[0047] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0048] Figure 1 is a diagram schematically illustrating a display device 10 according to an exemplary embodiment.

[0049] Reference Figure 1 , a display device 10 according to an exemplary embodiment may include a display unit 100 , a scan driver 200 , a data driver 300 , an emission driver 400 , and a timing controller 500 .

[0050] The display unit 100 can display an image. The display unit 100 can be implemented as a display panel. The display unit 100 can include various display elements, such as an organic light-emitting element (e.g., an organic light-emitting diode (OLED)) as an example. Hereinafter, for ease of explanation, the display device 10 will be described as an OLED display device including an organic light-emitting element as a display element. However, the disclosure is not limited thereto. For example, in an exemplary embodiment, the display device 10 can be various types of display devices, such as a liquid crystal display (LCD) device, an electrophoretic display (EPD) device, and an inorganic light-emitting display device as an example.

[0051] The display unit 100 includes data lines DL1 to DLm (where m is a positive integer), first scan lines SPL1 to SPLn (where n is a positive integer), second scan lines SNL1 to SNLn, emission control lines EL1 to ELn, and pixels PX.

[0052] The pixels PX may be connected to the data lines DL1 to DLm, the first scan lines SPL1 to SPLn, the second scan lines SNL1 to SNLn, and the emission control lines EL1 to ELn, respectively. The pixels PX may emit or supply light of predetermined brightness to the outside corresponding to data signals transmitted through the data lines DL1 to DLm.

[0053] However, the pixel PX is not limited thereto. For example, the pixel PX may be electrically connected to the first scan line and the second scan line corresponding to adjacent rows (e.g., the first scan line and the second scan line corresponding to the previous row of the row including the pixel PX and the first scan line and the second scan line corresponding to the next row of the row including the pixel PX).

[0054] In addition, the pixel PX can be electrically connected to the first power line and the second power line to receive the voltage of the first power VDD and the voltage of the second power VSS. The first power VDD and the second power VSS can be the power used to drive the pixel PX and the drivers 200, 300 and 400. The first power VDD can supply a high level of voltage, and the second power VSS can supply a low level of voltage. In addition, the pixel PX can be electrically connected to the initialization power line to further receive the initialization power VINT.

[0055] Will refer to later Figure 2 and Figure 3 The detailed configuration and operation of the pixel PX are described.

[0056] The scan driver 200 may generate first and second scan signals based on the gate control signal GCS, and provide the first and second scan signals to the first and second scan lines SPL1 to SPLn and SNL1 to SNLn.

[0057] The scan driver 200 may include a plurality of stage circuits, each of which may provide a first scan signal for the first scan lines SPL1 to SPLn and a second scan signal for the second scan lines SNL1 to SNLn.

[0058] The first scan signals supplied to the first scan lines SPL1 to SPLn may be scan signals including pulses of a low level, and the second scan signals supplied to the second scan lines SNL1 to SNLn may be scan signals including pulses of a high level.

[0059] For example, when the first scan signal is supplied to the gate electrode of the N-type transistor, the N-type transistor may be turned on. It can be assumed that a voltage of a sufficiently low level compared to the gate electrode of the N-type transistor is applied to the source electrode of the N-type transistor. The above-mentioned N-type transistor may be an N-type metal oxide semiconductor (NMOS) transistor. In addition, when the second scan signal is supplied to the gate electrode of the P-type transistor, the P-type transistor may be turned on. It can be assumed that a voltage of a sufficiently high level compared to the gate electrode of the P-type transistor is applied to the source electrode of the P-type transistor. The P-type transistor may be a P-type metal oxide semiconductor (PMOS) transistor.

[0060] The gate control signal GCS is a signal for controlling the operation of the scan driver 200, and may include a gate start pulse (or scan start signal) and one or more gate shift clocks. The gate start pulse may control the start timing of the first scan signal and the second scan signal, and the gate shift clock may refer to one or more clock signals for shifting the gate start pulse.

[0061] The scan driver 200 may be implemented as a shift register, but is not limited thereto. The scan driver 200 may be directly formed in an area of ​​the display unit 100 (or an area of ​​the display panel), or may be implemented as an integrated circuit and mounted on a flexible circuit board connected to the display unit 100.

[0062] The data driver 300 may generate a data signal based on the image data DATA2 and the data control signal DCS, and provide the data signal to the data lines DL1 to DLm in units of pixel rows. The data control signal DCS may be a signal for controlling the operation of the data driver 300, and may include, for example, a load signal, a data start signal, a data clock signal, etc.

[0063] The emission driver 400 may generate an emission signal based on the emission control signal ECS and provide the emission signal to the emission control lines EL1 to ELn. For example, the emission driver 400 may sequentially provide an emission signal having a pulse of an off level to the emission control lines EL1 to ELn. The emission driver 400 may be implemented as a shift register, but is not limited thereto.

[0064] The timing controller 500 may receive input image data DATA1 (e.g., RGB data) and input control signals from an external device (e.g., a graphics processor). The input image data DATA1 may include a grayscale value corresponding to each pixel PX. The input control signal may include, for example, a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a main clock signal MCLK, a data enable signal DE, and the like.

[0065] The vertical synchronization signal Vsync may include a plurality of pulses and may indicate the end of the previous frame period and the start of the current frame period based on the time point at which each pulse is generated. The interval between adjacent pulses of the vertical synchronization signal Vsync may be equal to one frame period 1FP (refer to Figure 3 )correspond.

[0066] The horizontal synchronization signal Hsync may include a plurality of pulses and may indicate the end of a previous horizontal period and the start of a new horizontal period based on the time point at which each pulse is generated. The interval between adjacent pulses of the horizontal synchronization signal Hsync may be the same as one horizontal period 1H (refer to Figure 5 )correspond.

[0067] The timing controller 500 may generate image data DATA2 based on input image data DATA1, and may generate a gate control signal GCS, a data control signal DCS, and an emission control signal ECS based on an input control signal. The timing controller 500 may provide the gate control signal GCS to the scan driver 200, the data control signal DCS and the image data DATA2 to the data driver 300, and the emission control signal ECS to the emission driver 400.

[0068] Figure 2 It is shown that the Figure 1 FIG. 1 is a diagram of an example of one of the pixels PX in the display device 10 .

[0069] Reference Figure 2 , a pixel PXij according to an exemplary embodiment may include first to seventh transistors M1, M2, M3, M4, M5, M6, and M7, a storage capacitor Cst, and a light emitting element LD.

[0070] According to an exemplary embodiment, Figure 1 Each pixel PX shown in FIG. Figure 2 The pixels PXij shown in are constructed in the same way.

[0071] Referring to the first transistor M1, the first electrode may be connected to the first electrode of the second transistor M2, the second electrode may be connected to the first electrode of the third transistor M3, and the gate electrode may be connected to the second electrode of the third transistor M3. The first transistor M1 may also be referred to as a driving transistor.

[0072] Referring to the second transistor M2, a first electrode may be connected to the first electrode of the first transistor M1, a second electrode may be connected to the data line DLj, and a gate electrode may be connected to the first scan line SPLi. The second transistor M2 may also be referred to as a scan transistor.

[0073] Referring to the third transistor M3, the first electrode may be connected to the second electrode of the first transistor M1, the second electrode may be connected to the gate electrode of the first transistor M1, and the gate electrode may be connected to the second scan line SNLi. The third transistor M3 may also be referred to as a diode-connected transistor.

[0074] Referring to the fourth transistor M4, the first electrode may be connected to the second electrode of the storage capacitor Cst, the second electrode may be connected to the initialization power line VINTL, and the gate electrode may be connected to the previous second scan line SNLi-1. The previous second scan line SNLi-1 may be a line that provides a second scan signal to the previous pixel row. The fourth transistor M4 may also be referred to as a gate initialization transistor.

[0075] Referring to the fifth transistor M5, a first electrode may be connected to the first power line VDDL, a second electrode may be connected to the first electrode of the first transistor M1, and a gate electrode may be connected to the emission control line ELi. The fifth transistor M5 may also be referred to as a first emission control transistor.

[0076] Referring to the sixth transistor M6, the first electrode may be connected to the second electrode of the first transistor M1, the second electrode may be connected to the anode electrode of the light emitting element LD, and the gate electrode may be connected to the emission control line ELi. The sixth transistor M6 may also be referred to as a second emission control transistor.

[0077] Referring to the seventh transistor M7, the first electrode may be connected to the anode electrode of the light emitting element LD, the second electrode may be connected to the initialization power line VINTL, and the gate electrode may be connected to the next first scan line SPLi+1. The next first scan line SPLi+1 may be a line for providing a first scan signal to the next pixel row. The seventh transistor M7 may also be referred to as an anode initialization transistor.

[0078] Referring to the storage capacitor Cst, a first electrode may be connected to the first power line VDDL, and a second electrode may be connected to the gate electrode of the first transistor M1.

[0079] Referring to the light emitting element LD, the anode electrode may be connected to the second electrode of the sixth transistor M6, and the cathode electrode may be connected to the second power line VSSL. A voltage applied to the second power line VSSL may be set lower than a voltage applied to the first power line VDDL.

[0080] The light emitting element LD may be, for example, an organic light emitting diode, an inorganic light emitting diode, a quantum dot light emitting diode, or the like.

[0081] The first transistor M1, the second transistor M2, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 may be P-type transistors. The channels of the first transistor M1, the second transistor M2, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 may be constructed of polysilicon. For example, the polysilicon transistor may be a low temperature polysilicon (LTPS) transistor. The polysilicon transistor may have high electron mobility and thus may have fast driving characteristics.

[0082] The third transistor M3 and the fourth transistor M4 may be N-type transistors. The channels of the third transistor M3 and the fourth transistor M4 may be constructed of oxide semiconductors. Oxide semiconductor transistors are capable of low temperature processes and may have low charge mobility compared to polysilicon. Therefore, the amount of leakage current generated in the off state of the oxide semiconductor transistor may be smaller than the amount of leakage current generated in the off state of the polysilicon transistor.

[0083] In an exemplary embodiment, the first scan line SPLi instead of the next first scan line SPLi+1 may be connected to the gate electrode of the seventh transistor M7.

[0084] In addition, in an exemplary embodiment, the seventh transistor M7 may be constructed of an oxide semiconductor transistor instead of polysilicon. That is, the seventh transistor M7 may be an N-type transistor. One of the second scan line SNLi and the previous second scan line SNLi-1 may be connected to the gate electrode of the seventh transistor M7 by replacing the next first scan line SPLi+1.

[0085] Figure 3 is a method for describing a driver according to an exemplary embodiment. Figure 2 FIG. 5 shows the method for a pixel PXij shown in FIG.

[0086] Reference Figure 2 and Figure 3 , the frame period 1FP may include a data writing period WP and an emission period EP.

[0087] First, the emission signal EM of a turn-off level (eg, a high level) may be supplied to the emission control line ELi during the data writing period WP. Therefore, the fifth transistor M5 and the sixth transistor M6 may be turned off during the data writing period WP.

[0088] Next, the previous second scan line SNLi-1 may be supplied with a previous second scan signal SN-1 of a turn-on level (e.g., a high level). Therefore, the fourth transistor M4 may be turned on, and the gate electrode of the first transistor M1 and the initialization power line VINTL may be connected to each other. The voltage of the gate electrode of the first transistor M1 may be initialized to the initialization voltage of the initialization power line VINTL and maintained by the storage capacitor Cst. The initialization voltage of the initialization power line VINTL may be a voltage sufficiently lower than the voltage of the first power line VDDL. For example, the initialization voltage may be a voltage equal to the voltage of the second power line VSSL or a voltage lower than the voltage of the second power line VSSL. Therefore, the first transistor M1 may be turned on.

[0089] Next, the first scan line SPLi may be supplied with a first scan signal SP of a conduction level (e.g., a low level), and the second scan line SNLi may be supplied with a second scan signal SN of a conduction level (e.g., a high level). Therefore, the second transistor M2 and the third transistor M3 corresponding to the first scan line SPLi and the second scan line SNLi, respectively, may be turned on. The data voltage applied to the data line DLj may be written to the storage capacitor Cst through the second transistor M2, the first transistor M1, and the third transistor M3. That is, the data voltage corresponding to the grayscale value of the pixel PXij may be written to the storage capacitor Cst. At this time, the data voltage written to the storage capacitor Cst may be a voltage in which the reduction of the threshold voltage of the first transistor M1 is reflected.

[0090] Finally, the next first scan line SPLi+1 may be supplied with a next first scan signal SP+1 of a turn-on level (eg, a low level), and the seventh transistor M7 may be turned on. Thus, the voltage of the anode electrode of the light emitting element LD may be initialized.

[0091] Thereafter, when the data write period WP ends, the emission signal EM may be at a conduction level (e.g., a low level), and the emission period EP may begin. The fifth transistor M5 and the sixth transistor M6 may be turned on according to the conduction level emission signal EM. Therefore, a drive current path connected to the first power line VDDL, the fifth transistor M5, the first transistor M1, the sixth transistor M6, the light emitting element LD, and the second power line VSSL may be formed, and the drive current may flow. The amount of the drive current may correspond to the data voltage stored in the storage capacitor Cst. At this time, since the drive current flows through the first transistor M1, the reduction in the threshold voltage of the first transistor M1 may be reflected. Therefore, since the reduction in the threshold voltage reflected in the data voltage stored in the storage capacitor Cst and the reduction in the threshold voltage reflected in the drive current are offset from each other, the drive current corresponding to the data voltage supplied by the data line DLj may flow, regardless of the threshold voltage value of the first transistor M1. That is, the light emitting element LD may emit light of desired brightness according to the above drive current amount in the emission period EP.

[0092] In an exemplary embodiment, for ease of description, each scan signal includes one pulse. However, the disclosure is not limited thereto. For example, in an exemplary embodiment, each scan signal may include a plurality of pulses. In this case, a process of applying a turn-on bias voltage before a desired data voltage is written to the first transistor M1 may be included, and the hysteresis phenomenon of the pixel PXij may be improved.

[0093] Figure 4 is a diagram schematically illustrating a scan driver 200 according to an exemplary embodiment. Figure 5 is a schematic diagram showing a Figure 4 2 is a waveform diagram of a scan signal of the scan driver 200.

[0094] Reference Figure 4 and Figure 5 , the scan driver 200 according to the exemplary embodiment may include a plurality of stage circuits ST1 to STn. Each of the stage circuits ST1 to STn may be connected to the corresponding clock lines CLKL1, CLKL2, CLKL3, and CLKL4 and the previous end scan line (or carry line). However, since there is no previous scan line of the first stage circuit ST1, the first stage circuit ST1 may be connected to the scan start line.

[0095] In addition, the stage circuits ST1 to STn may be connected to each other in the form of a shift register. Each of the stage circuits ST1 to STn may be connected to a corresponding first scan line among the first scan lines SPL1 to SPLn and a corresponding second scan line among the second scan lines SNL1 to SNLn, and may supply first scan signals SP1 to SPn and second scan signals SN1 to SNn to the first scan lines SPL1 to SPLn and the second scan lines SNL1 to SNLn in response to a start signal. The start signal may be a scan start signal FLM or a first scan signal of a previous stage circuit.

[0096] For example, the first stage circuit ST1 may supply the first scan signal SP1 (the first scan signal SP1 may include a pulse of a low voltage level) and the second scan signal SN1 (the second scan signal SN1 may include a pulse of a high voltage level) to the first scan line SPL1 and the second scan line SNL1 connected to the first stage circuit ST1, respectively, corresponding to the scan start signal FLM. The remaining stage circuits ST2 to STn may supply the first scan signals SP2 to SPn and the second scan signals SN2 to SNn to the first scan lines SPL2 to SPLn and the second scan lines SNL2 to SNLn connected thereto, respectively, corresponding to the carry signals CR1 to CRn-1 supplied from the previous stage circuit. The carry signals CR1 to CRn-1 may correspond to the first scan signals SP1 to SPn-1 outputted from the previous stage circuit, respectively.

[0097] Each of the stage circuits ST1 to STn may receive three clock signals among four clock signals CLK1 to CLK4 supplied to the scan driver 200 .

[0098] For example, the odd-numbered stage circuits (e.g., ST1, etc.) may receive the first clock signal CLK1, the second clock signal CLK2, and the third clock signal CLK3, and the even-numbered stage circuits (e.g., ST2, etc.) may receive the first clock signal CLK1, the second clock signal CLK2, and the fourth clock signal CLK4. That is, although both the odd-numbered stage circuits and the even-numbered stage circuits may receive the first clock signal CLK1 and the second clock signal CLK2, the third clock signal CLK3 may be supplied only to the odd-numbered stage circuits, and the fourth clock signal CLK4 may be supplied only to the even-numbered stage circuits.

[0099] like Figure 5 As shown in , the first to fourth clock signals CLK1 to CLK4 may be square wave signals that repeat a high level and a low level, and may be set to the same period.

[0100] The first clock signal CLK1 to the fourth clock signal CLK4 can be set to have a cycle of two horizontal time periods 2H. The first clock signal CLK1 to the fourth clock signal CLK4 can be set so that the high level and the low level have different widths during one cycle. For example, the first clock signal CLK1 and the second clock signal CLK2 can be set so that the low level has a width narrower than the width of the high level. That is, the first clock signal CLK1 and the second clock signal CLK2 can include a pulse of a low level. In addition, the third clock signal CLK3 and the fourth clock signal CLK4 can be set so that the high level has a width narrower than the width of the low level. That is, the third clock signal CLK3 and the fourth clock signal CLK4 can include a pulse of a high level.

[0101] The third clock signal CLK3 may be set to a signal that is inverted with respect to the second clock signal CLK2. For example, when the second clock signal CLK2 has a low level, the third clock signal CLK3 may have a high level, and when the second clock signal CLK2 has a high level, the third clock signal CLK3 may have a low level. In addition, the fourth clock signal CLK4 may be set to a signal that is inverted with respect to the first clock signal CLK1. In this case, the low level of the first clock signal CLK1 may overlap with at least some of the low levels of the third clock signal CLK3, and the low level of the second clock signal CLK2 may overlap with at least some of the low levels of the fourth clock signal CLK4.

[0102] However, the first to fourth clock signals CLK1 to CLK4 are not limited to the above description and may be set to have various cycles and duty ratios according to exemplary embodiments.

[0103] like Figure 4 and Figure 5 As shown in , the first stage circuit ST1 can output the second clock signal CLK2 as the first scanning signal SP1 and output the third clock signal CLK3 as the second scanning signal SN1 after one horizontal period 1H corresponding to the scanning start signal FLM. In addition, the first stage circuit ST1 can supply the first scanning signal SP1 as the carry signal CR1 to the next stage circuit ST2.

[0104] The second stage circuit ST2 can output the first clock signal CLK1 as the first scanning signal SP2 and output the fourth clock signal CLK4 as the second scanning signal SN2 after one horizontal period 1H corresponding to the carry signal CR1. In addition, the second stage circuit ST2 can supply the first scanning signal SP2 as the carry signal CR2 to the next stage circuit. The subsequent stage circuit can also output the first scanning signal and the second scanning signal by repeating the above process. That is, the first scanning signals SP1 to SPn and the second scanning signals SN1 to SNn outputted from the stage circuits ST1 to STn can be outputted in a period of one horizontal period 1H, respectively.

[0105] Figure 6 It is shown Figure 4 An example of a stage circuit and a connection stage of the stage circuit are shown in FIG.

[0106] exist Figure 6 In the figure, for the convenience of description, the k-th stage circuit STk and the k+1-th stage circuit STk+1 are shown. The k-th stage circuit STk may be an odd-numbered stage circuit, and the k+1-th stage circuit STk+1 may be an even-numbered stage circuit. Hereinafter, a description will be given based on the k-th stage circuit STk. Since the k+1-th stage circuit STk+1 may be substantially the same as or similar to the k-th stage circuit STk, for the convenience of explanation, only their differences may be described.

[0107] Reference Figure 6 According to the exemplary embodiment, the stage circuits STk and STk+1 may include first sub-stage circuit units STPk and STPk+1 (where k is a positive integer) and second sub-stage circuit units STNk and STNk+1. In addition, the stage circuits STk and STk+1 may include a first input terminal 201, a second input terminal 202, a third input terminal 203, a fourth input terminal 204, a first output terminal 205, a second output terminal 206, a first power input terminal 207, and a second power input terminal 208.

[0108] For example, the first sub-stage circuit units STPk and STPk+1 may include a first input terminal 201, a second input terminal 202, a third input terminal 203, a first output terminal 205, a first power input terminal 207 and a second power input terminal 208, and the second sub-stage circuit units STNk and STNk+1 may include a third input terminal 203, a fourth input terminal 204, a second output terminal 206, a first power input terminal 207 and a second power input terminal 208.

[0109] The first input terminal 201 of the first sub-stage circuit unit STPk can receive the first scan signal SPk-1 from the previous stage circuit. At this time, when the k-th stage circuit STk is set to Figure 4When the first-stage circuit ST1 is turned on, the scanning start signal FLM may be supplied to the first input terminal 201 .

[0110] The first input terminal 201 of the first sub-stage circuit unit STPk+1 positioned in the next row may receive the carry signal CRk. The carry signal CRk may be the first scan signal SPk output from the first sub-stage circuit unit STPk positioned in the previous row.

[0111] The second input terminal 202 can receive one of the first clock signal CLK1 and the second clock signal CLK2. For example, the second input terminal 202 of the k-th stage circuit STk can receive the first clock signal CLK1. In this case, the second input terminal 202 of the k+1-th stage circuit STk+1 can receive the second clock signal CLK2.

[0112] The third input terminal 203 may receive the other of the first clock signal CLK1 and the second clock signal CLK2 supplied to the second input terminal 202. For example, when the first clock signal CLK1 is supplied to the second input terminal 202 of the k-th stage circuit STk, the third input terminal 203 may receive the second clock signal CLK2. In this case, the third input terminal 203 of the k+1-th stage circuit STk+1 may receive the first clock signal CLK1.

[0113] The fourth input terminal 204 of the second sub-stage circuit unit STNk can receive one of the third clock signal CLK3 and the fourth clock signal CLK4. For example, the fourth input terminal 204 of the k-th stage circuit STk can receive the third clock signal CLK3. In this case, the fourth input terminal 204 of the k+1-th stage circuit STk+1 can receive the fourth clock signal CLK4.

[0114] The first output terminal 205 of the first sub-stage circuit unit STPk may output the first scan signal SPk. The first scan signal SPk outputted through the first output terminal 205 may be supplied to the kth first scan line. The first scan signal SPk outputted from the first output terminal 205 may be a signal having a pulse of a low level.

[0115] The first sub-stage circuit unit STPk may output the first scan signal SPk through the first output terminal 205 , and provide the first scan signal SPk as a carry signal CRk to the first sub-stage circuit unit STPk+1 of the next row.

[0116] The second output terminal 206 of the second sub-stage circuit unit STNk may output the second scan signal SNk. The second scan signal SNk outputted through the second output terminal 206 may be supplied to the kth second scan line. The second scan signal SNk outputted from the second output terminal 206 may be a signal having a pulse of a high level.

[0117] The first power VDD may be applied to the first power input terminal 207, and the second power VSS may be applied to the second power input terminal 208. As described above, the first power VDD may supply a high level voltage, and the second power VSS may supply a low level voltage.

[0118] For example, when the stage circuits STk and STk+1 of the scan driver 200 include P-type transistors, the voltage of the first power VDD may be set as a gate-off voltage and the voltage of the second power VSS may be set as a gate-on voltage.

[0119] In addition, in exemplary embodiments, a high level of the clock signals CLK1 to CLK4 may be set to a gate-off voltage (eg, a voltage of the first power VDD), and a low level may be set to a gate-on voltage (eg, a voltage of the second power VSS).

[0120] The first operation signal OS1 and the second operation signal OS2 may be generated based on signals supplied through the input terminals 201, 202, and 203 of the first sub-stage circuit units STPk and STPk+1 and power supplied through the power input terminals 207 and 208. For example, the first operation signal OS1 and the second operation signal OS2 may be generated based on the scan start signal FLM received through the first input terminal 201 of the first sub-stage circuit unit STPk, the first clock signal CLK1 received through the second input terminal 202 of the first sub-stage circuit unit STPk, and the second clock signal CLK2 received through the third input terminal 203 of the first sub-stage circuit unit STPk. The first scan signal SPk described above may be output based on the first operation signal OS1 and the second operation signal OS2.

[0121] The first sub-stage circuit unit STPk+1 can output the first scan signal SPk+1 through the first output terminal 205 in response to the first operation signal OS1 and the second operation signal OS2, and provide the first scan signal SPk+1 as the carry signal CRk+1 to the first sub-stage circuit unit of the next row. In addition, the second sub-stage circuit units STNk and STNk+1 can receive the first operation signal OS1 and the second operation signal OS2 from the first sub-stage circuit units STPk and STPk+1, and can output the second scan signals SNk and SNk+1 through the second output terminal 206 based on the first operation signal OS1 and the second operation signal OS2. Figure 7 and Figure 8 The first operation signal OS1 and the second operation signal OS2 are described in further detail.

[0122] Figure 7 is a diagram showing a method according to an exemplary embodiment Figure 4 A circuit diagram of one of the stage circuits shown in FIG.

[0123] In the following, for the convenience of description, the description of supplying the first clock signal CLK1 and the second clock signal CLK2 may represent supplying a gate-on voltage (e.g., a low-level voltage), and the description of not supplying the first clock signal CLK1 and the second clock signal CLK2 may represent supplying a gate-off voltage (e.g., a high-level voltage). In addition, the description of supplying the third clock signal CLK3 may represent supplying a gate-off voltage (e.g., a high-level voltage), and the description of not supplying the third clock signal CLK3 may represent supplying a gate-on voltage (e.g., a low-level voltage).

[0124] Reference Figure 7 , which shows by way of example Figure 4 The first stage circuit ST1 of the scan driver 200. Figure 4 The other stage circuits ST2 to STn may have substantially the same configuration as that of the first stage circuit ST1, and thus repeated description of such other stage circuits may be omitted for convenience of description.

[0125] The stage circuit ST1 may include a first sub-stage circuit unit STP1 and a second sub-stage circuit unit STN1.

[0126] The first sub-stage circuit unit STP1 may include a first driver 210 , a second driver 220 , and a first output unit 230 .

[0127] The first sub-stage circuit unit STP1 may include first to eighth transistors TP1 to TP8 , and may include first and second capacitors CP1 and CP2 .

[0128] The first sub-stage circuit unit STP1 may be connected to the first input terminal 201 , the second input terminal 202 , the third input terminal 203 , the first power input terminal 207 , and the second power input terminal 208 , and may output the first scan signal SP1 through the first output terminal 205 .

[0129] The first output unit 230 may be connected to the third input terminal 203, the first power input terminal 207, and the first output terminal 205. The first output unit 230 may control the voltage supplied to the first output terminal 205 corresponding to the voltage of the first node NP1 and the second node NP2. For example, the first output unit 230 may electrically connect the third input terminal 203 or the first power input terminal 207 to the first output terminal 205 corresponding to the voltage of the first node NP1 and the second node NP2. To this end, the first output unit 230 may include a fourth transistor TP4 and a fifth transistor TP5. Therefore, the first output unit 230 may supply the first scan signal SP1 to the first output terminal 205 in response to the voltage of the first node NP1 and the voltage of the second node NP2.

[0130] The fourth transistor TP4 may be connected between the first power input terminal 207 and the first output terminal 205, and a gate electrode of the fourth transistor TP4 may be connected to the first node NP1. The fourth transistor TP4 may control the connection between the first power input terminal 207 and the first output terminal 205 corresponding to the voltage applied to the first node NP1.

[0131] The fifth transistor TP5 may be connected between the first output terminal 205 and the third input terminal 203, and the gate electrode of the fifth transistor TP5 may be connected to the second node NP2. The fifth transistor TP5 may control the connection between the first output terminal 205 and the third input terminal 203 corresponding to the voltage applied to the second node NP2. The first output unit 230 may be driven as a buffer. In addition, the fourth transistor TP4 and the fifth transistor TP5 may be configured as a plurality of transistors connected in parallel.

[0132] The first driver 210 may be connected to the first input terminal 201, the second input terminal 202, the third input terminal 203, and the first power input terminal 207. The first driver 210 may control the voltage of the third node NP3 corresponding to the signal supplied to the first to third input terminals 201, 202, and 203. For example, the first driver 210 may control the voltage of the third node NP3 in response to the scan start signal FLM supplied to the first input terminal 201, the first clock signal CLK1 supplied to the second input terminal 202, and the second clock signal CLK2 supplied to the third input terminal 203. To this end, the first driver 210 may include first to third transistors TP1, TP2, and TP3.

[0133] The first transistor TP1 may be connected between the first input terminal 201 and the third node NP3, and a gate electrode of the first transistor TP1 may be connected to the second input terminal 202. The first transistor TP1 may control connection between the first input terminal 201 and the third node NP3 corresponding to a signal supplied to the second input terminal 202.

[0134] The second transistor TP2 and the third transistor TP3 may be connected in series between the third node NP3 and the first power input terminal 207. The second transistor TP2 may be positioned between the third transistor TP3 and the third node NP3, and a gate electrode of the second transistor TP2 may be connected to the third input terminal 203. The second transistor TP2 may control the connection between the third transistor TP3 and the third node NP3 in correspondence with a signal supplied to the third input terminal 203.

[0135] The third transistor TP3 may be positioned between the second transistor TP2 and the first power input terminal 207, and a gate electrode of the third transistor TP3 may be connected to the first node NP1. The third transistor TP3 may control the connection between the second transistor TP2 and the first power input terminal 207 corresponding to the voltage of the first node NP1.

[0136] The second driver 220 may be connected to the second input terminal 202, the first power input terminal 207, and the second power input terminal 208. The second driver 220 may control the voltages of the first node NP1 and the second node NP2 corresponding to the voltages of the second input terminal 202 and the third node NP3. To this end, the second driver 220 may include a sixth transistor TP6, a seventh transistor TP7, an eighth transistor TP8, a first capacitor CP1, and a second capacitor CP2.

[0137] The first capacitor CP1 may be connected between the second node NP2 and the first output terminal 205. The first capacitor CP1 may store a voltage corresponding to a turn-on voltage and a turn-off voltage of the fifth transistor TP5.

[0138] The second capacitor CP2 may be connected between the first node NP1 and the first power input terminal 207. The second capacitor CP2 may store a voltage applied to the first node NP1.

[0139] The seventh transistor TP7 may be connected between the first node NP1 and the second input terminal 202, and a gate electrode of the seventh transistor TP7 may be connected to the third node NP3. The seventh transistor TP7 may control the connection between the first node NP1 and the second input terminal 202 corresponding to the voltage of the third node NP3.

[0140] The eighth transistor TP8 may be connected between the first node NP1 and the second power input terminal 208, and a gate electrode of the eighth transistor TP8 may be connected to the second input terminal 202. The eighth transistor TP8 may control the connection between the first node NP1 and the second power input terminal 208 corresponding to a signal of the second input terminal 202.

[0141] The sixth transistor TP6 may be connected between the third node NP3 and the second node NP2, and a gate electrode of the sixth transistor TP6 may be connected to the second power input terminal 208. The second power VSS may be applied to the gate electrode of the sixth transistor TP6 through the second power input terminal 208, and the electrical connection between the third node NP3 and the second node NP2 may be maintained while maintaining a conductive state.

[0142] The sixth transistor TP6 can limit the voltage drop width of the third node NP3 corresponding to the voltage of the second node NP2. That is, even if the voltage of the second node NP2 drops to a voltage lower than the voltage of the second power VSS through the coupling of the first capacitor CP1, the voltage of the third node NP3 will not drop more than the voltage obtained by subtracting the threshold voltage of the sixth transistor TP6 from the second power VSS. Therefore, since the voltage of the third node NP3 is maintained, an excessive bias voltage is prevented from being applied to the transistor connected to the third node NP3, and therefore, the reliability of the stage circuit ST1 can be improved.

[0143] The second sub-stage circuit unit STN1 may include a third driver 240, a fourth driver 250, and a second output unit 260. The second sub-stage circuit unit STN1 may include ninth to seventeenth transistors TN1 to TN9, and may include third to fifth capacitors CN1 to CN3.

[0144] The second sub-stage circuit unit STN1 may be connected to the third input terminal 203, the fourth input terminal 204, the first power input terminal 207, and the second power input terminal 208, and may output the second scan signal SN1 through the second output terminal 206. The second sub-stage circuit unit STN1 may receive the first operation signal OS1 and the second operation signal OS2 from the first sub-stage circuit unit STP1. The second scan signal SN1 may be supplied to the second output terminal 206 through the second sub-stage circuit unit STN1 based on the first operation signal OS1, the second operation signal OS2, the second clock signal CLK2, and the third clock signal CLK3. The second scan signal SN1 may include a pulse of a high voltage level.

[0145] The second output unit 260 may be connected to the fourth input terminal 204, the second power input terminal 208, and the second output terminal 206. The second output unit 260 may control the voltage supplied to the second output terminal 206 corresponding to the voltages of the fourth node NN1 and the fifth node NN2. For example, the second output unit 260 may electrically connect the fourth input terminal 204 or the second power input terminal 208 to the second output terminal 206 corresponding to the voltages of the fourth node NN1 and the fifth node NN2. Therefore, the second output unit 260 may supply the second scan signal SN1 to the second output terminal 206 in response to the voltages of the fourth node NN1 and the fifth node NN2. To this end, the second output unit 260 may include a fifteenth transistor TN7, a sixteenth transistor TN8, a seventeenth transistor TN9, and a fifth capacitor CN3.

[0146] The fifteenth transistor TN7 may be connected between the fourth input terminal 204 and the fourth node NN1. In addition, a gate electrode of the fifteenth transistor TN7 may be connected to the fifth node NN2. The fifteenth transistor TN7 may be turned on or off corresponding to the voltage of the fifth node NN2.

[0147] The sixteenth transistor TN8 may be connected between the fourth input terminal 204 and the second output terminal 206, and the gate electrode of the sixteenth transistor TN8 may be connected to the fourth node NN1. The sixteenth transistor TN8 may be turned on or off corresponding to the voltage of the fourth node NN1. When the sixteenth transistor TN8 is turned on, the voltage (i.e., high level voltage) of the third clock signal CLK3 supplied to the fourth input terminal 204 may be output as the second scan signal SN1.

[0148] The seventeenth transistor TN9 may be connected between the second output terminal 206 and the second power input terminal 208. In addition, a gate electrode of the seventeenth transistor TN9 may be connected to the fifth node NN2. The seventeenth transistor TN9 may be turned on or off corresponding to the voltage of the fifth node NN2.

[0149] The fifth capacitor CN3 may be connected between the fourth input terminal 204 and the fourth node NN1. The fifth capacitor CN3 may store a voltage of the fourth node NN1.

[0150] When the fifth node NN2 is set to a low level voltage, the fifteenth transistor TN7 may be set to a turned-on state. When the fifteenth transistor TN7 is set to a turned-on state, the fourth input terminal 204 and the fourth node NN1 are electrically connected to each other, and thus, the voltage of the fourth node NN1 may be set to the voltage of the fourth input terminal 204. Therefore, when the fifteenth transistor TN7 is set to a turned-on state, the voltage of the gate electrode of the sixteenth transistor TN8 and the voltage of the first electrode connected to the fourth input terminal 204 may be set to be the same, and thus, the sixteenth transistor TN8 may be set to a turned-off state.

[0151] The third driver 240 may receive the first operation signal OS1 and the second operation signal OS2 from the first sub-stage circuit unit STP1. For example, the seventh node NN4 of the third driver 240 may be electrically connected to the first node NP1 of the first sub-stage circuit unit STP1, and may receive the voltage of the first node NP1 as the first operation signal OS1. For example, the first node NP1 and the seventh node NN4 may be electrically the same node (e.g., may be a common node), and therefore, the voltage values ​​may be the same. However, the connection structure of the first node NP1 and the seventh node NN4 is not limited thereto, and other circuit elements such as a transistor or a capacitor may be included between the first node NP1 and the seventh node NN4.

[0152] In addition, the sixth node NN3 of the third driver 240 can be electrically connected to the third node NP3 of the first sub-stage circuit unit STP1, and thus in an exemplary embodiment, the voltage of the third node NP3 can be received as the second operation signal OS2. For example, the third node NP3 and the sixth node NN3 can be electrically the same node (e.g., can be a common node), and thus, the voltage values ​​can be the same. However, the connection structure of the third node NP3 and the sixth node NN3 is not limited thereto, and other circuit elements such as a transistor or a capacitor can also be included between the third node NP3 and the sixth node NN3.

[0153] The third driver 240 may be connected to the first power input terminal 207, the second power input terminal 208, and the third input terminal 203, and may control the voltage of the eighth node NN5 corresponding to the voltage of the first operation signal OS1 and the voltage of the second operation signal OS2 supplied to the sixth node NN3 and the seventh node NN4. In addition, the third driver 240 may control the voltage of the fifth node NN2 in response to the second operation signal OS2 supplied to the sixth node NN3 and the first operation signal OS1 supplied to the seventh node NN4. To this end, the third driver 240 may include a ninth transistor TN1, a tenth transistor TN2, an eleventh transistor TN3, and a third capacitor CN1.

[0154] The ninth transistor TN1 may be connected between the seventh node NN4 and the fifth node NN2, and the gate electrode of the ninth transistor TN1 may be connected to the second power input terminal 208. The second power VSS may be applied to the gate electrode of the ninth transistor TN1 through the second power input terminal 208, and the electrical connection between the seventh node NN4 and the fifth node NN2 may be maintained while maintaining a conductive state.

[0155] The ninth transistor TN1 can limit the voltage drop width of the seventh node NN4 corresponding to the voltage of the fifth node NN2. That is, even if the voltage of the fifth node NN2 drops to a voltage lower than the voltage of the second power VSS through the coupling of the third capacitor CN1, the voltage of the seventh node NN4 will not drop more than the voltage obtained by subtracting the threshold voltage of the ninth transistor TN1 from the second power VSS. Therefore, since the voltage of the seventh node NN4 is maintained, an excessive bias voltage is prevented from being applied to the transistor connected to the seventh node NN4, and therefore, the reliability of the stage circuit ST1 can be improved.

[0156] The tenth transistor TN2 may be connected between the eighth node NN5 and the third input terminal 203. The tenth transistor TN2 may control the electrical connection between the eighth node NN5 and the third input terminal 203 while being turned on or off corresponding to the voltage of the fifth node NN2.

[0157] The eleventh transistor TN3 may be connected between the first power input terminal 207 and the eighth node NN5. The eleventh transistor TN3 may control the electrical connection between the first power input terminal 207 and the eighth node NN5 while being turned on or off corresponding to the voltage of the sixth node NN3.

[0158] The third capacitor CN1 may be connected between the eighth node NN5 and the fifth node NN2. The third capacitor CN1 may store a voltage corresponding to the fifth node NN2.

[0159] When the fifth node NN2 is set to a low level voltage, the eighth node NN5 included in the third driver 240 periodically receives the second clock signal CLK2 from the third input terminal 203. When the second clock signal CLK2 is supplied to the eighth node NN5, the voltage of the fifth node NN2 can be periodically dropped to a voltage lower than a certain voltage (e.g., the voltage of the second power VSS) by coupling of the third capacitor CN1. As described above, when the voltage of the fifth node NN2 periodically drops, the driving characteristics of the transistors TN2, TN7, and TN9 connected to the fifth node NN2 can be improved.

[0160] In addition, when the sixth node NN3 is set to a low level voltage, the third driver 240 can supply the voltage of the first power VDD to the eighth node NN5. When the voltage of the first power VDD is supplied to the eighth node NN5, the voltage of the fifth node NN2 can be stably maintained by coupling of the third capacitor CN1.

[0161] The fourth driver 250 may be connected to the sixth node NN3, and may control the voltage of the fourth node NN1 corresponding to the second clock signal CLK2 supplied to the third input terminal 203 and the voltage of the second power VSS supplied to the second power input terminal 208. To this end, the fourth driver 250 may include a twelfth transistor TN4, a thirteenth transistor TN5, a fourteenth transistor TN6, and a fourth capacitor CN2.

[0162] The twelfth transistor TN4 may be connected between the sixth node NN3 and the ninth node NN6, and the gate electrode of the twelfth transistor TN4 may be connected to the second power input terminal 208. The second power VSS may be applied to the gate electrode of the twelfth transistor TN4 through the second power input terminal 208, and the electrical connection between the sixth node NN3 and the ninth node NN6 may be maintained while maintaining a conductive state.

[0163] The twelfth transistor TN4 can limit the voltage drop width of the sixth node NN3 corresponding to the voltage of the ninth node NN6. That is, even if the voltage of the ninth node NN6 drops to a voltage lower than the voltage of the second power VSS through the coupling of the fourth capacitor CN2, the voltage of the sixth node NN3 will not drop more than the voltage obtained by subtracting the threshold voltage of the twelfth transistor TN4 from the second power VSS. Therefore, since the voltage of the sixth node NN3 is maintained, an excessive bias voltage is prevented from being applied to the transistor connected to the sixth node NN3, and therefore, the reliability of the stage circuit ST1 can be improved.

[0164] The fourth capacitor CN2 may be connected between the ninth node NN6 and the tenth node NN7. That is, a first terminal of the fourth capacitor CN2 may be connected to the ninth node NN6, and a second terminal may be connected to the tenth node NN7.

[0165] The thirteenth transistor TN5 may be connected between the tenth node NN7 and the third input terminal 203, and a gate electrode of the thirteenth transistor TN5 may be connected to the ninth node NN6. The thirteenth transistor TN5 may be turned on or off corresponding to a voltage of the ninth node NN6.

[0166] The fourteenth transistor TN6 may be connected between the tenth node NN7 and the fourth node NN1, and a gate electrode of the fourteenth transistor TN6 may be connected to the third input terminal 203. The fourteenth transistor TN6 may be turned on when the second clock signal CLK2 is supplied to the third input terminal 203 to electrically connect the tenth node NN7 and the fourth node NN1 to each other.

[0167] The first to eighth transistors TP1 to TP8 and the ninth to seventeenth transistors TN1 to TN9 may be, for example, P-type transistors.

[0168] Figure 8 is a method for describing a driver according to an exemplary embodiment. Figure 7 The waveform diagram of the stage circuit method shown in FIG. Figure 8 In order to facilitate description, the first-stage circuit ST1 may be used to describe the operation process.

[0169] exist Figure 8 , VNP1, VNP2 and VNP3 respectively indicate the voltage of the first node NP1, the voltage of the second node NP2 and the voltage of the third node NP3. Similarly, VNN1, VNN2, VNN3, VNN4, VNN6 and VNN7 respectively indicate the voltage of the fourth node NN1, the voltage of the fifth node NN2, the voltage of the sixth node NN3, the voltage of the seventh node NN4, the voltage of the ninth node NN6 and the voltage of the tenth node NN7.

[0170] Reference Figure 4 , Figure 7 and Figure 8 , the scan start signal FLM supplied to the first input terminal 201 may be supplied synchronously with the first clock signal CLK1 supplied to the second input terminal 202. In addition, when the scan start signal FLM is supplied, the first input terminal 201 may be set to a low level voltage (e.g., the voltage of the second power VSS), and when the scan start signal FLM is not supplied, the first input terminal 201 may be set to a high level voltage (e.g., the voltage of the first power VDD).

[0171] As described above, the first sub-stage circuit unit STP1 and the second sub-stage circuit unit STN1 of the stage circuit ST1 can output the first scan signal SP1 and the second scan signal SN1, respectively. Hereinafter, for the convenience of description, the operation of the first sub-stage circuit unit STP1 and the operation of the second sub-stage circuit unit STN1 may be described separately. The first time point t1 to the sixth time point t6 to be described later may be the time points common to the operation processes of the first sub-stage circuit unit STP1 and the second sub-stage circuit unit STN1.

[0172] First, an operation process of the first sub-stage circuit unit STP1 is described in detail: At a first time point t1, a scan start signal FLM may be supplied to the first input terminal 201. As shown in FIG.

[0173] When the first clock signal CLK1 is supplied, the first transistor TP1 and the eighth transistor TP8 may be turned on. When the first transistor TP1 is turned on, the first input terminal 201 and the third node NP3 may be electrically connected to each other. Since the sixth transistor TP6 is set to a conducting state in most time periods, the electrical connection between the second node NP2 and the third node NP3 may be maintained.

[0174] When the first input terminal 201 and the third node NP3 are electrically connected to each other, a voltage VNP3 of the third node NP3 and a voltage VNP2 of the second node NP2 may be set to a low level by a scan start signal FLM supplied to the first input terminal 201. When a voltage VNP2 of the second node NP2 and a voltage VNP3 of the third node NP3 are set to a low level, the fifth transistor TP5 and the seventh transistor TP7 may be turned on.

[0175] When the fifth transistor TP5 is turned on, the third input terminal 203 and the first output terminal 205 can be electrically connected to each other. The third input terminal 203 can be set to a high level voltage (i.e., the second clock signal CLK2 is not supplied), and therefore, the high level voltage is also output to the first output terminal 205. When the seventh transistor TP7 is turned on, the second input terminal 202 and the first node NP1 can be electrically connected to each other. According to the first clock signal CLK1 supplied to the second input terminal 202, the voltage VNP1 of the first node NP1 can be set to a low level.

[0176] In addition, when the first clock signal CLK1 is supplied, the eighth transistor TP8 may be turned on. When the eighth transistor TP8 is turned on, the voltage of the second power input terminal 208 may be supplied to the first node NP1. The voltage of the second power input terminal 208 may be the voltage of the second power VSS, and may be set to a voltage that is the same as or similar to the low level voltage of the first clock signal CLK1. Therefore, the first node NP1 may stably maintain a low level voltage.

[0177] When the first node NP1 is set to a low level voltage, the third transistor TP3 and the fourth transistor TP4 may be turned on. When the third transistor TP3 is turned on, the first power input terminal 207 and the second transistor TP2 may be electrically connected to each other. Since the second transistor TP2 is set to a cut-off state, even if the third transistor TP3 is turned on, the third node NP3 may stably maintain a low level voltage. When the fourth transistor TP4 is turned on, the voltage of the first power input terminal 207 may be supplied to the first output terminal 205. The voltage of the first power input terminal 207 may be the voltage of the first power VDD, and may be set to a voltage that is the same as or similar to the high level voltage supplied to the third input terminal 203. Therefore, the first output terminal 205 may stably maintain a high level voltage.

[0178] Thereafter, at a second time point t2, the supply of the scan start signal FLM and the first clock signal CLK1 may be stopped. When the supply of the first clock signal CLK1 is stopped, the first transistor TP1 and the eighth transistor TP8 may be turned off. At this time, the fifth transistor TP5 and the seventh transistor TP7 may remain in a turned-on state corresponding to the voltage stored in the first capacitor CP1. That is, the second node NP2 and the third node NP3 may maintain a low level voltage by the voltage stored in the first capacitor CP1.

[0179] When the fifth transistor TP5 remains in the on state, the electrical connection between the first output terminal 205 and the third input terminal 203 can be maintained. When the seventh transistor TP7 remains in the on state, the electrical connection between the first node NP1 and the second input terminal 202 can be maintained. Corresponding to the stop of the supply of the first clock signal CLK1, the voltage of the second input terminal 202 can be set to a high level voltage, and therefore, the first node NP1 can also be set to a high level voltage. When the high level voltage is supplied to the first node NP1, the third transistor TP3 and the fourth transistor TP4 can be turned off.

[0180] Thereafter, at a third time point t3, the second clock signal CLK2 may be supplied to the third input terminal 203. At this time, since the fifth transistor TP5 is set to a turned-on state, the second clock signal CLK2 supplied to the third input terminal 203 may be supplied to the first output terminal 205. In this case, the first output terminal 205 may output the second clock signal CLK2 as a first scan signal SP1 of a turned-on level (e.g., a low level) to the first first scan line SPL1.

[0181] When the second clock signal CLK2 is supplied to the first output terminal 205 , the voltage of the second node NP2 drops to a voltage lower than the voltage of the second power input terminal 208 by coupling of the first capacitor CP1 , and thus the fifth transistor TP5 may stably maintain a turned-on state.

[0182] As described above, even if the voltage VNP2 of the second node NP2 drops, the voltage VNP3 of the third node NP3 does not drop more than a voltage obtained by subtracting the threshold voltage of the sixth transistor TP6 from the second power VSS.

[0183] Thereafter, at a fourth time point t4, after the first scan signal SP1 of the on-level is output, the supply of the second clock signal CLK2 may be stopped. When the supply of the second clock signal CLK2 is stopped, the first output terminal 205 may output a high-level voltage. In addition, the voltage VNP2 of the second node NP2 may rise to approximately the voltage of the second power input terminal 208 corresponding to the high-level voltage of the first output terminal 205.

[0184] Thereafter, at a fifth time point t5, the first clock signal CLK1 may be supplied. When the first clock signal CLK1 is supplied, the first transistor TP1 and the eighth transistor TP8 may be turned on. When the first transistor TP1 is turned on, the first input terminal 201 and the third node NP3 may be electrically connected to each other. At this time, the scan start signal FLM may not be supplied to the first input terminal 201, and therefore, may be set to a high level voltage. Therefore, when the sixth transistor TP6 is turned on, a high level voltage may be supplied to the third node NP3 and the second node NP2, and therefore, the fifth transistor TP5 and the seventh transistor TP7 may be turned off.

[0185] When the eighth transistor TP8 is turned on, the voltage of the second power input terminal 208 may be supplied to the first node NP1, and thus, the third transistor TP3 and the fourth transistor TP4 may be turned on. When the fourth transistor TP4 is turned on, the voltage of the first power input terminal 207 may be supplied to the first output terminal 205. Thereafter, the third transistor TP3 and the fourth transistor TP4 may maintain a turned-on state corresponding to the voltage charged in the second capacitor CP2, and thus, the first output terminal 205 stably receives the voltage of the first power input terminal 207.

[0186] In addition, at the sixth time point t6, when the second clock signal CLK2 is supplied, the second transistor TP2 may be turned on. At this time, since the third transistor TP3 is set to the on state, the voltage of the first power input terminal 207 may be supplied to the third node NP3 and the second node NP2. In this case, the fifth transistor TP5 and the seventh transistor TP7 may stably maintain the off state.

[0187] Next, the operation process of the second sub-stage circuit unit STN1 is described in detail. Since the gate electrodes of the ninth transistor TN1 and the twelfth transistor TN4 can be connected to the second power input terminal 208, the ninth transistor TN1 and the twelfth transistor TN4 are turned on during most of the time period, so except for special cases, the special description of the ninth transistor TN1 and the twelfth transistor TN4 will be omitted.

[0188] As described above, the second sub-stage circuit unit STN1 may receive the first operation signal OS1 and the second operation signal OS2 from the first sub-stage circuit unit STP1. The first operation signal OS1 may be the voltage VNP1 of the first node NP1 of the first sub-stage circuit unit STP1, and the second operation signal OS2 may be the voltage VNP3 of the third node NP3 of the first sub-stage circuit unit STP1.

[0189] The first operation signal OS1 may be provided to the seventh node NN4 of the second sub-stage circuit unit STN1, and the second operation signal OS2 may be provided to the sixth node NN3 of the second sub-stage circuit unit STN1. For example, the voltage VNP1 of the first node NP1 may be the same as the voltage VNN4 of the seventh node NN4, and the voltage VNP2 of the second node NP2 may be the same as the voltage VNN3 of the sixth node NN3.

[0190] First, at the first time point t1, the voltage VNP3 of the third node NP3 may be set to a low level by the scan start signal FLM supplied to the first sub-stage circuit unit STP1, and thus the second operation signal OS2 transmitted to the sixth node NN3 may be a low level voltage. The voltage VNP1 of the first node NP1 may also be set to a low level, and the first operation signal OS1 transmitted to the seventh node NN4 may be a low level voltage.

[0191] When the second operating signal OS2 is supplied to the sixth node NN3 and the sixth node NN3 is set to a low voltage level, the eleventh transistor TN3 and the thirteenth transistor TN5 may be turned on.

[0192] When the eleventh transistor TN3 is turned on, the voltage of the first power VDD may be supplied to the eighth node NN5. When the voltage of the first power VDD is supplied to the eighth node NN5, the voltage of the fifth node NN2 may be stably maintained by coupling of the third capacitor CN1.

[0193] When the thirteenth transistor TN5 is turned on, the second terminal (e.g., the tenth node NN7) of the fourth capacitor CN2 and the third input terminal 203 may be electrically connected to each other. At this time, since the high-level second clock signal CLK2 is applied to the gate electrode of the fourteenth transistor TN6, the fourteenth transistor TN6 may be turned off. Therefore, the fourth node NN1 may maintain the voltage of the previous cycle.

[0194] When the first operating signal OS1 is supplied to the seventh node NN4 and the seventh node NN4 is set to a low voltage level, the tenth transistor TN2 , the fifteenth transistor TN7 , and the seventeenth transistor TN9 may be turned on.

[0195] When the tenth transistor TN2 is turned on, the third input terminal 203 and the eighth node NN5 may be electrically connected to each other.

[0196] When the fifteenth transistor TN7 is turned on, the fourth node NN1 and the fourth input terminal 204 may be electrically connected to each other. At this time, the fourth input terminal 204 may be set to a low voltage level, and thus the fourth node NN1 may be set to a low voltage level.

[0197] When the seventeenth transistor TN9 is turned on, the voltage of the second power VSS may be supplied to the second output terminal 206 .

[0198] Thereafter, at the second time point t2, the first operation signal OS1 of the high level voltage may be supplied. That is, the seventh node NN4 may be set to a high level voltage. When the seventh node NN4 is set to a high voltage level, the fifth node NN2 may be set to a high voltage level. When the fifth node NN2 is set to a high voltage level, the tenth transistor TN2, the fifteenth transistor TN7, and the seventeenth transistor TN9 may be turned off.

[0199] Thereafter, at a third time point t3, the third clock signal CLK3 may be supplied to the fourth input terminal 204, and the second clock signal CLK2 may be supplied to the third input terminal 203. As described above, the third clock signal CLK3 may include a pulse of a high level voltage and may be a signal inverted from the second clock signal CLK2.

[0200] When the second clock signal CLK2 is supplied to the third input terminal 203, the second clock signal CLK2 can be supplied to the second terminal (e.g., the tenth node NN7) of the fourth capacitor CN2 via the thirteenth transistor TN5. Then, the voltage of the sixth node NN3 can drop to a voltage lower than the voltage of the second power VSS through the coupling of the fourth capacitor CN2. When the voltage of the sixth node NN3 drops, the thirteenth transistor TN5 can stably maintain the on state and can improve its driving characteristics.

[0201] In addition, when the second clock signal CLK2 is supplied to the third input terminal 203, the fourteenth transistor TN6 may be turned on. When the fourteenth transistor TN6 is turned on, the second clock signal CLK2 may be supplied to the fourth node NN1. In this case, the fourth node NN1 may be set to a low voltage level, and therefore, the sixteenth transistor TN8 may be turned on. At this time, the fifteenth transistor TN7 may be kept in a cut-off state by the voltage of the fifth node NN2.

[0202] When the sixteenth transistor TN8 is turned on, the third clock signal CLK3 supplied to the fourth input terminal 204 may be supplied to the second output terminal 206. The third clock signal CLK3 supplied to the second output terminal 206 may be supplied to the first second scan line SNL1 as the second scan signal SN1.

[0203] Thereafter, at a fourth time point t4, the third clock signal CLK3 may be stopped from being supplied to the fourth input terminal 204, and the second clock signal CLK2 may be stopped from being supplied to the third input terminal 203. When the third clock signal CLK3 is stopped, the voltage of the fourth input terminal 204 may drop from a high voltage level to a low voltage level. Then, the voltage of the fourth node NN1 may drop to a voltage lower than the low level voltage through the coupling of the fifth capacitor CN3, and therefore, the sixteenth transistor TN8 may remain in a conducting state. When the sixteenth transistor TN8 remains in a conducting state, the low voltage level supplied to the fourth input terminal 204 may be supplied to the second output terminal 206. That is, at a fourth time point t4, the second scan signal SN1 may be stopped from being supplied.

[0204] Thereafter, at the fifth time point t5, the first operation signal OS1 of a low level voltage may be supplied, and the second operation signal OS2 of a high level voltage may be supplied. That is, the seventh node NN4 may be set to a low voltage level, and the sixth node NN3 may be set to a high voltage level.

[0205] When the sixth node NN3 is set to a high voltage level, the eleventh transistor TN3 and the thirteenth transistor TN5 may be turned off. In addition, when the seventh node NN4 is set to a low voltage level, the tenth transistor TN2, the fifteenth transistor TN7, and the seventeenth transistor TN9 may be turned on.

[0206] Thereafter, at a sixth time point t6 , the second clock signal CLK2 may be supplied to the third input terminal 203 , and the third clock signal CLK3 may be supplied to the fourth input terminal 204 .

[0207] At this time, since the tenth transistor TN2 is turned on, when the second clock signal CLK2 is supplied to the third input terminal 203, the second clock signal CLK2 can be supplied to the eighth node NN5. Then, the voltage of the fifth node NN2 can drop by coupling of the third capacitor CN1. That is, the voltage of the fifth node NN2 can drop to a voltage lower than the voltage of the second power VSS. Therefore, the seventeenth transistor TN9 can stably maintain the on state, and its driving characteristics can be improved.

[0208] Since the fifteenth transistor TN7 maintains the on state at the sixth time point t6, the third clock signal CLK3 supplied to the fourth input terminal 204 can be supplied to the fourth node NN1, and thus the fourth node NN1 can rise to a high voltage level. When the fourth node NN1 is set to a high voltage level, the sixteenth transistor TN8 can be turned off. Therefore, the second output terminal 206 can maintain the voltage of the second power VSS regardless of the third clock signal CLK3 supplied to the fourth input terminal 204.

[0209] As a result, the stage circuit ST1 can output the first scan signal SP1 and the second scan signal SN1 corresponding to the scan start signal FLM supplied synchronously with the first clock signal CLK1. For example, the first sub-stage circuit unit STP1 of the stage circuit ST1 can output the second clock signal CLK2 as the first scan signal SP1 corresponding to the voltage of the first node NP1 (or the first operation signal OS1) and the voltage of the second node NP2 (or the second operation signal OS2). In addition, the second sub-stage circuit unit STN1 of the stage circuit ST1 can receive the first operation signal OS1 and the second operation signal OS2 from the first sub-stage circuit unit STP1, control the voltages of the fourth node NN1 and the fifth node NN2 based on the first operation signal OS1 and the second operation signal OS2, and output the third clock signal CLK3 as the second scan signal SN1 corresponding to the voltage of the fourth node NN1 and the voltage of the fifth node NN2.

[0210] The first scan signal SP1 output at the third time point t3 may be transmitted to the next stage circuit ST2 as a carry signal CR1. That is, the next stage circuit ST2 may receive the first scan signal SP1 so as to synchronize it with the second clock signal CLK2. The next stage circuit ST2 may output the first scan signal SP2 of the conduction level (e.g., low level) to the second first scan line SPL2 so as to synchronize it with the first clock signal CLK1, and output the second scan signal SN2 of the conduction level (e.g., high level) to the second second scan line SNL2. The other stage circuits ST3 to STn may also sequentially output the first scan signals SP3 to SPn of the conduction level to the first scan lines SPL3 to SPLn while repeating the above process, and sequentially output the second scan signals SN3 to SNn of the conduction level to the second scan lines SNL3 to SNLn.

[0211] Since the stage circuit ST1 according to an exemplary embodiment may simultaneously supply the low-level first scan signal SP1 and the high-level second scan signal SN1 using one stage, a mounting area of ​​the stage circuit may be minimized or reduced, and a manufacturing cost of the display device may be reduced.

[0212] In addition, the stage circuit ST1 according to the exemplary embodiment may prevent the fourth capacitor CN2 from being unnecessarily charged and discharged, thereby improving power consumption of the stage circuit ST1 and the scan driver 200 including the stage circuit ST1 .

[0213] For example, in the first time period HT after the fifth time point t5, the voltages of the two terminals of the fourth capacitor CN2 can maintain a high voltage level. That is, the voltage of the ninth node NN6 as the first terminal of the fourth capacitor CN2 and the voltage of the tenth node NN7 as the second terminal of the fourth capacitor CN2 can both be set to a high voltage level.

[0214] As described above, at the fifth time point t5, the second operation signal OS2 of the high voltage level may be supplied, and therefore, the sixth node NN3 may be set to a high voltage level. Since the twelfth transistor TN4 remains in the on state, the ninth node NN6 may also be set to a high voltage level. Meanwhile, since the tenth node NN7 maintains a high voltage level after the fourth time point t4, both ends of the fourth capacitor CN2 may maintain a high voltage level in the first time period HT after the fifth time point t5. For example, the first time period HT may be a time period from the fifth time point t5 to a time point (e.g., the seventh time point t7) when the output of the last scan signals SPn and SNn of the corresponding frame ends, but is not limited thereto. For example, the first time period HT may be a time period until the end of the corresponding frame, and the voltage of the ninth node NN6 of the stage circuit ST1 and the voltage of the tenth node NN7 may both be set to a high voltage level during the corresponding time period. In addition, the first time period HT may be a time period before the scan start signal FLM is supplied to the stage circuit ST1 in the next frame.

[0215] When the voltage levels at both ends of the fourth capacitor CN2 are different, a voltage corresponding to the difference in the voltage levels is charged in the fourth capacitor CN2. Thereafter, when the difference in the voltage levels changes, the voltage charged in the fourth capacitor CN2 is discharged. When such charging and discharging are continued in an unnecessary period of time, the power consumption of the scan driver 200 increases. However, according to an exemplary embodiment, since the voltage at both ends of the fourth capacitor CN2 is maintained at a high voltage level after the fifth time point t5 (or the first period of time HT), unnecessary charging and discharging of the fourth capacitor CN2 does not occur, and the power consumption of the stage circuit ST1 and the scan driver 200 including the stage circuit ST1 can be improved.

[0216] Fig. 9 is a circuit diagram illustrating a stage circuit ST1 ′ according to an exemplary embodiment. For ease of explanation, further description of previously described elements and technical aspects will be omitted.

[0217] Reference Fig. 9 , the sub-stage circuit ST1' may include a first sub-stage circuit unit STP1' and a second sub-stage circuit unit STN1'. The first sub-stage circuit unit STP1' may generate a first operation signal OS1 and a second operation signal OS2', and provide the first operation signal OS1 and the second operation signal OS2' to the second sub-stage circuit unit STN1'. The second operation signal OS2' may be a voltage of a second node NP2' of the first sub-stage circuit unit STP1', and may be transmitted to the eleventh transistor TN3' of the third driver 240' through the sixth node NN3'.

[0218] As described above, the gate electrode of the sixth transistor TP6 may be connected to the second power input terminal 208 to receive the voltage of the second power VSS, thereby maintaining a turned-on state. That is, the voltage level of the third node NP3' and the voltage level of the second node NP2' may be substantially the same or similar.

[0219] Since the voltage of the second node NP2 ′ may drop to a voltage lower than the voltage of the second power VSS by coupling of the first capacitor CP1 , driving characteristics of the transistor connected to the second node NP2 ′ may be improved.

[0220] That is to say, Fig. 9 The stage circuit ST1' shown in FIG. Figure 7 The stage circuit ST1 shown in FIG. 1 operates identically or similarly, and therefore, further detailed description thereof is omitted.

[0221] Fig.10 is a circuit diagram illustrating a stage circuit ST1″ according to an exemplary embodiment. For ease of explanation, further description of previously described elements and technical aspects will be omitted.

[0222] Reference Fig.10 The first sub-stage circuit unit STP1 ″ of the stage circuit ST1 ″ may include a first driver 210 ″, a second driver 220 , and a first output unit 230 .

[0223] The first driver 210 ″ may include first transistors TP1 a and TP1 b , a second transistor TP2 , and a third transistor TP3 .

[0224] The first transistors TP1a and TP1b may be configured as a plurality of sub-transistors. For example, the first transistors TP1a and TP1b may be configured as a first sub-transistor TP1a and a second sub-transistor TP1b. When the first transistors TP1a and TP1b are configured as a plurality of sub-transistors, the occurrence of leakage current of the first transistors TP1a and TP1b may be prevented or reduced. In addition, the first transistors TP1a and TP1b may have robustness to the strongly biased first clock signal CLK1, thereby preventing degradation. Therefore, the reliability of the first transistors TP1a and TP1b may be improved.

[0225] In an exemplary embodiment, in addition to the first transistors TP1 a and TP1 b , the structure of the plurality of sub-transistors may also be applied to the other transistors TP2 to TN9 .

[0226] Since the structure and operation method of the stage circuit ST1 ″ are the same as or similar to those of the stage circuit ST1 described above, further detailed description thereof is omitted.

[0227] While the present disclosure has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit or scope of the present disclosure as defined by the claims.

Claims

1. A stage circuit, the stage circuit comprising: a first sub-stage circuit unit connected to a first input terminal receiving a start signal, a second input terminal receiving a first clock signal, and a third input terminal receiving a second clock signal, wherein the first sub-stage circuit unit generates a first operation signal and a second operation signal based on the start signal, the first clock signal, and the second clock signal, and supplies a first scan signal to a first output terminal based on the first operation signal and the second operation signal; and a second sub-stage circuit unit connected to the third input terminal and a fourth input terminal receiving a third clock signal, wherein the second sub-stage circuit unit supplies a second scan signal to a second output terminal based on the first operation signal, the second operation signal, the second clock signal, and the third clock signal; wherein the first scanning signal comprises a pulse of a low voltage level, and the second scanning signal comprises a pulse of a high voltage level, wherein each of the first sub-stage circuit unit and the second sub-stage circuit unit is connected to a first power input terminal and a second power input terminal, the first power input terminal receiving a first power set as a gate-off voltage, and the second power input terminal receiving a second power set as a gate-on voltage, and Wherein, the first sub-stage circuit unit comprises: a first output unit connected to the third input terminal and the first power input terminal, wherein the first output unit supplies the first scan signal to the first output terminal in response to a voltage of a first node and a voltage of a second node; a first driver connected to the first input terminal and the first power input terminal, wherein the first driver controls a voltage of a third node in response to the first clock signal and the second clock signal; and A second driver is connected to the second input terminal, the first power input terminal, the second power input terminal, and the third node, wherein the second driver controls the voltage of the first node and the voltage of the second node.

2. The stage circuit according to claim 1, wherein: The first driver comprises: a first transistor connected between the first input terminal and the third node and having a gate electrode connected to the second input terminal; and A second transistor and a third transistor are connected in series between the first power input terminal and the third node, wherein the gate electrode of the second transistor is connected to the third input terminal, and A gate electrode of the third transistor is connected to the first node.

3. The stage circuit according to claim 1, wherein: The first output unit comprises: a first transistor connected between the first power input terminal and the first output terminal and having a gate electrode connected to the first node; and The second transistor is connected between the third input terminal and the first output terminal and has a gate electrode connected to the second node.

4. The stage circuit according to claim 1, wherein: The second driver comprises: a first transistor connected between the second node and the third node and having a gate electrode connected to the second power input terminal; a second transistor connected between the first node and the second input terminal and having a gate electrode connected to the third node; a third transistor connected between the first node and the second power input terminal and having a gate electrode connected to the second input terminal; a first capacitor connected between the second node and the first output terminal; and The second capacitor is connected between the first node and the first power input terminal.

5. The stage circuit according to claim 1, wherein: The first operating signal is the voltage of the first node, and the second operating signal is the voltage of the third node.

6. The stage circuit according to claim 1, wherein: The first operating signal is the voltage of the first node, and the second operating signal is the voltage of the second node.

7. The stage circuit according to claim 1, wherein: The second sub-stage circuit unit comprises: a second output unit connected to the fourth input terminal and the second power input terminal, wherein the second output unit supplies the second scan signal to the second output terminal in response to the voltage of the fourth node and the voltage of the fifth node; a third driver connected to the third input terminal, the first power input terminal, the second power input terminal, a sixth node, and a seventh node, wherein the third driver controls the voltage of the fifth node in response to the second operation signal supplied to the sixth node and the first operation signal supplied to the seventh node; and a fourth driver connected to the third input terminal, the second power input terminal and the sixth node, wherein the fourth driver controls the voltage of the fourth node, and The sixth node is the same node as the third node, and the seventh node is the same node as the first node.

8. The stage circuit according to claim 7, wherein: The third driver comprises: a first transistor connected between the fifth node and the seventh node and having a gate electrode connected to the second power input terminal; a second transistor connected between the third input terminal and an eighth node and having a gate electrode connected to the fifth node; a third transistor connected between the first power input terminal and the eighth node and having a gate electrode connected to the sixth node; and A capacitor is connected between the fifth node and the eighth node.

9. The stage circuit according to claim 7, wherein: The fourth driver comprises: a first transistor connected between the sixth node and the ninth node and having a gate electrode connected to the second power input terminal; a second transistor connected between the third input terminal and the tenth node and having a gate electrode connected to the ninth node; a third transistor connected between the fourth node and the tenth node and having a gate electrode connected to the third input terminal; and A capacitor is connected between the ninth node and the tenth node.

10. The stage circuit according to claim 7, wherein: The second output unit comprises: a first transistor connected between the fourth node and the fourth input terminal and having a gate electrode connected to the fifth node; a second transistor connected between the fourth input terminal and the second output terminal and having a gate electrode connected to the fourth node; a third transistor connected between the second power input terminal and the second output terminal and having a gate electrode connected to the fifth node; and A capacitor is connected between the fourth input terminal and the fourth node.

11. The stage circuit according to any one of claims 1 to 10, wherein: The first clock signal and the second clock signal have the same cycle, and a high voltage supply period is set to be longer than a low voltage supply period in one cycle, The second clock signal is set to be a signal shifted by half a period from the first clock signal, and The third clock signal is a signal having a phase opposite to that of the second clock signal.

12. The stage circuit according to claim 1, wherein: The start signal is a scan start signal or a first scan signal of a previous first sub-stage circuit unit.

13. A scanning driver, comprising: a plurality of stage circuits configured to supply a first scan signal including a pulse of a low voltage level to a first scan line and a second scan signal including a pulse of a high voltage level to a second scan line, Wherein, each of the plurality of stage circuits comprises: a first sub-stage circuit unit connected to a first input terminal, a second input terminal, and a third input terminal, wherein the first sub-stage circuit unit generates a first operation signal and a second operation signal based on a voltage of the first input terminal, a voltage of the second input terminal, and a voltage of the third input terminal, and supplies the first scan signal to a first output terminal based on the first operation signal and the second operation signal; and a second sub-stage circuit unit connected to the fourth input terminal and the third input terminal, The second sub-stage circuit unit supplies the second scan signal to the second output terminal based on the first operation signal, the second operation signal, the voltage of the third input terminal, and the voltage of the fourth input terminal. wherein the second input terminal, the third input terminal and the fourth input terminal receive clock signals different from each other, and Wherein, the first sub-stage circuit unit comprises: a first output unit connected to the first power input terminal and the third input terminal, wherein the first output unit supplies the first scan signal to the first output terminal in response to a voltage of the first node and a voltage of the second node; a first driver connected to the first input terminal, the second input terminal, the third input terminal, and the first power input terminal, wherein the first driver controls a voltage of a third node; and A second driver is connected to the second input terminal, the first power input terminal, the second power input terminal and the third node, wherein the second driver controls the voltage of the first node and the voltage of the second node, and the first power input terminal supplies a gate-off voltage, and the second power input terminal supplies a gate-on voltage.

14. The scan driver according to claim 13, wherein: The second sub-stage circuit unit comprises: a second output unit connected to the fourth input terminal and the second power input terminal, wherein the second output unit supplies the second scan signal to the second output terminal in response to the voltage of the fourth node and the voltage of the fifth node; a third driver connected to the third input terminal, the first power input terminal, the second power input terminal, a sixth node, and a seventh node, wherein the third driver controls the voltage of the fifth node in response to the second operation signal supplied to the sixth node and the first operation signal supplied to the seventh node; and A fourth driver is connected to the third input terminal, the second power input terminal, and the sixth node, wherein the fourth driver controls the voltage of the fourth node.

15. The scan driver according to any one of claims 13 to 14, wherein: In odd-numbered stages, the second input terminal receives a first clock signal, the third input terminal receives a second clock signal, and the fourth input terminal receives a third clock signal, and In an even-numbered stage, the second input terminal receives the second clock signal, the third input terminal receives the first clock signal, and the fourth input terminal receives a fourth clock signal.

16. The scan driver according to claim 15, wherein: The first clock signal and the second clock signal have the same cycle, and in one cycle of the first clock signal and the second clock signal, a high voltage supply period is set to be longer than a low voltage supply period, The second clock signal is set to be a signal shifted by half a period from the first clock signal, The third clock signal and the fourth clock signal have the same cycle, and in one cycle of the third clock signal and the fourth clock signal, a high voltage supply period is set to be shorter than a low voltage supply period, and The fourth clock signal is set to a signal shifted by a half period from the third clock signal.

17. The scan driver according to claim 16, wherein: The third clock signal is a signal having a phase opposite to that of the second clock signal, and The fourth clock signal is a signal having a phase opposite to that of the first clock signal.

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