Semiconductor device and method of forming the same

Abstract

The present disclosure relates to a semiconductor device and a method for forming the same. A through hole is disclosed, including a sidewall having a first opening in a first region and a second opening in a second region, and a method for forming the through hole is also disclosed. In one embodiment, the semiconductor device includes: a first substrate; and a through hole extending through the substrate, the substrate including: a plurality of first openings adjacent to the through hole in the first region of the substrate; and a plurality of second openings adjacent to the through hole in the second region of the substrate, each of the plurality of first openings having a first depth, each of the plurality of second openings having a second depth, the first depth being greater than the second depth.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, and more particularly to a semiconductor device including a scallop. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material on a semiconductor substrate, and patterning the various material layers using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, allowing more components to be integrated into a given area. However, as the minimum feature size decreases, additional problems arise that need to be solved. Summary of the invention

[0004] A semiconductor device comprises: a first substrate; and a through via extending through the first substrate, the first substrate comprising: a plurality of first openings adjacent to the through via in a first region of the first substrate, each of the first openings having a first depth; and a plurality of second openings adjacent to the through via in a second region of the first substrate, each of the second openings having a second depth, wherein the second depth is greater than the first depth.

[0005] A method for forming a semiconductor device includes: etching a substrate with a first patterning process to form an opening in the substrate, the opening extending from a first surface of the substrate to a first depth, wherein the first patterning process includes a plurality of first iterations, each of which includes a first deposition and a first etching; and etching the substrate with a second patterning process to extend the opening in the substrate from the first depth to a second depth, wherein the second patterning process includes a plurality of second iterations, each of which includes a second deposition, a second etching, and a third etching, the third etching having process parameters different from those of the first etching and the second etching.

[0006] A method for forming a semiconductor device comprises: etching a substrate to form a first opening, the first opening comprising a first region and a second region, wherein the first region extends from a surface of the substrate to a first depth in the substrate, wherein the second region extends from the first depth in the substrate to a second depth, wherein the etching comprises: performing a first patterning process to form a first opening in the first region, the first patterning process comprising a plurality of first patterning repetition steps; and performing a second patterning process to form a first opening in the second region, the second patterning process comprising a plurality of second patterning repetition steps, wherein the duration of each second patterning repetition step is greater than the duration of each first patterning repetition step; and depositing a metal layer along a plurality of sidewalls of the first opening, wherein the conductivity of the metal layer in the first region is less than the conductivity of the metal layer in the second region. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The following will be described in detail with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale and are only used for illustration. In fact, the size of the components can be arbitrarily enlarged or reduced to clearly show the features of the embodiments of the present disclosure.

[0008] Figure 1 , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Fig. 8A , Figure 8B ,and Fig. 9 is a cross-sectional view of an intermediate stage in the fabrication of a semiconductor device according to some embodiments.

[0009] The reference numerals are described as follows:

[0010] 100: first semiconductor substrate

[0011] 102: Patterned photoresist

[0012] 104: First Opening

[0013] 104a: First Area

[0014] 104b: Second area

[0015] 106, 112, 134: Area

[0016] 108a: First opening

[0017] 108b: Second opening

[0018] 110: First metal layer

[0019] 114: Sacrificial Materials

[0020] 116: First passivation film

[0021] 118: Second passivation film

[0022] 120: Carrier substrate

[0023] 122: Second semiconductor substrate

[0024] 124: The third passivation film

[0025] 126: Fourth passivation film

[0026] 128: Cavity

[0027] 130: Second opening

[0028] 132: Second metal layer

[0029] 136: Draw a line

[0030] 150: Semiconductor devices

[0031] D 1 , D 2 , D 3 , D 4 :depth

[0032] S 1 , S 2 :depth

[0033] T 1 :thickness

[0034] W 1 : First width

[0035] W 2 : Second width DETAILED DESCRIPTION

[0036] The following disclosure provides many embodiments or examples for implementing different elements of the subject matter provided. Specific examples of each element and its configuration are described below to simplify the description of the embodiments of the present disclosure. Of course, these are merely examples and are not intended to limit the embodiments of the present disclosure. For example, if the description mentions that a first element is formed on a second element, an embodiment in which the first and second elements are in direct contact may be included, and an embodiment in which an additional element is formed between the first and second elements so that they are not in direct contact may also be included. In addition, the embodiments of the present disclosure may repeat reference numbers and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity, rather than for indicating the relationship between the different embodiments and / or configurations discussed.

[0037] Furthermore, spatially relative terms may be used, such as "under", "below", "lower", "above", "upper" and the like, to facilitate describing the relationship between one component or feature and another component or feature in the drawings. Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the drawings. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatially relative adjectives used therein will also be interpreted based on the orientation after the rotation.

[0038] Various embodiments provide improved through-holes for semiconductor devices and methods for forming the same. The through-holes may be formed using a first patterning process and then a second patterning process having different process conditions than the first patterning process. The first patterning process etches a first region of the through-hole and forms a first opening in the sidewall of the through-hole. The second patterning process etches a second region of the through-hole and forms a second opening in the sidewall of the through-hole, the second opening having a depth different from the depth of the first opening. A metal layer is then deposited in the through-hole. By utilizing different patterning processes, wherein the different patterning processes produce openings of different depths in the first region and the second region of the through-hole, the conductivity of the metal layer may be controlled in the first region and the second region without requiring additional deposition and etching steps. The metal layer and the through-hole may be used to provide shielding in devices such as microelectromechanical systems (MEMS) devices, light emitting diodes (LED) devices, electron beam devices (e.g., electron-beam writer control devices), and the like.

[0039] Figure 1According to some embodiments, a first semiconductor substrate 100 is shown, having a patterned photoresist 102 formed on its top surface. The first semiconductor substrate 100 may include a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, a multi-layer semiconductor substrate, etc. The material of the first semiconductor substrate 100 may be: silicon, germanium, a compound semiconductor including silicon germanium, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination of the foregoing. Other substrates, such as multi-layer or gradient substrates, may also be used. The first semiconductor substrate 100 may be doped or undoped. Devices such as transistors, capacitors, resistors, diodes, etc. (not shown individually) may be formed in and / or on the active surface (eg, the upward facing surface) of the first semiconductor substrate 100 .

[0040] The patterned photoresist 102 is formed on the top surface of the first semiconductor substrate 100. The film layer of the photoresist material can be deposited on the first semiconductor substrate 100 using a process such as spin coating. The patterned photoresist 102 can then be formed by exposing the photoresist material to a patterned energy source (e.g., patterned light), and then exposing the photoresist material to a developer to remove exposed or unexposed portions of the photoresist material. The portions of the photoresist material removed by the developer can correspond to the openings that are subsequently formed in the first semiconductor substrate 100 (e.g., as described below with respect to Figure 2A and Figure 2B The first opening 104 in question).

[0041] Figure 2A and Figure 2B According to some embodiments, a first opening 104 is formed in a first semiconductor substrate 100 using a patterned photoresist 102 as a mask. Figure 2B Shows Figure 2ADetailed view of region 106 of the first opening 104. The first patterning process can be used to etch a first region 104a of the first opening 104, the first region 104a having a first opening 108a in its sidewall. A second patterning process after the first patterning process can be used to etch a second region 104b of the first opening 104, the second region 104b having a second opening 108b in its sidewall. In various embodiments, the first patterning process and the second patterning process can be a Bosch process, other deep reactive ion etching (DRIE) processes, etc. The first opening 108a and the second opening 108b can be used to control the first metal layer (for example, as described below with respect to Figure 3A and Figure 3B The conductivity of the first metal layer 110 discussed above is deposited on the first semiconductor substrate 100 and in the first opening 104 .

[0042] The first patterning process for forming the first region 104a of the first opening 104 includes a first deposition and a first etch. Each first deposition is followed by a first etch, and this pattern is repeated for multiple repetitions. The first deposition and the first etch may both be plasma-based processes, and in some embodiments, may both use fluorine-based plasma. The first deposition is used to deposit a passivation film on the patterned photoresist 102 and on the portion of the first semiconductor substrate 100 exposed by the patterned photoresist 102. The first etch is then used to etch the passivation film through the portion of the bottom of the opening in the patterned photoresist that exposes the first semiconductor substrate 100, and to etch the first semiconductor substrate 100.

[0043] The first etch may be mostly isotropic but may include some ions attached in a nearly vertical direction. This may cause the first etch to penetrate the portion of the passivation film disposed at the bottom of the opening without penetrating the sidewalls of the passivation film, causing the first patterning process to pattern the first region 104a of the first opening 104 to have substantially vertical sidewalls. The isotropic nature of the first etch causes the first opening 108a to be formed in the sidewalls of the first opening 104 in the first region 104a. The number of repetitions of the first patterning process for forming the first region 104a of the first opening 104 may be from 50 to 150 repetitions, for example 84 repetitions, however, any other number of repetitions required to etch the first region 104a of the first opening 104 to a desired depth may also be used.

[0044] Each repeated step of the first patterning process extends the first opening 104 into the first semiconductor substrate 100 and surrounds the circumference of the first opening 104 to form one of the first openings 108a. Each of the first openings 108a may have a depth S of from about 40 nm to about 50 nm. 1 , for example, about 45 nm. The first patterning process may be repeated until the first region 104a reaches a depth D of from about 4 μm to about 17 μm. 1 , for example, about 10 μm.

[0045] The first deposition may be performed at a pressure of about 5 mTorr to about 200 mTorr, such as about 40 mTorr. The first deposition may be performed for a time of from about 0.5 seconds to about 5 seconds, such as about 0.9 seconds. A plasma power in a range of from about 1000 W to about 3000 W may be used for the first deposition, such as about 2500 W.

[0046] The first deposition may use a primary deposition gas and a secondary deposition gas, each comprising a fluorine-containing gas, such as difluoromethane (CH 2 F 2 ), octafluoropropane (octafluoropropane, C 3 F 8 ), octafluorocyclobutane (octafluorocyclobutane, C 4 F 8 ), sulfur hexafluoride (SF 6 ), combinations of the foregoing, and the like. In some embodiments, a carrier gas, such as argon (Ar), may be included in the primary deposition gas and / or the secondary deposition gas. In one embodiment, the primary deposition gas includes octafluorocyclobutane at a flow rate from about 100 sccm to about 800 sccm, such as about 360 sccm, and sulfur hexafluoride at a flow rate from about 0 sccm to about 100 sccm, such as about 1 sccm. The secondary deposition gas may include octafluorocyclobutane at a flow rate from about 10 sccm to about 500 sccm, such as about 150 sccm.

[0047] The first etch is performed at a pressure of from about 5 mTorr to about 200 mTorr, such as about 23 mTorr, for a time of from about 0.5 seconds to about 5 seconds, such as about 1.5 seconds, with a primary plasma power in a range of from about 1000 W to about 3000 W, such as about 2500 W, and a secondary plasma power in a range of from about 50 W to about 1000 W, such as about 400 W. The first etch can be performed using a substrate bias that is ramped from a first substrate bias at a first iteration of the first patterning process to a second substrate bias at a last iteration of the first patterning process. The first substrate bias can be from about 5 W to about 1000 W, such as about 150 W, and the second substrate bias can be from about 5 W to about 1000 W, such as about 270 W.

[0048] The first etching may use a primary etching gas and a secondary etching gas, each comprising a fluorine-containing gas, such as difluoromethane (CH 2 F 2 ), octafluoropropane (C 3 F 8 ), octafluorocyclobutane (C 4 F 8 ), sulfur hexafluoride (SF 6 ), combinations of the foregoing, and the like. In some embodiments, a carrier gas, such as argon (Ar), may be included in the primary etching gas and / or the secondary etching gas. In one embodiment, the primary etching gas includes octafluorocyclobutane at a flow rate from about 5 sccm to about 100 sccm, such as about 30 sccm, and sulfur hexafluoride at a flow rate from about 50 sccm to about 500 sccm, such as about 250 sccm. The secondary etching gas may include octafluorocyclobutane at a flow rate from about 0 sccm to about 100 sccm, such as about 1 sccm, and sulfur hexafluoride at a flow rate from about 0 sccm to about 500 sccm, such as about 100 sccm.

[0049] The second patterning process for forming the second region 104b of the first opening 104 includes a second deposition, a second etch, and a third etch. Each second deposition is followed by one of the second etches, followed by one of the third etches, and this pattern is repeated for multiple repetitions. The second deposition, the second etch, and the third etch can be plasma-based processes, and in some embodiments, fluorine-based plasma can be used. The second deposition is used to deposit a passivation film on the patterned photoresist 102 and on the portion of the first semiconductor substrate 100 exposed in the first opening 104. The second etch and the third etch are then used to etch through the passivation film at the bottom of the first opening 104, and to etch the first semiconductor substrate 100.

[0050] The second etch and the third etch may be mostly isotropic, but may include some ions attached in a nearly vertical direction. This may cause the second etch and the third etch to penetrate the portion of the passivation film disposed at the bottom of the first opening 104 without penetrating the sidewalls of the passivation film, causing the second patterning process to pattern the second region 104b of the first opening 104 to have substantially vertical sidewalls. The isotropic nature of the second etch and the third etch causes the second opening 108b to be formed in the sidewall of the first opening 104 in the second region 104b. The second etch and the third etch may each have similar process parameters and may be performed for a similar time as the first etch, and thus the combination of the second etch and the third etch may produce a second opening 108b in the second region 104b that is larger than the first opening 108a produced by the first etch in the first region 104a. Each repetition of the second patterning process may also be performed for a longer time than each repetition of the first patterning process. The number of repetitions of the second patterning process for forming the second region 104 b of the first opening 104 may be from 50 to 500 repetitions, for example 105 repetitions, however any other number of repetitions required to etch the second region 104 b of the first opening 104 to a desired depth may be used.

[0051] Each repeated step of the second patterning process extends the first opening 104 into the first semiconductor substrate 100 and surrounds the circumference of the first opening 104 to form one of the second openings 108b. Each second opening 108b may have a depth S of from about 150 nm to about 180 nm. 2 , for example, about 165 nm. In various embodiments, the depth S 1 For depth S 2 The ratio of is from 0.2 to about 0.6. The second patterning process is repeated until the first opening 104 reaches a depth D from about 10 μm to about 100 μm. 2 , for example, about 50 μm. The depth D of the second region 104 b of the first opening 3 It may be from about 10 μm to about 90 μm, for example about 40 μm.

[0052] The second deposition may be performed at a pressure of from about 5 mTorr to about 200 mTorr, such as about 40 mTorr, with a primary plasma power in a range of from about 1000 W to about 3000 W, such as about 2500 W, and a secondary plasma power in a range of from about 50 W to about 1000 W, such as about 400 W. The second deposition may be performed with a time period varying from a first time period at the first repetition step of the second patterning process to a second time period at the last repetition step. The first time period may be from about 0.5 seconds to about 5 seconds, such as about 1.0 seconds, and the second time period may be from about 0.5 seconds to about 5 seconds, such as about 2.0 seconds.

[0053] The second deposition may use a primary deposition gas and a secondary deposition gas, each of which includes a fluorine-containing gas, such as difluoromethane (CH 2 F 2 ), octafluoropropane (C 3 F 8 ), octafluorocyclobutane (C 4 F 8 ), sulfur hexafluoride (SF 6 ), combinations of the foregoing, and the like. In some embodiments, a carrier gas, such as argon (Ar), may be included in the primary deposition gas and / or the secondary deposition gas. In one embodiment, the primary deposition gas includes sulfur hexafluoride at a flow rate from about 0 sccm to about 100 sccm, for example, about 1 sccm, and octafluorocyclobutane at a flow rate varying from a first flow rate during the first repetition step of the second patterning process to a second flow rate during the last repetition step. The first flow rate may be from 50 sccm to about 500 sccm, for example, about 250 sccm, and the second flow rate may be from about 50 sccm to about 500 sccm, for example, about 240 sccm. The secondary deposition gas may include octafluorocyclobutane at a flow rate from about 10 sccm to about 500 sccm, for example, about 85 sccm, and sulfur hexafluoride at a flow rate from about 0 sccm to about 100 sccm, for example, about 1 sccm.

[0054] The second etch may be performed at a pressure of from about 5 mTorr to about 200 mTorr, for example, about 30 mTorr, with a primary plasma power in a range of from about 1000 W to about 3000 W, for example, about 2500 W, and a secondary plasma power in a range of from about 50 W to about 1000 W, for example, about 400 W. The second etch may be performed using a substrate bias of from about 5 W to about 1000 W, for example, about 80 W. The second etch may be performed for a period of time, the period of time varying from a first period of time at the first repetition step of the second patterning process to a second period of time at the last repetition step. The first period of time may be from about 0.5 seconds to about 5 seconds, for example, about 0.8 seconds, and the second period of time may be from about 0.5 seconds to about 5 seconds, for example, about 2.9 seconds.

[0055] The second etching may use a primary etching gas and a secondary etching gas, each of which includes a fluorine-containing gas, such as difluoromethane (CH 2 F 2 ), octafluoropropane (C 3 F 8 ), octafluorocyclobutane (C 4 F 8 ), sulfur hexafluoride (SF 6 ), combinations of the foregoing, and the like. In some embodiments, a carrier gas, such as argon (Ar), may be included in the primary etching gas and / or the secondary etching gas. In one embodiment, the primary etching gas includes octafluorocyclobutane at a flow rate from about 0 sccm to about 100 sccm, for example, about 1 sccm, and sulfur hexafluoride varying from a first flow rate during the first repetition step of the second patterning process to a second flow rate during the last repetition step. The first flow rate may be from 10 sccm to about 1000 sccm, for example, about 400 sccm, and the second flow rate may be from about 10 sccm to about 1000 sccm, for example, about 356 sccm. The secondary deposition gas may include octafluorocyclobutane at a flow rate from about 0 sccm to about 100 sccm, for example, about 1 sccm.

[0056] The third etch may be performed at a pressure of from about 5 mTorr to about 200 mTorr, for example, about 40 mTorr, with a primary plasma power in a range from about 1000 W to about 3000 W, for example, about 2500 W, and a secondary plasma power in a range from about 50 W to about 1000 W, for example, about 500 W. The third etch may be performed using a substrate bias of from about 50 W to about 1000 W, for example, about 500 W. The third etch may be performed for a period of time varying from a first period of time at the first repetition step of the second patterning process to a second period of time at the last repetition step. The first period of time may be from about 0.5 seconds to about 5 seconds, for example, about 0.8 seconds, and the second period of time may be from about 0.5 seconds to about 5 seconds, for example, about 3.6 seconds.

[0057] The second etching may use a primary etching gas and a secondary etching gas, each of which includes a fluorine-containing gas, such as difluoromethane (CH 2 F 2 ), octafluoropropane (C 3 F 8 ), octafluorocyclobutane (C 4 F 8 ), sulfur hexafluoride (SF 6), combinations of the foregoing, and the like. In some embodiments, a carrier gas, such as argon (Ar), may be included in the primary etching gas and / or the secondary etching gas. In one embodiment, the primary etching gas includes octafluorocyclobutane at a flow rate from about 0 sccm to about 100 sccm, for example, about 1 sccm, and sulfur hexafluoride varying from a first flow rate during the first repetition step of the second patterning process to a second flow rate during the last repetition step. The first flow rate may be from 10 sccm to about 1000 sccm, for example, about 400 sccm, and the second flow rate may be from about 10 sccm to about 1000 sccm, for example, about 356 sccm. The secondary deposition gas may include octafluorocyclobutane at a flow rate from about 0 sccm to about 100 sccm, for example, about 1 sccm.

[0058] Figure 3A and Figure 3B Removal of the patterned photoresist 102 and deposition of a first metal layer 110 on the first semiconductor substrate 100 and in the first opening 104 are shown according to some embodiments. Figure 3B Shows Figure 3A After the first opening 104 is formed in the first semiconductor substrate 100, the patterned photoresist 102 may be removed using a suitable photoresist stripping technique, such as chemical solvent cleaning, plasma ashing, dry stripping, and / or the like.

[0059] The first metal layer 110 may be deposited by sputtering deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), etc. The first metal layer 110 may include a conductive material, such as a metal. The first metal layer 110 may include a metal, such as copper, titanium, tungsten, aluminum, gold, a combination of the foregoing, etc. In a specific embodiment, the first metal layer 110 may include a titanium layer and a gold layer deposited on the titanium layer. The titanium layer may have a thickness from about 10 nm to about 500 nm, such as about 100 nm, and the gold layer may have a thickness from about 10 nm to about 1000 nm, such as about 400 nm. The first metal layer 110 may have a thickness from about 20 nm to about 1500 nm, such as about 500 nm.

[0060] In some embodiments, the first metal layer 110 may have a depth S greater than the first opening 108a. 1and is smaller than the depth S of the second opening 108b. 2 The thickness of Figure 3B As shown, this will cause the first metal layer 110 to fill the first opening 108a but not the second opening 108b, so that the first metal layer 110 is continuous in the first region 104a and discontinuous in the second region 104b. This will provide good conductivity in the first region 104a of the first opening 104 and provide insulation in the second region 104b of the first opening 104.

[0061] The device included in the first semiconductor substrate 100 may be disposed in a portion of the first semiconductor substrate 100 up to a depth D 1 The first metal layer 110 may be coupled to the first semiconductor substrate 100 and may be included to provide shielding for devices included in the first semiconductor substrate 100. In some embodiments, the first metal layer 110 provides a grounding electrical path to the first semiconductor substrate 100 and provides electrostatic discharge (ESD) protection.

[0062] In other embodiments, the first metal layer 110 may have a depth S greater than the first opening 108a. 1 and greater than the depth S of the second opening 108b 2 For example, the first metal layer 110 may have a thickness from about 20 nm to about 1500 nm, such as about 500 nm. In this way, both the first opening 108a and the second opening 108b may be filled with the first metal layer 110, and the first metal layer 110 may be continuous along the top surface of the first semiconductor substrate 100, along the sidewalls of the first opening 104, and along the bottom surface of the first opening 104. This provides conductivity in both the first region 104a and the second region 104b of the first opening 104, and the first region 104a has better conductivity than the second region 104b. By controlling the thickness of the first metal layer 110, and the depth of the first opening 108a and the second opening 108, the conductivity in the first region 104a and the second region 104b of the first opening 104 may be controlled and shielding may be provided, depending on customer needs.

[0063] Figure 4According to some embodiments, the deposition of the sacrificial material 114 in the first opening 104 and the bonding of the carrier substrate 120 to the first semiconductor substrate 100 are shown. The sacrificial material 114 may include silicon oxide, silicon oxynitride, SiCON, SiC, SiOC, and / or silicon nitride, and may be deposited using CVD, atomic layer deposition (ALD), PVD, spin-on coating, etc., or a combination thereof. The sacrificial material 114 may be deposited so that the sacrificial material 114 fills the first opening 104 and extends over the first semiconductor substrate 100. The sacrificial material 114 may then be planarized so that the top surface of the sacrificial material 114 is level with the top surface of the first metal layer 110. The sacrificial material 114 may be planarized using a process such as chemical mechanical polishing (CMP).

[0064] Next, a first passivation film 116 is formed on the first metal layer 110 and the sacrificial material 114. The first passivation film 116 may be formed by thermal oxidation, CVD, PVD, etc. The first passivation film 116 may include any suitable dielectric material that can be directly bonded to another dielectric layer in a subsequent process step. For example, the first passivation film 116 may include silicon oxide (e.g., SiO 2 ), silicon oxynitride, silicon nitride, etc.

[0065] The carrier substrate 120 may include a bulk semiconductor substrate, a semiconductor on insulator (SOI) substrate, a multilayer semiconductor substrate, etc. The semiconductor material of the carrier substrate 120 may be silicon, germanium, a compound semiconductor including silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination of the foregoing. Other substrates, such as multilayer or gradient substrates, may also be used. The carrier substrate 120 may be doped or undoped.

[0066] The second passivation film 118 is disposed on the carrier substrate 120. The second passivation film 118 may include any suitable dielectric material that can be directly bonded to another dielectric layer in a subsequent process step. For example, the second passivation film 118 may include silicon oxide (e.g., SiO 2 ), silicon oxynitride, silicon nitride, etc.

[0067] The first passivation film 116 of the first semiconductor substrate 100 may be physically contacted and bonded to the second passivation film 118 of the carrier substrate 120. Prior to bonding, at least one of the first passivation film 116 or the second passivation film 118 may be subjected to a surface treatment. The surface treatment may be a plasma treatment. The plasma treatment may be performed in a vacuum environment. The process gas used to generate the plasma may be a hydrogen-containing gas, which includes a hydrogen-containing gas. 2 ) and argon (Ar), a first gas containing H 2 and nitrogen (nitrogen, N 2 ) or a second gas containing H 2 and a third gas of helium (He). Through the surface treatment, the number of -OH groups on the surface of the first passivation film 116 and / or the second passivation film 118 will increase, which is beneficial for forming stronger fusion bonds. Pure or substantially pure H 2 , Ar, or N 2 Plasma treatment is performed as a process gas, and the process gas treats the surface of the first passivation film 116 and / or the second passivation film 118 through reduction and / or bombardment. After the surface treatment, a cleaning process (e.g., rinsing with deionized water) may be applied to the first passivation film 116 and / or the second passivation film 118.

[0068] After the cleaning process, the first semiconductor substrate 100 and the carrier substrate 120 are pressed against each other. A pre-bonding pressing force may be applied to press the first semiconductor substrate 100 and the carrier substrate 120 against each other. A pressing force of less than about 5N may be applied to each of the first semiconductor substrate 100 and the carrier substrate 120 in some exemplary embodiments, although greater or lesser forces may also be used. Pre-bonding may be performed at room temperature (e.g., between about 21° C. and about 25° C.), although higher temperatures may be used. For example, the bonding time may be shorter than about 1 minute.

[0069] After pre-bonding, the first passivation film 116 and the second passivation film 118 are bonded to each other. However, the above-mentioned bonding can be strengthened in a subsequent annealing step. For example, the first semiconductor substrate 100 and the carrier substrate 120 can be subjected to an optional annealing at a temperature of about 170° C. for about 1 hour. When the temperature rises, the -OH bonds in the first passivation film 116 and the second passivation film 118 are broken to form stronger Si-O-Si bonds, and the first semiconductor substrate 100 and the carrier substrate 120 are thus bonded to each other through fusion bonding.

[0070] Figure 5 According to some embodiments, it is shown Figure 4 1 and the thinning of the first semiconductor substrate 100. After the first semiconductor substrate 100 is bonded to the carrier substrate 120, a thinning process may be applied to the first semiconductor substrate 100. The thinning process may include performing a grinding or CMP process, an etch back process, or other acceptable processes on the surface of the first semiconductor substrate 100. The first semiconductor substrate 100 may be thinned to expose the sacrificial material 114. After the thinning process, the first semiconductor substrate 100 may have a thickness T1 from about 10 μm to about 100 μm, for example, about 50 μm.

[0071] Figure 6 According to some embodiments, the second semiconductor substrate 122 is shown bonded to the first semiconductor substrate 100. The third passivation film 124 is formed on the first semiconductor substrate 100 and the sacrificial material 114. The third passivation film 124 can be formed by thermal oxidation, CVD, PVD, etc. The third passivation film 124 can include any suitable dielectric material that can be directly bonded to another dielectric layer in a subsequent process step. For example, the third passivation film 124 can include silicon oxide (e.g., SiO 2 ), silicon oxynitride, silicon nitride, etc.

[0072] The second semiconductor substrate 122 may include a bulk semiconductor substrate, a semiconductor on insulator (SOI) substrate, a multilayer semiconductor substrate, etc. The semiconductor material of the second semiconductor substrate 122 may be silicon, germanium, a compound semiconductor including silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination of the foregoing. Other substrates may also be used, such as a multilayer or gradient substrate. The second semiconductor substrate 122 may be doped or undoped.

[0073] The fourth passivation film 126 is disposed on the second semiconductor substrate 122. The fourth passivation film 126 may include any suitable dielectric material, which can be directly bonded to another dielectric layer in a subsequent process step. For example, the fourth passivation film 126 may include silicon oxide (e.g., SiO 2 ), silicon oxynitride, silicon nitride, etc.

[0074] The third passivation film 124 of the first semiconductor substrate 100 may be in physical contact with and bonded to the fourth passivation film 126 of the second semiconductor substrate 122. Figure 4The third passivation film 124 is bonded to the fourth passivation film 126 by the same process as the bonding process. For example, before bonding, at least one of the third passivation film 124 or the fourth passivation film 126 may be subjected to a surface treatment, and the surface treatment may be a plasma treatment. After the surface treatment, a cleaning process (e.g., rinsing with deionized water) may be applied to the third passivation film 124 and / or the fourth passivation film 126. After the cleaning process, the first semiconductor substrate 100 and the second semiconductor substrate 122 are pressed against each other to form a pre-bonding between the third passivation film 124 and the fourth passivation film 126. Finally, the bonding between the third passivation film 124 and the fourth passivation film 126 may be strengthened by a subsequent annealing step.

[0075] Figure 7 According to some embodiments, the formation of a cavity 128 and a second opening 130 is shown. The cavity 128 can be formed by etching the second semiconductor substrate 122. The second semiconductor substrate 122 can be etched using an anisotropic etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc. In some embodiments, the fourth passivation film 126 can be used as an etch stop layer for etching the cavity 128 in the second semiconductor substrate 122. Figure 7 As shown, the cavity 128 may extend completely through the second semiconductor substrate 122. Figure 7 As further shown, the cavity 128 can be formed from a first width W distal to the first semiconductor substrate 100. 1 The second width W is tapered to be proximal to the first semiconductor substrate 100. 2 The cavity may have a depth D ranging from about 100 μm to about 800 μm. 4 , the first width W 1 can be from about 14 mm to about 18 mm, and the second width W 2 It can be from about 12 mm to about 16 mm.

[0076] After the cavity 128 is etched through the second semiconductor substrate 122, the fourth passivation film 126 and the third passivation film 124 may be etched to extend the cavity 128 to the first semiconductor substrate 100, and the sacrificial material 114, the second passivation film 118, and the first passivation film 116 may be etched to form the second opening 130. In some embodiments, the fourth passivation film 126, the third passivation film 124, the sacrificial material 114, the second passivation film 118, and the first passivation film 116 may be formed of the same material. For example, the fourth passivation film 126, the third passivation film 124, the sacrificial material 114, the second passivation film 118, and the first passivation film 116 may be formed of silicon oxide. In further embodiments, different materials may be used for any one of the fourth passivation film 126, the third passivation film 124, the sacrificial material 114, the second passivation film 118, and the first passivation film 116. The fourth passivation film 126, the third passivation film 124, the sacrificial material 114, the second passivation film 118, and the first passivation film 116 may be etched using a dry etching process or a wet etching process, and may be etched in a single etching process or in multiple etching processes. Figure 7 As shown, after etching of the second semiconductor substrate 122, the fourth passivation film 126, the third passivation film 124, the sacrificial material 114, the second passivation film 118, and the first passivation film 116, the side surfaces of the second semiconductor substrate 122, the fourth passivation film 126, and the third passivation film 124 and the top surface of the first semiconductor substrate 100 are exposed in the cavity 128. In addition, the side surfaces of the first semiconductor substrate 100, the first metal layer 110, the second passivation film 118, and the first passivation film 116 and the top surfaces of the first metal layer 110 and the carrier substrate 120 are exposed in the second opening 130.

[0077] Fig. 8A and Figure 8B The formation of a second metal layer 132 on the second semiconductor substrate 122 , in the cavity 128 , and in the second opening 130 is shown in accordance with some embodiments. Figure 8B Shows Fig. 8A Detailed view of region 134 of the second metal layer 132. The second metal layer 132 can be deposited by sputtering deposition, PVD, CVD, etc. The second metal layer 132 can include a conductive material, such as a metal. The second metal layer 132 can include a metal such as copper, titanium, tungsten, aluminum, gold, combinations of the foregoing, etc. In a specific embodiment, the second metal layer 132 can include a titanium layer and a gold layer disposed on the titanium layer. The titanium layer can have a thickness from about 10 nm to about 500 nm, such as about 100 nm, and the gold layer can have a thickness from about 10 nm to about 1000 nm, such as about 200 nm. The second metal layer 132 can have a thickness from about 20 nm to about 1500 nm, such as about 300 nm.

[0078] In some embodiments, the second metal layer 132 and the first metal layer 110 may have a depth S greater than that of the first opening 108a. 1 and is smaller than the depth S of the second opening 108b. 2 The combined thickness of Figure 8B As shown, this causes the second metal layer 132 and the first metal layer 110 to fill the first opening 108a, but not the second opening 108b, so that the second metal layer 132 and the first metal layer 110 are continuous in the first region 104a and discontinuous in the second region 104b. This provides good conductivity in the first region 104a of the second opening 130 and provides insulation in the second region 104b of the second opening 130.

[0079] The second metal layer 132 and the first metal layer 110 may be coupled to the first semiconductor substrate 100 and / or the second semiconductor substrate 122, and may be included to provide shielding for devices included in the first semiconductor substrate 100 and / or the second semiconductor substrate 122. In some embodiments, the second metal layer 132 and the first metal layer 110 provide a grounding circuit to the first semiconductor substrate 100 and / or the second semiconductor substrate 122, and provide electrostatic discharge (ESD) protection.

[0080] In other embodiments, the second metal layer 132 and the first metal layer may have a depth S greater than that of the first opening 108a. 1 and greater than the depth S of the second opening 108b 2 For example, the second metal layer 132 and the first metal layer 110 may have a thickness from about 20 nm to about 1500 nm, such as about 300 nm. In this way, both the first opening 108 a and the second opening 108 b may be filled with the second metal layer 132 and the first metal layer 110, and the second metal layer 132 and the first metal layer 110 may be continuous along the top surface of the second semiconductor substrate 122, along the surface of the cavity 128, along the surface of the first semiconductor substrate forming the sidewall of the second opening 130, and along the bottom surface of the first semiconductor substrate 100 (for example, at Fig. 8A and Figure 8B). This provides conductivity in both the first region 104a and the second region 104b of the second opening 130, with the first region 104a having a better conductivity than the second region 104b. By controlling the thickness of the second metal layer 132 and the first metal layer 110, and the depth of the first opening 108a and the second opening 108, the conductivity in the first region 104a and the second region 104b of the second opening 130 can be controlled and shielding can be provided, depending on the needs of the customer. Some embodiments may include only the first metal layer 110, only the second metal layer 132, or a combination of the first metal layer 110 and the second metal layer 132.

[0081] Fig. 9 The formation of the semiconductor device 150 is shown after the removal of the carrier substrate 120, the first passivation film 116, and the second passivation film 118 and the planarization of a portion of the second metal layer 132. A process, such as a grinding or CMP process, an etch-back process, or other acceptable processes, may be used to remove the carrier substrate 120, the first passivation film 116, and the second passivation film 118, and to planarize the second metal layer 132.

[0082] The semiconductor device 150 may be further singulated from other semiconductor devices by performing a singulation process along the scribe lines 136. The singulation may be performed by sawing, laser drilling, etc. along the scribe lines 136. The singulation process may separate the semiconductor device 150 from adjacent semiconductor devices.

[0083] The first metal layer 110 and / or the second metal layer 132 may be used to provide shielding in the semiconductor device 150. The first opening 108a and the second opening 108b having different depths in the first region 104a and the second region 104b are formed in the first opening 104 using the first patterning process and the second patterning process, respectively. This provides control of the conductivity of the first metal layer 110 and / or the second metal layer 132 in the first region 104a and the second region 104b without requiring additional deposition and etching steps, and reduces the cost of forming the semiconductor device 150.

[0084] According to one embodiment, a semiconductor device includes: a first substrate; and a through hole extending through the first substrate, the first substrate including a plurality of first openings adjacent to the through hole in a first region of the first substrate, each opening of the plurality of first openings having a first depth; and a plurality of second openings adjacent to the through hole in a second region of the first substrate, each opening of the plurality of second openings having a second depth, the second depth being greater than the first depth. In one embodiment, the first depth is from 30 nm to 50 nm, and the second depth is from 150 nm to 250 nm. In one embodiment, the ratio of the first depth to the second depth is from 0.2 to 0.6. In one embodiment, the through hole includes a metal layer adjacent to the first substrate, the thickness of the metal layer being greater than the first depth and less than the second depth. In one embodiment, the metal layer is continuous in the first region and discontinuous in the second region. In one embodiment, the first substrate includes a first surface and a second surface opposite to the first surface, the first region extending from the first surface to a point between the first surface and the second surface, and the second region extending from the point to the second surface. In one embodiment, the semiconductor device further includes a second substrate bonded to the first substrate, a cavity extending through the second substrate, the cavity having a tapered sidewall. In one embodiment, the semiconductor device further includes a first passivation film and a second passivation film between the first substrate and the second substrate, and the second substrate is bonded to the first substrate through a dielectric-to-dielectric bonding between the first passivation film and the second passivation film.

[0085] According to another embodiment, a method for forming a semiconductor device includes: etching a substrate with a first patterning process to form an opening in the substrate, the opening extending from a first surface of the substrate to a first depth, the first patterning process including a plurality of first repetition steps, each of the first repetition steps including a first deposition and a first etch; and etching the substrate with a second patterning process to extend the opening in the substrate from the first depth to a second depth, the second patterning process including a plurality of second repetition steps, each of the second repetition steps including a second deposition, a second etch, and a third etch, the third etch having different process parameters than the first etch and the second etch. In one embodiment, the first patterning process includes from 50 to 150 first repetition steps, and the second patterning process includes from 50 to 500 second repetition steps. In one embodiment, the step of etching the substrate with the first patterning process forms a plurality of first openings in a plurality of sidewalls of the opening, the plurality of first openings having a depth from about 40 nm to about 90 nm. In one embodiment, the step of etching the substrate with the second patterning process forms a plurality of second openings in a plurality of sidewalls of the opening, the plurality of second openings having a depth from about 100 nm to about 300 nm. In one embodiment, the first depth is from 4 μm to 17 μm, and the second depth is from 10 μm to 100 μm. In one embodiment, the process gas used for the first deposition and the second deposition includes octafluorocyclobutane (C 4 F 8 ), and the processing gas used for the first etching, the second etching, and the third etching includes sulfur hexafluoride (SF 6 ).

[0086] According to yet another embodiment, a method for forming a semiconductor device includes: etching a substrate to form a first opening, the first opening including a first region and a second region, the first region extending from a surface of the substrate to a first depth in the substrate, the second region extending from the first depth in the substrate to a second depth, the etching including: performing a first patterning process to form the first opening in the first region, the first patterning process including a plurality of first patterning repetition steps; and performing a second patterning process to form the first opening in the second region, the second patterning process including a plurality of second patterning repetition steps, wherein the duration of each second patterning repetition step is greater than the duration of each first patterning repetition step; and depositing a metal layer along a plurality of sidewalls of the first opening, the conductivity of the metal layer in the first region being less than the conductivity of the metal layer in the second region. In one embodiment, the plurality of sidewalls of the first opening in the first region include a plurality of openings having a first depth, the plurality of sidewalls of the first opening in the second region have a plurality of openings having a second depth, and the metal layer is deposited to a thickness between the first depth and the second depth. In one embodiment, the second depth is greater than the first depth, and the metal layer is deposited such that the metal layer is continuous in the first region and discontinuous in the second region. In one embodiment, the metal layer is deposited by sputtering deposition. In one embodiment, the plurality of sidewalls of the first opening in the first region include a plurality of openings having a first depth, the plurality of sidewalls of the first opening in the second region include a plurality of openings having a second depth, and the metal layer is deposited to a thickness greater than each of the first depth and the second depth. In one embodiment, the second depth is greater than the first depth, and the metal layer is continuous in both the first region and the second region.

[0087] The above summarizes the components of several embodiments so that those with ordinary knowledge in the technical field to which the present disclosure belongs can more easily understand the concepts of the embodiments of the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should understand that they can design or modify other processes and structures based on the embodiments of the present disclosure to achieve the same purposes and / or advantages as the embodiments introduced herein. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent processes and structures do not deviate from the spirit and scope of the present disclosure, and they can make various changes, substitutions and replacements without violating the spirit and scope of the appended claims.

Claims

1. A semiconductor device comprising: a first substrate; as well as A through hole extends through the first substrate, and the first substrate includes: A plurality of first openings are adjacent to the through hole in a first region of the first substrate, each of the first openings having a first depth; and A plurality of second openings are adjacent to the through hole in a second area of ​​the first substrate, each of the second openings having a second depth, wherein the second depth is greater than the first depth, wherein the through hole includes a metal layer adjacent to the first substrate, and the thickness of the metal layer is greater than the first depth and less than the second depth.

2. The semiconductor device according to claim 1, wherein: The first depth is from 30 nm to 50 nm, and the second depth is from 150 nm to 250 nm.

3. The semiconductor device according to claim 1, wherein: The ratio of the first depth to the second depth is from 0.2 to 0.

6.

4. The semiconductor device according to claim 1, wherein: The metal layer is continuous in the first region and discontinuous in the second region.

5. The semiconductor device according to claim 1, wherein: The first substrate includes a first surface and a second surface opposite to the first surface, wherein the first region extends from the first surface to a point between the first surface and the second surface, and wherein the second region extends from the point to the second surface. 6 . The semiconductor device of claim 1 , further comprising a second substrate bonded to the first substrate, wherein a cavity extends through the second substrate, wherein the cavity has a plurality of tapered sidewalls.

7. The semiconductor device as claimed in claim 6, further comprising a first passivation film and a second passivation film between the first substrate and the second substrate, wherein the second substrate is bonded to the first substrate by dielectric-to-dielectric bonding between the first passivation film and the second passivation film.

8. A method for forming a semiconductor device, comprising: Etching a substrate using a first patterning process to form an opening in the substrate, the opening extending from a first surface of the substrate to a first depth, wherein the first patterning process includes a plurality of first repetitive steps, each of the first repetitive steps including a first deposition and a first etching; etching the substrate using a second patterning process to extend the opening in the substrate from the first depth to a second depth, wherein the second patterning process includes a plurality of second repeated steps, each second repeated step including a second deposition, a second etch, and a third etch, the third etch having different process parameters than the first etch and the second etch; and A metal layer is deposited along a plurality of sidewalls of the opening, wherein the thickness of the metal layer is greater than the first depth and less than the second depth.

9. The method for forming a semiconductor device according to claim 8, wherein: The first patterning process includes from 50 to 150 first repetition steps, and the second patterning process includes from 50 to 500 second repetition steps.

10. The method for forming a semiconductor device according to claim 8, wherein: The step of etching the substrate with the first patterning process forms a plurality of first openings in a plurality of sidewalls of the opening, wherein the first openings have a depth ranging from 40 nm to 90 nm.

11. The method for forming a semiconductor device according to claim 8, wherein: The step of etching the substrate by the second patterning process forms a plurality of second openings in a plurality of sidewalls of the opening, wherein the second openings have a depth ranging from 100 nm to 300 nm.

12. The method for forming a semiconductor device according to claim 8, wherein: The first depth is from 4 μm to 17 μm, and the second depth is from 10 μm to 100 μm.

13. The method for forming a semiconductor device according to claim 8, wherein: The processing gas used for the first deposition and the second deposition includes octafluorocyclobutane (C4F8), and the processing gas used for the first etching, the second etching, and the third etching includes sulfur hexafluoride (SF6).

14. A method for forming a semiconductor device, comprising: Etching a substrate to form a first opening, the first opening comprising a first region and a second region, wherein the first region extends from a surface of the substrate to a first depth in the substrate, wherein the second region extends from the first depth in the substrate to a second depth, wherein the etching comprises: performing a first patterning process to form the first opening in the first region, the first patterning process comprising a plurality of first patterning repetition steps; and Performing a second patterning process to form the first opening in the second region, the second patterning process comprising a plurality of second patterning repetition steps, wherein the duration of each second patterning repetition step is greater than the duration of each first patterning repetition step; and A metal layer is deposited along a plurality of sidewalls of the first opening, wherein the conductivity of the metal layer in the first region is less than the conductivity of the metal layer in the second region.

15. The method for forming a semiconductor device according to claim 14, wherein: The multiple sidewalls of the first opening in the first region include multiple openings having a first depth, wherein the multiple sidewalls of the first opening in the second region have multiple openings having a second depth, and wherein the metal layer is deposited to a thickness between the first depth and the second depth.

16. The method for forming a semiconductor device according to claim 15, wherein: The second depth is greater than the first depth, and wherein the metal layer is deposited such that the metal layer is continuous in the first region and discontinuous in the second region.

17. The method for forming a semiconductor device according to claim 16, wherein: The metal layer is deposited by sputtering deposition.

18. The method for forming a semiconductor device according to claim 14, wherein: The multiple sidewalls of the first opening in the first region include multiple openings having a first depth, wherein the multiple sidewalls of the first opening in the second region have multiple openings having a second depth, and wherein the metal layer is deposited to a thickness greater than the first depth and the second depth respectively.

19. The method for forming a semiconductor device according to claim 18, wherein: The second depth is greater than the first depth, and wherein the metal layer is continuous in both the first region and the second region.

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