Hybrid lane height system, method of designing same, and hybrid lane height system designed by process

Abstract

A hybrid row height system discloses a plurality of rows having at least two different row heights and a plurality of cells disposed discretely on the rows. The plurality of cells includes first sub-cells disposed on a first cell row having a first row height, second sub-cells disposed on a second cell row having a second row height, and a blank space surrounding the first sub-cells and the second sub-cells. The first cell row and the second cell row have different numbers of fins corresponding to the at least two different row heights. The blank space is used to fill in other cells having matching geometries. The plurality of cells includes sub-cells covering more than one row. The first cell row is separated from the second cell row by a third cell row having a third row height. The third row height is different from the first row height. The first sub-cells and the second sub-cells are electrically connected by at least one wire in the blank space.

Description

Technical Field

[0001] This disclosure relates to a hybrid row height system, a method for designing a hybrid row height system, and a hybrid row height system designed by a manufacturing process. Background Technology

[0002] A fin field-effect transistor (FINFET) is a non-planar dual-gate transistor built on a silicon-on-insulator (SOI) substrate. A variant of the traditional MOSFET, FINFET is characterized by a thin silicon fin inversion channel on top of the substrate, allowing the gate to form two contact points: the left and right sides of the fin. More generally, FINFET refers to any fin-based, eccentric transistor architecture regardless of the number of gates; the fin electrodes allow multiple gates to operate on a single transistor. This type of multi-gate process extends Moore's Law, allowing semiconductor manufacturers to create smaller, faster, and more energy-efficient CPU and memory modules. FINFET devices offer significantly faster switching times and higher current densities than mainstream CMOS technologies.

[0003] In advanced nodes, standard cell programmable transistors are developed with different cell heights, corresponding to different numbers of fins in FINFET technology. While larger cell heights offer higher drive strength, this comes at the cost of larger area, higher power consumption, and larger fin capacity. In contrast, cells with smaller heights have relatively smaller areas, weaker drive strength, and are more susceptible to wiring congestion and fin accessibility issues. In advanced nodes, hybrid row-height systems are implemented instead of single-row-height systems to achieve increased area utilization.

[0004] In hybrid row height systems, cells of different row heights corresponding to different numbers of fins used for oxide diffusion are implemented together. For example, thinner rows have one fin for oxide diffusion, while taller rows have two fins for oxide diffusion. As technology advances, hybrid row height systems cannot maintain cell area shrinkage while maintaining performance. Summary of the Invention

[0005] This disclosure provides a hybrid row height system comprising multiple rows having at least two different row heights and discrete multiple row units deployed on these rows. Each multiple row unit comprises a first sub-unit, a second sub-unit, and multiple empty spaces surrounding the first and second sub-units. The first sub-unit is deployed on at least one first unit row having a first row height. The second sub-unit is deployed on at least one second unit row having a second row height. The first and second unit rows have different numbers of multiple fins corresponding to at least two different multiple row heights. These empty spaces are used to fill other multiple units having matching geometries. The multiple row unit includes sub-units covering more than one of these rows. The first and second unit rows are separated by a third unit row having a third row height. The third row height is different from the first row height. The first and second sub-units are electrically connected in these empty spaces by at least one lead.

[0006] This disclosure provides a method for designing a hybrid row height system, comprising: obtaining multiple hybrid row specifications with different row heights; obtaining multiple unit-driven target specifications; analyzing these hybrid row specifications with different row heights; deriving multiple discrete multi-row unit patterns; generating discrete multi-row units by dividing the units into multiple discrete sub-units with matching geometries and target unit-driven specifications; performing quality control on the discrete multi-row units to ensure that the generated discrete multi-row units match multiple quality control targets; and regenerating the discrete multi-row units by dividing the units into multiple sub-units with matching geometries and target unit-driven specifications if the quality control is not passed.

[0007] This disclosure provides a hybrid row height system designed by a process that includes obtaining multiple hybrid row specifications with different row heights. Multiple cell-driven target specifications are obtained. These hybrid row specifications with different row heights are analyzed. Multiple discrete multi-row cell patterns are derived. Discrete multi-row cells are generated by dividing the cells into multiple discrete sub-cells with matching geometries and target cell-driven specifications. Quality control of the discrete multi-row cells is performed to ensure that the generated discrete multi-row cells match multiple quality control targets. If the quality control fails, the discrete multi-row cells are regenerated by dividing the cells into multiple sub-cells with matching geometries and target cell-driven specifications.

[0008] This disclosure provides a hybrid row height system comprising multiple rows having at least two different row heights and a discrete multi-row unit deployed on these rows. The multi-row unit includes a first sub-unit deployed on at least one first unit row having a first row height, a second sub-unit deployed on at least one second unit row having a second row height, and multiple empty spaces surrounding the first and second sub-units. The first and second unit rows have different numbers of multiple fins corresponding to at least two different row heights. These empty spaces are used to fill other multiple units having matching geometries. The multi-row unit includes sub-units covering more than one of these rows, and the first and second sub-units are electrically connected in these empty spaces via at least one lead.

[0009] This disclosure provides a method for designing a hybrid row height system, comprising: obtaining multiple hybrid row specifications with different row heights; obtaining multiple unit-driven target specifications; analyzing these hybrid row specifications with different row heights; deriving multiple discrete multi-row unit patterns; generating discrete multi-row units by dividing the units into multiple discrete sub-units with matching geometries and target unit-driven specifications; and performing quality control on the discrete multi-row units to ensure that the generated discrete multi-row units match multiple quality control targets.

[0010] This disclosure provides a hybrid row height system designed by a process that includes obtaining multiple hybrid row specifications with different row heights. Multiple cell-driven target specifications are obtained. These hybrid row specifications with different row heights are analyzed. Multiple discrete multi-row cell patterns are derived. Discrete multi-row cells are generated by dividing the cells into multiple discrete sub-cells with matching geometries and target cell-driven specifications. Quality control of the discrete multi-row cells is performed to ensure that the generated discrete multi-row cells match multiple quality control targets. Attached Figure Description

[0011] When accompanied by Figure 1 The following detailed description will provide the best understanding of the nature of this disclosure. It should be noted that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased.

[0012] Figure 1 This is a diagram of a single-row height system based on some embodiments;

[0013] Figure 2 This is a diagram of a hybrid row height system according to some embodiments;

[0014] Figure 3 This is an illustration of another hybrid row height system according to some embodiments;

[0015] Figure 4 It is a diagram of four discrete multi-row unit systems according to some embodiments;

[0016] Figure 5 This is a diagram of another four discrete multi-row unit systems according to some embodiments;

[0017] Figure 6 It is a diagram of blank space and marker layer in a discrete multi-row cell system according to some embodiments;

[0018] Figure 7 It is a diagram of cell placement and wiring in a discrete multi-row cell system according to some embodiments;

[0019] Figure 8 This is a flowchart illustrating a method for designing a multi-row cell system for a discrete multi-row cell system according to some embodiments;

[0020] Figure 9 This is a system diagram illustrating a layout design system according to some embodiments.

[0021] [Symbol Explanation]

[0022] 100: Single-line high system

[0023] 101, 102, 103: Lines

[0024] 121: Unit 1

[0025] 122: Unit 2

[0026] 200: Hybrid Row Height System

[0027] 201,202,203,204,205: rows

[0028] 221: Unit 1

[0029] 222,222': Unit 2

[0030] 300: Hybrid Row Height System

[0031] 301, 302, 303, 304, 305: Lines

[0032] 321: Unit 1

[0033] 322,322': Unit 2

[0034] 401-408: Line

[0035] 410A, 410B: Lead wires

[0036] 411, 412: Subunits

[0037] 421, 422, 423: Subunits

[0038] 420A, 420B, 420C: Lead wires

[0039] 430A, 430B, 430C: Lead wires

[0040] 431, 432, 433: Subunits

[0041] 440: Multi-line unit

[0042] 440A, 440B, 440C, 440D: Lead wires

[0043] 441, 442, 443, 444: Subunits

[0044] 450A, 450B, 450C: Lead wires

[0045] 451, 452, 453: Subunits

[0046] 460: Multi-line unit

[0047] 461, 462, 463: Subunits

[0048] 470: Multi-line unit

[0049] 470A, 470B, 470C, 470D, 470E: Lead wires

[0050] 471, 472, 473: Subunits

[0051] 480: Multi-line unit

[0052] 480A, 480B, 480C, 480D: Lead wires

[0053] 481, 482: Subunits

[0054] 610: Multi-line unit

[0055] 610A, 610B: Lead wires

[0056] 611, 612: Subunits

[0057] 615: Blank Space

[0058] 640: Multi-line unit

[0059] 640A, 640B, 640C, 640D: Lead wires

[0060] 641, 642, 643, 644: Subunits

[0061] 645, 646, 647, 647', 648, 649: Blank space

[0062] 681, 683, 684: Other units

[0063] 682: Unit

[0064] 685, 686, 687, 689: Another unit

[0065] 710A, 710B, 710C, 720A, 720A, 720C: Lead wire connection

[0066] 800: Multi-line unit system

[0067] 810, 820, 830, 840, 850, 860, 870, 880, 890: Steps

[0068] 900: Layout Design System

[0069] 910: Network

[0070] 920: Memory Module

[0071] 930: Input and Output Module

[0072] 940: Manufacturing Tools

[0073] 990: Processor Detailed Implementation

[0074] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided object. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features so that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0075] Figure 1 This is an illustration of a single-row-height system according to some embodiments. According to some embodiments, the single-row-height system 100 includes three rows 101, 102, and 103 with the same height, the same height corresponding to the same number of fins. According to some embodiments, rows 101, 102, and 103 each have two fins. According to some embodiments, a first unit 121 is deployed above the first row 101, and a second unit 122 is deployed above the second row 102 and the third row 103.

[0076] Figure 2 This is an illustration of a hybrid row-height system according to some embodiments. According to some embodiments, the hybrid row-height system 200 includes multiple rows having at least two different heights. According to some embodiments, rows 201, 203, and 205 have a first height, and rows 202 and 204 have a second height. According to some embodiments, the first height corresponds to two fins, and the second height corresponds to one fin. According to some embodiments, a first unit 221 is deployed above row 201 having the first row height, and a second unit 222 is deployed above rows 203 and 204 having the first and second row heights, respectively. According to some embodiments, row 204 has a smaller row height than row 203 having the first row height. Alternatively, row 203 may have more fins than row 204, thus row 203 has greater actuation strength than row 204, since a smaller row height results in weaker actuation strength. According to some embodiments, the area of ​​unit 222 needs to be enlarged to unit 222' to compensate for performance degradation. According to some embodiments, cell 222' is deployed above rows 203, 204, and 205, wherein rows 203 and 205 have greater height or more fins, and row 204 has less height or fewer fins. According to some embodiments, cell area shrinkage cannot be maintained on multi-row-height cells in a hybrid row-height system because the cell height is changed while maintaining the cell width.

[0077] Figure 3 This is an illustration of another hybrid row height system according to some embodiments. According to some embodiments, the other hybrid row height system 300 includes multiple rows having at least two different heights. According to some embodiments, rows 301, 302, 304, and 305 have a first height, and row 303 has a second height. According to some embodiments, the first height corresponds to a larger number of fins, and the second height corresponds to a smaller number of fins. Figure 2 Similar to the discussion above, the first unit 321 is deployed above row 301, and the second unit 322 is deployed above rows 303 and 304, which have a second height and a first height, respectively. Based on the above... Figure 2 For the same reasons discussed above, the second cell 322 needs to be expanded to 322' to cover rows 302, 303, and 304 to compensate for performance degradation. Furthermore, as discussed above, the cell area shrinkage rate cannot be maintained in multi-row-height cells in a hybrid row-height system because the cell height is changed while maintaining the cell width.

[0078] Figure 4This is a diagram of a four discrete multi-row cell system according to some embodiments. According to some embodiments, rows 401, 403, 405, and 407 have a first row height, and rows 402, 404, 406, and 408 have a second row height. According to some embodiments, the first row height corresponds to two fins, and the second row height corresponds to one fin. According to some embodiments, rows 401-408 have more than two row heights. According to some embodiments, the first discrete multi-row cell 410 deployed above rows 401, 402, and 403 is divided into two discrete sub-cells 411 and 412, each deployed above rows 401 and 403 respectively. FEOL (front-end process) is the first part of the IC manufacturing process, in which various devices (such as transistors, capacitors, and resistors) are patterned on the semiconductor. FEOL typically covers everything except the deposition of metal interconnect layers. BEOL (back-end process) is the second part of the IC manufacturing process, in which various devices are interconnected with wiring (metallization layers) on the wafer. According to some embodiments, BEOL typically begins when the first metal layer is deposited on the wafer. BEOL includes connectors, insulating layers (dielectrics), metal layers, and bonding sites for wafer-to-package connections. MEOL (Mid-Process) refers to a process or process unit that fabricates metal channels in a wafer fab or in an outsourced assembly or test station. Processes and process units extend beyond those described in FEOL and BEOL. MEOL emerged after the advent of 3DS ICs. According to some embodiments, sub-cells 411 and 412 are connected via leads 410A and 410B in MEOL or BEOL. According to some embodiments, the blank space between sub-cells 411 and 412 can be used to fill other cells or signal routes. According to some embodiments, similarly, discrete multi-row cells 420 are divided into sub-cells 421, 422, and 423 connected above rows 401, 403, and 405 via leads 420A, 420B, and 420C in MEOL or BEOL, respectively. According to some embodiments, similarly, discrete multi-row units 430 are divided into sub-units 431, 432, and 433 connected above rows 401, 403, and 405 by leads 430A, 430B, and 430C in MEOL or BEOL, respectively. According to some embodiments, the sub-units are not aligned. For example, sub-unit 432 is not aligned with either sub-unit 431 or sub-unit 433. According to some embodiments, leads connect sub-units separated by more than one row. For example, lead 430A connects sub-units 431 and 433 separated by rows 402-404. According to some embodiments, discrete multi-row units 440 are similarly divided into sub-units 441, 442, 443, and 444 connected above rows 401, 403, 405, and 407 by leads 440A, 440B, 440C, and 440D in MEOL or BEOL, respectively. According to some embodiments, the sub-units have varying sizes.For example, sub-cell 442 is smaller than sub-cells 441 and 443, and sub-cell 444 is larger than sub-cells 441-443. The empty space surrounding all sub-cells can be used to fill other cells or signal routes.

[0079] Figure 5 This is a diagram of another four discrete multi-row unit system according to some embodiments. According to some embodiments, discrete multi-row units 450 deployed above rows 401-407 are divided into three discrete sub-units 451, 452, and 453, each deployed above rows 401, 405, and 407 respectively. According to some embodiments, sub-units 451, 452, and 453 are connected via leads 450A, 450B, and 450C in a MEOL or BEOL. According to some embodiments, discrete multi-row units 460 deployed above rows 401-407 are divided into three discrete sub-units 461, 462, and 463, each deployed above rows 401, 403, and 407 respectively. According to some embodiments, sub-units 461, 462, and 463 are connected via leads 460A, 460B, and 460C in a MEOL or BEOL. According to some embodiments, a discrete multi-row unit 470 deployed above rows 401-407 is divided into three discrete sub-units 471, 472, and 473, each deployed above rows 401, 403-405, and 407, respectively. According to some embodiments, sub-units 471, 472, and 473 are connected by leads 470A, 470B, 470C, and 470D in a MEOL or BEOL. According to some embodiments, a sub-unit covers more than one row. According to some embodiments, a sub-unit covers rows with different heights. For example, sub-unit 473 covers three rows 403-405 with at least two different heights. According to some embodiments, leads connect the sub-units within the discrete multi-row unit to components outside the discrete multi-row unit. For example, leads 470A and 470E connect sub-units 471 and 473 to components outside the discrete multi-row unit 470. According to some embodiments, the discrete multi-row units 480 deployed above rows 401-408 are divided into two discrete sub-units 481 and 482, each deployed above rows 403 and 405 respectively. According to some embodiments, sub-units 481 and 482 are connected via leads 480A, 480B, 480C, and 480D in a MEOL or BEOL. As discussed above, all empty space surrounding the sub-units can be used to fill other units or signal routes. According to some embodiments, rows 401-408 have more than two row heights.

[0080] Figure 6This is a diagram of blank space and marker layers in a discrete multi-row unit system according to some embodiments. For illustrative purposes, the discrete multi-row unit 610 has the same configuration as the discrete multi-row unit 410 discussed above, with unit 610 deployed above rows 401, 402, and 403. Unit 610 is divided into two discrete sub-units 611 and 612, respectively, deployed above rows 401 and 403 and connected by leads 610A and 610B. According to some embodiments, the space 615 between discrete sub-units 611 and 612 is a blank space that can be filled with other units (e.g., units 682 with matching geometry). According to some embodiments, the other unit 682 is another functional unit with matching geometry. According to some embodiments, the other unit 682 is a spare unit or simulation of the matching geometry. According to some embodiments, the other unit 682 with matching geometry does not need to occupy the entire blank space 615; instead, the other unit 682 with matching geometry may only fill a portion of the blank space 615.

[0081] For illustrative purposes, the discrete multi-row unit 640 has the same configuration as the discrete multi-row unit 440 discussed above. According to some embodiments, unit 640 is divided into sub-units 641, 642, 643, and 644 connected above rows 401, 403, 405, and 407 via leads 640A, 640B, 640C, and 640D in MEOL or BEOL, respectively. The empty spaces surrounding the sub-units can be filled with other units or signal routes. According to some embodiments, empty space 645 is filled with another unit 685 with matching geometry, empty space 646 is filled with another unit 686 with matching geometry, empty spaces 647 and 647' are filled with another unit 687 with matching geometry, empty space 649 is filled with another unit 689 with matching geometry, and empty space 648 remains empty. As illustrated, other units can be placed entirely or partially within the empty spaces, provided their geometry matches. According to some embodiments, some other units 681, 683, and 684 are outside any blank spaces of the discrete multi-line units 610 and 640. According to some embodiments, the marker layer is implemented for the layout as either text or polygons to identify blank spaces 645, 646, 647, 647', 648, and 649.

[0082] Figure 7 This is a diagram illustrating cell placement and routing in a discrete multi-row cell system according to some embodiments. According to some embodiments, the empty space surrounding the discrete sub-cells can be used for signal routing, power routing, grounding routing, and clock networks. Besides... Figure 6 Discrete sub-units and other units in the process, Figure 7Examples include horizontal lead wire connections 710A, 710B, 710C, 720A, 720B, and 720C. For example, lead wire 710C is implemented as a lead wire feedthrough. According to some embodiments, these lead wire connections are implemented to connect or feed through discrete sub-units, other functional units, or spare units. According to some embodiments, this effective use of blank space between or among discrete sub-units maintains unit area reduction and efficiency while reducing negative impacts on other units.

[0083] Figure 8 This is a flowchart illustrating a method for designing a multi-row cell in a discrete multi-row cell system according to some embodiments. According to some embodiments, the method for designing a multi-row cell in a discrete multi-row cell system 800 includes step 810: obtaining a hybrid row specification, which includes, for example, the geometric configuration of the hybrid rows, row height, number of fins, position, and order. At step 820, obtaining a cell drive target specification, which includes, for example, cell drive target information for each cell, discrete sub-cells, etc. At step 830, analyzing the discrete multi-row specification. According to some embodiments, each row has a row height corresponding to the number of fins. According to some embodiments, all row heights are the same. According to some embodiments, there are at least two different row heights corresponding to at least two different numbers of fins. Step 830 includes: decomposing the hybrid row system to understand the specifications of each row pattern, such as row height and available fins for oxide diffusion. Step 830 also includes: estimating the achievable drive strength of the discrete multi-row cells based on the hybrid row specification and the cell drive target specification. At step 840, deriving the discrete multi-row cell pattern. According to some embodiments, by analyzing the row height and cell configuration, the cell is divided into discrete multi-row sub-cells that match the row height and cell drive target specifications, as discussed above. Step 840 includes: generating usable discrete multi-row patterns and components, such as Figure 4 and Figure 5Examples of cells 410-480 are shown. At step 850, discrete multi-row cells are generated by dividing the cells into sub-cells with matching geometries and target cell drive specifications. Step 850 includes generating target discrete multi-row cells based on the patterns and specifications discussed above. At step 860, discrete multi-row cell quality control is performed to ensure that the generated discrete multi-row cells match the quality control target. Step 860 includes analyzing each generated cell to ensure that there are no design rule violations within or between cells. At step 870, if quality control fails, the process returns to step 850 to regenerate discrete multi-row cells. At step 870, if quality control passes, the process proceeds to step 880. At step 880, a marker layer is generated in the blank space to potentially accommodate other cells with matching geometries and performance specifications in the blank space. Step 880 includes implementing the marker layer in the blank space to allow lead feedthroughs and other cell placement to achieve better area shrinkage and reduce the impact of discrete multi-row cells. At step 890, the discrete multi-row cell matching specification is completed.

[0084] Figure 9 This is a system diagram illustrating a layout design system according to some embodiments. According to some embodiments, the layout design system 900 includes at least a processor 990 for processing all information related to the design of the floor plan and cell layout, etc. The layout design system 900 also includes at least a memory module 920 for storing information related to the floor plan and cell layout. The memory module 920 may also be implemented to store software and tools for layout design and related tasks. According to some embodiments, the layout design system 900 may include an input and output module 930, and the layout design system 900 may be connected to a network 910 for information exchange. According to some embodiments, the layout design system 900 may be connected to a manufacturing tool 940, after which the layout design is transferred to the manufacturing tool 940 for manufacturing integrated circuits according to the layout design. According to some embodiments, the layout design system 900 may be connected to a layout generation tool, an IC manufacturing tool, and a mask manufacturing tool.

[0085] According to some embodiments, a hybrid row height system is disclosed. The hybrid row height system includes: a plurality of rows having at least two different row heights, a first sub-unit deployed on a first unit row having a first row height, and a second sub-unit deployed on a second unit row having a second row height, wherein the first row and the second row are separated by a third unit row having a third row height different from the first row height, and wherein the first sub-unit and the second sub-unit are electrically connected at least by leads.

[0086] In some embodiments, the height of the third row is different from the height of the second row. In some embodiments, the height of the first row is the same as the height of the second row. In some embodiments, the height of the first row is different from the height of the second row. In some embodiments, the height of the third row is less than the height of the first row. In some embodiments, the height of the third row is less than both the height of the first row and the height of the second row. In some embodiments, the first sub-unit has the same size as the second sub-unit. In some embodiments, the first sub-unit has a different size than the second sub-unit.

[0087] According to some embodiments, a method for designing a hybrid row height system is disclosed. The method includes: obtaining hybrid row specifications; obtaining unit-driven target specifications; analyzing discrete multi-row specifications; deriving discrete multi-row unit patterns; generating discrete multi-row units by dividing the units into discrete sub-units with matching geometries and target unit-driven specifications; performing discrete multi-row unit quality control to ensure that the generated discrete multi-row units match the quality control target; and, if the quality control fails, regenerating the discrete multi-row units by dividing the units into sub-units with matching geometries and target unit-driven specifications.

[0088] According to some embodiments, the method further includes: generating a marker layer for blank spaces under quality control conditions to potentially accommodate other cells with matching geometry and performance specifications in the blank spaces. According to some embodiments, the method further includes: generating discrete multi-row cells with matching specifications. According to some embodiments, analyzing the discrete multi-row specifications further includes: decomposing the hybrid row system to understand the specifications of each row pattern. According to some embodiments, analyzing the discrete multi-row specifications further includes: estimating the achievable drive strength of the discrete multi-row cells based on the hybrid row specifications and the cell drive target specifications. According to some embodiments, deriving the discrete multi-row cell patterns further includes: generating usable discrete multi-row patterns and components. According to some embodiments, performing quality control on the discrete multi-row cells further includes: analyzing the generated discrete multi-row cells to ensure that design rules are not violated in the generated discrete multi-row cells and other cells. According to some embodiments, generating a marker layer for blank spaces further includes: implementing the marker layer for blank spaces to allow lead feedthrough. According to some embodiments, generating a marker layer for blank spaces further includes: implementing the marker layer for blank spaces to allow the placement of other cells. According to some embodiments, generating a marker layer in the blank space is implemented to achieve a better area shrinkage rate and reduce the impact of discrete multi-row cells.

[0089] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made therein without departing from the spirit and scope of this disclosure.

Claims

1. A hybrid ride height system characterized by, comprising: a plurality of rows having at least two different row heights; and a discrete multi-row cell disposed on the rows, the multi-row cell comprising: a first sub-cell disposed on at least a first cell row having a first row height; a second sub-cell disposed on at least a second cell row having a second row height; and a plurality of void spaces surrounding the first sub-cell and the second sub-cell, wherein the first cell row and the second cell row have different numbers of fins, and the first cell row and the second cell row have row heights corresponding to the numbers of fins, respectively, wherein the void spaces are used to fill other cells having matching geometries, wherein the multi-row cell comprises a sub-cell covering more than one of the rows, wherein the second cell row is separated from the first cell row by a third cell row having a third row height, wherein the third row height is different from the first row height, and wherein the first sub-cell and the second sub-cell are electrically connected by at least a wire in the void spaces. wherein the third row height is different from the second row height.

2. The hybrid ground clearance system of claim 1, wherein, wherein the first row height is the same as the second row height.

3. The hybrid ground clearance system of claim 1, wherein, wherein the first row height is different from the second row height.

4. The hybrid ground clearance system of claim 1, wherein, wherein the third row height is less than the first row height.

5. The hybrid ground clearance system of claim 1, wherein, wherein the third row height is less than the first row height and the second row height.

6. The hybrid ground clearance system of claim 1, wherein, wherein the first sub-cell has the same size as the second sub-cell.

7. The hybrid ground clearance system of claim 1, wherein, wherein the first sub-cell has a different size than the second sub-cell.

8. The hybrid ground clearance system of claim 1, wherein, The method comprises:

9. A method of designing a hybrid step height system, characterized by, obtaining a plurality of hybrid row specifications having different row heights; obtaining a plurality of cell drive target specifications; analyzing the hybrid row specifications having different row heights; deriving a plurality of discrete multi-row cell patterns; generating a discrete multi-row cell by dividing a cell into a plurality of discrete sub-cells having matching geometries and target cell drive specifications; performing a quality control of the discrete multi-row cell to ensure that the generated discrete multi-row cell matches a plurality of quality control targets; and re-generating the discrete multi-row cell by dividing the cell into a plurality of sub-cells having matching geometries and target cell drive specifications under a condition that the discrete multi-row cell fails the quality control. further comprising:

10. The method of claim 9, wherein, under a condition that the discrete multi-row cell passes the quality control, generating a mark layer of a plurality of void spaces to potentially accommodate other cells having matching geometries and performance specifications in the void spaces. further comprising:

11. The method of claim 9, wherein, completing the generation of the discrete multi-row cell having a matching specification. wherein analyzing the hybrid row specifications further comprises:

12. The method of claim 9, wherein, decomposing a hybrid row system to understand a specification of each row pattern. wherein analyzing the hybrid row specifications further comprises:

13. The method of claim 12, wherein, estimating an achievable drive strength of the discrete multi-row cell from the hybrid row specifications and the cell drive target specifications. wherein deriving the discrete multi-row cell patterns further comprises:

14. The method of claim 9, wherein, generating a plurality of discrete multi-row patterns and a plurality of compositions available. wherein performing a quality control of the discrete multi-row cell further comprises:

15. The method of claim 9, wherein, analyzing the generated discrete multi-row cell to ensure that a design rule is not violated in the generated discrete multi-row cell and among other cells. wherein generating the mark layer of the void spaces further comprises:

16. The method of claim 10, wherein, ​ The mark layer implementing the blank spaces allows a wire feed-through.

17. The method of claim 10, wherein, The mark layer creating the blank spaces further comprises: The mark layer implementing the blank spaces allows other cells to be placed.

18. The method of claim 10, wherein, The mark layer creating the blank spaces is implemented to achieve a better area shrinkage and to reduce the impact of the discrete multi-row cells.

19. A hybrid lane system designed by a process, characterized by, The process comprises: Obtaining mixed row specifications having different row heights; Obtaining cell drive target specifications; Analyzing the mixed row specifications having different row heights; Deriving discrete multi-row cell patterns; Creating a discrete multi-row cell by splitting a cell into discrete sub-cells having matching geometry and target cell drive specifications; Performing a quality control of the discrete multi-row cell to ensure that the created discrete multi-row cell matches quality control targets; and Re-creating the discrete multi-row cell by splitting the cell into sub-cells having matching geometry and target cell drive specifications in a condition that the quality control is not passed.

20. The hybrid ground clearance system of claim 19, wherein, The process further comprises: In a condition that the quality control is passed, creating a mark layer of blank spaces to potentially accommodate other cells having matching geometry and performance specifications in the blank spaces.

21. A hybrid ride height system characterized by, Comprises: rows having at least two different row heights; and a discrete multi-row cell disposed on the rows, the multi-row cell comprising: a first sub-cell disposed on at least a first cell row having a first row height; a second sub-cell disposed on at least a second cell row having a second row height; and blank spaces surrounding the first sub-cell and the second sub-cell, wherein the first cell row and the second cell row have different numbers of fins, and the first cell row and the second cell row have row heights corresponding to the numbers of fins, respectively, wherein the blank spaces are used to fill other cells having matching geometry, wherein the multi-row cell comprises a sub-cell covering more than one of the rows, wherein the second cell row is separated from the first cell row by a third cell row having a third row height, wherein the third row height is smaller than the first row height and the second row height, and wherein the first sub-cell and the second sub-cell are electrically connected by at least a wire in the blank spaces. wherein the blank spaces are further used for a power routing.

22. The hybrid ground clearance system of claim 21, wherein, wherein the blank spaces are further used for a ground routing.

23. The hybrid ground clearance system of claim 21, wherein, wherein the blank spaces are further used for a clock network.

24. The hybrid ground clearance system of claim 21, wherein, wherein the first row height and the second row height are the same.

25. The hybrid ground clearance system of claim 21, wherein, wherein the first row height and the second row height are different.

26. The hybrid ground clearance system of claim 21, wherein, wherein the first sub-cell has the same size as the second sub-cell.

27. The hybrid ground clearance system of claim 21, wherein, wherein the first sub-cell has a different size than the second sub-cell.

28. The hybrid ground clearance system of claim 21, wherein, The method comprises:

29. A method of designing a hybrid step height system, characterized by, Obtaining mixed row specifications having different row heights; Obtaining cell drive target specifications; Analyzing the mixed row specifications having different row heights; Deriving discrete multi-row cell patterns; Creating a discrete multi-row cell by splitting a cell into discrete sub-cells having matching geometry and target cell drive specifications; and ​ performing a quality control of the discrete multi-row cell to ensure that the generated discrete multi-row cell matches a quality control target.

30. The method of claim 29, wherein, further comprising: generating a marker layer of blank spaces in the blank spaces to potentially accommodate other cells having matching geometry and performance specifications under a condition of passing the quality control.

31. The method of claim 29, wherein, further comprising: completing the generation of the discrete multi-row cell having a matching specification.

32. The method of claim 29, wherein, wherein analyzing the mixed row specifications further comprises: decomposing a mixed row system to understand a specification of each row pattern.

33. The method of claim 32, wherein, wherein analyzing the mixed row specifications further comprises: estimating an achievable drive strength of the discrete multi-row cell from the mixed row specifications and the cell drive target specifications.

34. The method of claim 29, wherein, wherein deriving the discrete multi-row cell patterns further comprises: generating available discrete multi-row patterns and compositions.

35. The method of claim 29, wherein, wherein performing a quality control of the discrete multi-row cell further comprises: analyzing the generated discrete multi-row cell to ensure that a design rule is not violated in the generated discrete multi-row cell and among other cells.

36. The method of claim 30, wherein, wherein generating the marker layer of blank spaces further comprises: implementing the marker layer of blank spaces to allow a wire feedthrough.

37. The method of claim 30, wherein, wherein generating the marker layer of blank spaces further comprises: implementing the marker layer of blank spaces to allow other cell placement.

38. The method of claim 30, wherein, wherein generating the marker layer on the blank spaces is implemented to achieve a better area shrinkage and reduce the impact of the discrete multi-row cell.

39. A hybrid lane system designed by a process, wherein the process comprises: obtaining mixed row specifications having different row heights; obtaining cell drive target specifications; analyzing the mixed row specifications having different row heights; deriving discrete multi-row cell patterns; generating a discrete multi-row cell by splitting a cell into discrete sub-cells having matching geometry and target cell drive specifications; and performing a quality control of the discrete multi-row cell to ensure that the generated discrete multi-row cell matches a quality control target.

40. The hybrid track system of claim 39, wherein, wherein the process further comprises: generating a marker layer of blank spaces in the blank spaces to potentially accommodate other cells having matching geometry and performance specifications under a condition of passing the quality control. further comprising: completing the generation of the discrete multi-row cell having a matching specification. wherein analyzing the mixed row specifications further comprises: decomposing a mixed row system to understand a specification of each row pattern. wherein analyzing the mixed row specifications further comprises: estimating an achievable drive strength of the discrete multi-row cell from the mixed row specifications and the cell drive target specifications. wherein deriving the discrete multi-row cell patterns further comprises: generating available discrete multi-row patterns and compositions. wherein performing a quality control of the discrete multi-row cell further comprises: analyzing the generated discrete multi-row cell to ensure that a design rule is not violated in the generated discrete multi-row cell and among other cells. wherein generating the marker layer of blank spaces further comprises: implementing the marker layer of blank spaces to allow a wire feedthrough. wherein generating the marker layer of blank spaces further comprises: implementing the marker layer of blank spaces to allow other cell placement. wherein generating the marker layer on the blank spaces is implemented to achieve a better area shrinkage and reduce the impact of the discrete multi-row cell. the process comprises: obtaining mixed row specifications having different row heights; obtaining cell drive target specifications; analyzing the mixed row specifications having different row heights; deriving discrete multi-row cell patterns; generating a discrete multi-row cell by splitting a cell into discrete sub-cells having matching geometry and target cell drive specifications; and performing a quality control of the discrete multi-row cell to ensure that the generated discrete multi-row cell matches a quality control target. wherein the process further comprises: generating a marker layer of blank spaces in the blank spaces to potentially accommodate other cells having matching geometry and performance specifications under a condition of passing the quality control.

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