Display device and method for inspecting a display device

Abstract

A display device and a method of inspecting the display device are disclosed. The display device includes: a data line; a first gate line arranged in parallel with the data line; a second gate line intersecting the first gate line; a line contact portion in which each of a plurality of first gate lines and each of a plurality of second gate lines are in contact with each other; a non-contact portion in which each of the plurality of first gate lines and each of the plurality of second gate lines are insulated from each other in their intersecting regions; a first pixel including a first switching element connected to a corresponding second gate line among the second gate lines; and a second pixel including a second switching element connected to the second gate line connected to the first pixel, wherein a magnitude of a first capacitance of the first switching element is different from a magnitude of a first capacitance of the second switching element.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2020-0002202, filed with the Korean Intellectual Property Office on January 7, 2020, and Korean Patent Application No. 10-2020-0052679, filed with the Korean Intellectual Property Office on April 29, 2020, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0002] The present disclosure relates to a display device, and more particularly, to a display device capable of preventing spots caused by luminance variations of a plurality of pixels. Background Art

[0003] Recently, the demand for various types of display devices for displaying images has increased. For example, display devices are applied to various electronic devices such as smart phones, digital cameras, laptop computers, navigators, and smart TVs. The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, or an organic light emitting display device.

[0004] Generally, a liquid crystal display device includes two substrates facing each other, pixel electrodes disposed between the two substrates, a liquid crystal layer, and a common electrode. The liquid crystal display device uses an electric field formed between the pixel electrode and the common electrode to determine the orientation of liquid crystal molecules and controls the polarization of incident light to display an image. Recently, technologies for minimizing the bezel area of liquid crystal displays have been studied and developed. However, there are still many problems such as deterioration or spots when displaying images on different display devices. Therefore, it is necessary to develop a novel display device to prevent spots or deterioration and thus improve the display quality. Summary of the Invention

[0005] An aspect of the present disclosure provides a display device capable of compensating for a difference in kickback voltage according to a capacitance difference between a plurality of vertical gate lines and a plurality of pixel electrodes, thereby preventing spots caused by luminance variations of a plurality of pixels.

[0006] An aspect of the present disclosure provides a method of inspecting a display device, in which an illumination inspection is performed by using a data pad unit and a gate driver disposed at one side of a substrate.

[0007] However, the aspects of the present disclosure are not limited to one aspect set forth herein. The above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referring to the following detailed description of the present disclosure.

[0008] According to an embodiment, a display device is provided. The display device includes: a plurality of data lines extending in a first direction; a plurality of first gate lines arranged in parallel with the plurality of data lines; a plurality of second gate lines intersecting the plurality of first gate lines; a line contact portion in which each of the plurality of first gate lines and each of the plurality of second gate lines are in contact with each other; a non-contact portion in which each of the plurality of first gate lines and each of the plurality of second gate lines are insulated from each other in an intersection region of the plurality of first gate lines and the plurality of second gate lines; a first pixel including a first switching element connected to a corresponding second gate line among the plurality of second gate lines and disposed adjacent to the line contact portion; and a second pixel including a second switching element connected to the second gate line connected to the first pixel and disposed adjacent to the non-contact portion, wherein a magnitude of a first capacitance between a gate electrode and a first electrode of the first switching element is different from a magnitude of a first capacitance between a gate electrode and a first electrode of the second switching element.

[0009] The magnitude of the first capacitance of the first switching element may be smaller than the magnitude of the first capacitance of the second switching element.

[0010] The first electrode of the first switching element may be connected to a first pixel electrode of the first switching element, and the first electrode of the second switching element may be connected to a second pixel electrode of the second switching element, and wherein a size of an overlapping region between the gate electrode and the first electrode of the first switching element may be smaller than a size of an overlapping region between the gate electrode and the first electrode of the second switching element.

[0011] The size of the gate electrode of the first switching element may be smaller than the size of the gate electrode of the second switching element.

[0012] The size of the active region of the first switching element may be smaller than the size of the active region of the second switching element.

[0013] The first electrode of the first switching element may be connected to a first pixel electrode of the first switching element, and the first electrode of the second switching element may be connected to a second pixel electrode of the second switching element, and wherein the size of the first electrode of the first switching element may be smaller than the size of the first electrode of the second switching element.

[0014] The magnitude of a second capacitance between the first pixel electrode of the first pixel and an adjacent first gate line among the plurality of first gate lines of the first switching element may be different from the magnitude of a second capacitance between the second pixel electrode of the second pixel and an adjacent first gate line among the plurality of first gate lines of the second switching element.

[0015] The magnitude of the second capacitance of the first switching element may be larger than the magnitude of the second capacitance of the second switching element.

[0016] When the gate electrode of the first switching element receives a gate-on voltage from the second gate line, the first gate line among the plurality of first gate lines adjacent to the first pixel can supply the gate-on voltage.

[0017] When the gate electrode of the second switching element receives a gate-on voltage from the second gate line, the first gate line among the plurality of first gate lines adjacent to the second pixel can have a gate-off voltage.

[0018] According to another embodiment, a display device is provided. The display device includes: a plurality of first gate lines extending in a first direction; a plurality of second gate lines extending in a second direction intersecting the first direction; a line contact portion in which each of the plurality of first gate lines contacts each of the plurality of second gate lines; a non-contact portion in which each of the plurality of first gate lines and each of the plurality of second gate lines are insulated from each other in an intersection region of the plurality of first gate lines and the plurality of second gate lines; a first pixel including a first switching element connected to a corresponding second gate line among the plurality of second gate lines and disposed adjacent to the line contact portion; a second pixel including a second switching element connected to the second gate line connected to the first pixel and disposed adjacent to the non-contact portion; and a third pixel including a third switching element connected to the second gate line connected to the first pixel and the second pixel and disposed between the first switching element and the second switching element, wherein the magnitudes of the first capacitances between the gate electrodes and the first electrodes of each of the first to third switching elements are different from each other.

[0019] The magnitude of the first capacitance of the third switching element can be larger than the magnitude of the first capacitance of the first switching element, and the magnitude of the first capacitance of the second switching element can be larger than the magnitude of the first capacitance of the third switching element.

[0020] The first electrode of the first switching element can be connected to the first pixel electrode of the first switching element, the first electrode of the second switching element can be connected to the second pixel electrode of the second switching element, and the first electrode of the third switching element can be connected to the third pixel electrode of the third switching element, and the size of the overlapping region of the gate electrode and the first electrode of the third switching element can be larger than the size of the overlapping region of the gate electrode and the first electrode of the first switching element, and the size of the overlapping region of the gate electrode and the first electrode of the second switching element can be larger than the size of the overlapping region of the gate electrode and the first electrode of the third switching element.

[0021] The size of the gate electrode of the third switching element can be larger than the size of the gate electrode of the first switching element, and the size of the gate electrode of the second switching element can be larger than the size of the gate electrode of the third switching element.

[0022] The size of the active region of the third switching element may be larger than the size of the active region of the first switching element, and the size of the active region of the second switching element is larger than the size of the active region of the third switching element.

[0023] The first electrode of the first switching element may be connected to the first pixel electrode of the first switching element, the first electrode of the second switching element may be connected to the second pixel electrode of the second switching element, and the first electrode of the third switching element may be connected to the third pixel electrode of the third switching element, and wherein, the size of the first electrode of the third switching element may be larger than the size of the first electrode of the first switching element, and the size of the first electrode of the second switching element may be larger than the size of the first electrode of the third switching element.

[0024] According to an embodiment of the present disclosure, a display device includes: a substrate having a display area and a non-display area, and including a gate pad unit and a data pad unit disposed at one side of the non-display area; a flexible film connected to the gate pad unit and the data pad unit; and a display driving circuit disposed on the flexible film. The substrate includes: a plurality of data lines extending in a first direction in the display area; a plurality of first gate lines arranged parallel to the plurality of data lines; and a plurality of second gate lines intersecting the plurality of first gate lines. The display driving circuit includes: a data driver connected to the data pad unit to supply data voltages to the plurality of data lines; and a gate driver connected to the gate pad unit to supply gate signals to the plurality of first gate lines.

[0025] The substrate may include: a line contact portion in which each of the plurality of first gate lines contacts each of the plurality of second gate lines; a non-contact portion in which each of the plurality of first gate lines and each of the plurality of second gate lines are insulated from each other at the intersection of the plurality of first gate lines and the plurality of second gate lines; a plurality of first pixels including a first switching element, the first switching element being connected to a corresponding second gate line of the plurality of second gate lines and disposed adjacent to the line contact portion; a plurality of second pixels including a second switching element, the second switching element being connected to the second gate line connected to the first pixel and disposed adjacent to the non-contact portion; and a plurality of third pixels including a third switching element, the third switching element being connected to the second gate line connected to the first switching element and the second switching element and disposed between the first switching element and the second switching element.

[0026] The plurality of third pixels include: a third-first pixel connected to a first data line among a plurality of data lines and a second-first gate line among a plurality of second gate lines; a third-second pixel disposed below the third-first pixel and connected to a second data line among the plurality of data lines and the second-first gate line; a third-third pixel disposed below the third-second pixel and connected to the second data line and a second-second gate line among the plurality of second gate lines; and a third-fourth pixel disposed below the third-third pixel and connected to the first data line and the second-second gate line.

[0027] According to an embodiment of the present disclosure, a method for inspecting a display device includes the following steps: applying a data test voltage to a data test pad unit disposed on a second substrate, and supplying the data test voltage to a data pad unit connected to the data test pad unit and disposed at one side of a first substrate; and applying a gate test signal to a gate test pad unit disposed on the second substrate, and supplying the gate test signal to a gate pad unit connected to the gate test pad unit and disposed at one side in the first substrate.

[0028] Supplying the data test voltage may include the following steps: allowing the data test pad unit to supply the data test voltage to a first fan-out line; allowing the first fan-out line to supply the data test voltage to a data connection line intersecting the first fan-out line; allowing the data connection line to supply the data test voltage to a second fan-out line extending from the first fan-out line; and allowing the second fan-out line to supply the data test voltage to the data pad unit.

[0029] Supplying the gate test signal may include the following steps: allowing the gate test pad unit to supply the gate test signal to a first fan-out line; allowing the first fan-out line to supply the gate test signal to a gate connection line intersecting the first fan-out line; allowing the gate connection line to supply the gate test signal to a second fan-out line extending from the first fan-out line; and allowing the second fan-out line to supply the gate test signal to the gate pad unit.

[0030] Supplying the gate test signal may further include the following steps: allowing the first fan-out line to supply the gate test signal to a gate contact line parallel to the gate connection line.

[0031] According to an embodiment of the present disclosure, a method for inspecting a display device includes the following steps: supplying a data voltage to a data pad unit disposed at one side of a substrate; allowing the data pad unit to supply the data voltage to a plurality of data lines extending in a first direction; supplying a gate signal to a gate pad unit disposed at one side of the substrate; allowing the gate pad unit to supply the gate signal to a plurality of first gate lines parallel to the plurality of data lines; and allowing each of the plurality of first gate lines to supply the gate signal to each of a plurality of second gate lines intersecting the plurality of first gate lines.

[0032] Supplying a data voltage to a data pad unit may include the steps of allowing a data driver to supply the data voltage to the data pad unit through leads of a flexible film, the data driver being disposed on the flexible film attached to one side of a substrate.

[0033] Supplying a gate signal to a gate pad unit may include the steps of allowing a gate driver to supply the gate signal to the gate pad unit through leads of the flexible film, the gate driver being disposed on the flexible film.

[0034] According to an embodiment of the display device, the display device may use a difference between a gate-source capacitance of a first pixel and a gate-source capacitance of a second pixel to compensate for a difference between a capacitance between a vertical gate line supplying a gate-on voltage and a first pixel electrode and a capacitance between a vertical gate line supplying a gate-off voltage and a second pixel electrode, thereby minimizing a difference in kickback voltages of a plurality of pixels and preventing blotches caused by a brightness change of the plurality of pixels.

[0035] Furthermore, according to an embodiment of the display device, the display device may use a difference in gate-source capacitances of a first pixel to a third pixel to compensate for a difference in kickback voltages between a plurality of vertical gate lines and a first pixel electrode to a third pixel electrode, thereby minimizing a difference in kickback voltages between the first pixel to the third pixel and removing a brightness change of the plurality of pixels.

[0036] Furthermore, according to a method of inspecting a display device according to an embodiment, an illumination inspection may be performed by using a data pad unit and a gate driver disposed at one side of a substrate, thereby reducing a non-display area of the display device, improving reliability of the display device, and reducing a cost of the illumination inspection. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The above and other features and aspects of the present disclosure will become more apparent by referring to the following detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0038] Figure 1 is a perspective view of a display device according to an embodiment;

[0039] Figure 2 is a plan view of a display device according to an embodiment;

[0040] Figure 3 shows a connection relationship between a plurality of pixels and a plurality of gate lines in a display device according to an embodiment;

[0041] Figure 4 is a circuit diagram showing a pixel circuit of a first pixel in a display device according to an embodiment;

[0042] Figure 5is a circuit diagram showing a pixel circuit of a second pixel in a display device according to an embodiment;

[0043] Figure 6 is a circuit diagram showing a pixel circuit of a third pixel in a display device according to an embodiment;

[0044] Figure 7 is a plan view showing first to third pixels in a display device according to an embodiment;

[0045] Figure 8 is along Figure 7 a cross-sectional view taken along line I-I';

[0046] Figure 9 is a plan view showing first to third pixels and first to third pixel electrodes in a display device according to an embodiment;

[0047] Figure 10 is along Figure 9 a cross-sectional view taken along line II-II';

[0048] Figure 11 is a plan view showing first to third switching elements in a display device according to an embodiment;

[0049] Figure 12 briefly shows Figure 11 the gate electrodes and source electrodes of each of the first to third switching elements shown in;

[0050] Figure 13 is a plan view showing first to third switching elements in a display device according to another embodiment;

[0051] Figure 14 briefly shows Figure 13 the first to third switching elements shown in;

[0052] Figure 15 is a plan view showing first to third switching elements in a display device according to still another embodiment;

[0053] Figure 16 briefly shows Figure 15 the gate electrodes and source electrodes of each of the first, second, and third switching elements shown in;

[0054] Figure 17 is a plan view of a display device in an inspection process in a method of inspecting a display device according to an embodiment;

[0055] Figure 18 is Figure 17An enlarged view of region A1;

[0056] Figure 19 Shows the connection relationship between test pads and pixels in a method for inspecting a display device according to an embodiment;

[0057] Figure 20 Is a flowchart showing a process for inspecting a display device according to an embodiment;

[0058] Figure 21 Is a flowchart showing a process for supplying a data test voltage in a method for inspecting a display device according to an embodiment;

[0059] Figure 22 Is a flowchart showing a process for supplying a gate test signal in a method for inspecting a display device according to an embodiment;

[0060] Figure 23 Shows the connection relationship between a display driving circuit and a panel pad unit in a method for inspecting a display device according to another embodiment; and

[0061] Figure 24 Is a flowchart showing a process for inspecting a display device according to another embodiment. Detailed Description of the Embodiments

[0062] By referring to the following detailed description of the embodiments and the accompanying drawings, the features of the present disclosure and the methods for implementing the present disclosure can be more easily understood. However, the present disclosure can be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the concept of the present disclosure to those skilled in the art, and the present disclosure will be defined only by the appended claims. Throughout the specification, the same reference numerals refer to the same elements.

[0063] It will be understood that when an element or layer is referred to as being "on", "connected to", or "coupled to" another element or layer, the element or layer can be directly on, directly connected to, or directly coupled to the other element or layer, or there can be intervening elements or layers. In contrast, when an element is referred to as being "directly on", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. As used herein, the term "and / or" includes any combination and all combinations of one or more of the associated listed items.

[0064] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0065] Figure 1 Is a perspective view of a display device according to an embodiment, Figure 2It is a plan view of a display device according to an embodiment.

[0066] In this specification, "on", "above", "top", "upper side", or "upper surface" refer to the upward direction with respect to the display device 10, that is, the Z-axis direction, and "below", "beneath", "bottom", "lower side", or "lower surface" refer to the downward direction with respect to the display device 10, that is, the direction opposite to the Z-axis direction. In addition, "left", "right", "up", and "down" refer to the directions when viewing the display device 10 from a plane. For example, "left" refers to the direction opposite to the X-axis direction, "right" refers to the X-axis direction, "up" refers to the Y-axis direction, and "down" refers to the direction opposite to the Y-axis direction.

[0067] Referring to Figure 1 and Figure 2 , the display device 10 as a device for displaying moving images or still images can be used as a display screen for various products such as televisions, notebooks, monitors, billboards, the Internet of Things (IoT), and portable electronic devices (such as mobile phones, smartphones, tablet personal computers (tablet PCs), smartwatches, watch phones, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigators, and ultra-mobile personal computers (UMPCs)).

[0068] The display device 10 may include a display panel 100 and a display driver 200.

[0069] The display panel 100 may have a rectangular shape in a plan view. For example, the display panel 100 may have a rectangular planar shape having a long side in a first direction (X-axis direction) and a short side in a second direction (Y-axis direction). The corner where the long side in the first direction (X-axis direction) intersects the short side in the second direction (Y-axis direction) may be formed in a right-angle shape or a circular shape having a predetermined curvature. The planar shape of the display panel 100 is not limited to a rectangular shape and may be formed into any polygonal shape, circular shape, or elliptical shape. For example, the display panel 100 may be formed flat, but is not limited thereto. As another example, the display panel 100 may be formed to be curved with a predetermined curvature.

[0070] The display panel 100 may include a first substrate 110 and a second substrate 120. The first substrate 110 and the second substrate 120 may face each other along the thickness direction (Z-axis direction). The first substrate 110 and the second substrate 120 may be made of glass or plastic. For example, the display panel 100 may be implemented as a liquid crystal display panel including a liquid crystal layer disposed between the first substrate 110 and the second substrate 120.

[0071] The length of the first substrate 110 in the second direction (Y-axis direction) may be longer than the length of the second substrate 120 in the second direction (Y-axis direction). For example, a part of the upper surface of the first substrate 110 may be exposed without being covered by the second substrate 120. The exposed upper surface of the first substrate 110 may include a pad (or referred to as a "bond pad") unit (not shown) to which the display driver 200 is connected.

[0072] As Figure 2 described, the first substrate 110 may include a display area DA and a non-display area NDA.

[0073] The display area DA, which is an area for displaying an image, may be defined as the central area of the first substrate 110. The display area DA may include a plurality of pixels SP formed for each pixel area where a plurality of data lines DL and a plurality of gate lines GL intersect. The plurality of gate lines GL may include a plurality of first gate lines VGL and a plurality of second gate lines HGL. For example, the plurality of first gate lines VGL may be a plurality of vertical gate lines VGL connected to the display driving circuit 220 and extending in the second direction (Y-axis direction), and the plurality of second gate lines HGL may be a plurality of horizontal gate lines HGL connected to any one of the plurality of vertical gate lines VGL and extending in the first direction (X-axis direction). Each of the plurality of pixels SP may be connected to at least one horizontal gate line HGL and at least one data line DL. Each of the plurality of pixels SP may be defined as an area of a minimum unit for outputting light.

[0074] The plurality of data lines DL may extend in the second direction (Y-axis direction) and may be spaced apart from each other in the first direction (X-axis direction). For example, a plurality of pixels SP arranged in a column may receive data voltages through two data lines DL. Among the plurality of pixels SP, the pixels SP arranged in some rows may receive data voltages from the data line DL provided on the left side, and the pixels SP arranged in other rows may receive data voltages from the data line DL provided on the right side.

[0075] A plurality of vertical gate lines VGL may extend in a second direction (Y-axis direction) and may be spaced apart from each other in a first direction (X-axis direction). The plurality of vertical gate lines VGL may be arranged in parallel with the plurality of data lines DL. A plurality of horizontal gate lines HGL may extend in the first direction (X-axis direction) and may be spaced apart from each other in the second direction (Y-axis direction). Each of the plurality of horizontal gate lines HGL may intersect with the plurality of vertical gate lines VGL. For example, one vertical gate line VGL may be connected to two horizontal gate lines HGL. Each of one vertical gate line VGL and two horizontal gate lines HGL may be connected through a line contact portion MDC. Each of the line contact portions MDC may correspond to a portion where the gate insulating film is omitted in the overlapping region of the vertical gate line VGL and the horizontal gate line HGL.

[0076] For example, one vertical gate line VGL may be connected to two horizontal gate lines HGL. In this case, among the plurality of pixels SP, the pixels SP arranged in some rows may receive a data voltage from the data line DL provided on the left side, and the pixels SP arranged in other rows may receive a data voltage from the data line DL provided on the right side. As another example, one vertical gate line VGL may be connected to one horizontal gate line HGL. In this case, each of the plurality of pixels SP may receive a data voltage from the data line DL provided on one side. Therefore, the connection relationship among the plurality of data lines DL, the plurality of vertical gate lines VGL, the plurality of horizontal gate lines HGL, and the plurality of pixels SP is not limited to Figure 2 the connection relationship shown in. The connection relationship among the plurality of data lines DL, the plurality of vertical gate lines VGL, the plurality of horizontal gate lines HGL, and the plurality of pixels SP may vary according to the number and arrangement of the plurality of pixels SP.

[0077] The non-display area NDA may be defined in the remaining area of the first substrate 110 except for the display area DA. For example, the non-display area NDA may include fan-out lines connecting the data line DL or the vertical gate line VGL to the display driving circuit 220 and pad units connected to the flexible film 210.

[0078] The display driver 200 may be connected to the pad units provided in the non-display area NDA of the first substrate 110 to display an image on the plurality of pixels SP based on image data supplied from a display driving system (not shown). The display driver 200 may include a flexible film 210, a display driving circuit 220, a circuit board 230, a timing controller 240, and a power supply unit 250.

[0079] An input terminal provided at one end of the flexible film 210 may be fixedly attached to the circuit board 230 through a film attachment process, and an output terminal provided at the other end of the flexible film 210 may be fixedly attached to the pad unit through the film attachment process. For example, the flexible film 210 may be a bendable flexible film such as a tape carrier package or a chip on film. The flexible film 210 may be bent toward the lower part of the first substrate 110 to reduce the bezel area of the display device 10.

[0080] The display driving circuit 220 may be mounted on the flexible film 210. For example, the display driving circuit 220 may be implemented as an integrated circuit (IC). The display driving circuit 220 may receive digital video data and a data control signal from the timing controller 240, convert the digital video data into an analog positive / negative data voltage according to the data control signal, and transmit the analog positive / negative data voltage to the data line DL through the fan-out line. In addition, the display driving circuit 220 may generate a gate signal according to the gate control signal supplied from the timing controller 240, and may sequentially supply the gate signal to the plurality of vertical gate lines VGL in a set order.

[0081] The circuit board 230 may support the timing controller 240 and the power supply unit 250, and may transmit signals and power between the components of the display driver 200. For example, the circuit board 230 may supply the signals supplied from the timing controller 240 and the driving power supplied from the power supply unit 250 to the display driving circuit 220 to display an image on each pixel SP. To this end, signal transmission lines and a plurality of power lines may be provided on the circuit board 230.

[0082] The timing controller 240 may be mounted on the circuit board 230, and receive image data and a timing synchronization signal supplied from the display driving system through a user connector provided on the circuit board 230. The timing controller 240 may generate digital video data by aligning the image data according to the pixel arrangement structure based on the timing synchronization signal, and may supply the generated digital video data to the corresponding display driving circuit 220. The timing controller 240 may generate a data control signal and a gate control signal based on the timing synchronization signal. The timing controller 240 may control the data voltage supply timing of the display driving circuit 220 based on the data control signal, and may control the gate signal supply timing of the display driving circuit 220 based on the gate control signal.

[0083] The power supply unit 250 may be disposed on the circuit board 230 to supply a driving voltage to the display driving circuit 220 and the display panel 100. For example, the power supply unit 250 may generate a first driving voltage and supply the first driving voltage to each of a plurality of pixels SP disposed on the first substrate 110, and may generate a second driving voltage and supply the second driving voltage to a common electrode disposed on the second substrate 120. The first driving voltage may correspond to a high potential voltage for driving the plurality of pixels SP, and the second driving voltage may correspond to a common voltage commonly supplied to the plurality of pixels SP.

[0084] For example, the display device 10 may further include a sealing member (not shown) disposed between the first substrate 110 and the second substrate 120. The sealing member may surround a liquid crystal layer formed between the first substrate 110 and the second substrate 120. The sealing member may be disposed around an edge of the display area DA to attach the first substrate 110 and the second substrate 120 to each other. The sealing member may seal the liquid crystal layer to prevent the liquid crystal layer from being exposed to the outside of the display area DA.

[0085] Figure 3 The connection relationship between a plurality of pixels and a plurality of gate lines in a display device according to an embodiment is shown.

[0086] Referring to Figure 3 , the plurality of pixels SP may include a first pixel to a third pixel SP1, SP2, and SP3. Each of the first pixel to the third pixel SP1, SP2, and SP3 may be connected to at least one data line DL and at least one horizontal gate line HGL.

[0087] The data lines from DLm to DLm+11 (where m is a natural number hereinafter) can extend in the second direction (Y-axis direction) and can be separated from each other in the first direction (X-axis direction). A plurality of pixels SP arranged along a column can receive data voltages through two data lines DL. For example, the pixels SP arranged in column COLj (where j is a natural number hereinafter) can receive data voltages from data line DLm and data line DLm+1. In addition, among the plurality of pixels SP, the pixels SP arranged in row ROWk and row ROWk+3 (where k is a natural number hereinafter) can receive data voltages from data lines DLm, DLm+2,..., and DLm+10 arranged on the left side. Among the plurality of pixels SP, the pixels SP arranged in row ROWk+1 and row ROWk+2 can receive data voltages from data lines DLm+1, DLm+3,..., and DLm+11 arranged on the right side. Since the n-th horizontal gate line HGLn can supply the gate conduction voltage to the pixels SP arranged in the k-th row ROWk and the pixels SP arranged in the k+1-th row ROWk+1 simultaneously, the pixels SP arranged in the k-th row ROWk can receive data voltages from the data lines DL arranged on the left side, and the pixels SP arranged in the k+1-th row ROWk+1 can receive data voltages from the data lines DL arranged on the right side, so that each of the plurality of pixels SP can independently display gray levels.

[0088] A plurality of vertical gate lines VGL can be arranged in parallel with the plurality of data lines DL. Each of the plurality of horizontal gate lines HGL can cross each of the plurality of vertical gate lines VGL. In this case, each of the plurality of horizontal gate lines HGL can be substantially perpendicular to each of the plurality of vertical gate lines VGL. One vertical gate line VGL can be connected to two horizontal gate lines HGL. For example, the n-th vertical gate line VGLn can be connected to two n-th horizontal gate lines HGLn arranged along each of the k-th row ROWk and the k+1-th row ROWk+1. The n-th vertical gate line VGLn can be connected to the n-th horizontal gate line HGLn through a line contact portion MDC. The n-th vertical gate line VGLn can be insulated from other horizontal gate lines among the plurality of horizontal gate lines HGL except the n-th horizontal gate line HGLn in a non-contact portion NMC. The non-contact portion NMC can correspond to the portions insulated from each other at the intersection of the vertical gate line VGL and the horizontal gate line HGL. The n-th vertical gate line VGLn can be insulated from the n+1-th horizontal gate line HGLn+1 and the non-contact portion NMC.

[0089] The first pixel SP1 may include a first switching element. The first switching element is connected to a corresponding one of a plurality of horizontal gate lines HGL and is disposed adjacent to a line contact portion MDC. The first pixel SP1 may be disposed in a pixel region where an n-th vertical gate line VGLn intersects an n-th horizontal gate line HGLn (hereinafter, n is a natural number greater than or equal to 2). For example, when the first pixel SP1 receives a gate-on voltage from the n-th horizontal gate line HGLn, the n-th vertical gate line VGLn adjacent to the first pixel SP1 may supply the gate-on voltage to the n-th horizontal gate line HGLn. In addition, the first pixel SP1 may be disposed in a pixel region where an (n + 1)-th vertical gate line VGLn+1 intersects an (n + 1)-th horizontal gate line HGLn+1. When the first pixel SP1 receives a gate-on voltage from the (n + 1)-th horizontal gate line HGLn+1, the (n + 1)-th vertical gate line VGLn+1 adjacent to the first pixel SP1 may supply the gate-on voltage to the (n + 1)-th horizontal gate line HGLn+1. In this case, a first capacitor of the first pixel SP1 may be formed between a gate electrode and a source electrode of the first switching element, and a second capacitor of the first pixel SP1 may be formed between a first pixel electrode and a vertical gate line VGL that supplies the gate-on voltage.

[0090] The second pixel SP2 may include a second switching element. The second switching element is connected to the horizontal gate line HGL to which the first pixel SP1 is connected and is adjacent to a non-contact portion NMC. The second pixel SP2 may be disposed in a pixel region where a vertical gate line VGL and a horizontal gate line HGL that are insulated from each other intersect. The second pixel SP2 may be disposed in a pixel region where the n-th horizontal gate line HGLn intersects an (n - 1)-th vertical gate line VGLn-1. For example, when the second pixel SP2 receives a gate-on voltage from the n-th horizontal gate line HGLn, the (n - 1)-th vertical gate line VGLn-1 adjacent to the second pixel SP2 may have a gate-off voltage. In addition, the second pixel SP2 may be disposed in a pixel region where the (n + 1)-th horizontal gate line HGLn+1 intersects the n-th vertical gate line VGLn. When the second pixel SP2 receives a gate-on voltage from the (n + 1)-th horizontal gate line HGLn+1, the n-th vertical gate line VGLn adjacent to the second pixel SP2 may have a gate-off voltage. In this case, a first capacitor of the second pixel SP2 may be formed between a gate electrode and a source electrode of the second switching element, and a second capacitor of the second pixel SP2 may be formed between a second pixel electrode and a vertical gate line VGL that has a gate-off voltage.

[0091] For example, the second capacitance between the first pixel electrode of the first pixel SP1 and the vertical gate line VGL that supplies the gate-on voltage may be different from the second capacitance between the second pixel electrode of the second pixel SP2 and the vertical gate line VGL having the gate-off voltage. Accordingly, the display device may adjust the first capacitance between the gate electrode and the source electrode of the first switching element of the first pixel SP1 and the first capacitance between the gate electrode and the source electrode of the second switching element of the second pixel SP2, thereby compensating for the difference between the second capacitance of the first pixel SP1 and the second capacitance of the second pixel SP2. The display device may compensate for the difference between the second capacitance of the first pixel SP1 and the second capacitance of the second pixel SP2, thereby minimizing the difference in the kick-back voltage between the plurality of pixels SP and preventing blotches caused by the brightness variation of the plurality of pixels SP.

[0092] The third pixel SP3 may be disposed between the first pixel SP1 and the second pixel SP2, or may be disposed among the second pixels SP2. For example, the third pixel SP3 may be disposed between the first pixel SP1 and the second pixel SP2, the first pixel SP1 is disposed in the pixel region where the n-th vertical gate line VGLn and the n-th horizontal gate line HGLn intersect, and the second pixel SP2 is disposed in the pixel region where the (n-1)-th vertical gate line VGLn-1 and the n-th horizontal gate line HGLn intersect. That is, the third pixel SP3 disposed in the k-th row ROWk and the (j+1)-th column COLj+1 may be disposed between the first pixel SP1 and the second pixel SP2, the first pixel SP1 is disposed in the k-th row ROWk and the (j+2)-th column COLj+2, and the second pixel SP2 is disposed in the k-th row ROWk and the j-th column COLj.

[0093] In addition, the third pixel SP3 can be disposed between a second pixel SP2 (the second pixel SP2 is disposed in a pixel region where the n-th vertical gate line VGLn intersects with the (n + 1)-th horizontal gate line HGLn+1) and a second pixel SP2 (the second pixel SP2 is disposed in a pixel region where the (n - 1)-th vertical gate line VGLn-1 intersects with the (n + 1)-th horizontal gate line HGLn+1). That is, the third pixel SP3 disposed in the (k + 2)-th row ROWk+2 and the (j + 1)-th column COLj+1 can be disposed between a second pixel SP2 (the second pixel SP2 is disposed in the (k + 2)-th row ROWk+2 and the (j + 2)-th column COLj+2) and a second pixel SP2 (the second pixel SP2 is disposed in the (k + 2)-th row ROWk+2 and the j-th column COLj). Therefore, for both cases, compared with a plurality of vertical gate lines VGL, the third pixel SP3 can be closer to the first pixel SP1 (in the k-th row ROWk) or the second pixel SP2 (in the (k + 2)-th row ROWk+2). Since the third pixel SP3 is not directly adjacent to the vertical gate line VGL, the third pixel SP3 can be less affected by the second capacitor than the first pixel SP1 or the second pixel SP2.

[0094] For example, the first pixel SP1 can have a second capacitor between the first pixel electrode and the vertical gate line VGL that supplies the gate-on voltage, the second pixel SP2 can have a second capacitor between the second pixel electrode and the vertical gate line VGL that has the gate-off voltage, and the third pixel SP3 can be less affected by the second capacitor than the first pixel SP1 or the second pixel SP2. In this case, the first to third pixels SP1, SP2, and SP3 can have different kickback voltages from each other. Therefore, the display device can adjust the first capacitance between the gate electrode and the source electrode of each of the first switching element of the first pixel SP1, the second switching element of the second pixel SP2, and the third switching element of the third pixel SP3, so as to minimize the difference in the kickback voltages of the first to third pixels SP1, SP2, and SP3. The display device can compensate for the difference in the kickback voltages of the first to third pixels SP1, SP2, and SP3, thereby preventing blotches caused by the brightness change of the plurality of pixels SP.

[0095] Figure 4 is a circuit diagram showing a pixel circuit of a first pixel in a display device according to an embodiment.

[0096] Refer to Figure 4, the pixel circuit of the first pixel SP1 may include a first switching element ST1 and a first pixel electrode. The first pixel SP1 may further include a liquid crystal capacitor Clc formed between the first pixel electrode and the common electrode, a storage capacitor Cst formed between the source electrode of the first switching element ST1 and the storage electrode, a first capacitor Cgs1 formed between the source electrode and the gate electrode of the first switching element ST1, and a second capacitor Cgs2 formed between the first pixel electrode and the nth vertical gate line VGLn. Hereinafter, the first capacitor Cgs1 may have a first capacitance, and the second capacitor Cgs2 may have a second capacitance.

[0097] The first switching element ST1 may be connected to the nth horizontal gate line HGLn and the data line DL. For example, the first switching element ST1 may include a gate electrode connected to the nth horizontal gate line HGLn, a drain electrode connected to the data line DL, and a source electrode connected to the first pixel electrode. Here, each of the drain electrode and the source electrode may be referred to as the first electrode or the second electrode of the switching element.

[0098] The first switching element ST1 may be turned on based on the gate signal to supply the data voltage to the first pixel electrode.

[0099] One end of the liquid crystal capacitor Clc may be formed by the first pixel electrode, and the other end of the liquid crystal capacitor Clc may be formed by the common electrode on the second substrate. The first pixel electrode may receive the data voltage, and the common electrode may receive the common voltage VCOM. The liquid crystal capacitor Clc may be charged with the voltage between the first pixel electrode and the common electrode. The liquid crystal layer may be disposed between the first pixel electrode and the common electrode, and the alignment of the liquid crystal molecules in the liquid crystal layer may be changed according to the voltage difference between the first pixel electrode and the common electrode, thereby changing the transmittance of the light passing through the liquid crystal layer.

[0100] One end of the storage capacitor Cst may be formed by the source electrode of the first switching element ST1, and the other end of the storage capacitor Cst may be formed by the storage electrode. When the first switching element ST1 is turned on, the source electrode of the first switching element ST1 may receive the data voltage, and the storage electrode may receive the storage voltage VST. For example, the storage electrode may be grounded, but the present disclosure is not limited thereto. The storage capacitor Cst may be charged with the voltage between the source electrode of the first switching element ST1 and the storage electrode.

[0101] For example, when the n-th horizontal gate line HGLn supplies a gate-on voltage, the first switching element ST1 can be turned on, and the data line DL can supply a data voltage to the first pixel electrode. The storage capacitor Cst can charge the data voltage within one frame period and supply the charged data voltage to the liquid crystal capacitor Clc. Therefore, the liquid crystal capacitor Clc can maintain a constant potential difference through the storage capacitor Cst, and the liquid crystal layer can maintain a constant alignment of liquid crystal molecules to transmit light.

[0102] One end of the first capacitor Cgs1 can be formed by the gate electrode of the first switching element ST1, and the other end of the first capacitor Cgs1 can be formed by the source electrode of the first switching element ST1. For example, one end of the first capacitor Cgs1 can correspond to a part of the n-th horizontal gate line HGLn, and the other end of the first capacitor Cgs1 can be the source electrode of the first switching element ST1 that overlaps with the n-th horizontal gate line HGLn. Therefore, the first capacitance can be formed between the gate electrode and the source electrode of the first switching element ST1.

[0103] One end of the second capacitor Cgs2 can be formed by the first pixel electrode, and the other end of the second capacitor Cgs2 can be formed by the n-th vertical gate line VGLn. For example, when the first pixel SP1 is disposed in the pixel region where the n-th vertical gate line VGLn intersects with the n-th horizontal gate line HGLn, one end of the second capacitor Cgs2 can be the first pixel electrode that receives the data voltage, and the other end of the second capacitor Cgs2 can be the n-th vertical gate line VGLn that supplies the gate-on voltage. Therefore, the second capacitance can be formed between the first pixel electrode and the n-th vertical gate line VGLn.

[0104] Figure 5 is a circuit diagram showing a pixel circuit of a second pixel in a display device according to an embodiment.

[0105] Referring to Figure 5 , the pixel circuit of the second pixel SP2 can include a second switching element ST2 and a second pixel electrode. The second pixel SP2 can also include a liquid crystal capacitor Clc formed between the second pixel electrode and the common electrode, a storage capacitor Cst formed between the source electrode of the second switching element ST2 and the storage electrode, a first capacitor Cgs1 formed between the source electrode and the gate electrode of the second switching element ST2, and a second capacitor Cgs2 formed between the second pixel electrode and the (n - 1)-th vertical gate line VGLn - 1.

[0106] The second switching element ST2 can be connected to the n-th horizontal gate line HGLn and the data line DL. For example, the second switching element ST2 can include a gate electrode connected to the n-th horizontal gate line HGLn, a drain electrode connected to the data line DL, and a source electrode connected to the second pixel electrode. The second switching element ST2 can be turned on based on a gate signal to supply a data voltage to the second pixel electrode.

[0107] One end of the liquid crystal capacitor Clc can be formed by the second pixel electrode, and the other end of the liquid crystal capacitor Clc can be formed by a common electrode on the second substrate. The second pixel electrode can receive a data voltage, and the common electrode can receive a common voltage VCOM. The liquid crystal capacitor Clc can be charged with the voltage between the second pixel electrode and the common electrode. The liquid crystal layer can be disposed between the second pixel electrode and the common electrode, and the alignment of the liquid crystal molecules in the liquid crystal layer can be changed according to the voltage difference between the second pixel electrode and the common electrode, thereby changing the transmittance of light passing through the liquid crystal layer.

[0108] One end of the storage capacitor Cst can be formed by the source electrode of the second switching element ST2, and the other end of the storage capacitor Cst can be formed by a storage electrode. When the second switching element ST2 is turned on, the source electrode of the second switching element ST2 can receive a data voltage, and the storage electrode can receive a storage voltage VST. For example, the storage electrode can be grounded, but the present disclosure is not limited thereto. The storage capacitor Cst can be charged with the voltage between the source electrode of the second switching element ST2 and the storage electrode.

[0109] For example, when the n-th horizontal gate line HGLn supplies a gate-on voltage, the second switching element ST2 can be turned on, and the data line DL can supply a data voltage to the second pixel electrode. The storage capacitor Cst can be charged with the data voltage within one frame period and supply the charged data voltage to the liquid crystal capacitor Clc. Therefore, the liquid crystal capacitor Clc can maintain a constant potential difference through the storage capacitor Cst, and the liquid crystal layer can maintain a constant alignment of the liquid crystal molecules to transmit light.

[0110] One end of the first capacitor Cgs1 can be formed by the gate electrode of the second switching element ST2, and the other end of the first capacitor Cgs1 can be formed by the source electrode of the second switching element ST2. For example, one end of the first capacitor Cgs1 can correspond to a part of the n-th horizontal gate line HGLn, and the other end of the first capacitor Cgs1 can be the source electrode of the second switching element ST2 that overlaps with the n-th horizontal gate line HGLn. Therefore, the first capacitance can be formed between the gate electrode and the source electrode of the second switching element ST2.

[0111] One end of the second capacitor Cgs2 may be formed by the second pixel electrode, and the other end of the second capacitor Cgs2 may be formed by the (n - 1)-th vertical gate line VGLn-1. For example, when the second pixel SP2 is disposed in a pixel region where the (n - 1)-th vertical gate line VGLn-1 intersects with the n-th horizontal gate line HGLn, one end of the second capacitor Cgs2 may be the second pixel electrode that receives a data voltage, and the other end of the second capacitor Cgs2 may be the (n - 1)-th vertical gate line VGLn-1 that supplies a gate-on voltage. Accordingly, the second capacitor may be formed between the second pixel electrode and the (n - 1)-th vertical gate line VGLn-1.

[0112] Figure 6 FIG. is a circuit diagram showing a pixel circuit of a third pixel in a display device according to an embodiment.

[0113] Referring to Figure 6 , the pixel circuit of the third pixel SP3 may include a third switching element ST3 and a third pixel electrode. The third pixel SP3 may further include a liquid crystal capacitor Clc formed between the third pixel electrode and a common electrode, a storage capacitor Cst formed between a source electrode of the third switching element ST3 and a storage electrode, and a first capacitor Cgs1 formed between the source electrode of the third switching element ST3 and a gate electrode.

[0114] The third switching element ST3 may be connected to the n-th horizontal gate line HGLn and a data line DL. For example, the third switching element ST3 may include a gate electrode connected to the n-th horizontal gate line HGLn, a drain electrode connected to the data line DL, and a source electrode connected to the third pixel electrode. The third switching element ST3 may be turned on based on a gate signal to supply a data voltage to the third pixel electrode.

[0115] One end of the liquid crystal capacitor Clc may be formed by the third pixel electrode, and the other end of the liquid crystal capacitor Clc may be formed by the common electrode on the second substrate. The third pixel electrode may receive a data voltage, and the common electrode may receive a common voltage VCOM. The liquid crystal capacitor Clc may be charged with a voltage between the third pixel electrode and the common electrode. A liquid crystal layer may be disposed between the third pixel electrode and the common electrode, and the alignment of liquid crystal molecules in the liquid crystal layer may be changed according to a voltage difference between the third pixel electrode and the common electrode, thereby changing the transmittance of light passing through the liquid crystal layer.

[0116] One end of the storage capacitor Cst may be formed by the source electrode of the third switching element ST3, and the other end of the storage capacitor Cst may be formed by a storage electrode. When the third switching element ST3 is turned on, the source electrode of the third switching element ST3 may receive a data voltage, and the storage electrode may receive a storage voltage VST. For example, the storage electrode may be grounded, but the present disclosure is not limited thereto. The storage capacitor Cst may be charged with the voltage between the source electrode of the third switching element ST3 and the storage electrode.

[0117] For example, when the n-th horizontal gate line HGLn supplies a gate-on voltage, the third switching element ST3 may be turned on, and the data line DL may supply a data voltage to the third pixel electrode. The storage capacitor Cst may be charged with the data voltage within one frame period and supply the charged data voltage to the liquid crystal capacitor Clc. Accordingly, the liquid crystal capacitor Clc may maintain a constant potential difference through the storage capacitor Cst, and the liquid crystal layer may maintain a constant alignment of liquid crystal molecules to transmit light.

[0118] One end of the first capacitor Cgs1 may be formed by the gate electrode of the third switching element ST3, and the other end of the first capacitor Cgs1 may be formed by the source electrode of the third switching element ST3. For example, one end of the first capacitor Cgs1 may correspond to a part of the n-th horizontal gate line HGLn, and the other end of the first capacitor Cgs1 may be the source electrode of the third switching element ST3 that overlaps with the n-th horizontal gate line HGLn. Accordingly, a first capacitance may be formed between the gate electrode and the source electrode of the third switching element ST3.

[0119] Figure 7 is a plan view showing a first pixel, a second pixel, and a third pixel in a display device according to an embodiment, Figure 8 is along Figure 7 a cross-sectional view taken along line I-I'.

[0120] Referring to Figure 7 and Figure 8 , the display panel 100 includes a first substrate 110, an n-th horizontal gate line HGLn, a storage electrode STE, an auxiliary electrode AE, a gate insulating film GI, a plurality of data lines DL, an (n - 1)-th vertical gate line VGLn-1, an n-th vertical gate line VGLn, a passivation layer PAS, and a first pixel SP1, a second pixel SP2, and a third pixel SP3.

[0121] The n-th horizontal gate line HGLn may be disposed on the first substrate 110. Each of the plurality of horizontal gate lines HGL may be connected to a corresponding vertical gate line VGL. For example, the n-th horizontal gate line HGLn may be connected to the n-th vertical gate line VGLn through a line contact portion MDC. The line contact portion MDC may correspond to a portion where the gate insulating film GI is omitted in the overlapping region of the vertical gate line VGL and the horizontal gate line HGL. The n-th horizontal gate line HGLn may be insulated from other vertical gate lines VGL among the plurality of vertical gate lines VGL except the n-th vertical gate line VGLn in a non-contact portion NMC. For example, the n-th horizontal gate line HGLn may be insulated from the (n - 1)-th vertical gate line VGLn - 1 in the non-contact portion NMC.

[0122] The storage electrode STE may be disposed on the first substrate 110. The storage electrode STE may receive a storage voltage VST. For example, the storage electrode STE may be grounded, but the present disclosure is not necessarily limited thereto. The storage electrode STE may form a storage capacitor Cst of the first pixel SP1 together with the source electrode SE1 of the first switching element ST1. The storage electrode STE may form a storage capacitor Cst of the second pixel SP2 together with the source electrode SE2 of the second switching element ST2. The storage electrode STE may form a storage capacitor Cst of the third pixel SP3 together with the source electrode SE3 of the third switching element ST3.

[0123] The auxiliary electrode AE may be disposed on the first substrate 110 to overlap with the vertical gate line VGL. At least three surfaces of the auxiliary electrode AE may face the storage electrode STE in a plane. Each of the plurality of vertical gate lines VGL may be connected to a corresponding horizontal gate line HGL, and the entire length of the gate line GL may be increased. Therefore, the auxiliary electrode AE may contact each of the plurality of vertical gate lines VGL, thereby reducing the resistance of the plurality of vertical gate lines VGL.

[0124] The gate insulating film GI may cover the n-th horizontal gate line HGLn, the storage electrode STE, and the auxiliary electrode AE. For example, the gate insulating film GI may include an inorganic insulating material such as a silicon compound or a metal oxide. The gate insulating film GI may be a single-layer film or a multi-layer film formed of different materials.

[0125] A plurality of data lines DL may be disposed on the gate insulating film GI. The plurality of data lines DL may extend in a second direction (Y-axis direction) and may be separated from each other in a first direction (X-axis direction). For example, a plurality of pixels SP arranged in a column may receive data voltages through two data lines DL. Each of the plurality of data lines DL may supply a data voltage to the drain electrode DE1 of the first switching element ST1, the drain electrode DE2 of the second switching element ST2, or the drain electrode DE3 of the third switching element ST3.

[0126] Each of the (n - 1)-th vertical gate line VGLn-1 and the n-th vertical gate line VGLn may be disposed on the gate insulating film GI. The (n - 1)-th vertical gate line VGLn-1 and the n-th vertical gate line VGLn may extend in the second direction (Y-axis direction) and may be spaced apart from each other in the first direction (X-axis direction). Each of the (n - 1)-th vertical gate line VGLn-1 and the n-th vertical gate line VGLn may intersect the n-th horizontal gate line HGLn. For example, the (n - 1)-th vertical gate line VGLn-1 may be insulated from the n-th horizontal gate line HGLn in the non-contact portion NMC. The n-th vertical gate line VGLn may be connected to the n-th horizontal gate line HGLn through the line contact portion MDC.

[0127] The passivation layer PAS may cover the plurality of data lines DL, the (n - 1)-th vertical gate line VGLn-1, the n-th vertical gate line VGLn, and the first switching element ST1, the second switching element ST2, and the third switching element ST3. For example, the passivation layer PAS may be made of an organic material and may protect the plurality of data lines DL, the (n - 1)-th vertical gate line VGLn-1, the n-th vertical gate line VGLn, and the first switching element ST1, the second switching element ST2, and the third switching element ST3.

[0128] The first switching element ST1 of the first pixel SP1 may include a gate electrode GE1, an active region ACT1, a drain electrode DE1, and a source electrode SE1. The gate electrode GE1 of the first pixel SP1 is a part of the n-th horizontal gate line HGLn and may correspond to the region overlapping with the active region ACT1. The active region ACT1 of the first switching element ST1 may be disposed on the gate insulating film GI. The drain electrode DE1 of the first switching element ST1 may cover one end of the active region ACT1, and the source electrode SE1 of the first switching element ST1 may cover the other end of the active region ACT1. The drain electrode DE1 of the first switching element ST1 may be connected to the data line DL to receive a data voltage. The source electrode SE1 of the first switching element ST1 may be connected to the first pixel electrode and may receive the data voltage when the first switching element ST1 is turned on.

[0129] The first switching element ST1 of the first pixel SP1 may be connected to the n-th horizontal gate line HGLn and may be adjacent to the line contact portion MDC to which the n-th vertical gate line VGLn and the n-th horizontal gate line HGLn are connected. Therefore, when the n-th vertical gate line VGLn adjacent to the first pixel SP1 supplies a gate conduction voltage, the first switching element ST1 may receive the gate conduction voltage from the n-th horizontal gate line HGLn.

[0130] In Figure 8In this case, the gate electrode GE1 of the first switching element ST1 may correspond to one electrode of the first capacitor Cgs1, and the source electrode SE1 of the first switching element ST1 may correspond to the other electrode of the first capacitor Cgs1. For example, one electrode of the first capacitor Cgs1 of the first pixel SP1 may correspond to a part of the n-th horizontal gate line HGLn, and the other electrode of the first capacitor Cgs1 may correspond to the source electrode SE1 of the first switching element ST1 that overlaps with the n-th horizontal gate line HGLn. Therefore, the first capacitance of the first pixel SP1 may be formed between the gate electrode GE1 and the source electrode SE1 of the first switching element ST1.

[0131] The protection member PRT may be formed of the same material as the active region ACT1 of the first switching element ST1 and is provided on the same layer as the active region ACT1 of the first switching element ST1. The protection member PRT may be formed in the overlapping region of the horizontal gate line HGL and the drain electrode DE1 of the first switching element ST1. The protection member PRT may prevent one end of the horizontal gate line HGL from contacting the drain electrode DE1 of the first switching element ST1.

[0132] The second switching element ST2 of the second pixel SP2 may include a gate electrode GE2, a drain electrode DE2, and a source electrode SE2. The gate electrode GE2 of the second switching element ST2 is a part of the n-th horizontal gate line HGLn and may correspond to the region overlapping with the active region. The drain electrode DE2 of the second switching element ST2 may be connected to the data line DL to receive a data voltage. The source electrode SE2 of the second switching element ST2 may be connected to the second pixel electrode and may receive the data voltage when the second switching element ST2 is turned on.

[0133] The second switching element ST2 of the second pixel SP2 may be connected to the n-th horizontal gate line HGLn and may be adjacent to the non-contact portion NMC where the (n - 1)-th vertical gate line VGLn-1 and the n-th horizontal gate line HGLn intersect. Therefore, when the (n - 1)-th vertical gate line VGLn-1 adjacent to the second pixel SP2 has a gate cut-off voltage, the second switching element ST2 may receive a gate conduction voltage from the n-th horizontal gate line HGLn.

[0134] The third switching element ST3 of the third pixel SP3 may include a gate electrode GE3, a drain electrode DE3, and a source electrode SE3. The gate electrode GE3 of the third switching element ST3 is a part of the n-th horizontal gate line HGLn and may correspond to the region overlapping with the active region. The drain electrode DE3 of the third switching element ST3 may be connected to the data line DL to receive a data voltage. The source electrode SE3 of the third switching element ST3 may be connected to the third pixel electrode and may receive the data voltage when the third switching element ST3 is turned on.

[0135] The third pixel SP3 may be disposed between the first pixel SP1 and the second pixel SP2, or may be disposed between adjacent second pixels SP2. For example, the third pixel SP3 may be disposed between the first pixel SP1 and the second pixel SP2, the first pixel SP1 is disposed in a pixel region where the nth vertical gate line VGLn intersects the nth horizontal gate line HGLn, and the second pixel SP2 is disposed in a pixel region where the (n - 1)th vertical gate line VGLn - 1 intersects the nth horizontal gate line HGLn. Therefore, compared with the (n - 1)th vertical gate line VGLn - 1 or the nth vertical gate line VGLn, the third pixel SP3 may be closer to the first pixel SP1 or the second pixel SP2. Since the third pixel SP3 is not directly adjacent to the vertical gate line VGL, the third pixel SP3 may be less affected by the second capacitor than the first pixel SP1 or the second pixel SP2.

[0136] Figure 9 is a plan view showing a first pixel, a second pixel, and a third pixel, and a first pixel electrode, a second pixel electrode, and a third pixel electrode in a display device according to an embodiment, Figure 10 is a cross-sectional view taken along line II-II' of Figure 9 . Figure 9 and Figure 10 The display device shown in also includes a first pixel electrode, a second pixel electrode, and a third pixel electrode, and components identical to the above components will be briefly described or omitted.

[0137] Referring to Figure 9 and Figure 10 , the display panel 100 includes a first substrate 110, an nth horizontal gate line HGLn, a storage electrode STE, an auxiliary electrode AE, a gate insulating film GI, a plurality of data lines DL, an (n - 1)th vertical gate line VGLn - 1, an nth vertical gate line VGLn, a passivation layer PAS, a first pixel SP1, a second pixel SP2, and a third pixel SP3, a color filter CF, a planarization layer OC, a liquid crystal layer LC, a common electrode CE, and a second substrate 120.

[0138] The nth horizontal gate line HGLn may be disposed on the first substrate 110. Each of the plurality of horizontal gate lines HGL may be connected to a corresponding vertical gate line VGL. The nth horizontal gate line HGLn may supply a gate signal to each of a gate electrode GE1, a gate electrode GE2, and a gate electrode GE3 of a first switching element ST1, a second switching element ST2, and a third switching element ST3.

[0139] The storage electrode STE may be disposed on the first substrate 110. The storage electrode STE may receive a storage voltage VST.

[0140] The auxiliary electrode AE may be disposed on the first substrate 110 to overlap with the vertical gate lines VGL. The auxiliary electrode AE may be in contact with each of the plurality of vertical gate lines VGL, thereby reducing the resistance of the plurality of vertical gate lines VGL.

[0141] The gate insulating film GI may cover the nth horizontal gate line HGLn, the storage electrode STE, and the auxiliary electrode AE.

[0142] A plurality of data lines DL may be disposed on the gate insulating film GI. Each of the plurality of data lines DL may supply a data voltage to the drain electrode DE1 of the first switching element ST1, the drain electrode DE2 of the second switching element ST2, or the drain electrode DE3 of the third switching element ST3.

[0143] Each of the (n - 1)th vertical gate line VGLn-1 and the nth vertical gate line VGLn may be disposed on the gate insulating film GI. The (n - 1)th vertical gate line VGLn-1 and the nth vertical gate line VGLn may extend in the second direction (Y-axis direction) and may be separated from each other in the first direction (X-axis direction). Each of the (n - 1)th vertical gate line VGLn-1 and the nth vertical gate line VGLn may intersect with the nth horizontal gate line HGLn. For example, the (n - 1)th vertical gate line VGLn-1 may be insulated from the nth horizontal gate line HGLn in the non-contact portion NMC. The nth vertical gate line VGLn may be connected to the nth horizontal gate line HGLn through the line contact portion MDC. The line contact portion MDC may correspond to a portion where the gate insulating film GI is omitted in the overlapping region of the vertical gate line VGL and the horizontal gate line HGL.

[0144] The passivation layer PAS may cover the plurality of data lines DL, the (n - 1)th vertical gate line VGLn-1, the nth vertical gate line VGLn, and the first switching element ST1, the second switching element ST2, and the third switching element ST3.

[0145] The first pixel SP1 may include the first switching element ST1 and the first pixel electrode PE1 connected to the source electrode SE1 of the first switching element ST1. For example, when the first pixel SP1 receives the gate-on voltage from the nth horizontal gate line HGLn, the nth vertical gate line VGLn adjacent to the first pixel SP1 may supply the gate-on voltage to the nth horizontal gate line HGLn. In this case, the first capacitor Cgs1 of the first switching element ST1 may be formed between the gate electrode GE1 and the source electrode SE1, and the second capacitor Cgs2 of the first switching element ST1 may be formed between the first pixel electrode PE1 of the first pixel SP1 and the nth vertical gate line VGLn that supplies the gate-on voltage.

[0146] The second pixel SP2 may include a second switching element ST2 and a second pixel electrode PE2 connected to a source electrode SE2 of the second switching element ST2. For example, when the second pixel SP2 receives a gate-on voltage from the n-th horizontal gate line HGLn, the (n-1)-th vertical gate line VGLn-1 adjacent to the second pixel SP2 may have a gate-off voltage. In this case, a first capacitor Cgs1 may be formed between a gate electrode GE2 and the source electrode SE2 of the second switching element ST2, and a second capacitor Cgs2 may be formed between the second pixel electrode PE2 of the second pixel SP2 and the (n-1)-th vertical gate line VGLn-1 having the gate-off voltage.

[0147] A second capacitance between the first pixel electrode PE1 of the first pixel SP1 and the n-th vertical gate line VGLn that supplies a gate-on voltage may be different from a second capacitance between the second pixel electrode PE2 of the second pixel SP2 and the (n-1)-th vertical gate line VGLn-1 having the gate-off voltage. For example, the magnitude of the second capacitance of the first pixel SP1 may be larger than the magnitude of the second capacitance of the second pixel SP2.

[0148] The third pixel SP3 may include a third switching element ST3 and a third pixel electrode PE3 connected to a source electrode SE3 of the third switching element ST3. The third pixel SP3 may be disposed between the first pixel SP1 and the second pixel SP2. The first pixel SP1 is disposed in a pixel region where the n-th vertical gate line VGLn intersects the n-th horizontal gate line HGLn, and the second pixel SP2 is disposed in a pixel region where the (n-1)-th vertical gate line VGLn-1 intersects the n-th horizontal gate line HGLn. Since the third pixel SP3 is not directly adjacent to the vertical gate line VGL, the third pixel SP3 may be less affected by the second capacitance than the first pixel SP1 or the second pixel SP2.

[0149] For example, the first pixel SP1 has a second capacitance between the first pixel electrode PE1 and the n-th vertical gate line VGLn that supplies a gate-on voltage, the second pixel SP2 has a second capacitance between the second pixel electrode PE2 and the (n-1)-th vertical gate line VGLn-1 having the gate-off voltage, and the third pixel SP3 may be less affected by the second capacitance than the first pixel SP1 or the second pixel SP2.

[0150] The color filter CF may be disposed on the passivation layer PAS to overlap with each of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3. The color filter CF may provide a specific color to the light passing through the display panel 100. The color filter CF may include a first color filter, a second color filter, and a third color filter that transmit light of different colors. The first color filter may overlap with the first pixel electrode PE1, the second color filter may overlap with the second pixel electrode PE2, and the third color filter may overlap with the third pixel electrode PE3. For example, each of the first color filter, the second color filter, and the third color filter may be one of a red color filter, a green color filter, and a blue color filter.

[0151] The planarization layer OC may cover the color filter CF and planarize the upper portion of the first substrate 110.

[0152] Each of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may be disposed on the planarization layer OC. The first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may be connected to the source electrode SE1 of the first switching element ST1, the source electrode SE2 of the second switching element ST2, and the source electrode SE3 of the third switching element ST3, respectively. Each of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may face the common electrode CE on the second substrate 120.

[0153] The liquid crystal layer LC may be formed between the first substrate 110 and the second substrate 120. The liquid crystal layer LC may be disposed between the first pixel electrode PE1 and the common electrode CE. That is, the liquid crystal capacitor Clc may be formed between the first pixel electrode PE1 and the common electrode CE to maintain the voltage between the first pixel electrode PE1 and the common electrode CE. Accordingly, the alignment of the liquid crystal molecules in the liquid crystal layer LC may be changed according to the voltage between the first pixel electrode PE1 and the common electrode CE, thereby changing the transmittance of the light passing through the liquid crystal layer LC.

[0154] The common electrode CE may be disposed on the second substrate 120. When the second substrate 120 is attached to the first substrate 110, the common electrode CE on the second substrate 120 may face the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 on the first substrate 110.

[0155] Figure 11 is a plan view showing the first switching element, the second switching element, and the third switching element in the display device according to an embodiment, Figure 12 briefly shows Figure 11 the gate electrodes and source electrodes of each of the first switching element, the second switching element, and the third switching element shown in. Hereinafter, components identical to the above components will be briefly described or omitted.

[0156] Referring to Figure 11 and Figure 12

[0157]

[0156]

[0158] Figure 11

[0159] The gate electrode GE2 of the second switching element ST2 may include a first extension portion EXP1 protruding toward the source electrode SE2. The size of the gate electrode GE2 of the second switching element ST2 may be larger than the size of the gate electrode GE1 of the first switching element ST1. That is, the length of the gate electrode GE2 of the second switching element ST2 (along the Y-axis direction) may be larger than the length of the gate electrode GE1 of the first switching element ST1 (along the Y-axis direction). The magnitude of the first capacitance between the gate electrode GE2 of the second switching element ST2 and the source electrode SE2 may be larger than the magnitude of the first capacitance between the gate electrode GE1 of the first switching element ST1 and the source electrode SE1. Accordingly, the display device may adjust the difference between the first capacitance of the first pixel SP1 and the first capacitance of the second pixel SP2, thereby compensating for the difference between the first capacitance of the first pixel SP1 and the first capacitance of the second pixel SP2. The display device may compensate for the difference between the first capacitance of the first pixel SP1 and the first capacitance of the second pixel SP2, thereby minimizing the difference in the recoil voltage between the plurality of pixels SP and preventing blotches caused by the brightness change of the plurality of pixels SP.

[0160] The third pixel SP3 may be disposed between the first pixel SP1 and the second pixel SP2. The first pixel SP1 is disposed in a pixel region where the n-th vertical gate line VGLn and the n-th horizontal gate line HGLn intersect, and the second pixel SP2 is disposed in a pixel region where the (n - 1)-th vertical gate line VGLn-1 and the n-th horizontal gate line HGLn intersect. Since the third pixel SP3 is not directly adjacent to the vertical gate line VGL, the third pixel SP3 may be less affected by the second capacitance than the first pixel SP1 or the second pixel SP2.

[0161] For example, the first pixel SP1 has a second capacitance between the first pixel electrode PE1 and the n-th vertical gate line VGLn that supplies the gate conduction voltage, the second pixel SP2 has a second capacitance between the second pixel electrode PE2 and the (n - 1)-th vertical gate line VGLn-1 that has the gate cut-off voltage, and the third pixel SP3 may be less affected by the second capacitance than the first pixel SP1 or the second pixel SP2. In this case, in addition to the value of the first capacitance, the first pixel SP1, the second pixel SP2, and the third pixel SP3 may have different recoil voltages.

[0162] The gate electrode GE3 of the third switching element ST3 may include a second extension portion EXP2 protruding toward the source electrode SE3. The size of the second extension portion EXP2 may be smaller than the size of the first extension portion EXP1. That is, the length of the second extension portion EXP2 (along the Y-axis direction) may be smaller than the length of the first extension portion EXP1 (along the Y-axis direction). Since the size of the gate electrode GE3 of the third switching element ST3 (the length along the Y-axis direction) may be larger than the size of the gate electrode GE1 of the first switching element ST1 (the length along the Y-axis direction), the magnitude of the first capacitance of the third switching element ST3 may be larger than the magnitude of the first capacitance of the first switching element ST1. Since the size of the gate electrode GE2 of the second switching element ST2 (the length along the Y-axis direction) may be larger than the size of the gate electrode GE3 of the third switching element ST3 (the length along the Y-axis direction), the magnitude of the first capacitance of the second switching element ST2 may be larger than the magnitude of the first capacitance of the third switching element ST3.

[0163] Therefore, the display device can adjust the difference between the first capacitances of the first pixel SP1, the second pixel SP2, and the third pixel SP3, so as to minimize the difference in the kickback voltage between the first pixel SP1, the second pixel SP2, and the third pixel SP3. The display device can compensate for the difference in the kickback voltage between the first pixel SP1, the second pixel SP2, and the third pixel SP3, thereby preventing blotches caused by the brightness change of the plurality of pixels SP.

[0164] Figure 13 is a plan view showing the first to third switching elements in a display device according to another embodiment, Figure 14 briefly shows Figure 13 the first to third switching elements shown in Figure 13 and Figure 14 The display device of Figure 11 and Figure 12 is different from the display device of

[0165] in the structure of the first, second, and third switching elements. Therefore, the components identical to those described above will be briefly described or omitted. Figure 13 and Figure 14, the first switching element ST1 of the first pixel SP1 may include a gate electrode GE1, an active region ACT1, a drain electrode DE1, and a source electrode SE1. The gate electrode GE1 of the first pixel SP1 is a part of the n-th horizontal gate line HGLn and may correspond to the region overlapping with the active region ACT1. The active region ACT1 of the first switching element ST1 may be disposed on the gate insulating film GI. The drain electrode DE1 of the first switching element ST1 may cover one end of the active region ACT1, and the source electrode SE1 of the first switching element ST1 may cover the other end of the active region ACT1. The drain electrode DE1 of the first switching element ST1 may be connected to the data line DL to receive a data voltage. The source electrode SE1 of the first switching element ST1 may be connected to the first pixel electrode and may receive the data voltage when the first switching element ST1 is turned on.

[0166] The second switching element ST2 of the second pixel SP2 may include a gate electrode GE2, an active region ACT2, a drain electrode DE2, and a source electrode SE2. The third switching element ST3 of the third pixel SP3 may include a gate electrode GE3, an active region ACT3, a drain electrode DE3, and a source electrode SE3.

[0167] The protection member PRT may be formed of the same material as the active region ACT1 of the first switching element ST1 and disposed on the same layer as the active region ACT1 of the first switching element ST1. The protection member PRT may be formed in the overlapping region of the data line DL and the horizontal gate line HGL, and may be formed in the overlapping region of the data line DL and the storage electrode STE. The protection member PRT may be formed in the non-contact portion NMC, and may be formed in the overlapping region of the vertical gate line VGL and the storage electrode STE. The protection member PRT may be formed in the overlapping region of the horizontal gate line HGL and the drain electrode DE1 of the first switching element ST1. Therefore, the protection member PRT can prevent the horizontal gate line HGL or the storage electrode STE provided in the first layer from contacting the data line DL, the drain electrodes DE1, DE2, and DE3, or the vertical gate line VGL provided in the second layer on the first layer.

[0168] The first capacitance between the gate electrode GE1 and the source electrode SE1 of the first switching element ST1 of the first pixel SP1 may be different from the first capacitance between the gate electrode GE2 and the source electrode SE2 of the second switching element ST2 of the second pixel SP2. The second capacitance between the first pixel electrode PE1 of the first pixel SP1 and the n-th vertical gate line VGLn supplying the gate-on voltage may be different from the second capacitance between the second pixel electrode PE2 of the second pixel SP2 and the (n - 1)-th vertical gate line VGLn-1 having the gate-off voltage. For example, the second capacitance between the first pixel electrode PE1 of the first pixel SP1 and the n-th vertical gate line VGLn supplying the gate-on voltage may be larger than the second capacitance between the second pixel electrode PE2 of the second pixel SP2 and the (n - 1)-th vertical gate line VGLn-1 having the gate-off voltage.

[0169] The size of the active region ACT2 of the second switching element ST2 may be larger than the size of the active region ACT1 of the first switching element ST1. Accordingly, the substantial area of the source electrode SE2 of the second switching element ST2 may be larger than the source electrode SE1 of the first switching element ST1, and the source electrode SE2 serves as one electrode of the first capacitor Cgs1 of the second switching element ST2. Accordingly, the magnitude of the first capacitance between the gate electrode GE2 and the source electrode SE2 of the second switching element ST2 may be larger than the magnitude of the first capacitance between the gate electrode GE1 and the source electrode SE1 of the first switching element ST1. Accordingly, the display device may adjust the difference between the first capacitance of the first pixel SP1 and the first capacitance of the second pixel SP2 to compensate for the difference between the first capacitance of the first pixel SP1 and the first capacitance of the second pixel SP2. The display device may compensate for the difference between the first capacitance of the first pixel SP1 and the first capacitance of the second pixel SP2 to minimize the difference in the kickback voltage between the plurality of pixels SP and prevent blotches caused by the luminance change of the plurality of pixels SP.

[0170] The third pixel SP3 may be disposed between the first pixel SP1 and the second pixel SP2. The first pixel SP1 is disposed in the pixel region where the n-th vertical gate line VGLn and the n-th horizontal gate line HGLn intersect, and the second pixel SP2 is disposed in the pixel region where the (n - 1)-th vertical gate line VGLn-1 and the n-th horizontal gate line HGLn intersect. Since the third pixel SP3 is not directly adjacent to the vertical gate line VGL, the third pixel SP3 may be less affected by the second capacitance than the first pixel SP1 or the second pixel SP2.

[0171] For example, the first pixel SP1 has a second capacitance between the first pixel electrode PE1 and the n-th vertical gate line VGLn that supplies a gate-on voltage, the second pixel SP2 has a second capacitance between the second pixel electrode PE2 and the (n-1)-th vertical gate line VGLn-1 that has a gate-off voltage, and the third pixel SP3 can be less affected by the second capacitance than the first pixel SP1 or the second pixel SP2. In this case, in addition to the value of the first capacitance, the first to third pixels SP1, SP2, and SP3 can have different kickback voltages.

[0172] The size (length along the Y-axis direction) of the active region ACT3 of the third switching element ST3 can be larger than the size (length along the Y-axis direction) of the active region ACT1 of the first switching element ST1. Accordingly, the substantial area of the source electrode SE3 of the third switching element ST3 can be larger than that of the source electrode SE1 of the first switching element ST1, such that the magnitude of the first capacitance of the third switching element ST3 can be larger than the magnitude of the first capacitance of the first switching element ST1, and the source electrode SE3 serves as one electrode of the first capacitor Cgs1 of the third switching element ST3.

[0173] The size (length along the Y-axis direction) of the active region ACT2 of the second switching element ST2 can be larger than the size (length along the Y-axis direction) of the active region ACT3 of the third switching element ST3. Accordingly, the substantial area of the source electrode SE2 of the second switching element ST2 can be larger than that of the source electrode SE3 of the third switching element ST3, such that the magnitude of the first capacitance of the second switching element ST2 can be larger than the magnitude of the first capacitance of the third switching element ST3, and the source electrode SE2 serves as one electrode of the first capacitor Cgs1 of the second switching element ST2.

[0174] Accordingly, the display device can adjust the difference between the first capacitance of the first pixel SP1, the first capacitance of the second pixel SP2, and the first capacitance of the third pixel SP3, thereby minimizing the difference in the kickback voltages between the first pixel SP1, the second pixel SP2, and the third pixel SP3. The display device can compensate for the difference in the kickback voltages between the first pixel SP1, the second pixel SP2, and the third pixel SP3, thereby preventing blotches caused by the brightness variation of the plurality of pixels SP.

[0175] Figure 15 is a plan view showing first to third switching elements in a display device according to still another embodiment, Figure 16 briefly showing Figure 15 the gate electrodes and source electrodes of each of the first to third switching elements shown in

[0176] Referring to Figure 15 and Figure 16, the first capacitance between the gate electrode GE1 and the source electrode SE1 of the first switching element ST1 of the first pixel SP1 may be different from the first capacitance between the gate electrode GE2 and the source electrode SE2 of the second switching element ST2 of the second pixel SP2. The second capacitance between the first pixel electrode PE1 of the first pixel SP1 and the n-th vertical gate line VGLn supplying the gate-on voltage may be different from the second capacitance between the second pixel electrode PE2 of the second pixel SP2 and the (n - 1)-th vertical gate line VGLn-1 having the gate-off voltage. For example, the second capacitance between the first pixel electrode PE1 of the first pixel SP1 and the n-th vertical gate line VGLn supplying the gate-on voltage may be larger than the second capacitance between the second pixel electrode PE2 of the second pixel SP2 and the (n - 1)-th vertical gate line VGLn-1 having the gate-off voltage.

[0177] The width W2 of the source electrode SE2 of the second switching element ST2 may be larger than the width W1 of the source electrode SE1 of the first switching element ST1. Here, the width W2 of the source electrode SE2 of the second switching element ST2 and the width W1 of the source electrode SE1 of the first switching element ST1 may correspond to the widths in the region overlapping with the horizontal gate line HGL. Accordingly, the magnitude of the first capacitance between the gate electrode GE2 and the source electrode SE2 of the second switching element ST2 may be larger than the magnitude of the first capacitance between the gate electrode GE1 and the source electrode SE1 of the first switching element ST1. Accordingly, the display device may adjust the difference between the first capacitance of the first pixel SP1 and the first capacitance of the second pixel SP2 to compensate for the difference between the first capacitance of the first pixel SP1 and the first capacitance of the second pixel SP2. The display device may compensate for the difference between the first capacitance of the first pixel SP1 and the first capacitance of the second pixel SP2 to minimize the difference in the kickback voltage between the plurality of pixels SP and prevent blotches caused by the brightness change of the plurality of pixels SP.

[0178] The third pixel SP3 may be disposed between the first pixel SP1 and the second pixel SP2. The first pixel SP1 is disposed in the pixel region where the n-th vertical gate line VGLn and the n-th horizontal gate line HGLn intersect, and the second pixel SP2 is disposed in the pixel region where the (n - 1)-th vertical gate line VGLn-1 and the n-th horizontal gate line HGLn intersect. Since the third pixel SP3 is not directly adjacent to the vertical gate line VGL, the third pixel SP3 may be less affected by the second capacitance than the first pixel SP1 or the second pixel SP2.

[0179] For example, the first pixel SP1 has a second capacitance between the first pixel electrode PE1 and the n-th vertical gate line VGLn that supplies a gate-on voltage, the second pixel SP2 has a second capacitance between the second pixel electrode PE2 and the (n-1)-th vertical gate line VGLn-1 that has a gate-off voltage, and the third pixel SP3 can be less affected by the second capacitance than the first pixel SP1 or the second pixel SP2. In this case, in addition to the value of the first capacitance, the first pixel SP1, the second pixel SP2, and the third pixel SP3 can have different kickback voltages from each other.

[0180] The width W3 of the source electrode SE3 of the third switching element ST3 can be larger than the width W1 of the source electrode SE1 of the first switching element ST1. Here, the width W3 of the source electrode SE3 of the third switching element ST3 and the width W1 of the source electrode SE1 of the first switching element ST1 can correspond to the widths in the region overlapping with the horizontal gate line HGL. Therefore, the magnitude of the first capacitance of the third switching element ST3 can be larger than the magnitude of the first capacitance of the first switching element ST1.

[0181] The width W2 of the source electrode SE2 of the second switching element ST2 can be larger than the width W3 of the source electrode SE3 of the third switching element ST3. Here, the width W2 of the source electrode SE2 of the second switching element ST2 and the width W3 of the source electrode SE3 of the third switching element ST3 can correspond to the widths in the region overlapping with the horizontal gate line HGL. Therefore, the magnitude of the first capacitance of the second switching element ST2 can be larger than the magnitude of the first capacitance of the third switching element ST3.

[0182] Therefore, the display device can adjust the difference between the first capacitance of the first pixel SP1, the first capacitance of the second pixel SP2, and the first capacitance of the third pixel SP3, so as to minimize the difference in kickback voltage between the first pixel SP1, the second pixel SP2, and the third pixel SP3. The display device can compensate for the difference in kickback voltage between the first pixel SP1, the second pixel SP2, and the third pixel SP3, thereby preventing blotches caused by brightness variations of multiple pixels SP.

[0183] Figure 17 is a plan view of the display device in the inspection process in the method for inspecting a display device according to an embodiment. Figure 17 of the first substrate 110 of the display panel is the same as Figure 2 the first substrate 110, and the structures that are the same as those described above will be briefly described or omitted.

[0184] Referring to Figure 17 , the display panel 100 can include a first substrate 110 and a third substrate 130.

[0185] The first substrate 110 may include a display area DA and a non-display area NDA.

[0186] The display area DA, which is an area for displaying an image, may be defined as a central area of the first substrate 110. The display area DA may include a plurality of pixels SP formed in each pixel area intersected by a plurality of data lines DL and a plurality of gate lines GL. The plurality of gate lines GL may include a plurality of first gate lines VGL and a plurality of second gate lines HGL. For example, the plurality of first gate lines VGL may be a plurality of vertical gate lines VGL connected to the gate pad unit GP and extending in the second direction (Y-axis direction), and the plurality of second gate lines HGL may be a plurality of horizontal gate lines HGL connected to any one of the plurality of vertical gate lines VGL and extending in the first direction (X-axis direction). Each of the plurality of pixels SP may be connected to at least one horizontal gate line HGL and at least one data line DL. Each of the plurality of pixels SP may be defined as an area of a minimum unit for outputting light.

[0187] The non-display area NDA may be defined as a remaining area except the display area DA of the first substrate 110. For example, the non-display area NDA may include a plurality of panel pad units PP and a plurality of third fan-out lines FOL3.

[0188] Each of the plurality of panel pad units PP may include a plurality of first data pad units DPa, a plurality of gate pad units GP, and a plurality of second data pad units DPb. The arrangement of the plurality of first data pad units DPa, the plurality of gate pad units GP, and the plurality of second data pad units DPb is not limited to Figure 17 , Figure 18 and Figure 19 , and may vary according to the configurations of the first substrate 110 and the third substrate 130. For example, one panel pad unit PP may correspond to one flexible film 210. Each of the plurality of panel pad units PP may be connected to each of the plurality of flexible films 210.

[0189] A plurality of first data pad units DPa may be arranged at one side of the panel pad unit PP, and a plurality of second data pad units DPb may be arranged at the other side of the panel pad unit PP. The plurality of first data pad units DPa are different in arrangement from the plurality of second data pad units DPb, but the plurality of first data pad units DPa may be substantially the same as the plurality of second data pad units DPb in structure and function. The first data pad unit DPa and the second data pad unit DPb may be connected to the first data test pad unit DTPa and the second data test pad unit DTPb through the first fan-out line FOL1, the connection line unit CLU, and the second fan-out line FOL2. The first data pad unit DPa and the second data pad unit DPb may be connected to the data line DL through the third fan-out line FOL3. Accordingly, the first data pad unit DPa and the second data pad unit DPb may supply the data test voltages received from the first data test pad unit DTPa and the second data test pad unit DTPb to the data line DL, respectively.

[0190] A plurality of gate pad units GP may be arranged between the plurality of first data pad units DPa and the plurality of second data pad units DPb. The gate pad unit GP may be connected to the gate test pad unit GTP through the first fan-out line FOL1, the connection line unit CLU, and the second fan-out line FOL2. The gate pad unit GP may be connected to the vertical gate line VGL through the third fan-out line FOL3. Accordingly, the gate pad unit GP may supply the gate test signal received from the gate test pad unit GTP to the vertical gate line VGL.

[0191] The third substrate 130 may extend from one end of the first substrate 110. The third substrate 130 may be formed together with the first substrate 110 in the process of manufacturing the display panel 100 and may be used in the process of inspecting the illumination of the display panel 100. The third substrate 130 may include a plurality of test pad units TP. The plurality of test pad units TP may be connected to an external light source (not shown) during the process of inspecting the illumination of the display panel 100 and may receive a data test voltage and a gate test signal from the external light source. For example, the data test voltage may be a gray voltage for turning on a plurality of pixels SP or a black voltage for turning off a plurality of pixels SP, but is not limited thereto. When the illumination inspection of the display panel 100 is completed, the third substrate 130 may be separated from the first substrate 110.

[0192] Each of the plurality of test pad units TP may include a plurality of first data test pad units DTPa, a plurality of gate test pad units GTP, and a plurality of second data test pad units DTPb. The arrangement of the plurality of first data test pad units DTPa, the plurality of gate test pad units GTP, and the plurality of second data test pad units DTPb is not limited to Figure 17 、Figure 18 and Figure 19 illustrations of, and can vary according to the configurations of the first substrate 110 and the third substrate 130. One test pad unit TP can correspond to one panel pad unit PP of the first substrate 110. Each of the plurality of test pad units TP can be connected to each of the plurality of panel pad units PP of the first substrate 110.

[0193] A plurality of first data test pad units DTPa can be arranged at one end of the test pad unit TP, and a plurality of second data test pad units DTPb can be arranged at the other side of the test pad unit TP. The plurality of first data test pad units DTPa are different in arrangement from the plurality of second data test pad units DTPb, but the plurality of first data test pad units DTPa can be substantially the same as the plurality of second data test pad units DTPb in structure and function. The first data test pad units DTPa and the second data test pad units DTPb can be connected to the first data pad units DPa and the second data pad units DPb through a first fan-out line FOL1, a connection line unit CLU, and a second fan-out line FOL2. Accordingly, the first data test pad units DTPa and the second data test pad units DTPb can supply data test voltages received from an external light source to the first data pad units DPa and the second data pad units DPb, respectively.

[0194] A plurality of gate test pad units GTP can be arranged between the plurality of first data test pad units DTPa and the plurality of second data test pad units DTPb. The gate test pad units GTP can be connected to the gate pad units GP through a first fan-out line FOL1, a connection line unit CLU, and a second fan-out line FOL2. Accordingly, the gate test pad units GTP can supply gate test signals received from an external light source to the vertical gate lines VGL.

[0195] Figure 18 is Figure 17 an enlarged view of region A1 of

[0196] Referring to Figure 18 , the test pad unit TP includes a plurality of first data test pad units DTPa, a plurality of gate test pad units GTP, a plurality of second data test pad units DTPb, a first dummy pad unit DUM1 and a second dummy pad unit DUM2, and a first voltage supply pad unit VSPa and a second voltage supply pad unit VSPb.

[0197] The plurality of first data test pad units DTPa can be provided at one end of the test pad unit TP. The plurality of first data test pad units DTPa can be connected to the first data pad units DPa through a first fan-out line FOL1, a connection line unit CLU, and a second fan-out line FOL2.

[0198] A plurality of first data test pad units DTPa may include a first - first data test pad unit to a first - sixth data test pad unit DTP1, DTP2, DTP3, DTP4, DTP5, and DTP6. Some of the first - first data test pad unit to the first - sixth data test pad unit DTP1, DTP2, DTP3, DTP4, DTP5, and DTP6 may supply a data test voltage to pixels SP among the plurality of pixels SP that output light of a first color. Some of the first - first data test pad unit to the first - sixth data test pad unit DTP1, DTP2, DTP3, DTP4, DTP5, and DTP6 may supply a data test voltage to pixels SP among the plurality of pixels SP that output light of a second color. Other of the first - first data test pad unit to the first - sixth data test pad unit DTP1, DTP2, DTP3, DTP4, DTP5, and DTP6 may supply a data test voltage to pixels SP among the plurality of pixels SP that output light of a third color. Here, the light of the first color, second color, and third color output by the pixels SP may be red light, green light, and blue light, but is not limited thereto.

[0199] A plurality of second data test pad units DTPb may be provided at the other end of the test pad unit TP. The plurality of second data test pad units DTPb may be connected to the second data pad unit DPb through a first fan - out line FOL1, a connection line unit CLU, and a second fan - out line FOL2. The plurality of second data test pad units DTPb may include a second - first data test pad unit to a second - sixth data test pad unit DTP1, DTP2, DTP3, DTP4, DTP5, and DTP6. The plurality of first data test pad units DTPa are different in layout from the plurality of second data test pad units DTPb, but the plurality of first data test pad units DTPa are substantially the same as the plurality of second data test pad units DTPb in structure and function. Therefore, the description of the plurality of second data test pad units DTPb will be omitted.

[0200] A plurality of gate test pad units GTP may be provided between the plurality of first data test pad units DTPa and the plurality of second data test pad units DTPb. The plurality of gate test pad units GTP may include a first gate test pad unit to a fourth gate test pad unit GTP1, GTP2, GTP3, and GTP4. Each of the first gate test pad unit to the fourth gate test pad unit GTP1, GTP2, GTP3, and GTP4 may supply a gate test signal to a plurality of horizontal gate lines HGL through a plurality of vertical gate lines VGL.

[0201] The first dummy pad unit DUM1 can be disposed between the first data test pad unit DTPa and the gate test pad unit GTP. The first dummy pad unit DUM1 can prevent the formation of an electrostatic capacitance between the first data test pad unit DTPa and the gate test pad unit GTP, or can prevent signal interference between the first data test pad unit DTPa and the gate test pad unit GTP.

[0202] The second dummy pad unit DUM2 can be disposed between the gate test pad unit GTP and the second data test pad unit DTPb. The second dummy pad unit DUM2 can prevent the formation of an electrostatic capacitance between the gate test pad unit GTP and the second data test pad unit DTPb, or can prevent signal interference between the gate test pad unit GTP and the second data test pad unit DTPb.

[0203] The first voltage supply pad unit VSPa and the second voltage supply pad unit VSPb can be respectively disposed at both ends of the test pad unit TP. For example, the first voltage supply pad unit VSPa and the second voltage supply pad unit VSPb can be respectively connected to the common voltage pad and the storage voltage pad of the first substrate 110.

[0204] Figure 19 is a diagram showing the connection relationship between the test pad and the pixel in the method of inspecting a display device according to an embodiment.

[0205] Referring to Figure 19 , the test pad unit TP can be connected to the panel pad unit PP through the first fan-out line FOL1, the connection line unit CLU, and the second fan-out line FOL2.

[0206] The connection line unit CLU can include a data connection line DCL, a gate connection line GCL, and a gate contact line CNL.

[0207] The data connection line DCL can intersect with the first fan-out line FOL1 and the second fan-out line FOL2. For example, a plurality of first fan-out lines FOL1 can extend in the second direction (Y-axis direction) and can be separated from each other in the first direction (X-axis direction). A plurality of second fan-out lines FOL2 can extend in the second direction (Y-axis direction) and can be separated from each other in the first direction (X-axis direction). A plurality of data connection lines DCL can extend in the first direction (X-axis direction) and can be separated from each other in the second direction (Y-axis direction). The plurality of data connection lines DCL can include the first data connection line to the sixth data connection line DCL1, DCL2, DCL3, DCL4, DCL5, and DCL6.

[0208] Some of the plurality of first fan-out lines FOL1 can be connected to a plurality of first data pad units DPa one-to-one through second fan-out lines FOL2. Some of the first fan-out lines FOL1 corresponding to the plurality of first data pad units DPa among the plurality of first fan-out lines FOL1 can be connected to a first-first data test pad unit DTP1. Other first fan-out lines FOL1 corresponding to the plurality of first data pad units DPa among the plurality of first fan-out lines FOL1 may not be connected to the first-first data test pad unit DTP1. For example, the first-first data test pad unit DTP1 can be connected to some of the first fan-out lines FOL1 among the plurality of first fan-out lines FOL1, and some of the first fan-out lines FOL1 can be connected to a first data connection line DCL1. The first data connection line DCL1 can extend to an area where the first-first data test pad unit DTP1 is not provided, and can supply a data test voltage to the second fan-out line FOL2, rather than the first fan-out line FOL1 that is not directly connected to the first-first data test pad unit DTP1.

[0209] Therefore, each of the first data connection line to the sixth data connection line DCL1, DCL2, DCL3, DCL4, DCL5, and DCL6 can supply a data test voltage to the second fan-out line FOL2 extending from the corresponding first fan-out line FOL1, rather than the first fan-out line FOL1 that is not directly connected to the plurality of first data test pad units DTPa.

[0210] The gate connection line GCL can intersect with the first fan-out line FOL1 and the second fan-out line FOL2. For example, the plurality of first fan-out lines FOL1 can extend in the second direction (Y-axis direction) and can be separated from each other in the first direction (X-axis direction). The plurality of second fan-out lines FOL2 can extend in the second direction (Y-axis direction) and can be separated from each other in the first direction (X-axis direction). The plurality of gate connection lines GCL can extend in the first direction (X-axis direction) and can be separated from each other in the second direction (Y-axis direction). The plurality of gate connection lines GCL can include a first gate connection line to a fourth gate connection line GCL1, GCL2, GCL3, and GCL4.

[0211] Some of the plurality of first fan-out lines FOL1 can be connected to a plurality of gate pad units GP one-to-one through the second fan-out lines FOL2. Some of the first fan-out lines FOL1 corresponding to each of the plurality of gate pad units GP among the plurality of first fan-out lines FOL1 can be connected to the first gate test pad unit GTP1. Some of the first fan-out lines FOL1 corresponding to the plurality of gate pad units GP among the plurality of first fan-out lines FOL1 can be connected to the first gate test pad unit GTP1. Other first fan-out lines FOL1 corresponding to the plurality of gate pad units GP among the plurality of first fan-out lines FOL1 may not be connected to the first gate test pad unit GTP1. For example, the first gate test pad unit GTP1 can be connected to some of the first fan-out lines FOL1 among the plurality of first fan-out lines FOL1, and some of the first fan-out lines FOL1 among the first fan-out lines FOL1 can be connected to the first gate connection line GCL1. The first gate connection line GCL1 can extend to an area where the first gate test pad unit GTP1 is not provided, and can supply a gate test voltage to the second fan-out line FOL2, rather than the first fan-out line FOL1 that is not directly connected to the first gate test pad unit GTP1.

[0212] Therefore, each of the first gate connection line to the fourth gate connection line GCL1, GCL2, GCL3, and GCL4 can supply a gate test voltage to the second fan-out line FOL2 extending from the corresponding first fan-out line FOL1, rather than the first fan-out line FOL1 that is not directly connected to the plurality of gate test pad units GTP.

[0213] The gate contact line CNL can cross the first fan-out line FOL1. For example, the plurality of first fan-out lines FOL1 can extend in the second direction (Y-axis direction) and can be separated from each other in the first direction (X-axis direction). The plurality of gate contact lines CNL can extend in the first direction (X-axis direction) and can be separated from each other in the second direction (Y-axis direction). One of the plurality of gate test pad units GTP can be connected to the corresponding gate contact line CNL through the first fan-out line FOL1. The plurality of gate contact lines CNL can reduce the contact resistance between the first fan-out line FOL1 and the second fan-out line FOL2 corresponding to the plurality of gate pad units GP.

[0214] Therefore, in the method of inspecting a display device, lighting inspection can be performed by using the first data pad unit DPa and the second data pad unit D Pb provided at one end of the first substrate 110 and the gate pad unit GP, thereby reducing the non-display area of the display device, improving the reliability of the display device, and reducing the cost of lighting inspection.

[0215] Figure 20 is a flowchart showing a process of inspecting a display device according to an embodiment.

[0216] Reference Figure 20 , an external light source (not shown) may apply a data test voltage to a first data test pad unit DTPa or a second data test pad unit DTPb provided on the third substrate 130 (step S110).

[0217] The first data test pad unit DTPa or the second data test pad unit DTPb may supply the data test voltage to a first data pad unit DPa or a second data pad unit DPb provided at one end of the first substrate 110 through a first fan-out line FOL1, a data connection line DCL, and a second fan-out line FOL2 (step S120).

[0218] An external light source (not shown) may apply a gate test signal to a gate test pad unit GTP provided on the third substrate 130 (step S130).

[0219] The gate test pad unit GTP may supply the gate test signal to a gate pad unit GP provided on one side of the first substrate 110 through a first fan-out line FOL1, a gate connection line GCL, and a second fan-out line FOL2 (step S140).

[0220] Figure 21 is a flowchart showing a process of supplying a data test voltage in a method for inspecting a display device according to an embodiment.

[0221] Refer together to Figure 21 with Figure 20 , the step of supplying the data test voltage (step S120) may include the following steps S121, S122, S123, and S124.

[0222] Each of the first data test pad unit DTPa and the second data test pad unit DTPb may supply the data test voltage to some of the plurality of first fan-out lines FOL1 (step S121).

[0223] Some of the first fan-out lines FOL1 connected to the first data test pad unit DTPa or the second data test pad unit DTPb may supply the data test voltage to the corresponding data connection line DCL (step S122).

[0224] The data connection line DCL may supply the data test voltage to the corresponding second fan-out line FOL2 (step S123).

[0225] The second fan-out line FOL2 may supply the data test voltage to the corresponding first data pad unit DPa or the second data pad unit DPb (step S124).

[0226] Therefore, in the method of inspecting a display device, a data test voltage can be stably supplied to the first data pad unit DPa or the second data pad unit DPb through the first fan-out line FOL1, the data connection line DCL, and the second fan-out line FOL2.

[0227] Figure 22 FIG. is a flowchart showing a process of supplying a gate test signal in a method of inspecting a display device according to an embodiment.

[0228] Refer to together Figure 22 With Figure 20 , the step of supplying a gate test voltage (step S140) may include the following steps S141, S142, S143, and S144.

[0229] The gate test pad unit GTP may supply a gate test signal to some of the plurality of first fan-out lines FOL1 (step S141).

[0230] Some of the first fan-out lines FOL1 connected to the gate test pad unit GTP among the first fan-out lines FOL1 may supply the gate test signal to the corresponding gate connection line GCL (step S142).

[0231] The gate connection line GCL may supply the gate test signal to the corresponding second fan-out line FOL2 (step S143).

[0232] The second fan-out line FOL2 may supply the gate test signal to the corresponding gate pad unit GP (step S144).

[0233] Therefore, in the method of inspecting a display device, a gate test signal can be stably supplied to the gate pad unit GP through the first fan-out line FOL1, the gate connection line GCL, and the second fan-out line FOL2.

[0234] Figure 23 FIG. is a diagram showing a connection relationship between a display driving circuit and a panel pad unit in a method of inspecting a display device according to another embodiment.

[0235] Refer to Figure 23 , the display driving circuit 220 may include a first data driver DICa, a gate driver GIC, and a second data driver DICb. For example, one display driving circuit 220 may correspond to one flexible film 210 and one panel pad unit PP. Each of the plurality of display driving circuits 220 may be connected to each of the plurality of panel pad units PP.

[0236] The first data driver DICa may be disposed at one end of the display driving circuit 220, and the second data driver DICb may be disposed at the other end of the display driving circuit 220. The first data driver DICa is different in layout from the second data driver DICb, but the first data driver DICa may be substantially the same as the second data driver DICb in structure and function. The first data driver DICa and the second data driver DICb may be connected to the contact pads CP of the flexible film 210 through leads LL. The contact pads CP of the flexible film 210 may be connected to the panel pad unit PP of the first substrate 110. Accordingly, each of the first data driver DICa and the second data driver DICb may supply a data voltage to each of the first data pad unit DPa and the second data pad unit DPb.

[0237] The gate driver GIC may be disposed between the first data driver DICa and the second data driver DICb. The gate driver GIC may be connected to the contact pads CP of the flexible film 210 through leads LL. The contact pads CP of the flexible film 210 may be connected to the panel pad unit PP of the first substrate 110. Accordingly, the gate driver GIC may supply a gate signal to the gate pad unit GP.

[0238] The first substrate 110 may further include a common voltage pad VCOMP, a storage voltage pad VCSTP, and a cut-off voltage pad VOFFP. The common voltage pad VCOMP may receive a common voltage from the first data driver DICa or the second data driver DICb or the power supply unit 250. The storage voltage pad VCSTP may receive a storage voltage from the first data driver DICa or the second data driver DICb or the power supply unit 250. For example, the cut-off voltage pad VOFFP may receive a cut-off voltage from the first data driver DICa or the second data driver DICb or the power supply unit 250. For another example, the cut-off voltage pad VOFFP may be floating or grounded.

[0239] Accordingly, in the method of inspecting a display device, lighting inspection may be performed by using the first data driver DICa, the second data driver DICb, and the gate driver GIC attached to the flexible film 210, thereby reducing the non-display area of the display device, improving the reliability of the display device, and reducing the cost of lighting inspection.

[0240] Figure 24 is a flowchart showing a process of inspecting a display device according to another embodiment.

[0241] Refer to Figure 24, each of the first data driver DICa and the second data driver DICb may supply a data voltage to each of the first data pad unit DPa and the second data pad unit DPb (step S210). The first data pad unit DPa and the second data pad unit DPb may supply the data voltage to a plurality of data lines DL (step S220).

[0242] The gate driver GIC may supply a gate signal to the gate pad unit GP (step S230). The gate pad unit GP may supply the gate signal to a plurality of vertical gate lines VGL (step S240). Each of the plurality of vertical gate lines VGL may supply the gate signal to each of the plurality of horizontal gate lines HGL (step S250).

[0243] The effects of the present disclosure are not limited by the foregoing, and various other effects are expected herein.

[0244] Although the preferred embodiments of the present disclosure have been disclosed for illustrative purposes, those skilled in the art will understand that various modifications, additions, and substitutions are possible without departing from the scope and spirit of the disclosure as disclosed in the appended claims.

Claims

1. A display device, the display device comprising: A plurality of data lines extending in a first direction; A plurality of first gate lines extending in the first direction and arranged parallel to the plurality of data lines; A plurality of second gate lines extending in a second direction intersecting the first direction and intersecting the plurality of first gate lines; A line contact portion, in which each of the plurality of first gate lines contacts each of the plurality of second gate lines; A non-contact portion, in which each of the plurality of first gate lines and each of the plurality of second gate lines are insulated from each other at their intersection regions; A first pixel including a first switching element connected to a corresponding second gate line among the plurality of second gate lines and disposed adjacent to the line contact portion; And A second pixel including a second switching element connected to the second gate line connected to the first pixel and disposed adjacent to the non-contact portion, wherein the first pixel and the second pixel are disposed between first gate lines among the plurality of first gate lines adjacent to each other in the second direction, and wherein a magnitude of a first capacitance between a gate electrode and a first electrode of the first switching element is different from a magnitude of a first capacitance between a gate electrode and a first electrode of the second switching element.

2. The display device according to claim 1, Among them, The magnitude of the first capacitance of the first switching element is smaller than the magnitude of the first capacitance of the second switching element.

3. The display device according to claim 1, Among them, A size of the gate electrode of the first switching element is smaller than a size of the gate electrode of the second switching element.

4. The display device according to claim 1, Among them, A size of an active region of the first switching element is smaller than a size of an active region of the second switching element.

5. The display device according to claim 1, Among them, The first electrode of the first switching element is connected to a first pixel electrode of the first switching element, and the first electrode of the second switching element is connected to a second pixel electrode of the second switching element, and wherein a size of the first electrode of the first switching element is smaller than a size of the first electrode of the second switching element.

6. The display device according to claim 1, Among them, A magnitude of a second capacitance between a first pixel electrode of the first pixel and an adjacent first gate line among the plurality of first gate lines is different from a magnitude of a second capacitance between a second pixel electrode of the second pixel and an adjacent first gate line among the plurality of first gate lines.

7. The display device according to claim 6, Among them, The magnitude of the second capacitance of the first switching element is larger than the magnitude of the second capacitance of the second switching element.

8. A display device, the display device comprising: A substrate having a display area and a non-display area, and including a gate pad unit and a data pad unit provided at one end of the non-display area; A flexible film connected to each of the gate pad unit and the data pad unit; And A display driving circuit provided on the flexible film, Wherein the substrate includes: a plurality of data lines extending in a first direction in the display area; a plurality of first gate lines extending in the first direction and arranged parallel to the plurality of data lines; and a plurality of second gate lines extending in a second direction intersecting the first direction and crossing the plurality of first gate lines; a line contact portion in which each of the plurality of first gate lines contacts each of the plurality of second gate lines; a non-contact portion in which each of the plurality of first gate lines and each of the plurality of second gate lines are insulated from each other at their intersection regions; a first pixel including a first switching element connected to a corresponding second gate line among the plurality of second gate lines and provided adjacent to the line contact portion; and a second pixel including a second switching element connected to the second gate line connected to the first pixel and provided adjacent to the non-contact portion, wherein the first pixel and the second pixel are provided between first gate lines adjacent to each other in the second direction among the plurality of first gate lines, and a magnitude of a first capacitance between a gate electrode and a first electrode of the first switching element is different from a magnitude of a first capacitance between a gate electrode and a first electrode of the second switching element, and Wherein the display driving circuit includes: a data driver connected to the data pad unit to supply a data voltage to the plurality of data lines; and a gate driver connected to the gate pad unit to supply a gate signal to the plurality of first gate lines.

9. A method for inspecting a display device, the display device comprising: A plurality of data lines extending in a first direction; A plurality of first gate lines extending in the first direction and arranged parallel to the plurality of data lines; A plurality of second gate lines extending in a second direction intersecting the first direction and intersecting the plurality of first gate lines; a line contact portion in which each first gate line of the plurality of first gate lines contacts each second gate line of the plurality of second gate lines; a non-contact portion in which each first gate line of the plurality of first gate lines and each second gate line of the plurality of second gate lines are insulated from each other at their intersection regions; a first pixel including a first switching element connected to a corresponding second gate line among the plurality of second gate lines and disposed adjacent to the line contact portion; and a second pixel including a second switching element connected to the second gate line connected to the first pixel and disposed adjacent to the non-contact portion, wherein the first pixel and the second pixel are disposed between first gate lines among the plurality of first gate lines adjacent to each other in the second direction, and a magnitude of a first capacitance between a gate electrode and a first electrode of the first switching element is different from a magnitude of a first capacitance between a gate electrode and a first electrode of the second switching element, The method includes the following steps: Supplying a data voltage to a data pad unit provided at one end of a substrate; Supplying the data voltage to the plurality of data lines through the data pad unit; Supplying a gate signal to a gate pad unit provided at one end of the substrate; Supplying the gate signal to the plurality of first gate lines through the gate pad unit; and Supplying the gate signal to each second gate line of the plurality of second gate lines through each first gate line of the plurality of first gate lines.

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