Semiconductor device and method for manufacturing semiconductor device

Abstract

A semiconductor device and a method for manufacturing the semiconductor device. The method includes: providing a sub-panel substrate on a sub-panel base, the sub-panel substrate including a dielectric structure and a conductive structure, wherein the sub-panel substrate includes a singulated portion of the panel substrate; providing: a first electronic component, the first electronic component is on a first side of the sub-panel substrate and electrically coupled to a first portion of the conductive structure, and a second electronic component, the second electronic component is on the first side of the sub-panel substrate and electrically coupled to a second portion of the conductive structure; removing the sub-panel base; providing: a first external interconnect, the first external interconnect is on a second side of the sub-panel substrate and electrically coupled to the first portion of the conductive structure, and a second external interconnect is on a second side of the sub-panel substrate and electrically coupled to the second portion of the conductive structure; and singulating the sub-panel substrate to provide individual unit substrates.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Non-Provisional Application No. 16 / 748,956, filed on January 22, 2020, entitled “Semiconductor Device and Method of Fabricating a Semiconductor Device,” which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to electronic devices, and more particularly to semiconductor devices and methods of fabricating semiconductor devices. Background Art

[0004] Previous semiconductor packages and methods for forming or providing semiconductor packages are inadequate, for example, resulting in excessive cost, reduced reliability, relatively low performance, or excessively large package sizes. Other limitations and disadvantages of conventional and traditional methods will become apparent to those skilled in the art by comparing such methods with the present disclosure and referring to the drawings. Summary of the Invention

[0005] According to one aspect of the present invention, a method includes providing a subpanel substrate on a subpanel base, the subpanel substrate including a dielectric structure and a conductive structure, wherein the subpanel substrate includes a singulated portion of a panel substrate; providing: a first electronic component on a first side of the subpanel substrate and electrically coupled to a first portion of the conductive structure, and a second electronic component on the first side of the subpanel substrate and electrically coupled to a second portion of the conductive structure; removing the subpanel base; providing: a first external interconnect on a second side of the subpanel substrate and electrically coupled to the first portion of the conductive structure, and a second external interconnect on the second side of the subpanel substrate and electrically coupled to the second portion of the conductive structure; and singulating the subpanel substrate to provide individual unit substrates. The method further includes providing a subpanel body on a top side of the subpanel substrate, the subpanel body contacting a side edge of the first electronic component and a side edge of the second electronic component. The method further includes providing a first metal cover on the top side of the subpanel substrate above the first electronic component and electrically coupled to the first portion of the conductive structure; and a second metal cover on the top side of the subpanel substrate above the second electronic component and electrically coupled to the second portion of the conductive structure. The method further includes providing a first cover on the top side of the subpanel substrate above the first electronic component; and a second cover on the top side of the subpanel substrate above the second electronic component, wherein the covers comprise a dielectric material. In the method, the subpanel substrate has a strip array form factor. In the method, the subpanel base is secured to the second side of the subpanel substrate via an adhesive. The method further includes removing the subpanel base before providing the first and second external interconnects. The method further includes providing a support carrier on the second side of the subpanel substrate; providing a subpanel body on the unit substrate and on the support carrier, the subpanel body contacting sides of the first and second electronic components; and removing the support carrier. In the method, the sub-panel body contacts a side surface of the unit substrate. In the method, the first electronic component or the second electronic component is exposed through the sub-panel body. In the method, the sub-panel substrate includes a bottom encapsulant on a bottom side of the sub-panel substrate, and the bottom encapsulant contacts a side edge of the external interconnect. In the method, the support carrier is removed after singulating the sub-panel substrate.In the method, the subpanel base is removed before providing the first electronic component and the second electronic component on the first side of the individual unit substrate.

[0006] According to another aspect of the present invention, a method includes: receiving a first sub-panel substrate on a first sub-panel base, the first sub-panel substrate including: a sub-panel dielectric structure; a sub-panel conductive structure, the sub-panel conductive structure coupled to the sub-panel dielectric structure; a first unit substrate, the first unit substrate including: a first unit conductive structure, the first unit conductive structure including a first portion of the sub-panel conductive structure; and a first unit dielectric structure, the first unit dielectric structure including a first portion of the sub-panel dielectric structure; a second unit substrate, the second unit substrate electrically coupled to the first unit substrate and including: a second unit conductive structure, the second unit conductive structure including a second portion of the sub-panel conductive structure; and a second unit dielectric structure, the second unit dielectric structure including a second portion of the sub-panel dielectric structure; coupling a first electronic component to the first unit substrate; coupling a second electronic component to the second unit substrate; and singulating a semiconductor device from the first sub-panel substrate, the semiconductor device including: a first semiconductor device, the first semiconductor device including the first unit substrate and the first electronic component; and a second semiconductor device, the second semiconductor device including the second unit substrate and the second electronic component. The method includes: removing the sub-panel base prior to singulation; wherein: a temporary adhesive between the sub-panel base and the sub-panel substrate is light-releasable; and removing the sub-panel base includes reducing the adhesion of the temporary adhesive by exposure to light. The method includes: receiving a panel substrate on a panel base, the panel base including: a first sub-panel base; and a second sub-panel base, the second sub-panel base being integral with the first sub-panel base; the panel substrate including: the first sub-panel substrate on the first sub-panel base; and a second sub-panel substrate, the second sub-panel substrate on the second sub-panel base and electrically coupled to the first sub-panel substrate; and before coupling the first electronic component: singulating the first sub-panel base and the first sub-panel substrate from the panel base and the panel substrate. In the method: the first sub-panel substrate includes a chip form factor; and the panel substrate includes a rectangular area having a side dimension of at least 400 mm. In the method: the first sub-panel substrate includes a strip array form factor; and the panel substrate includes a rectangular area having a side dimension of at least 400 mm.

[0007] According to yet another aspect of the present invention, a semiconductor device includes: a unit substrate including a unit conductive structure and a unit dielectric structure; and an electronic component coupled to the unit conductive structure; wherein the unit substrate comprises a portion of a sub-panel substrate singulated from a panel substrate. The semiconductor device further includes the sub-panel substrate, wherein: the sub-panel substrate includes a sub-panel conductive structure; and the sub-panel conductive structure includes the unit conductive structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A cross-sectional view of an example semiconductor device is shown.

[0009] Figure 2 A schematic diagram illustrating an example method for fabricating an example semiconductor device.

[0010] Figures 3A to 3G Cross-sectional views illustrating an example method for manufacturing an example semiconductor device.

[0011] Figure 4 A cross-sectional view of an example semiconductor device is shown.

[0012] Figure 5 A cross-sectional view of an example semiconductor device is shown.

[0013] Figure 6 A schematic diagram illustrating an example method for fabricating an example semiconductor device.

[0014] Figure 7 A schematic diagram illustrating an example method for fabricating an example semiconductor device.

[0015] Figure 8 A cross-sectional view of an example semiconductor device is shown.

[0016] Figures 9A to 9S Cross-sectional views illustrating an example method for manufacturing an example semiconductor device.

[0017] Figure 10 A schematic diagram illustrating an example method for fabricating an example semiconductor device.

[0018] Figures 11A to 11C Cross-sectional views illustrating an example method for manufacturing an example semiconductor device.

[0019] Figure 12 A schematic diagram illustrating an example method for fabricating an example semiconductor device. DETAILED DESCRIPTION

[0020] The following discussion provides various examples of semiconductor devices and methods of manufacturing semiconductor devices. Such examples are non-limiting, and the scope of the appended claims should not be limited to the specific examples disclosed. In the following discussion, the terms "example" and "for example" are non-limiting.

[0021] The drawings illustrate general constructional aspects and may omit descriptions and details of well-known features and techniques to avoid unnecessarily obscuring the present disclosure. Furthermore, the components in the drawings are not necessarily drawn to scale. For example, the dimensions of some components in the drawings may be exaggerated relative to other components to facilitate understanding of the examples discussed herein. Identical reference numerals in different figures denote identical components.

[0022] The term "or" means any one or more of the items in the list connected by "or". As an example, "x or y" means any element of the three-element set {(x), (y), (x, y)}. As another example, "x, y or z" means any element of the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}.

[0023] The terms "comprises / comprising" or "includes / including" are "open" terms and specify the presence of the stated features, but do not preclude the presence or addition of one or more other features. The terms "first," "second," etc. may be used herein to describe various components, and these components should not be limited by these terms. These terms are only used to distinguish one component from another. Thus, for example, a first component discussed in the present disclosure could be referred to as a second component without departing from the teachings of the present disclosure.

[0024] Unless otherwise specified, the term "coupled" can be used to describe two components that are in direct contact with each other or to describe two components that are indirectly connected through one or more other components. For example, if component A is coupled to component B, component A can be directly in contact with component B or indirectly connected to component B through an intervening component C. Similarly, the terms "over" or "on" can be used to describe two components that are in direct contact with each other or to describe two components that are indirectly connected through one or more other components.

[0025] Several examples are included in this disclosure. Such examples may be found in the drawings, claims, or specification of this disclosure. In one example, a method for manufacturing a semiconductor device includes providing a sub-panel substrate on a sub-panel base, the sub-panel substrate including a dielectric structure and a conductive structure, wherein the sub-panel substrate includes a singulated portion of a panel substrate; providing a first electronic component on a first side of the sub-panel substrate and electrically coupled to a first portion of the conductive structure, and a second electronic component on the first side of the sub-panel substrate and electrically coupled to a second portion of the conductive structure; removing the sub-panel base; providing a first external interconnect on a second side of the sub-panel substrate and electrically coupled to the first portion of the conductive structure, and a second external interconnect on a second side of the sub-panel substrate and electrically coupled to the second portion of the conductive structure; and singulating the sub-panel substrate to provide individual unit substrates.

[0026] In another example, a method for manufacturing a semiconductor device includes receiving a first sub-panel substrate on a first sub-panel base, the first sub-panel substrate including a sub-panel dielectric structure; a sub-panel conductive structure coupled to the sub-panel dielectric structure; a first unit substrate, the first unit substrate including a first unit conductive structure including a first portion of the sub-panel conductive structure, and a first unit dielectric structure including a first portion of the sub-panel dielectric structure; a second unit substrate, the second unit substrate electrically coupled to the first unit substrate and including a second unit conductive structure including a second portion of the sub-panel conductive structure, and a second unit dielectric structure including a second portion of the sub-panel dielectric structure; coupling a first electronic component to the first unit substrate; coupling a second electronic component to the second unit substrate; and singulating semiconductor devices from the first sub-panel substrate, the semiconductor devices including a first semiconductor device including the first unit substrate and the first electronic component, and a second semiconductor device including the second unit substrate and the second electronic component.

[0027] In another example, a semiconductor device includes a unit substrate including a unit conductive structure and a unit dielectric structure; and an electronic component coupled to the unit conductive structure, wherein the unit substrate includes a portion of a singulated sub-panel substrate of a panel substrate.

[0028] Figure 1 1 shows a cross-sectional view of an example semiconductor device 10. Figure 1 In the example shown in , semiconductor device 10 may include a cell substrate 11 , external interconnects 12 , electronic components 14 , a cell body 15 , and (optionally) an underfill 16 .

[0029] The unit substrate 11 may include a conductive structure 111 including a conductive path 1111 , a top terminal 1112 , and a bottom terminal 1113 , and a dielectric structure 112 . The electronic component 14 may include or may be coupled to a device interconnect 142 .

[0030] Cell substrate 11, external interconnects 12, cell body 15, and (optional) underfill 16 may be referred to as a semiconductor package and may prevent electronic components 14 from being exposed to external components or the environment. In some examples, the semiconductor package may provide electrical coupling between external devices and external interconnects.

[0031] Figure 2 A schematic diagram illustrating an example method for manufacturing an example semiconductor device 10 is shown. Figure 2 In the example shown, the method for manufacturing the semiconductor device 10 may include the following steps: (A) preparing a panel 48; (B) forming or providing a panel substrate 41 or 41A; (C) singulating or separating the sub-panel substrate 21 from the panel substrate 41; (D) assembling the sub-panel device array 10A; and (E) singulating or separating the unit semiconductor device 10 from the sub-panel device array 10A.

[0032] In some instances, preparing panel 48 may include preparing a substantially square or rectangular panel base 481. In some instances, preparing panel 48 may include forming, providing, or applying a temporary adhesive 382 on panel base 481. In some instances, forming or providing panel substrate 41 or 41A may include forming or providing panel substrate 41 or 41A on temporary adhesive 382. In some instances, panel substrate 41 or 41A may be referred to as a redistribution layer (RDL) panel. In some instances, singulating or separating sub-panel substrate 21 may include cutting or separating multiple sub-panel substrates 21 from panel substrate 41 or 41A. In some instances, sub-panel substrate 21 may be referred to as an array of redistribution layer (RDL) substrates, or an RDL array. In some instances, assembling sub-panel device array 10A may include attaching multiple electronic components to sub-panel substrate 21, and covering the multiple electronic components with sub-panel body 25. In some examples, singulation and separation of the unit semiconductor devices 10 may include singulating or cutting a plurality of unit semiconductor devices 10 from the sub-panel device array 10A. In some examples, the panel substrate 41 may be received on a panel base 481. The panel base 481 may include a first sub-panel base 381 and a second sub-panel base 381 integral with the first sub-panel base 381. The panel substrate 41 includes a first sub-panel substrate 21 on the first sub-panel base 381 and a second sub-panel substrate 21 on the second sub-panel base 381. The first and second sub-panel substrates 21 are electrically coupled.

[0033] In some instances, the panel substrate 41 may include, for example, approximately 28×28 unit substrates 11. In some instances, the sub-panel substrate 21 may include, for example, approximately 4×7 unit substrates 11. In some instances, the panel substrate 41 may include, for example, approximately 7×4 sub-panel substrates 21. For a better understanding of the present disclosure, the number of sub-panel substrates 21 or the number of unit substrates 11 stated in the present disclosure is provided herein by way of example and may be less than or greater than those numbers stated in the present disclosure. Figure 2 In the illustrated example, although unit substrate 11 may be located over the entire area of ​​panel substrate 41, this is not a limitation of the present disclosure. In some examples, as shown with respect to panel substrate 41A, unit substrate 11 may be located only over the inner region of a corresponding sub-panel substrate 21 to be separated from panel substrate 41A, thereby leaving the region between sub-panel substrates 21 free of unit substrate 11. In some examples, unit substrate 11 may comprise a portion of a singulated sub-panel substrate 21 of panel substrate 41 or 41A.

[0034] In some examples, the sub-panel substrate 21 may have a generally rectangular or square area. In some examples, the sub-panel substrate 21 may have a strip array form factor, and the panel substrate 41 or 41A may have a side dimension of at least 400 mm. In some examples, the sub-panel substrate 21 may have a substantially circular planar surface. In some examples, the sub-panel substrate 21 may be omitted during the manufacture of the semiconductor device and will be described further below.

[0035] Figures 3A to 3G A cross-sectional view illustrating an example method for manufacturing the semiconductor device 10 is shown. Figure 2 Can be used with Figures 3A to 3G related to different stages. Figure 3A A cross-sectional view of semiconductor device 10 at an early stage of fabrication is shown.

[0036] exist Figure 3A In the example shown in , a substantially planar panel 48 can be prepared or provided. In some examples, the panel 48 can include a panel base 481 and a temporary adhesive 382.

[0037] The panel base 481 may have a substantially planar top side and a substantially planar bottom side opposite the top side. The panel base 481 may include or be referred to as a glass panel, a silicon panel, a ceramic panel, or a metal panel. In some examples, the panel base 481 may have side dimensions of, for example, approximately 400 millimeters (mm) × 400 mm to approximately 2880 mm × 3130 mm. The panel base 481 may support the panel substrate 41 during the manufacturing process and may facilitate handling of the panel substrate 41. Portions of the panel base 481 may also support the sub-panel device array 10A during its assembly process and may facilitate handling of the sub-panel device array 10A.

[0038] A temporary adhesive 382 may be provided on the panel base 481. In some examples, the temporary adhesive 382 may include or be referred to as, for example, a releasable layer. In some examples, the temporary adhesive 382 may include or be referred to as a photo-releasable layer configured to be releasable from the sub-panel substrate 21 after reacting with light, such as ultraviolet light or laser light. In some examples, the temporary adhesive 382 may include a heat-releasable layer, a thermosetting adhesive resin, or a thermoplastic resin.

[0039] In some examples, the temporary adhesive 382 can be coated on the panel base 481 using spin coating, spray coating, or slit die coating. The temporary adhesive 382 can have a thickness in a range of about 0.5 micrometers (μm) to about 10 μm.

[0040] Temporary adhesive 382 can provide adhesion to facilitate preparation of panel substrate 41, singulation of sub-panel substrate 21, or assembly of sub-panel device array 10A. In some examples, temporary adhesive 382 can be chemically and heat resistant to prevent damage during preparation of panel substrate 41, singulation of sub-panel substrate 21, or assembly of sub-panel device array 10A.

[0041] In some instances, the temporary adhesive 382 may lose its adhesiveness due to heat or light to allow easy release of the sub-panel substrate 21 or the unit substrate 11 in a subsequent process. In some instances, the adhesiveness of the temporary adhesive 382 may be removed by heat energy or light energy of a laser beam irradiated into the glass panel.

[0042] Figure 3B FIG. 1 shows a cross-sectional view of a semiconductor device 10 at a later stage in its manufacture. Figure 3B In the example shown in FIG, a panel substrate 41 may be formed or provided on a panel base 481. In some examples, the panel substrate 41 may include a plurality of unit substrates 11 or a plurality of sub-panel substrates 21 (refer to FIG. Figure 2 ).

[0043] In some instances, a seed layer may be formed or provided on the panel base 481. In some instances, the seed layer may be formed or provided by sputtering. In some instances, titanium (Ti) may be sputtered, and then copper (Cu) may be sputtered on the titanium (Ti) to ultimately form or provide a seed layer. The seed layer may have a thickness in the range of about 0.1 μm to about 1 μm. This seed layer may allow power to be applied in subsequent processes to form portions of the conductive structure 111. In some instances, a temporary adhesive 382 may be formed or provided on the panel base 481, and a seed layer may then be formed or provided on the temporary adhesive 382.

[0044] A dielectric structure 112 may be applied to the seed layer. In some examples, the dielectric structure 112 may include one or more dielectric layers formed or provided by spin coating, spray coating, or extrusion coating. In some examples, the dielectric structure 112 may include or may be referred to as, for example, polyimide, benzocyclobutene, or polybenzoxazole. The dielectric structure 112 may have a thickness in a range of approximately 2 μm to approximately 20 μm. The dielectric structure 112 may support the conductive structure 111 and may serve as a dielectric layer.

[0045] In some examples, a mask having a pattern can be positioned over dielectric structure 112, and light can then be irradiated onto the mask to transfer the pattern to dielectric structure 112. In some examples, this photolithography process can be performed using a stepper device. The pattern-transferred portion or the non-transferred portion of dielectric structure 112 can be developed so that dielectric structure 112 can have a pattern or an opening. In some examples, this development process can be performed using a rotary development device. Dielectric structure 112 having an opening can be used as a mask to expose a region of the seed layer through the opening of dielectric structure 112. The region of the seed layer can be exposed through the opening of dielectric structure 112 so that power can be supplied through the seed layer in a subsequent electroplating process.

[0046] In some examples, residual polymer remaining in the opening of dielectric structure 112 may be removed to clean the surface of the seed layer within the opening of dielectric structure 112. In some examples, the residual polymer may be removed by O2 deslagging and spin rinse drying (SRD) equipment.

[0047] The conductive structure 111 may include one or more conductive layers formed or provided on a panel 48 stacked with one or more dielectric layers of the dielectric structure 112. For example, the bottom terminal 1113 of the conductive structure 111 may be formed or provided on a seed layer. The bottom terminal 1113 may include or may be referred to as, for example, a pad, a pad, an under-bump metallization (UBM) pad, or a pillar. In some examples, copper (Cu) or gold (Au), nickel (Ni), and copper (Cu) may be sequentially electroplated on an area of ​​the seed layer within the opening of the dielectric structure 112 to form or provide the bottom terminal 1113. The bottom terminal 1113 may have a line / space / thickness in the range of approximately 0.5 / 0.5 / 0.5 μm to approximately 10 / 10 / 10 μm, respectively. In some examples, the bottom terminal 1113 may be formed or provided by an electroplating device containing a copper (Cu) solution, a nickel (Ni), or a gold (Au) solution, respectively. The external interconnect 12 may be connected to the bottom terminal 1113 in a subsequent process.

[0048] Other seed layers, dielectric layers of the dielectric structure 112, and conductive layers of the conductive structure 111 may be further provided in a manner similar to that described above to form conductive paths 1111 and top terminals 1112 of the conductive structure 111 that pass through the dielectric layers of the dielectric structure 112 or traverse the dielectric layers of the dielectric structure 112. The conductive paths 1111 may include or may be referred to as, for example, traces, vias, down vias, or patterns. In some instances, the conductive paths 1111 may generally be located within or on the corresponding dielectric layers of the dielectric structure 112. In some instances, the top terminals 1112 may include or may be referred to as, for example, pads, pads, bumps, copper (Cu), nickel (Ni), or gold (Au) plated under bump metallization (UBM) pads, vias, down vias, or pillars. In some instances, the top terminals 1112 may be exposed from the dielectric structure 112 and may protrude from above it. As in Figure 1 As seen in FIG, conductive path 1111 can be electrically connected to bottom terminal 1113 and top terminal 1112, and top terminal 1112 can be electrically connected to electronic component 14 and conductive path 1111. In some examples, a bonding material, such as solder or gold, can be further located on top terminal 1112. In some examples, a stencil having openings corresponding to top terminal 1112 can be positioned, solder paste can be located on the stencil, and a predetermined amount of solder paste can then be located on top terminal 1112 through a subsequent extrusion process using a blade. In some examples, solder can be electroplated on top terminal 1112 and then reflowed.

[0049] although Figure 3B3 layers of conductive structure 111 (e.g., one layer of bottom terminal 1113, one layer of conductive path 1111, and one layer of top terminal 1112) and 2 layers of dielectric structure 112 are shown, but this does not limit the present disclosure. In some examples, the number of layers of conductive structure 111 and dielectric structure 112 can be greater or less than those described above.

[0050] In some instances, although Figure 3B A section of panel substrate 41 is shown including 14 unit substrates 11 or two sub-panel substrates 21, but this does not limit the present disclosure. In some examples, the respective numbers of unit substrates 11 and sub-panel substrates 21 can be greater or less than those shown in the various figures. In some examples, sub-panel substrate 21 can include sub-panel conductive structure 111, and sub-panel conductive structure 111 can include unit conductive structure 11.

[0051] In some instances, the panel substrate 41 or its corresponding sub-panel substrate 21 or unit substrate 11 can be a redistribution layer ("RDL") substrate. The RDL substrate can include one or more conductive redistribution layers and one or more dielectric layers, which can be (a) formed or provided layer by layer on an electronic component to which the RDL substrate can be electrically connected, or (b) formed or provided layer by layer on a carrier that can be completely or at least partially removed after the electronic component and the RDL substrate are coupled together. The RDL substrate can be manufactured layer by layer as a panel-level substrate on a rectangular or square panel carrier in a panel-level process. The RDL substrate can be formed or provided in an additive buildup process, which can include alternating stacking of one or more dielectric layers with one or more conductive layers defining corresponding conductive redistribution patterns or traces, which are configured to collectively (a) fan the electrical traces out of the footprint of the electronic component, or (b) fan the electrical traces into the footprint of the electronic component. The conductive pattern can be formed or provided using a plating process, such as an electroplating process or an electroless plating process. The conductive pattern may include a conductive material, such as copper or other plateable metal. The location of the conductive pattern may be made using a photopatterning process, such as a photolithography process, and a photoresist material for forming a photolithography mask. The dielectric layer of the RDL substrate may be patterned using a photopatterning process that may include a photolithography mask, through which light is exposed to the desired features of the photopattern, such as through-holes in the dielectric layer. Thus, the dielectric layer may be made of a photo-definable organic dielectric material, such as polyimide (PI), benzocyclobutene (BCB), or polybenzoxazole (PBO). Such dielectric materials may be spin-coated or otherwise applied in liquid form, rather than attached in the form of a preformed film. In order to allow the desired photo-defined features to be properly formed, such photo-definable dielectric materials may omit structural reinforcements, or may be filler-free and free of strands, woven fabrics, or other particles that may interfere with the light from the photopatterning process. In some instances, such filler-free properties of the filler-free dielectric material may reduce the thickness of the resulting dielectric layer. Although the photodefinable dielectric material described above may be an organic material, in some instances, the dielectric material of the RDL substrate may include one or more inorganic dielectric layers. Some examples of inorganic dielectric layers may include silicon nitride (Si3N4), silicon oxide (SiO2), or SiON. The inorganic dielectric layer may be formed or provided not by using a photodefinable organic dielectric material but by growing an inorganic dielectric layer using an oxidation or nitridation process. Such an inorganic dielectric layer may be filler-free, without strands, woven fabrics, or other different inorganic particles. In some instances, the RDL substrate may omit a permanent core structure or carrier, such as a dielectric material including bismaleimide triazine (BT) or FR4, and these types of RDL substrates may be referred to as coreless substrates.

[0052] In some instances, the panel substrate 41 or its corresponding sub-panel substrate 21 or unit substrate 11 can be a preformed substrate. The preformed substrate can be manufactured before being attached to the electronic component and can include a dielectric layer between the corresponding conductive layers. The conductive layer can include copper and can be formed or provided using an electroplating process. The dielectric layer can be a relatively thick non-photodefinable layer that can be attached in the form of a preformed film rather than in liquid form, and can include a resin with fillers such as strands, woven fabrics and / or other inorganic particles for rigidity and / or structural support. Since the dielectric layer is non-photodefinable, features such as through holes or openings can be formed or provided by using drilling or lasers. In some instances, the dielectric layer can include a prepreg material or an Ajinomoto built-up film (ABF). The preformed substrate can include a permanent core structure or carrier, such as a dielectric material including bismaleimide triazine (BT) or a glass-reinforced epoxy laminate such as FR4, and the dielectric layer and the conductive layer can be formed or provided on the permanent core structure. In some examples, the preformed substrate may be a coreless substrate and omit a permanent core structure, and the dielectric and conductive layers may be formed or provided on a sacrificial carrier that is removed after the dielectric and conductive layers are formed and before attachment to the electronic component. The preformed substrate may be referred to as a printed circuit board (PCB) or a laminate substrate. Such a preformed substrate may be formed or provided by a semi-additive or simulated semi-additive process.

[0053] Figure 3C FIG. 1 shows a cross-sectional view of the semiconductor device 10 at a later stage of fabrication. Figure 3C In the illustrated example, the sub-panel substrate 21 is shown as being singulated from and separated from the panel substrate 41. In some examples, if the panel substrate 41 includes, for example, two sub-panel substrates 21, the panel substrate 41 can be separated into two sub-panel substrates 21. In some examples, if the panel substrate 41 includes, for example, seven sub-panel substrates 21, the panel substrate 41 can be separated into seven sub-panel substrates 21. In some examples, one sub-panel substrate 21 can include, for example, seven unit substrates 11, but the present disclosure does not limit the number of unit substrates 11 to seven or any other number. In some examples, the panel substrate 41 and the panel 48 can be cut together using an impeller or a laser beam. In this way, the sub-panel substrate 21 can include an underlying sub-panel base 381 and a temporary adhesive layer 382 to facilitate handling of the sub-panel substrate 21 during manufacture. In some examples, due to the use of an impeller or a laser beam to perform the cutting, the lateral sides of the sub-panel substrate 21, the temporary adhesive 382, ​​and the sub-panel base 381 can be coplanar. In some examples, the subpanel substrate 21 can be received on the subpanel base 381. The subpanel substrate 21 can include a subpanel conductive structure 111 and a subpanel dielectric structure 112.

[0054] In some instances, generating sub-panel substrates 21 from a panel substrate 41 can allow this seed panel substrate 21 to be further processed or assembled using tools or machinery that are typically not capable of handling the dimensions of a panel such as the panel substrate 41 to produce the semiconductor device 10. Thus, the panel substrate 41 can be divided or resized by singulating or separating the sub-panel substrates 21 into standard form factors, such as a strip array form factor or a chip / disc form factor, that can be processed by conventional methods or standard equipment used in a pre-existing manufacturing line. In some instances, the first sub-panel base 381 and the first sub-panel substrate 21 can be singulated from the panel base 481 and the panel substrate 41 or 41A before coupling the electronic component 14 to the first sub-panel substrate 21.

[0055] Figure 3D FIG. 1 shows a cross-sectional view of the semiconductor device 10 at a later stage of fabrication. Figure 3D In the example shown in , the electronic component 14 can be attached to the sub-panel substrate 21. In some examples, the sub-panel substrate 21 can include a plurality of unit substrates 11. The first unit substrate 11 can include: a first unit conductive structure 111, the first unit conductive structure including a first portion of the sub-panel conductive structure 111; and a first unit dielectric structure 112, the first unit dielectric structure including a first portion of the sub-panel dielectric structure 112. The second unit substrate 11 can include: a second unit conductive structure 111, the second unit conductive structure including a second portion of the sub-panel conductive structure 111; and a second unit dielectric structure 112, the second unit dielectric structure including a second portion of the sub-panel dielectric structure 112. In some examples, the electronic component 14 can be electrically connected to the top terminal 1112 of the conductive structure 111 of the sub-panel substrate 21, for example on a first side or top side of the sub-panel substrate 21. In some examples, the first electronic component 14 can be electrically coupled to the first portion of the conductive structure 111, and the second electronic component 14 can be electrically coupled to the second portion of the conductive structure 111. Electronic component 14 may include or may be referred to as, for example, a chip, a die, or a package. In some instances, the chip or die may include an integrated circuit die separated from a semiconductor chip. In some instances, electronic component 14 may include a digital signal processor (DSP), a network processor, a power management unit, an audio processor, a radio frequency (RF) circuit, a wireless baseband system-on-chip (SoC) processor, a sensor, or an application-specific integrated circuit (ASIC). In some instances, electronic component 14 may have a thickness in the range of about 20 μm to about 300 μm. In some instances, electronic component 14 may have a thickness in the range of about 50 μm to about 780 μm.

[0056] In some examples, electronic component 14 may include a device interconnect 142, and device interconnect 142 may be electrically connected to top terminal 1112. In some examples, a first electronic component 14 may be coupled to first unit substrate 11, and a second electronic component 14 may be coupled to second unit substrate 11. Device interconnect 142 may include or be referred to as a pad, pillar, or bump of electronic component 14. In some examples, device interconnect 142 may include top terminal 1112, or may be connected to top terminal 1112 via a bonding tip or material such as solder. In some examples, electronic component 14 may be electrically connected to top terminal 1112 using a mass reflow process, a thermal compression process, or a laser-assisted bonding process. In some examples, device interconnect 142 may have a thickness in a range of approximately 1 μm to approximately 50 μm. There may be examples where electronic component 14 may be attached face-up to subpanel substrate 21 via device interconnect 142, and device interconnect 142 may be coupled to substrate top terminal 1112 via a wire bond.

[0057] In some instances, an underfill 16 may be filled between the sub-panel substrate 21 and the electronic component 14. The underfill 16 may include or may be referred to as a capillary underfill, a no-flow underfill also known as a non-conductive paste (NCP), a molded underfill (MUF), or a non-conductive film (NCF). In some instances, the underfill 16 may be a capillary underfill that may fill the gap between the electronic component 14 and the sub-panel substrate 21 after the electronic component 14 is electrically connected to the sub-panel substrate 21. In some instances, the underfill 16 may be a no-flow underfill that may be pressed by the electronic component 14 after being coated on the sub-panel substrate 21. In some instances, after the underfill 16 is coated on the device interconnect 142 of the electronic component 14, the underfill 16 may be attached to the sub-panel substrate 21 when the electronic component 14 presses the underfill 16. In some instances, the bottom filler 16 may be a MUF that can fill the gap between the electronic component 14 and the sub-panel substrate 21 and can cover the electronic component 14. In some instances, the bottom filler 16 may be a non-conductive film (NCF) that can be located in a film form on the top terminal 1112 of the sub-panel substrate 21 and then pressed by the electronic component 14, after which a solder reflow process and a bottom filler curing process are performed simultaneously. In this way, the bottom filler 16 can be located between the electronic component 14 and the sub-panel substrate 21 to cover the device interconnect 142 and allow the electronic component 14 and the sub-panel substrate 21 to be mechanically connected to each other. Due to the difference between the coefficient of thermal expansion (CTE) of the electronic component 14 (e.g., 2-4 ppm / °C) and the CTE of the sub-panel substrate 21 (e.g., 20-30 ppm / °C), the bottom filler 16 can redistribute stress and deformation. The underfill 16 may prevent physical or chemical impact from being transferred to the electronic component 14 , while preventing moisture from penetrating, and may quickly transfer heat from the electronic component 14 to the outside of the underfill 16 .

[0058] Figure 3E FIG. 1 shows a cross-sectional view of the semiconductor device 10 at a later stage of fabrication. Figure 3EIn the example shown, the subpanel body 25 can cover the electronic component 14 or the underfill 16 located on the subpanel substrate 21. When the semiconductor device 10 is later singulated, the subpanel body 25 can include or define multiple unit bodies 15. In some examples, the subpanel body 25 can be on the top side of the subpanel substrate 21, contacting the side edges of the first electronic component 14 and the side edges of the second electronic component 14. In some examples, the top side of the electronic component 14 and the top side of the subpanel body 25 can be coplanar. In some examples, the top side of the electronic component 14 can be exposed through the top side of the subpanel body 25. The subpanel body 25 can include or be referred to as an encapsulant, molding compound, resin, sealant, or organic body. In some examples, the subpanel body 25 can be formed or provided using compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, solder paste printing, or film-assisted molding. In some examples, the subpanel body 25 can have a thickness in the range of about 80 μm to about 1500 μm. Subpanel body 25 can prevent electronic components 14 from being exposed to external components or the environment. Subpanel body 25 can quickly dissipate heat to the outside of electronic components 14. In some examples, such as when underfill 16 is MUF, underfill 16 can include a portion of the material of subpanel body 25 or be integrated with the material of subpanel body 25.

[0059] Figure 3F FIG. 1 shows a cross-sectional view of the semiconductor device 10 at a later stage of fabrication. Figure 3F In the example shown in , the sub-panel carrier 38 can be removed from the sub-panel substrate 21. In some examples, when the temporary adhesive 382 is located between the sub-panel substrate 21 and the sub-panel base 381, heat or light, such as a laser beam, can be supplied to the temporary adhesive 382 to remove the adhesion of the temporary adhesive 382, ​​thereby releasing the sub-panel base 381 from the sub-panel substrate 21. In some examples, the sub-panel base 381 can be peeled off from the sub-panel substrate 21 using mechanical force. In some examples, the sub-panel base 381 can be removed by a mechanical polishing or chemical etching process. In some examples, the sub-panel base 381 can be removed before singulation, such as where the adhesive 382 or the temporary adhesive 382 between the sub-panel base 381 and the sub-panel substrate 21 is light releasable, and the sub-panel base 381 can be removed by reducing the adhesion of the adhesive 382 or the temporary adhesive 382 by exposure to light. In some examples, the seed layer can be removed from the bottom terminal 1113 and the dielectric structure 112 located in the sub-panel substrate 21. In some examples, the seed layer on the bottom side of the bottom terminal 1113 can be removed by a chemical etching process. Thus, the bottom side of the bottom terminal 1113 can be exposed through the dielectric structure 112.

[0060] Figure 3GFIG. 1 shows a cross-sectional view of the semiconductor device 10 at a later stage of fabrication. Figure 3G In the examples shown in , the external interconnect 12 can be attached or formed or provided on the sub-panel substrate 21. In some examples, the sub-panel base 381 can be removed before the external interconnect 12 is provided on the sub-panel substrate 21. In some examples, the first external interconnect 12 can be on the second side or bottom side of the sub-panel substrate 21 and electrically coupled to the first portion of the conductive structure 111, and the second external interconnect 12 can be on the second side or bottom side of the sub-panel substrate 21 and electrically coupled to the second portion of the conductive structure 111. In some examples, the external interconnect 12 can be connected to the bottom terminal 1113 of the conductive structure 111 provided on the second side or bottom side of the sub-panel substrate 21 or the unit substrate 11. The external interconnect 12 may include or may be referred to as a pad, a pad, a bump, or a solder ball. After the external interconnect 12 is located on the bottom terminal 1113, the external interconnect 12 can be electrically connected to the bottom terminal 1113 using a mass reflow process or a laser assisted bonding process. External interconnect 12 may have a diameter in a range of about 20 μm to about 400 μm. External interconnect 12 may electrically connect semiconductor device 10 to an external device.

[0061] In some instances, you can Figure 3G The dashed lines shown in FIG are used to perform singulation to produce individual semiconductor devices 10. For example, as shown in FIG. Figure 4 or Figure 5 As shown in , the sub-panel substrate 21 can be singulated into individual unit substrates 11. In some examples, the semiconductor device 10 may include: a first semiconductor device 10 including a first unit substrate 11 and a first electronic component 14; and a second semiconductor device 10 including a second unit substrate 11 and a second electronic component 14. In some examples, the sub-panel body 25 and the sub-panel substrate 21 can be singulated using an impeller or a laser beam to provide individual semiconductor devices 10. Figure 3G In the example shown in , for example, seven semiconductor devices 10 can be provided by singulation. In this way, each of the individual semiconductor devices 10 can include a unit substrate 11 and a unit body 15, and the sides of the unit substrate 11 and the sides of the unit body 15 can be coplanar.

[0062] Figure 4 1 shows a cross-sectional view of an example semiconductor device 50. The semiconductor device 50 may be similar to Figure 1 The semiconductor device 10 shown in FIG. 1 includes a metal cover 51 instead of the unit body 15 .

[0063] The metal lid 51 can include a lid top 52 adhered to the top side of the electronic component 14, a lid sidewall 53 extending from the top lid 52 to the unit substrate 11, and a lid bottom 54 attached to the unit substrate 11. In some examples, the lid top 52 of the metal lid 51 can be adhered to the electronic component 14 using a thermally conductive adhesive. In some examples, the lid bottom 54 of the metal lid 51 can be attached to the unit substrate 11 using a conductive adhesive. The lid sidewall 53 is shown as being inclined or slanted, but in some embodiments, can be orthogonal to the lid top 52. In some examples, the metal lid 51 is electrically connected to the conductive structure 111 for grounding of the unit substrate 11. In some examples, a first metal lid 51 can be on the top side of the sub-panel substrate 21 or the unit substrate 11 above the first electronic component 14, and a second metal lid 51 can be on the top side of the sub-panel substrate 21 or the unit substrate 11 above the second electronic component 14. Before or after singulating the subpanel substrate 21 into individual unit substrates 11, a metal cover 51 may be provided on the electronic component 14. The metal cover 51 may include aluminum, copper, or stainless steel. The metal cover 51 may have a thickness in the range of about 1 millimeter (mm) to about 10 mm.

[0064] In this manner, metal cover 51 can protect electronic component 14 from the external mechanical / chemical environment, can quickly dissipate heat from electronic component 14 to the outside of electronic component 14, and can protect electronic component 14 from electromagnetic waves. In some examples, metal cover 51 can prevent electromagnetic waves generated by electronic component 14 from being dissipated to the outside of electronic component 14.

[0065] Figure 5 A cross-sectional view of an example semiconductor device 60 is shown. The semiconductor device 60 may be similar to Figure 1 The semiconductor device 10 shown in FIG. 1 includes a cover 61 instead of the unit body 15 .

[0066] Cover 61 may include cover sides 62 and a cover top 63. Cover sides 62 may be adhered to unit substrate 11 and may be partially parallel to the side surfaces of electronic component 14. In some examples, cover top 63 may be adhered to the top end of side cover 62 and may be parallel to the top side of electronic component 14. In some examples, cover top 63 may be adhered to the top side of electronic component 14 using a thermally conductive adhesive. In some examples, cover top 63 may be adhered to cover sides 62 using a conductive adhesive. Cover sides 62 may be adhered to unit substrate 11 using a conductive adhesive. In some examples, cover sides 62 may be electrically connected to conductive structures 111 for grounding unit substrate 11. In some examples, a first cover 61 may be positioned on the top side of subpanel substrate 21 or unit substrate 11 above a first electronic component 14, and a second cover 61 may be positioned on the top side of subpanel substrate 21 or unit substrate 11 above a second electronic component 14. Covers 61 may be provided on electronic components 14 before or after the subpanel substrate 21 is singulated into individual unit substrates 11. The lid side 62 or lid top 63 can include a metal material such as aluminum, copper, or stainless steel, or a dielectric material such as a thermoplastic or laminate cavity substrate. In some examples, the lid side 62 and lid top 63 can have a thickness in the range of about 1 mm to about 10 mm.

[0067] Figure 6 A schematic diagram illustrating an example method for manufacturing an example semiconductor device 10 is shown. Figure 6 In the example shown in FIG, an example method for manufacturing the semiconductor device 10 may be similar to Figure 2 , except for the following steps: (C') forming or providing the sub-panel substrate 21 to have a circular or chip shape, and (D') forming or providing the sub-panel device array 10A to have a circular or chip shape.

[0068] In some examples, a plurality of circular sub-panel substrates 21 are singulated or separated from a rectangular panel substrate 41. The circular dashed lines indicated on the rectangular panel substrate 41 represent cutting lines for separating the circular sub-panel substrates 21 from the panel substrate 41. In some examples, the sub-panel substrates 21 may include a chip form factor, and the panel substrate 41 may include a rectangular area having a side dimension of at least 400 mm.

[0069] In some instances, the circular sub-panel substrate 21 may include, for example, approximately 32 discrete unit substrates 11. In some instances, the panel substrate 41 may include a 3×3 array of nine circular sub-panel substrates 21. Although multiple unit substrates 11 of a single sub-panel substrate 21 or multiple sub-panel substrates 21 of a single panel substrate 41 are provided by way of example only, this is not a limitation of the present disclosure. In some instances, the number of unit substrates 11 or the number of sub-panel substrates 21 may be greater or less than those stated in the present disclosure. In this way, because the sub-panel substrate 21 has a substantially circular or chip shape, existing semiconductor assembly equipment can be used without modification or replacement.

[0070] Figure 7 A schematic diagram illustrating an example method for manufacturing an example semiconductor device 10 is shown. Figure 7 In the example shown in FIG, an example method for manufacturing the semiconductor device 10 may be similar to Figure 2 The manufacturing method shown in FIG. 3 is different in the step of singulating the sub-panel substrate 21 from the panel substrate 41 .

[0071] In some examples, individual unit substrates 11 may be singulated from the panel substrate 41 and the semiconductor assembly process may be performed using such unit substrates 11 alone, rather than as part of the sub-panel substrate 21. This approach may be applicable to semiconductors with an area greater than 144 square millimeters (mm 2 ) or a larger unit substrate 11 having a size greater than 12 mm x 12 mm array, such as a flip chip ball grid array (FCBGA) substrate. In some examples, this assembly process can be similar to one or more of the assembly processes described herein, such as in Figures 3D to 3G The process described above is described separately, rather than as part of the process of the sub-panel substrate 21. In some instances, the unit substrate 11 may be tested to determine whether it is good or bad. Unit substrates 11 that have passed the test may be used in the semiconductor device assembly process. Except for unit substrates 11 determined to be defective products, the assembly process may be performed on good unit substrates 11 to avoid material waste.

[0072] Figure 8 FIG. 7 is a cross-sectional view of an example semiconductor device 70. In some examples, the semiconductor device 70 may be similar to Figure 1, but the unit body 75 covers the side edges of the unit substrate 11 and the bottom encapsulant 77 covers the bottom surface of the unit substrate 11. In some examples, the unit body 75 may cover not only the side edges of the unit substrate 11 but also the side edges of the bottom encapsulant 77. In some examples, the bottom encapsulant 77 may cover not only the bottom surface of the unit substrate 11 but also the side edges of the external interconnect 12. In some examples, when the unit body 75 covers the side edges of the unit substrate 11 and the side edges of the bottom encapsulant 77, and the bottom encapsulant 77 covers the bottom surface of the unit substrate 11, warping of the semiconductor device 70 can be suppressed.

[0073] Figures 9A to 9S A cross-sectional view illustrating an example method for manufacturing an example semiconductor device 70. Figures 9A to 9S The example fabrication methods, features, structures, or components of the semiconductor device 70 shown in FIG. 7 may be similar to those described with respect to FIG. Figures 3A to 3G Those features, structures, or components described with reference to the example semiconductor device 10 shown in FIG. 1 are omitted so that the following description will be simplified.

[0074] Figure 9A A cross-sectional view of a semiconductor device 70 is shown at an early stage of fabrication. Figure 9A In the example shown in , a panel base 481 can be provided. In some examples, the panel base 481 can have a substantially planar top surface and a substantially planar bottom surface opposite the top surface. The panel base 481 can include or be made of glass, silicon, ceramic, or metal.

[0075] Figure 9B A cross-sectional view of a semiconductor device 70 is shown at a later stage of fabrication. Figure 9B In the example shown in FIG, a temporary adhesive 382 may be provided on a panel base 481. In some examples, the temporary adhesive 382 may include or may be referred to as a thermosetting adhesive resin or a thermoplastic resin. The panel base 481 and the temporary adhesive 382 may be collectively referred to herein as the panel 48, as described above (see, for example, FIG. Figure 3A ).

[0076] Figure 9C A cross-sectional view of a semiconductor device 70 is shown at a later stage of fabrication. Figure 9C In the example shown in , a seed layer 383 can be provided on the temporary adhesive 382. In some examples, the seed layer 383 can include titanium (Ti), titanium tungsten (TiW), copper (Cu), titanium / copper (Ti / Cu), titanium tungsten / copper (TiW / Cu), or nickel vanadium (NiV).

[0077] Figure 9D A cross-sectional view of a semiconductor device 70 is shown at a later stage of fabrication. Figure 9DIn the example shown in FIG, a first layer of conductive structure 111 can be formed or provided on the seed layer 383. In some examples, the first layer of conductive structure 111 can be provided by the steps of photolithographic mask patterning and electroplating. The conductive structure 111 can include one or more conductive paths 1111 having traces or vias. In some examples, one or more traces of the conductive path 1111 can include or be referred to as a top embedded trace 1114. In some examples, the conductive structure 111 can include a substrate top terminal 1112, which can be a portion or part of the conductive path 1111.

[0078] Figure 9E A cross-sectional view of a semiconductor device 70 is shown at a later stage of fabrication. Figure 9E In the example shown in FIG, a first dielectric structure 112 may be formed or provided on the first conductive structure 111 and the panel 48. In some examples, the dielectric structure 112 may be coated on the entire surface of the conductive structure 111 and the seed layer 383 and cured, a photoresist may be coated on the dielectric structure 112, and photolithography may be performed to pattern the photoresist. The photoresist may be used as a mask to etch a region of the dielectric structure 112 to expose a portion of the first conductive structure 111 through the opening 112a.

[0079] Figure 9F A cross-sectional view of a semiconductor device 70 is shown at a later stage of fabrication. Figure 9F In the example shown in FIG, a second layer of conductive structure 111 can be formed or provided on the first layer of dielectric structure 112 in a manner similar to that described above. The second layer of conductive structure 111 can be connected to the pre-existing first layer of conductive structure 111 through the opening 112a of the first layer of dielectric structure 112. The second layer of conductive structure 111 can include corresponding conductive paths 1111.

[0080] Figure 9G A cross-sectional view of a semiconductor device 70 is shown at a later stage of fabrication. Figure 9G In the example shown in , the second dielectric structure 112 may be provided on the second conductive structure 111 in a manner similar to the first dielectric structure 112. A region of the second dielectric structure 112 may be etched to expose a portion of the second conductive structure 111 through the opening 112b.

[0081] Figure 9H A cross-sectional view of a semiconductor device 70 is shown at a later stage of fabrication. Figure 9HIn the example shown in , a third layer of conductive structure 111 can be formed or provided on the second layer of dielectric structure 112 in a manner similar to that described above. The third layer of conductive structure 111 can be connected to the pre-existing second layer of conductive structure 111 through the opening 112b of the second layer of dielectric structure 112. The third layer of conductive structure 111 can protrude above the second layer of dielectric structure 112, or can include corresponding conductive paths 1111 having traces or vias. In some examples, one or more of such traces can include or be referred to as protruding traces 1115. Compared to the first layer of conductive structure 111, which is provided below and embedded in the dielectric structure 112, the third layer of conductive structure 111 is provided on the dielectric structure 112 and protrudes above the dielectric structure 112. In some examples, the conductive structure 111 can include a substrate bottom terminal 1113, which can be a portion or part of the conductive path 1111.

[0082] exist Figures 9A to 9H The steps described in the foregoing can produce a panel substrate 91 formed or provided on panel 48. In some examples, aspects of panel substrate 91 can be similar to corresponding aspects of other panel substrates described in this disclosure. Singulation can be performed to divide panel substrate 91 and panel 48 into different sub-panel substrates 91A and sub-panel bases 481A.

[0083] Figure 9I A cross-sectional view of a semiconductor device 70 is shown at a later stage of fabrication. Figure 9I In the example shown in , the sub-panel base 481A and the sub-panel substrate 91A are shown as being singulated from a previous stage, where the sub-panel substrate 91A is singulated from the panel substrate 41 or 41A. The sub-panel substrate 91A may include a conductive structure 111 and a dielectric structure 112. In some examples, the sub-panel base 481A and the sub-panel substrate 91A may be circular or strip-shaped. The external interconnect 12 may be attached to the sub-panel substrate 91A. In some examples, the external interconnect 12 may be connected to a substrate bottom terminal 1113 provided on the sub-panel substrate 91A. In some examples, the external interconnect 12 may be attached to the substrate bottom terminal 1113 prior to the singulation process.

[0084] In the manufacture of Figures 3A to 3G In the example method for manufacturing the example semiconductor device 10 shown in FIG, the electronic component 14 may be attached to the substrate first and the external interconnect 12 may be attached later. Figures 9A to 9S In the example method of the example semiconductor device 70 shown in FIG, however, the external interconnects 12 may be attached to the substrate first and the electronic components 14 may be attached later.

[0085] Figure 9J A cross-sectional view of a semiconductor device 70 is shown at a later stage of fabrication. Figure 9J In the example shown in FIG, a bottom encapsulant 77 can be provided on the subpanel substrate 91A. In some examples, the bottom encapsulant 77 can cover the dielectric structure 112, the conductive path 1111, or the substrate bottom terminal 1113 located on the subpanel substrate 91A.

[0086] In some examples, the bottom encapsulant 77 may also cover the sides of the external interconnect 12. In some examples, some areas of the external interconnect 12 may be exposed or protruded by the bottom encapsulant 77. The bottom encapsulant 77 may include or may be referred to as a molding compound resin, encapsulant, or organic host. In some examples, the bottom encapsulant 77 may be formed or provided by a compression molding process, a transfer molding process, a liquid phase encapsulant molding process, a vacuum lamination process, a solder paste printing process, or a film-assisted molding process. The thickness of the bottom encapsulant 77 may be less than or equal to the thickness of the external interconnect 12. The bottom encapsulant 77 may have a thickness in the range of about 1 μm to about 400 μm. The bottom encapsulant 77 may prevent the conductive structure 111 and the external interconnect 12 from being exposed to external components or the environment, may provide structural reinforcement for the connection between the external interconnect 12 and the substrate bottom terminal 1113, or may suppress substrate warping.

[0087] Figure 9K A cross-sectional view of a semiconductor device 70 is shown at a later stage of fabrication. Figure 9K , the subpanel base 481A can be removed. In some examples, the temporary adhesive 382 can be exposed. In some examples, when the subpanel base 481A is removed, the temporary adhesive 382 can also be removed. In some examples, the subpanel base 481A can be removed before the electronic components 14 are provided on the subpanel substrate 91A or the individual unit substrates 11.

[0088] Figure 9L A cross-sectional view of a semiconductor device 70 is shown at a later stage of fabrication. Figure 9L In the example shown in , temporary adhesive 382 can be removed from subpanel substrate 91 A. In some examples, seed layer 383 can be exposed.

[0089] Figure 9M A cross-sectional view of a semiconductor device 70 is shown at a later stage of fabrication. Figure 9MIn the example shown in FIG, seed layer 383 can be removed from subpanel substrate 91A. The first layer conductive structure 111, top terminal 1112, top embedded trace 1114, or first layer dielectric structure 112 of subpanel substrate 91A can be exposed. In some examples, the exposed sides of conductive structure 111, substrate top terminal 1112, top embedded trace 1114, and dielectric structure 112 can be coplanar with each other. Coplanar sides can provide excellent flow of underfill during subsequent stages, or provide excellent flow of encapsulant or subpanel body during subsequent stages.

[0090] Figure 9N A cross-sectional view of a semiconductor device 70 is shown at a later stage of fabrication. Figure 9N In the example shown in FIG, the subpanel substrate 91A can be singulated, for example, by a diamond wheel or a laser beam, to separate the unit substrates 11 with the corresponding external interconnects 12. In some examples, the singulation can make the sides of the dielectric structure 112 of the unit substrate 11 and the bottom encapsulant 77 coplanar with each other.

[0091] Figure 9O A cross-sectional view is shown at a later stage in the fabrication of a semiconductor device 70. Figure 9O In the example shown in , a support carrier 581 and an elastic film 582 may be provided. The elastic film 582 may include or may be referred to as a photosensitive polyimide (PSPI) tape film, a pressure-sensitive adhesive (PSA) tape film, or a double-sided adhesive. The thickness of the elastic film 582 may be equal to or greater than the external interconnect 12 protruding from the bottom encapsulant 77. The support carrier 581 may include or may be referred to as a metal substrate, a plastic substrate, a glass substrate, or a ceramic substrate. The support carrier 581 may support a plurality of unit substrates 11 in a later stage described below.

[0092] Figure 9P A cross-sectional view of a semiconductor device 70 is shown at a later stage of fabrication. Figure 9P In the example shown in , a pre-tested known good unit substrate 11 can be arranged on an elastic membrane 582 located on a support carrier 581, and the electronic components 14 can be electrically connected to the arranged unit substrates 11. In some examples, the external interconnects 12 of the unit substrates 11 are inserted into the elastic membrane 582, and the bottom encapsulant 77 of the unit substrates 11 can be in close contact with the elastic membrane 582. The device interconnects 142 of the electronic components 14 can be connected to the substrate top terminals 1112 of each unit substrate 11 by bonding tips or a material such as solder.

[0093] In some examples, underfill 16 may be located between electronic component 14 and unit substrate 11. In some examples, underfill may not be located between electronic component 14 and unit substrate 11. In some examples, a larger array of unit substrates 11 may be arranged on support carrier 581 and gaps may exist between each unit substrate 11.

[0094] Figure 9Q A cross-sectional view of a semiconductor device 70 is shown at a later stage of fabrication. Figure 9Q In the example shown in , the sub-panel body 75 can cover the unit substrate 11, the electronic component 14, or the bottom filler 16. In some examples, the sub-panel body 75 can be similar to the sub-panel body 25 described previously. In some examples, the sub-panel body 75 can cover the side of the unit substrate 11, or the side of the bottom encapsulant 77. The sub-panel body 75 can fill the gap between each unit substrate 11. In some examples, the top side of the sub-panel body 75 and the top side of the electronic component 14 can be substantially coplanar. In some examples, the top side of the electronic component 14 can be exposed through the top side of the sub-panel body 75. In some examples, the sub-panel body 75 can be provided on the sub-panel substrate 91A before singulation or partial singulation, or provided on the unit substrate 11 after singulation or partial singulation. The sub-panel body 75 can contact the side of the first electronic component 14 and the side of the second electronic component 14. In some examples, the sub panel body 75 may contact a side of the unit substrate 11 , or may contact a side of the bottom encapsulant 77 .

[0095] Figure 9R A cross-sectional view of a semiconductor device 70 is shown at a later stage of fabrication. Figure 9R In the example shown in FIG, singulation can be performed through the sub-panel body 75 along the gap between each unit substrate 11, thereby defining a unit body 75A. In some examples, the unit body 75A can be similar to the previously described unit body 15. After singulation, the unit body 75A can remain covering the side edges of the unit substrate 11 or the side edges of the bottom encapsulant 77.

[0096] Figure 9S A cross-sectional view of a semiconductor device 70 is shown at a later stage of fabrication. Figure 9S In the example shown in FIG, the elastic film 582 and the support carrier 581 can be removed from the semiconductor device 70. Therefore, the external interconnection 12 provided on the unit substrate 11 can be exposed to the completely independent semiconductor device 70.

[0097] Figure 10 A perspective view showing an example method for manufacturing a semiconductor device 70 and may correspond to the above Figures 9P to 9Q The view shown in . Figure 10In the example shown in FIG, one or more elastic films 582 can be arranged on a single support carrier 581, and a plurality of pre-singulated unit substrates 11 can be arranged on the one or more elastic films 582. In some examples, the plurality of pre-singulated unit substrates 11 can be arranged in an array having rows and columns. In some examples, the sub-panel body 75 can independently cover individual elastic films 582 located on the support carrier 581, or can completely cover all elastic films 582 located on the support carrier 581.

[0098] Figures 11A to 11C A cross-sectional view illustrating an example method for manufacturing an example semiconductor device 70. Figures 11A to 11C The instance method shown in can be similar to Figures 9A to 9S , but the sub-panel substrate 91A may be attached to an elastic film 582 located on a support carrier 581 and then partially cut to provide the unit substrate 11.

[0099] Figure 11A A cross-sectional view of a semiconductor device 70 is shown at a later stage of fabrication. In some examples, Figure 11A Can correspond to Figure 9M The next stage after that. Figure 11A In the example shown in , the sub-panel substrate 91A can be optionally singulated. The singulation can provide a sub-panel substrate 91A having an area smaller than the initial sub-panel substrate 91A. In some examples, the sub-panel substrate 91A provided by the singulation can also be in the form of a matrix or strip having rows and columns. In some examples, the sub-panel substrate 91A can include at least two unit substrates 11 that are still bonded.

[0100] Figure 11B A cross-sectional view of a semiconductor device 70 is shown at a later stage of fabrication. Figure 11B , the subpanel substrate 91A can be attached to the elastic membrane 582 located on the support carrier 581, and the electronic components 14 can be electrically connected to the subpanel substrate 91A. In some examples, the support carrier 581 can be provided on the second side or bottom side of the subpanel substrate 91A. In some examples, the support carrier 518 can be removed after singulation or after partially singulating the subpanel substrate 91A.

[0101] Figure 11C A cross-sectional view of a semiconductor device 70 is shown at a later stage of fabrication. Figure 11CIn the example shown in , a partial singulation process can be performed. In some examples, the sub-panel substrate 91A can be partially singulated to define a plurality of spaced-apart unit substrates 11 on the support carrier 581. The partial singulation can form a gap between each unit substrate 11. In some examples, the gap between each unit substrate 11 can be in the range of about 100 μm to about 1000 μm. After completing Figure 11C After the stages shown in , the same steps as above regarding Figures 9Q to 9S Stages similar to those shown and described are used to manufacture the semiconductor device 70. In some examples, the sub-panel body 75 ( Figure 9Q ) can be provided on the sub-panel substrate 91A before singulation or partial singulation, or can be provided on the unit substrate 11 after singulation or partial singulation. Figure 9Q As shown in , the sub-panel body 75 can contact the side of the first electronic component 14 and the side of the second electronic component 14. Figure 9S As shown in , the support carrier 581 can then be removed.

[0102] Figure 12 A perspective view showing an example method for manufacturing a semiconductor device 70 and may correspond to the above Figure 11B The view shown in . Figure 12 In the example shown in , one or more elastic membranes 582 can be attached to a single support carrier 581, and one or more sub-panel substrates 91A can be attached to the one or more elastic membranes 582. The sub-panel substrate 91A can be singulated into a plurality of unit substrates 11 later.

[0103] This disclosure includes references to certain examples. However, those skilled in the art will appreciate that various changes may be made and equivalents may be substituted without departing from the scope of this disclosure. Additionally, modifications may be made to the disclosed examples without departing from the scope of this disclosure. Therefore, it is intended that this disclosure not be limited to the disclosed examples, but rather that the disclosure encompass all examples within the scope of the appended claims.

Claims

1. A method, characterized in that include: providing a sub-panel substrate on a sub-panel base, the sub-panel substrate comprising a dielectric structure and a conductive structure, wherein the sub-panel substrate comprises a singulated portion of a panel substrate, wherein the panel substrate comprises a plurality of sub-panel substrates, and wherein the sub-panel substrate comprises a plurality of individual unit substrates; supply: a first electronic component on a first side of the subpanel substrate and electrically coupled to a first portion of the conductive structure, and a second electronic component on the first side of the subpanel substrate and electrically coupled to a second portion of the conductive structure; removing the sub-panel base; supply: a first external interconnect on a second side of the subpanel substrate and electrically coupled to the first portion of the conductive structure, and a second external interconnect on the second side of the subpanel substrate and electrically coupled to the second portion of the conductive structure; as well as singulating the sub-panel substrate to provide the individual unit substrates; wherein the sub-panel base is removed after providing the first electronic component and the second electronic component and before providing the first external interconnect and the second external interconnect; and Wherein, before providing the first electronic component and the second electronic component and before singulating the sub-panel substrate into the individual unit substrates by a second singulation operation, the panel substrate is singulated into the singulated portions of the panel substrate by a first singulation operation.

2. The method according to claim 1, characterized in that Further including: A sub-panel body is provided on a top side of the sub-panel substrate, the sub-panel body contacting a side edge of the first electronic component and a side edge of the second electronic component.

3. The method according to claim 1, characterized in that Further including: providing a first metal cover on a top side of the subpanel substrate over the first electronic component and electrically coupled to the first portion of the conductive structure; and a second metal cover on the top side of the subpanel substrate over the second electronic component and electrically coupled to the second portion of the conductive structure.

4. The method according to claim 1, characterized in that Further including: providing a first cover on a top side of the subpanel substrate above the first electronic component; and a second cover on the top side of the subpanel substrate over the second electronic component, wherein the first cover comprises a dielectric material.

5. The method according to claim 1, characterized in that The subpanel substrate has a strip array form factor.

6. The method according to claim 1, characterized in that The subpanel mount is secured to the second side of the subpanel substrate via an adhesive.

7. The method according to claim 6, characterized in that Further comprising removing the sub-panel base prior to providing the first external interconnect and the second external interconnect.

8. The method according to claim 1, characterized in that: Further including: providing a support carrier on the second side of the subpanel substrate; providing a sub-panel body on the individual unit substrates and on the support carrier, the sub-panel body contacting sides of the first electronic component and the second electronic component; as well as The support carrier is removed.

9. The method according to claim 8, characterized in that The sub-panel body contacts a side surface of the individual unit substrate.

10. The method according to claim 8, characterized in that The first electronic component or the second electronic component is exposed through the sub-panel body.

11. The method according to claim 8, characterized in that The sub-panel substrate includes a bottom encapsulant on a bottom side of the sub-panel substrate, and the bottom encapsulant contacts a side edge of the first external interconnect.

12. The method according to claim 8, characterized in that The support carrier is removed after the sub-panel substrate is singulated.

13. The method according to claim 1, characterized in that The sub-panel base is removed before providing the first electronic component and the second electronic component on the first side of the individual unit substrate.

14. A method, characterized in that include: A first sub-panel substrate is received on the first sub-panel base, wherein the first sub-panel substrate comprises a portion of a panel substrate, the first sub-panel substrate comprising: Subpanel dielectric structure; a sub-panel conductive structure, the sub-panel conductive structure coupled to the sub-panel dielectric structure; A first unit substrate, the first unit substrate comprising: a first unit conductive structure, the first unit conductive structure comprising a first portion of the sub-panel conductive structure; and a first unit dielectric structure, the first unit dielectric structure comprising a first portion of the sub-panel dielectric structure; A second unit substrate, the second unit substrate being electrically coupled to the first unit substrate and comprising: a second unit conductive structure, the second unit conductive structure comprising a second portion of the sub-panel conductive structure; and a second unit dielectric structure, the second unit dielectric structure comprising a second portion of the sub-panel dielectric structure; coupling a first electronic component to the first unit substrate; coupling a second electronic component to the second unit substrate; and Singulating a semiconductor device from the first sub-panel substrate, the semiconductor device comprising: a first semiconductor device including the first unit substrate and the first electronic component; and a second semiconductor device including the second unit substrate and the second electronic component; Before coupling the first electronic component and the second electronic component and before singulating the semiconductor device from the first sub-panel substrate by a second singulation operation, the panel substrate is singulated into the first sub-panel substrate by a first singulation operation.

15. The method according to claim 14, characterized in that include: Before singulation, removing the first sub-panel base; in: the temporary adhesive between the first subpanel base and the first subpanel substrate is light releasable; as well as Removing the first sub-panel mount includes reducing adhesion of the temporary adhesive by exposure to light.

16. The method according to claim 14, characterized in that include: receiving a panel substrate on a panel base, The panel base comprises: the first sub-panel base; and a second sub-panel base, the second sub-panel base being integrated with the first sub-panel base; The panel substrate comprises: the first sub-panel substrate on the first sub-panel base; and a second sub-panel substrate on the second sub-panel base and electrically coupled to the first sub-panel substrate; And before coupling the first electronic component: The first sub-panel chassis and the first sub-panel substrate are singulated from the panel chassis and the panel substrate.

17. The method according to claim 16, characterized in that: The first sub-panel substrate comprises a chip form factor; and The panel substrate comprises a rectangular area having a side dimension of at least 400 mm.

18. The method according to claim 14, characterized in that: The first subpanel substrate comprises a ribbon array form factor; and The panel substrate comprises a rectangular area having a side dimension of at least 400 mm.

19. A semiconductor device, characterized in that: include: A unit substrate, the unit substrate comprising a unit conductive structure and a unit dielectric structure; as well as an electronic component coupled to the unit conductive structure; Wherein the unit substrate comprises a portion of a singulated sub-panel substrate of a panel substrate, wherein the panel substrate comprises a plurality of sub-panel substrates, and wherein the plurality of sub-panel substrates comprises a plurality of unit substrates.

20. The semiconductor device according to claim 19, wherein: Further comprising singulating the subpanel substrate, wherein: The singulated sub-panel substrate includes a sub-panel conductive structure; and The sub-panel conductive structure includes the unit conductive structure.

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