A Triple-Gate SiC JFET Lateral Device

Abstract

The present invention provides a three-gate SiC JFET lateral device, comprising a body electrode, an epitaxial layer, a channel region, a source, a drain, two first side gates and a top gate from bottom to top in a vertical direction; the top of each first side gate is connected to the top gate, the two first side gates and the top gate form an inverted U-shaped gate metal structure, the bottom of each first side gate is connected to the epitaxial layer, and a gate electrode is formed at the top gate; the top gate and the first side gate are both in direct contact with the channel region to form a pn junction; the source and the drain are both connected to the epitaxial layer and are both connected to the channel region; under a relatively low gate voltage, there is a sufficiently low specific contact resistance, and under the condition of low operating frequency application, the driving power consumption can be greatly reduced.

Description

[Technical field]

[0001] The present invention relates to a triple-gate SiC JFET lateral device. [Background technology]

[0002] Silicon carbide materials of SiC devices have attracted extensive attention and research due to their superior physical properties. Their high-temperature and high-power electronic devices have the advantages of high input impedance, fast switching speed, high operating frequency, high temperature and high pressure resistance, etc., and have been widely used in switching power supplies, high-frequency heating, automotive electronics, and power amplifiers.

[0003] However, it still has technical and economic problems such as high threshold voltage, high driving voltage at saturation current, many material defects, low channel mobility, and high cost, which seriously restrict the development of SiC devices. [Summary of the invention]

[0004] The technical problem to be solved by the present invention is to provide a three-gate SiC JFET lateral device, which has a sufficiently low specific contact resistance under low gate voltage conditions and can significantly reduce driving power consumption under low operating frequency applications.

[0005] The present invention is implemented as follows: a three-gate SiC JFET lateral device includes a body electrode, an epitaxial layer, a channel region, a source electrode, a drain electrode, two first side gates and a top gate vertically from bottom to top;

[0006] The top of each first side gate is connected to the top gate, the two first side gates and the top gate form an inverted U-shaped gate metal structure, the bottom of each first side gate is connected to the epitaxial layer, and a gate electrode is formed at the top gate; the top gate and the first side gate are directly in contact with the channel region to form a pn junction;

[0007] The source and the drain are both connected to the epitaxial layer and are also connected to the channel region.

[0008] Furthermore, it includes at least one second side gate, the top of the second side gate is connected to the top gate, the bottom of the second side gate is connected to the epitaxial layer, and the second side gate is evenly spaced between the two first side gates; the second side gate divides the channel region.

[0009] Furthermore, the body electrode is heavily doped with P type.

[0010] Furthermore, the epitaxial layer is lightly doped with P type.

[0011] Furthermore, the channel region is lightly N-type doped.

[0012] Furthermore, the drain is lightly N-type doped.

[0013] Furthermore, the source electrode is lightly N-type doped.

[0014] Furthermore, the top gate is heavily P-type doped.

[0015] The advantages of the present invention are:

[0016] It has three connected gate structures, including a planar gate and two trench gates, and the three gates wrap the conductive channel from three directions; the three gates are all heavily doped P-type, forming PN junctions with the lightly doped N-type channel region from three directions, so that the SiC lateral JFET device can form a space charge region under a negative pressure with a small absolute value, thereby pinching off the conductive channel; when a positive voltage is applied to the three connected gate structures, since the three-gate structure surrounds the channel region from three directions, more carriers can be generated when a smaller positive voltage is applied, so that a sufficiently low specific contact resistance can be achieved under a lower gate voltage, and in low operating frequency applications, the driving power consumption can be greatly reduced.

Brief Description of the Drawings

[0017] The present invention will be further described below in conjunction with embodiments with reference to the accompanying drawings.

[0018] Figure 1 A top view of a three-gate SiC lateral JFET device provided by an embodiment of the present invention;

[0019] Figure 2 A side center cross-sectional view of a three-gate SiC lateral JFET device provided by an embodiment of the present invention;

[0020] Figure 3 A front view of a three-gate SiC lateral JFET device provided by an embodiment of the present invention;

[0021] Figure 4 The invention provides a multi-gate application of a three-gate SiC lateral JFET device. [Specific implementation method]

[0022] The embodiment of the present invention solves the technical problems of high threshold voltage, high driving voltage at saturation current, low channel mobility and high cost in the prior art by providing a three-gate SiC JFET lateral device, and achieves a technical effect of having a sufficiently low specific contact resistance under low gate voltage conditions and significantly reducing driving power consumption under low operating frequency applications.

[0023] See also Figures 1 to 3 As shown, a three-gate SiC JFET lateral device of the present invention includes a body electrode, an epitaxial layer, a channel region, a source electrode, a drain electrode, two first side gates and a top gate vertically from bottom to top;

[0024] The top of each first side gate is connected to the top gate, the two first side gates and the top gate form an inverted U-shaped gate metal structure, the bottom of each first side gate is connected to the epitaxial layer, and a gate electrode is formed at the top gate; the top gate and the first side gate are directly in contact with the channel region to form a pn junction;

[0025] The source and drain are both connected to the epitaxial layer and to the channel region, the body electrode is heavily doped with P type, the epitaxial layer is lightly doped with P type, the channel region is lightly doped with N type, the drain is lightly doped with N type, the source is lightly doped with N type, and the top gate is heavily doped with P type.

[0026] like Figure 4 As shown, in another embodiment of the present invention, at least one second side gate is further included, the top of the second side gate is connected to the top gate, the bottom of the second side gate is connected to the epitaxial layer, and the second side gate is evenly spaced between the two first side gates; the second side gate divides the channel region. The provided three-gate SiC lateral JFET device has a multi-gate application, in which the multi-gate structure can continue to increase the number of second side gates, further reduce the threshold voltage, and improve the current carrying capacity. A multi-channel structure is formed to increase the carrier density of the conductive channel and reduce the on-resistance.

[0027] A SiC lateral JFET device with a top gate and two first side gates has a source and a drain that are symmetrical to each other when viewed from the forward middle section. The top gate is at the top of the entire device, and the channel region is below the top gate. The left and right sides of the channel region are interchangeable source and drain electrodes, and the source and drain electrodes are symmetrically positioned.

[0028] The two first side gates of the three-gate SiC lateral JFET device are symmetrical to each other when viewed from the middle side section. The top of the entire device is the top gate, the channel region is directly below the top gate, and the left and right sides of the channel region are symmetrically positioned side gates.

[0029] The conductive channel region of the three-gate SiC lateral JFET device is surrounded by a top gate and two first side gates, and through the form of a pn junction, a space charge region is formed in the channel region when a negative voltage is applied to pinch off the conductive channel. Because the entire channel region is surrounded by a top gate and two first side gates from three directions, the conductive channel can be pinched off under a relatively small negative voltage. Compared with the traditional SiC lateral JFET, the absolute value of the negative off-end voltage can be reduced, thereby reducing the driving power consumption.

[0030] The conductive channel of the three-gate SiC lateral JFET device is surrounded by three gates, and through the form of pn junction, the carrier concentration in the N-type channel region is increased in the channel region when a positive voltage is applied, so that the JFET on-resistance is reduced. Because the entire channel region is surrounded by a top gate and two first side gates from three directions, the carrier concentration can be rapidly increased under a smaller positive voltage. Compared with the traditional SiC lateral JFET, the positive driving voltage can be reduced to achieve a lower on-resistance, thereby reducing the driving power consumption.

[0031] Tri-gate SiC lateral JFET devices are used in SiC power devices and SiC power integrated circuits.

[0032] Although the specific implementation modes of the present invention are described above, those skilled in the art should understand that the specific implementation modes described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A three-gate SiC JFET lateral device, characterized in that: It includes a body electrode, an epitaxial layer, a channel region, a source electrode, a drain electrode, two first side gates and a top gate vertically from bottom to top; The top of each of the first side gates is connected to the top gate, the two first side gates and the top gate form an inverted U-shaped gate metal structure, the bottom of each of the first side gates is connected to the epitaxial layer, and a gate electrode is formed at the top gate; the top gate and the first side gates are directly in contact with the channel region to form a pn junction; The source and the drain are both connected to the epitaxial layer and are also connected to the channel region.

2. A three-gate SiC JFET lateral device according to claim 1, characterized in that: It also includes at least one second side gate, the top of the second side gate is connected to the top gate, the bottom of the second side gate is connected to the epitaxial layer, and the second side gate is evenly spaced between the two first side gates; the second side gate divides the channel region.

3. A three-gate SiC JFET lateral device according to claim 1, characterized in that: The body electrode is heavily doped with P type.

4. A three-gate SiC JFET lateral device according to claim 1, characterized in that: The epitaxial layer is lightly doped with P type.

5. A three-gate SiC JFET lateral device according to claim 1, characterized in that: The channel region is lightly N-type doped.

6. A three-gate SiC JFET lateral device according to claim 1, characterized in that: The drain is lightly N-type doped.

7. A tri-gate SiC JFET lateral device according to claim 1, characterized in that: The source electrode is lightly doped with N type.

8. A three-gate SiC JFET lateral device according to claim 1, characterized in that: The top gate is heavily doped with P type.

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