Apparatus including an input buffer and method of operating the input buffer

Abstract

Apparatus including an input buffer and a method for operating the input buffer are described. An exemplary input buffer includes a plurality of input buffer circuits, each input buffer circuit receiving input data and being activated by a respective clock signal. The input buffer circuit includes a decision feedback equalizer (DFE) having an adjustable capacitor and a reference capacitor to set a reference level of the input buffer circuit. The capacitance of the adjustable capacitor can be set by code. The DFE provides the capacitance of the adjustable capacitor to a first sensing node and further provides the capacitance of the reference capacitor to a second sensing node to set the reference level of the input buffer circuit. The input buffer circuit provides output data based on the input data and the reference level set by the DFE.

Description

BACKGROUND OF THE INVENTION

[0001] Current low-power double data rate random access memories (RAMs) are expected to support data rates exceeding 4266 Mbps using a 2133 MHz clock frequency. The design of the input data latch is important for achieving this performance level. Challenges include relatively low power levels and extremely small input signal energy. Inter-symbol interference (ISI) caused by lossy routing, reflections caused by characteristic impedance discontinuities, crosstalk between parallel signal lines, and clock jitter all degrade the input signal to the extent that the input data latch should resolve pulses of less than 80 ps at 50 mV.

[0002] Conventional sense amplifier latches have difficulty operating under these conditions and exhibit relatively poor rank margin tool (RMT) margins. The selection for the input data latch is to use a decision feedback equalizer (DFE). In a typical DFE implementation, past sensing decisions are used to improve the reliability of future sensing decisions by offsetting the input signal or a reference voltage compared to the input signal.

[0003] However, the offset provided by the DFE may be too coarse and provides an undesirably large offset, and it cannot be scaled to provide a desired offset. SUMMARY OF THE INVENTION

[0004] Apparatus including an input buffer and a method for operating the input buffer are described. In one aspect of the present disclosure, an exemplary apparatus includes an external data terminal and an input buffer, with input data provided on the external data terminal. The input buffer includes a plurality of input buffer circuits coupled to the external data terminal. Each input buffer circuit includes a sensing circuit, a decision feedback equalizer, and a latching circuit. The sensing circuit is configured to compare a voltage of the input data with a reference voltage and provide a first voltage and a second voltage to a first node and a second node. The decision feedback equalizer is coupled to the first sensing node and the second sensing node and is configured to set a reference level of the input buffer. The decision feedback equalizer includes a first tunable capacitor and a second tunable capacitor respectively coupled to the first sensing node and the second sensing node, and further includes a first reference capacitor and a second reference capacitor respectively coupled to the first sensing node and the second sensing node. The sensing circuit is further configured to provide a sensing output based on the reference level and the comparison of the voltage of the input data with the reference voltage. The latching circuit is coupled to the first sensing node and the second sensing node and is configured to latch and provide output data having a logic level based on the voltage of the sensing output.

[0005] In another aspect of the present disclosure, an exemplary input buffer includes a sensing circuit, a latching circuit, and a decision feedback equalizer. The sensing circuit is configured to compare a voltage of input data with a reference voltage and provide a first voltage and a second voltage to a first node and a second node, respectively, based on the comparison. The latching circuit is coupled to the sensing circuit and is configured to latch and provide output data having a logic level based on a voltage of a sensing output provided by the sensing circuit. The decision feedback equalizer is coupled to the first sensing node and the second sensing node and is configured to provide a first capacitance to the first sensing node and a second capacitance to the second sensing node simultaneously to set a reference level of the input buffer circuit. The sensing output provided by the sensing circuit is based on the first voltage, the second voltage, and the reference level.

[0006] In another aspect of the present disclosure, an exemplary method includes activating an input buffer circuit to receive input data, comparing a voltage of the input data with a reference voltage, and providing voltages to a first node and a second node based thereon. A first capacitance is provided to one of the first node or the second node, and a second capacitance is provided to the other node simultaneously to set a reference level of the input buffer. The exemplary method further includes providing a sensing output based on the reference level and a comparison of the voltage of the input data with the reference voltage, and latching and providing output data based on the voltage of the sensing output. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram of a semiconductor device according to an embodiment of the present disclosure.

[0008] Figure 2 is a block diagram of an input buffer according to an embodiment of the present disclosure.

[0009] Figure 3 is a timing diagram of various clocks and voltages during operation of an input buffer according to an embodiment of the present disclosure.

[0010] Figure 4 is a schematic diagram of an input buffer circuit 400 according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0011] Various embodiments of the present disclosure will be explained in detail below with reference to the drawings. The following detailed description refers to the drawings which illustrate specific aspects and embodiments of the present disclosure by way of illustration. The detailed description includes sufficient details for those skilled in the art to practice the embodiments of the present disclosure. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present disclosure. The various embodiments disclosed herein are not necessarily mutually exclusive, as some disclosed embodiments may be combined with one or more other disclosed embodiments to form new embodiments.

[0012] Figure 1 It is a block diagram of a semiconductor device 100 according to an embodiment of the present disclosure. The semiconductor device 100 may include a memory cell array 145, and the memory cell array includes a plurality of banks 0-N. Each bank 0-N includes a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC arranged at the intersections of the plurality of word lines WL and the plurality of bit lines BL. The selection of the word lines WL of each bank is performed by the corresponding row decoder 130, and the selection of the bit lines BL is performed by the corresponding column decoder 140. A plurality of sense amplifiers 150 are provided for their corresponding bit lines BL and are coupled to at least one corresponding local I / O line LIOT / B. The local I / O line LIOT / B is further coupled to a corresponding one of at least two main I / O line pairs via a transmission gate TG 195 serving as a switch.

[0013] The address / command input circuit 115 may receive an address signal and a bank address signal from the outside (e.g., via a memory controller) at the command / address terminal via the command / address bus 110, and may transmit the address signal and the bank address signal to the address decoder 120. The address decoder 120 may decode the address signal received from the address / command input circuit 115, and provide a row address signal XADD to the row decoder 130, and a column address signal YADD to the column decoder 140. The address decoder 120 may also receive the bank address signal, and provide the bank address signal BADD to the row decoder 130 and the column decoder 140.

[0014] The address / command input circuit 115 may also receive a command signal and a chip select signal from the outside at the command / address terminal via the command / address bus 110, and may provide the command signal and the chip select signal to the command decoder 125. The command signal may include various memory commands, such as activate, read, write, and other commands. The chip select signal selects the semiconductor device 100 to respond to the commands and addresses provided to the command and address terminals. The command decoder 125 may decode the command signal to generate various internal command signals. For example, the internal command signals may include a row command signal for selecting a word line and a column command signal for selecting a bit line.

[0015] When an activation command is issued with a row address and a column address is provided in a timely manner with a read command, read data is read from a memory cell in the memory cell array 145 specified by the row address and the column address. The read command may be received by a command decoder 125. A read / write amplifier of a serializer / deserializer (SERDES) circuit 165 may receive the read data and provide the read data to an input / output (I / O) circuit 160. The I / O circuit 160 may provide the read data to the outside via data terminals DQ and DM. Similarly, when an activation command is issued with a row address and a column address is provided in a timely manner with a write command, an input buffer of the I / O circuit 160 may receive write data and a data mask DM signal at the data terminal DQ. The I / O circuit 160 provides the write data to the memory cell array 145 via the read / write amplifier of the SERDES circuit 165. Thus, the write data can be written into the memory cell specified by the row address and the column address.

[0016] Power supply terminals may receive power supply voltages VDD1, VDD2, and VSS. These power supply voltages VDD1, VDD2, and VSS may be supplied to a voltage generator circuit 190. The voltage generator circuit 190 may generate various internal voltages VPP, VOD, VARY, VPERI, VIB, etc. based on the power supply voltages VDD1, VDD2, and VSS. For example, the internal voltage VIB may be generated using the VDD1 voltage. The internal voltage VIB may have an amplitude greater than the power supply voltage VDD2. The internal voltage VPP is mainly used for a row decoder 130 and a column decoder 140. The internal voltages VOD and VARY are mainly used for sense amplifiers 150 included in the memory cell array 145. The internal voltage VIB (together with the power supply voltage VDD2) is used for a data clock (WCK) input circuit 105 and a frequency division and buffer circuit 107. The internal voltage VPERI is used for many other circuit modules. The I / O circuit 160 may receive power supply voltages VDDQ and VSSQ. For example, the power supply voltages VDDQ and VSSQ may be the same voltages as the power supply voltages VDD2 and VSS, respectively. However, dedicated power supply voltages VDDQ and VSSQ may be used for the I / O circuit 160.

[0017] Clock terminals WCK_T and WCK_N may receive an external clock signal WCK_T and a complementary external clock signal WCK_N, respectively. The WCK_T clock signal and the WCK_N clock signal may be supplied to a WCK input circuit 105. The WCK input circuit 105 may generate complementary internal clock signals T and an internal clock signal N based on the WCK_T clock signal and the WCK_N clock signal. The WCK input circuit 105 may provide the T clock signal and the N clock signal to a frequency division and buffer circuit 107. The frequency division and buffer circuit 107 may be based on the T clock signal and the N clock signal and a clock enable signal CKE( Figure 1(not shown in the figure) generates phase- and frequency-controlled internal clock signals PH0 - PH3. In some embodiments of the present disclosure, the PH0 - PH3 clock signals may be phase-shifted 90 degrees relative to each other. For example, the PH0 clock signal is phase-shifted 0 degrees relative to the internal clock signal T, the PH1 clock signal is phase-shifted 90 degrees relative to the internal clock signal T, the PH2 clock signal is phase-shifted 180 degrees relative to the internal clock signal T, and the PH3 clock signal is phase-shifted 270 degrees relative to the internal clock signal T.

[0018] The frequency division and buffering circuit 107 may supply the PH0 - PH3 clock signals to the SERDES circuit 165 and the I / O circuit 160. The SERDES circuit 165 may support read and write operations by deserializing write data and serializing high-speed read data. For example, during a write operation, the SERDES circuit 165 may be configured to receive serialized write data from the I / O circuit 160, deserialize the serialized write data (e.g., make it parallel) to provide deserialized write data, and may supply the deserialized write data to the memory cell array 145. Additionally, deserialized read data may be received from the memory cell array 145, and the SERDES circuit 165 may be configured to serialize the deserialized read data to provide serialized read data, and may supply the serialized read data to the I / O circuit 160.

[0019] Figure 2 is a block diagram of the input buffer 200 according to an embodiment of the present disclosure. In some embodiments of the present disclosure, the input buffer 200 may be included in the Figure 1 input / output circuit 160.

[0020] The input buffer 200 receives data serially provided to the external data terminal DQ and latches the data bit by bit within one or more clock cycles of the multi-phase clock signals PH0 - PH3. The input buffer 200 includes input buffer circuits 210(0) - 210(3), which are coupled to the external data terminal DQ and to a reference voltage supply line on which a data reference voltage VrefDQ is provided. In some embodiments of the present disclosure, each external data terminal DQn of the semiconductor device (e.g., Figure 1 the semiconductor device 100) may have a corresponding input buffer, such as the input buffer 200.

[0021] Each of input buffer circuits 210(0)-210(3) is provided with a respective one of the multi-phase clock signals. For example, input buffer circuit 210(0) is provided with clock PH0, input buffer circuit 210(1) is provided with clock PH1, input buffer circuit 210(2) is provided with clock PH2, and input buffer circuit 210(3) is provided with clock PH3. Each of the multi-phase clock signals PH0-PH3 can have a different phase from each other. For example, in some embodiments of the present disclosure, the multi-phase clock signals PH0-PH3 have a 90-degree phase with respect to each other (e.g., "orthogonal" clock signals). The PH0 clock can have a 0-degree phase, the PH1 clock can have a 90-degree phase, the PH2 clock can have a 180-degree phase, and the PH3 clock can have a 270-degree phase. Other embodiments of the present disclosure can have multi-phase clock signals with other relationships to each other.

[0022] Input buffer circuit 210(0) includes a sensing circuit 220(0) coupled to an external data terminal DQ and a VrefDQ voltage supply line. The sensing circuit 220(0) includes an activation circuit provided with the respective multi-phase clock PH0. When activated by the PH0 clock (e.g., a high clock level), the input circuit of the sensing circuit 220(0) senses the voltage difference between the voltage at the external data terminal DQ and the VrefDQ voltage of the voltage supply line, and provides corresponding voltages to a sense node CN and a sense node CT based on the voltage difference between the DQ voltage and the VrefDQ voltage. For example, the input circuit compares the voltage at the external data terminal DQ with the VrefDQ voltage and provides voltages to the CN node and the CT node based on this comparison. The output circuit of the sensing circuit 220(0) provides a sensing output to a latch circuit 230(0), and the sensing output is based on the voltages of the CN node and the CT node and a reference level (the transition point level of the input buffer circuit 210) set by a decision feedback equalizer (DFE) circuit 240(0) coupled to the CN node and the CT node. The latch circuit 230(0) latches and provides output data DPH0 and output data DPH0B having a logic level based on the sensing output. The output data DPH0 and the output data DPH0B can be complementary. That is, one of the output data DPH0 and the output data DPH0B can have a first logic level (e.g., a "0" logic level) and the other output data will have a second logic level opposite to the first logic level (e.g., a "1" logic level), and vice versa.

[0023] Output data DPH(n-1) and output data DPH(n-1)B are provided from another input buffer circuit 210 to the DFE circuit 240(0). The DFE circuit 240(0) may set a reference level of the sensing circuit 220(0) based on the output data DPH(n-1) and the output data DPH(n-1)B from the other input buffer circuit 210. For example, the DFE circuit 240(0) may set the reference level by changing (e.g., shifting) the reference level from a first reference level to a second reference level, and vice versa. The DFE circuit 240(0) may also set the reference level by maintaining the reference level from a previous reference level. The reference level set by the DFE circuit 240(0) may be relative to a reference voltage VrefDQ (e.g., higher than the reference voltage VrefDQ or lower than the reference voltage VrefDQ). In some embodiments of the present disclosure, the DFE circuit 240(0) may provide capacitances to the sensing node CN and the sensing node CT to set the reference level to improve sensing accuracy of data at the external data terminal DQ. The capacitances provided by the DFE circuit to the sensing node CN and the sensing node CT may be based on the output data DPH(n-1) and the output data DPH(n-1)B from the other sensing circuit 220.

[0024] The input buffer circuits 210(1)-210(3) are similar to the input buffer circuit 210(0), and the description of the input buffer circuit 210(0) applies correspondingly to the input buffer circuits 210(1)-210(3).

[0025] In operation, as described above, the DFE circuit 240(0) sets a reference level (e.g., a high reference level or a low reference level) based on the output data DPH(n-1) and the output data DPH(n-1)B from another sense amplifier. For example, when the output data DPH(n-1) is a high logic level (e.g., a high logic level voltage) and the output data DPH(n-1)B is a low logic level (e.g., a low logic level voltage), the DFE circuit 240(0) may effectively increase the reference level of the input buffer circuit 210(0) relative to the VrefDQ voltage. Conversely, when the output data DPH(n-1) is a low logic level and the output data DPH(n-1)B is a high logic level, the DFE circuit 240(0) may reduce the voltage of the reference level of the input buffer circuit 210(0) relative to the VrefDQ voltage. Therefore, the DFE circuit 240(0) sets the reference level of the input buffer circuit 210(0) based on the output data DPH(n-1) and the output data DPH(n-1)B from the other input buffer circuit 210.

[0026] The activated PH0 clock activates the input circuit of the sensing circuit 220(0) to compare the voltage at the external node DQ with the VrefDQ voltage. Based on this comparison (e.g., the voltage difference), the input circuit provides voltages to the sensing node CN and the sensing node CT. The sensing node CN and the sensing node CT each generate corresponding voltages affected by the DFE circuit 240(0). The output circuit provides a sensing output to the latch circuit 230(0) based on the voltages at the CN node and the CT node. The latch circuit 230(0) latches and provides output data DPH0 and output data DPH0B with corresponding logic levels based on the sensing output. The latch circuit 230(0) provides output data DPH0 and output data DPH0B, one with the latched logic level and the other with the complementary logic level. The sensing circuit 220(0) becomes deactivated with the non-activated PH0 clock, and the sensing node CN and the sensing node CT can be changed, and the output of the input buffer circuit 210(0) can be changed to the corresponding initial voltage to prepare for the next activation (e.g., pre-charge the input buffer circuit 210(0)). The sensing circuit 220(0) remains deactivated until the next activated PH0 clock.

[0027] As described above, each input buffer circuit 210(0)-210(3) receives corresponding clock signals that have different phases from the clock signals provided to the other input buffer circuits 210. As a result, the sensing circuits 220(0)-220(3) are activated by the PH0-PH3 clocks at different phases.

[0028] Figure 3 is a timing diagram of various clock signals and voltages during the operation of multiple input buffers according to an embodiment of the present disclosure. Figure 3 The exemplary operation of shows multiple bits input to the input buffer (e.g., the leading bits D(-2) and D(-1), and the data bits D0-D8). In some embodiments of the present disclosure, Figure 3 The timing diagram of can show including in Figure 1 the input / output circuit 160 of and / or Figure 2 the operation of the input buffers in the input buffer circuits 210(0)-210(3) of.

[0029] Figure 3 shows the clock signals WCK_t and WCK_c, and further shows the multi-phase clock signals PH0, PH1, PH2, and PH3. In Figure 3In an exemplary operation, the multi-phase clock signals PH0 - PH3 have a lower clock frequency than the WCK_t clock signal and the WCK_c clock signal, and have different phases from each other. For example, the multi-phase clock signals PH0 - PH3 have half of the clock frequency of the WCK_t clock signal and the WCK_c clock signal, and the multi-phase clock signals PH0 - PH3 have a 90-degree phase relative to each other (e.g., PH0 = 0 degrees, PH1 = 90 degrees, PH2 = 180 degrees, and PH3 = 270 degrees).

[0030] The data reference voltage VrefDQ and the voltage of the external data terminal DQ are also as Figure 3 shown. The high reference level up and the low reference level down of the input buffer are also as Figure 3 shown. As will be described, the reference level of the input buffer circuit is set to the high reference level up or the low reference level down by the corresponding DFE circuit of the input buffer.

[0031] The exemplary operation of the reference input buffer circuits 210(0) - 210(3) will be described Figure 3 herein.

[0032] Before time T0R, the external data terminal DQ has the same voltage for two data unit intervals (UI). Figure 3 Each UI in the exemplary operation is half of the clock period of the WCK_t clock signal and the WCK_c clock signal. Referring to the voltage of the external data terminal DQ of UI(-1), at the rising edge and the high clock level of the PH3 clock after time T0R, the sensing circuit 220(3) of the input buffer circuit 210(3) is activated to sense the low voltage relative to the VrefDQ voltage. The sensing circuit 220(3) provides a sensing output based on the relatively low voltage of the external data terminal DQ and the reference level set for the input buffer circuit 210(3), which causes the latch circuit 230(3) to latch the low logic level for the data D(-1), provide the low logic level voltage for DPH3, and provide the high logic level voltage for DPH3B.

[0033] The low logic level of DPH3 and the high logic level of DPH3B are provided to the DFE circuit 240(0) of the input buffer circuit 210(0). The DFE circuit 240(0) sets the reference level of the input buffer circuit 210(0) based on the logic levels of DPH3 and DPH3B. For example, in Figure 3 the exemplary operation, based on the low logic level of DPH3 and the high logic level of DPH3B, the DFE circuit 240(0) sets the reference level of the input buffer circuit 210(0) to the low reference level down.

[0034] After the low logic level of the latched data D(-1), the voltage of the external data terminal DQ becomes the higher voltage of UI0. The rising edge of the PH0 clock appears at the time tWCK2DQI after the clock edge of the WCK_t clock at time T0R. The time tWCK2DQI can be the timing specification of the rising edge of the multi-phase clock signal after the corresponding clock edge (e.g., rising edge or falling edge) of the WCK_t clock. More specifically, the time tWCK2DQI is Figure 1 the propagation delay time from WCK_T / WCK_N to PH0 - PH3 in Figure 1 . The rising edge and high clock level of the PH0 clock activate the sensing circuit 220(0) of the input buffer circuit 210(0) to sense a larger voltage downward relative to the low reference level set by the DFE circuit 240(0). The sensing circuit 220(0) provides a sensing output based on the relatively high voltage of the external data terminal DQ and the reference level set for the input buffer circuit 210(0). As a result, the latching circuit 230(0) latches the high logic level of the data D0, provides a high logic level voltage for DPH0, and provides a low logic level voltage for DPH0B.

[0035] The high logic level of DPH0 and the low logic level of DPH0B are provided to the DFE circuit 240(1) of the input buffer circuit 210(1). The DFE circuit 240(1) sets the reference level of the input buffer circuit 210(1) based on the logic levels of DPH0 and DPH0B. For example, based on the high logic level of DPH0 and the low logic level of DPH0B, the DFE circuit 240(1) sets the reference level of the input buffer circuit 210(1) to be upward at a high reference level.

[0036] After the high logic level of the latched data D(0), the voltage of the external data terminal DQ becomes the lower voltage of UI1. The rising edge of the PH1 clock appears at the time tWCK2DQI after the clock edge of the WCK_t clock at time T0F. The rising edge and high clock level of the PH1 clock activate the sensing circuit 220(1) of the input buffer circuit 210(1) to sense a lower voltage upward relative to the high reference level set by the DFE circuit 240(1). The sensing circuit 220(1) provides a sensing output based on the relatively low voltage of the external data terminal DQ and the reference level set for the input buffer circuit 210(1). As a result, the latching circuit 230(1) latches the low logic level of the data D1, provides a low logic level voltage for DPH1, and provides a high logic level voltage for DPH1B.

[0037] The low logic level of DPH1 and the high logic level of DPH1B are provided to the DFE circuit 240(2) of the input buffer circuit 210(2). Based on the low logic level DPH1 and the high logic level DPH1B, the DFE circuit 240(2) sets the reference level of the input buffer circuit 210(2) to a lower low reference level.

[0038] After latching the high logic level of the data D1, the voltage of the external data terminal DQ is reduced to a lower voltage of UI2. The rising edge of the PH2 clock appears at the time tWCK2DQI after the clock edge of the WCK_t clock at the time T1R. The rising edge and the high clock level of the PH2 clock activate the sensing circuit 220(2) of the input buffer circuit 210(2) to sense a voltage lower than the lower low reference level set by the DFE circuit 240(2). The sensing circuit 220(2) provides a sensing output based on the relatively low voltage of the external data terminal DQ and the reference level set for the input buffer circuit 210(2). As a result, the latching circuit 230(2) latches the low logic level of the data D2 and provides a low logic level voltage for DPH2 and a high logic level voltage for DPH2B.

[0039] The low logic level of DPH2 and the high logic level of DPH2B are provided to the DFE circuit 240(3) of the input buffer circuit 210(3). Based on the low logic level DPH2 and the high logic level DPH2B, the DFE circuit 240(3) sets the reference level of the input buffer circuit 210(3) to a lower low reference level.

[0040] After latching the low logic level of the data D(2), the voltage of the external data terminal DQ of UI2 becomes a higher voltage of UI3. The rising edge of the PH3 clock appears at the time tWCK2DQI after the clock edge of the WCK_t clock at the time T1F. The rising edge and the high clock level of the PH3 clock activate the sensing circuit 220(3) of the input buffer circuit 210(3) to sense a voltage higher than the lower low reference level set by the DFE circuit 240(3). The sensing circuit 220(3) provides a sensing output based on the relatively high voltage of the external data terminal DQ and the reference level set for the input buffer circuit 210(3). As a result, the latching circuit 230(3) latches the high logic level of the data D3 and provides a high logic level voltage for DPH3 and a low logic level voltage for DPH3B.

[0041] The high logic level of DPH3 and the low logic level of DPH3B are provided to the DFE circuit 240(0) of the input buffer circuit 210(0). Based on the high logic level DPH3 and the low logic level DPH3B, the DFE circuit 240(0) sets the reference level of the input buffer circuit 210(0) to a higher high reference level.

[0042] After latching four data bits D0 - D3 in one clock period of the multi - phase clock signal, other data bits D4 - D7 are latched in another clock period of the multi - phase clock signal.

[0043] The voltage of the external data terminal DQ becomes the lower voltage of UI4. The sensing circuit 220(0) of the input buffer circuit 210(0) is activated at the rising edge of the PH0 clock and the high clock level of the PH0 clock during UI4 to sense a voltage lower upward relative to the high reference level set by the DFE circuit 240(0). The sensing circuit 220(0) provides a sensing output based on the relatively low voltage of the external data terminal DQ and the reference level set for the input buffer circuit 210(0). As a result, the latching circuit 230(0) latches the low logic level of data D4, provides a low logic level voltage for DPH0, and provides a high logic level voltage for DPH0B.

[0044] The low logic level of DPH0 and the high logic level of DPH0B are provided to the DFE circuit 240(1) of the input buffer circuit 210(1). Based on the low logic level DPH0 and the high logic level DPH0B, the DFE circuit 240(1) sets the reference level of the input buffer circuit 210(1) downward from the low reference level.

[0045] After latching the high logic level of data D4, the voltage of the external data terminal DQ of UI4 becomes the higher voltage of UI5. The sensing circuit 220(1) of the input buffer circuit 210(1) is activated at the rising edge of the PH1 clock and the high clock level of the PH1 clock during UI5 to sense a voltage higher downward relative to the low reference level set by the DFE circuit 240(1). The sensing circuit 220(1) provides a sensing output based on the relatively high voltage of the external data terminal DQ and the reference level set for the input buffer circuit 210(1). As a result, the latching circuit 230(1) latches the high logic level of data D5, provides a high logic level voltage for DPH1, and provides a low logic level voltage for DPH1B.

[0046] The high logic level of DPH1 and the low logic level of DPH1B are provided to the DFE circuit 240(2) of the input buffer circuit 210(2). Based on the high logic level DPH1 and the low logic level DPH1B, the DFE circuit 240(2) sets the reference level of the input buffer circuit 210(2) upward from the high reference level.

[0047] After the low logic level of the latched data D5, the voltage of the external data terminal DQ of UI5 rises to the higher voltage of UI6. During UI6, the rising edge of the PH2 clock and the high clock level of the PH2 clock activate the sensing circuit 220(2) of the input buffer circuit 210(2) to sense a voltage higher upward relative to the high reference level set by the DFE circuit 240(2). The sensing circuit 220(2) provides a sensing output based on the relatively high voltage of the external data terminal DQ and the reference level set for the input buffer circuit 210(2). As a result, the latching circuit 230(2) latches the high logic level of the data D6, and provides a high logic level voltage for DPH2, and a low logic level voltage for DPH2B.

[0048] The high logic level of DPH2 and the low logic level of DPH2B are provided to the DFE circuit 240(3) of the input buffer circuit 210(3). Based on the high logic level DPH2 and the low logic level DPH2B, the DFE circuit 240(3) sets the reference level of the input buffer circuit 210(3) upward from the high reference level.

[0049] After the low logic level of the latched data D6, the voltage of the external data terminal DQ of UI6 becomes the lower voltage of UI7. During UI7, the rising edge of the PH3 clock and the high clock level of the PH3 clock activate the sensing circuit 220(3) of the input buffer circuit 210(3) to sense a voltage lower upward relative to the high reference level set by the DFE circuit 240(3). The sensing circuit 220(3) provides a sensing output based on the relatively low voltage of the external data terminal DQ and the reference level set for the input buffer circuit 210(3). As a result, the latching circuit 230(3) latches the low logic level of the data D7, and provides a low logic level voltage for DPH3, and a high logic level voltage for DPH3B.

[0050] The low logic level of DPH3 and the high logic level of DPH3B are provided to the DFE circuit 240(0) of the input buffer circuit 210(0). Based on the low logic level DPH3 and the high logic level DPH3B, the DFE circuit 240(0) sets the reference level of the input buffer circuit 210(0) downward from the low reference level.

[0051] The data D8 is latched by the latching circuit 230(0) of the input buffer circuit 210(0) during UI8 in a manner similar to that discussed previously.

[0052] Figure 4 is a schematic diagram of an input buffer circuit 400 according to an embodiment of the present disclosure. In some embodiments of the present disclosure, the input buffer circuit 400 may be included in an input buffer, which is included in Figure 1the input / output circuit 160 and / or Figure 2 in the input buffer 200.

[0053] The input buffer circuit 400 includes a sensing circuit 420 coupled to a latch circuit 430, and further includes a decision feedback equalizer (DFE) circuit 440.

[0054] The sensing circuit 420 is provided with a clock PHn (and a complementary clock PHnB in some embodiments of the present disclosure), and is further provided with a data reference voltage VrefDQ and data on an external data terminal DQ to which the input buffer circuit 400 is coupled. The PHn clock can be a clock from a plurality of multi-phase clock signals and has a phase relationship with other clocks of the multi-phase clock signals.

[0055] The sensing circuit 420 includes an activation circuit 421 that is powered by a power supply (e.g., vdd2) when the PHn clock is active (e.g., a high clock level). As Figure 4 shown, the activation circuit 421 can include an inverter circuit and a p-channel transistor (e.g., a P-type field effect transistor) coupled to the power supply. However, some embodiments of the present disclosure can include an activation circuit 421 that includes alternative circuits and / or additional circuits. Power from the activation circuit 421 is provided to the input circuit 422.

[0056] The input circuit 422 is coupled to the output circuit 424 of the sensing circuit 420 at a sensing node CN and a sensing node CT. Data is provided from the external terminal DQ to a first input transistor of the input circuit 422, and the VrefDQ voltage is provided to a second input transistor of the input circuit 422. The first input transistor is coupled to a first output transistor of the output circuit 424, and the second input transistor is coupled to a second output transistor of the output circuit 424. As Figure 4 shown, the first input transistor and the second input transistor of the input circuit 422 can be implemented as p-channel transistors, and the first output transistor and the second output transistor of the output circuit 424 can be implemented as n-channel transistors. However, in other embodiments of the present disclosure, the input circuit 422 and the output circuit 424 can be implemented using different circuits. In some embodiments of the present disclosure, the p-channel transistors of the input circuit 422 can be low threshold voltage (Vt) devices (e.g., Vt in the range of 100 - 300 mV). The p-channel transistors of the input circuit 422 can be matched (e.g.) to have the same circuit layout as each other. Similarly, the n-channel transistors of the output circuit 424 can be matched (e.g.) to have the same circuit layout as each other.

[0057] When activated by the PHn clock, the input circuit 422 of the sensing circuit 420 compares the voltage at the external data terminal DQ with the VrefDQ voltage and provides corresponding voltages to the CN node and the CT node. The output circuit 424 of the sensing circuit 420 provides a sensing output with a corresponding voltage level based on the voltages provided to the CN node and the CT node and the reference level set by the DFE circuit 440.

[0058] The sensing circuit 420 further includes a precharge circuit 426 and a precharge circuit 427. The precharge circuit 426 is coupled to the sensing node CN and provides a first output for the output data DPHn. The precharge circuit 427 is coupled to the sensing node CT and provides a second output for the output data DPHnB. Figure 4 Embodiments of the present disclosure are shown where the precharge circuit 426 and the precharge circuit 427 can each include a p-channel transistor for precharging the corresponding output and further include an n-channel transistor for precharging the sensing nodes CN / CT. Other embodiments of the present disclosure may have precharge circuits including different circuits. The precharge circuit 426 and the precharge circuit 427 precharge the sensing node CN and the sensing node CT and, when the PHn clock is deactivated (e.g., low clock level), precharge the outputs to an initial voltage. For example, the precharge circuit 426 and the precharge circuit 427 can provide a first precharge voltage to the sensing node CN and the sensing node CT and can provide a second precharge voltage to the first output and the second output. In some embodiments of the present disclosure, the first precharge voltage can be a reference voltage (such as ground), and the second precharge voltage can be a power supply voltage (such as vdd2).

[0059] The latch circuit 430 includes cross-coupled p-channel transistors 432 and cross-coupled n-channel transistors 434, which are coupled to the first output and the second output providing the output data DPHn and the output data DPHnB. The cross-coupled p-channel transistors 432 are powered by a power supply (e.g., vdd2), and the cross-coupled n-channel transistors 434 are coupled to the output circuit 424. The latch circuit 430 latches and provides the output data DPHn and the output data DPHnB with logic levels based on the sensing output from the sensing circuit 420. The p-channel transistors can match each other, and the n-channel transistors can match each other. For example, in some embodiments of the present disclosure, the p-channel transistors and / or the n-channel transistors have the same circuit layout with each other.

[0060] The DFE circuit 440 is coupled to the sense node CN and the sense node CT, and includes a tunable capacitor 442 coupled to the sense node CN and a tunable capacitor 443 coupled to the sense node CT. The DFE circuit 440 further includes a reference capacitor 444 coupled to the sense node CN and a reference capacitor 445 coupled to the sense node CT. When the data DPH(n - 1)B is at a high logic level, the capacitance of the tunable capacitor 442 is provided to the sense node CN, and the capacitance of the reference capacitor 445 is provided to the sense node CT. When the data DPH(n - 1) is at a high logic level, the capacitance of the tunable capacitor 443 is provided to the sense node CT, and the capacitance of the reference capacitor 444 is provided to the sense node CN.

[0061] The data DPH(n - 1) and the data DPH(n - 1)B are data from another input buffer circuit. For example, in some embodiments of the present disclosure, the data DPH(n - 1) and the data DPH(n - 1)B are provided by an input buffer circuit that is activated by a clock PH(n - 1) whose phase is earlier than the PHn clock, where both clocks are included in a set of multi - phase clock signals. For example, for quadrature multi - phase clock signals, and where the input buffer circuit 400 is activated by a 0 - degree clock, the data DPH(n - 1) and the data DPH(n - 1)B are provided by an input buffer circuit activated by a 270 - degree clock. In another example, where the input buffer circuit 400 is activated by a 90 - degree clock, the data DPH(n - 1) and the data DPH(n - 1) are provided by an input buffer circuit activated by a 0 - degree clock.

[0062] The tunable capacitor 442 provides a capacitance that can be adjusted by the DFE code Code_T <n:0>Set capacitance. Code_T <n:0>The code can be a value programmed in a mode register (not shown). Code_T can be <n:0>The adjustable capacitor 442 is provided to set the capacitance. Code_T <n:0>may include one or more bits, where N is an integer greater than or equal to zero. Changing Code_T <n:0>The code can change the capacitance provided by the tunable capacitor 442. For example, Figure 4 An embodiment of the present disclosure is shown, in which the tunable capacitor 442 includes a plurality of capacitors. Each of the plurality of capacitors can be provided with Code_T <n:0>The corresponding bits of the code. The capacitors providing the high logic bits provide a higher capacitance than the capacitors providing the low logic bits. As the number of capacitors with a higher capacitance changes (e.g., changing Code_T <n:0>value), the capacitance of the adjustable capacitor 442 changes. The capacitance range of the adjustable capacitor can be from when Code_T <n:0>The minimum capacitance when the code includes all "0" bits to when Code_T <n:0>The code includes the maximum capacitance when all bits are "1". When the switch of the adjustable capacitor 442 is activated by the high logic level data DPH(n - 1)B, the switch conducts, and multiple capacitors provide capacitance to the sense node CN. Therefore, the capacitance provided by the adjustable capacitor 442 can be changed by varying Code_T <n:0>Adjusted by the value of the code.

[0063] In some embodiments of the present disclosure, each of the plurality of capacitors is provided by a field effect transistor (FET) capacitor whose gate receives Code_T <n:0>The corresponding bits. In some embodiments of the present disclosure, each of the plurality of capacitors of the tunable capacitor provides the same capacitance when activated and the same capacitance when not activated. In some embodiments of the present disclosure, each of the plurality of capacitors of the tunable capacitor provides a different capacitance. For example, each capacitor can be of a different size, which provides different capacitances. The sizes of the capacitors in some embodiments of the present disclosure can be binary weighted (e.g., 1, 2, 4, 8, etc.).

[0064] The tunable capacitor 443 also provides that can be used by the DFE code Code_T <n:0>Adjustable capacitor. When the data DPH(n - 1) is at a high logic level, the adjustable capacitor 443 provides capacitance to the sensing node CT. The adjustable capacitor 443 may have a structure similar to the aforementioned adjustable capacitor 442.

[0065] When the data DPH(n - 1) is at a high logic level, the reference capacitor 444 provides capacitance to the sensing node CN. Figure 4 An embodiment of the present disclosure is shown, where the reference capacitor 444 includes a plurality of capacitors and a switch. When the switch is activated by the high logic level data DPH(n - 1), the switch conducts, and the plurality of capacitors provide capacitance to the sensing node CN. In some embodiments of the present disclosure, when the data DPH(n - 1) is at a high logic level, the reference capacitor 444 provides the same capacitance as the minimum capacitance of the adjustable capacitor 443. For example, in some embodiments of the present disclosure, each of the plurality of capacitors in the reference capacitor 444 is matched with the capacitors included in the adjustable capacitor 443 (e.g., each of the plurality of capacitors in the reference capacitor 444 has the same electrical characteristics as the corresponding capacitor of the adjustable capacitor 443 that receives a "0" bit). When matching the capacitance of the adjustable capacitor 443, the reference capacitor 444 may include capacitors having a structure similar to the capacitors of the adjustable capacitor. For example, in the case where the adjustable capacitor 443 includes FET capacitors, each capacitor of the reference capacitor 444 may also be an FET capacitor, and its corresponding gate effectively provides a "0" bit (e.g., grounding the corresponding gate). In some embodiments of the present disclosure, the circuit layout of the FET capacitors is similar to reduce the deviation between the FET capacitors.

[0066] When the data DPH(n - 1)B is at a high logic level, the reference capacitor 445 provides capacitance to the sensing node CT. In some embodiments of the present disclosure, when the data DPH(n - 1)B is at a high logic level, the reference capacitor 445 provides the same capacitance as the minimum capacitance of the adjustable capacitor 442. The reference capacitor 445 may have a structure similar to the aforementioned reference capacitor 444.

[0067] The DFE circuit 440 sets the reference level of the input buffer circuit 400 based on the output data DPH(n - 1) and the output data DPH(n - 1)B from other input buffer circuits. The sensing circuit 420 uses the reference level to determine whether the voltage of the data provided to the external data terminal DQ when the input buffer circuit is activated represents a high logic level (e.g., the output data DPHn is at a high logic level and DPHnB is at a low logic level) or represents a low logic level (e.g., the output data DPHn is at a low logic level and DPHnB is at a high logic level).

[0068] In some embodiments of the present disclosure, the DFE circuit 440 sets the reference level to a first reference level or a second reference level based on the output data DPH(n - 1) and the output data DPH(n - 1)B from other input buffer circuits. For example, based on the output data DPH(n - 1) and the output data DPH(n - 1)B, the DFE circuit 440 can set the reference level of the input buffer circuit 400 to a high reference level that is effectively higher than the VrefDQ voltage reference level, or to a low reference level that is effectively lower than the VrefDQ voltage reference level.

[0069] The levels of the first reference level and the second reference level can be determined by the DFE code Code_T <n:0>Settings. The levels of the first reference level and the second reference level can be relative to the VrefDQ voltage. For example, the high reference level may be greater than the VrefDQ voltage by an amount, and the low reference level may be less than the VrefDQ voltage by an amount. The deviation amounts of the high reference level and the low reference level from the VrefDQ voltage can be determined by Code_T <n:0>Code setting. For example, Code_T <n:0>The first value causes the high reference level and the low reference level to deviate from the VrefDQ voltage by a first amount. Code_T <n:0>The second value causes the high reference level and the low reference level to have a deviation of a second amount different from the first amount with respect to the VrefDQ voltage. Change Code_T <n:0>The value of the code can change the levels of the first reference level and the second reference level.

[0070] As previously mentioned, in some embodiments of the present disclosure, the adjustment range of the reference level is within Code_T <n:0>Between the minimum and maximum values of the code (e.g., between Code_T <n:0>= all "0" and Code_T <n:0>= between all "1"s). For Code_T <n:0>= All "0" reference levels may be the same as the VrefDQ voltage. For Code_T <n:0>= All "1" reference levels can be changed by a maximum value with respect to the VrefDQ voltage.

[0071] Change Code_T <n:0>The code will cause the reference level to increase / decrease step by step. For example, Code_T <n:0>Changing from "001" to "010" causes a step change in the reference level. In some embodiments of the present disclosure, the amount of the step increase / decrease of the reference level can be based on the capacitance of the tunable capacitor that provides capacitance to one sensing node (e.g., sensing node CN or sensing node CT) relative to the reference capacitance that provides capacitance to other sensing nodes (e.g., sensing node CT or sensing node CN).

[0072] When the capacitance of the tunable capacitor changes by the minimum amount, providing capacitance to the node opposite the node that provides the tunable capacitor (e.g., for adjusting the reference level of the input buffer circuit) provides greater flexibility in setting the amount of the step change in the reference level. For example, in the case where a capacitor formed with the minimum feature size still provides a capacitance that causes the step change in the reference level to be too large, providing capacitance to the opposite node of the input buffer circuit can reduce the amount of the step change. In some embodiments of the present disclosure, the capacitance provided by the reference capacitance (such as Figure 4 the reference capacitances 444 and 445 of the input buffer circuit 400) can be used to provide such capacitance.

[0073] The exemplary operation of the input buffer circuit 400 will be described for (1) DPH(n - 1) data being a high logic level and (2) DPH(n - 1) data being a low logic level. Assume that the voltage provided to the external terminal DQ when the input buffer circuit 400 is activated by the PHn clock is less than the VrefDQ voltage and is also less than the low reference level set by the DFE circuit 440. The low reference level is less than the high reference level. In the exemplary operation, the input circuit 422 includes a low-Vt p-channel transistor. The DFE code Code_T <n:0>Set the capacitance provided by the adjustable capacitor 442 and the adjustable capacitor 443, which is greater than the capacitance provided by the reference capacitor 444 and the reference capacitor 445.

[0074] When the DPH(n - 1) data is at a high logic level (and the DPH(n - 1)B data is at a low logic level), the adjustable capacitor 443 provides capacitance to the node CT, and the reference capacitor 444 provides capacitance to the sense node CN. As a result, the sense node CT has a larger capacitive load than the sense node CN, which causes the voltage of the sense node CT to change more slowly than the voltage of the sense node CN. The larger capacitive load on the sense node CT has the effect of raising the reference level of the input buffer circuit 400 to be greater than the VrefDQ voltage (e.g., to a high reference level).

[0075] When the PHn clock is activated, the activation circuit 421 supplies power, which turns on the p-channel transistor of the input circuit 422 and supplies power to the sense node CN and the sense node CT respectively. The voltage provided to the first transistor coupled to the external data terminal DQ is less than the VrefDQ voltage provided to the second transistor, which makes the first transistor more conductive than the second transistor. As a result, the voltage of the sense node CN rises faster from the pre-charge voltage (e.g., ground) than the voltage of the sense node CT. The additional effect of the larger capacitive load on the sense node CT compared to the sense node CN further contributes to the higher rate of change of the voltage of the sense node CN. As the voltage of the sense node CN rises faster than the voltage of the sense node CT, the first transistor of the output circuit 424 becomes more conductive than the second transistor of the output circuit 424. The conductive first transistor causes the first output of the latch circuit 430 (where the DPHn data is provided) to drop from the pre-charge voltage (e.g., vdd2) to a low logic level voltage (e.g., ground). The reduced voltage causes the latch circuit 430 to latch and provide low logic level DPHn data and high logic level DPHnB data.

[0076] When the DPH(n - 1) data is at a low logic level (and the DPH(n - 1)B data is at a high logic level), the adjustable capacitor 442 provides capacitance to the sense node CN, and the reference capacitor 445 provides capacitance to the sense node CT. As a result, the sense node CN has a larger capacitive load than the sense node CT, which causes the voltage of the sense node CN to change more slowly than the voltage of the sense node CT. The larger capacitive load on the sense node CN has the effect of lowering the reference level of the input buffer circuit 400 to be less than the VrefDQ voltage (e.g., to a low reference level).

[0077] When the PHn clock is activated, the activation circuit 421 is powered, which turns on the p-channel transistors of the input circuit 422 and supplies power to the sense node CN and the sense node CT, respectively. The voltage supplied to the first transistor coupled to the external data terminal DQ is less than the VrefDQ voltage supplied to the second transistor, which makes the first transistor more conductive than the second transistor. As a result, the voltage of the sense node CN increases from the low pre-charge voltage. The additional effect of the larger capacitive load on the sense node CN compared to the sense node CT (to which a reference capacitor is supplied) reduces the rate of change of the voltage of the sense node CN. However, since the voltage supplied to the first transistor is also less than the low reference level, as described above, the voltage of the sense node CN still rises faster than the voltage of the sense node CT. The voltage of the sense node CN makes the first transistor of the output circuit more conductive than the second transistor of the output circuit 424. The conductive first transistor causes the first output of the latch circuit 430 to decrease from the high pre-charge voltage to the low logic level voltage (e.g., ground). The decreased voltage causes the latch circuit 430 to latch and provide the low logic level DPHn data and the high logic level DPHnB data.

[0078] As shown in the operation example described above, the DFE circuit 440 sets a reference level for the input buffer circuit 400, which is used to determine whether the voltage supplied to the external data terminal DQ when the input buffer circuit 400 is activated is sensed and provided as a high logic level (e.g., high logic level DPHn data and low logic level DPHnB data) or a low logic level (e.g., low logic level DPHn data). Additionally, the DFE circuit 440 includes the adjustable capacitor 442 and the adjustable capacitor 443, and includes the reference capacitor 444 and the reference capacitor 445. As described above, for the DFE code Code_T <n:0>For a change in value, the step change amount of the reference level can be based on the tunable capacitance provided to one node and the reference capacitance provided to another node. By including reference capacitor 444 and reference capacitor 445, the step change amount of the reference level of the input buffer circuit 400 can be less compared to a DFE circuit that does not include a reference capacitance. Therefore, a DFE circuit that includes a tunable capacitance and a reference capacitance that provides a corresponding capacitance to opposite nodes provides greater flexibility in setting the step change amount of the reference level.

[0079] From the foregoing, it should be understood that although specific embodiments of the present disclosure have been described herein for purposes of illustration, various modifications may be made without departing from the spirit and scope of the present disclosure. Accordingly, the scope of the present disclosure should not be limited to any specific embodiment described herein.

Claims

1. An apparatus including an input buffer, comprising: An external data terminal to which input data is provided; An input buffer including a plurality of input buffer circuits coupled to the external data terminal, wherein each of the input buffer circuits includes: A sensing circuit configured to compare a voltage of the input data with a reference voltage and provide a first voltage and a second voltage to a first sensing node and a second sensing node respectively based on the comparison; A decision feedback equalizer coupled to the first sensing node and the second sensing node and configured to set a reference level of a corresponding input buffer circuit based on output data from another input buffer circuit, wherein the decision feedback equalizer includes a first adjustable capacitor and a second adjustable capacitor coupled to the first sensing node and the second sensing node via a first switch and a second switch respectively, and further includes a first reference capacitor and a second reference capacitor coupled to the first sensing node and the second sensing node via a third switch and a fourth switch respectively, wherein the sensing circuit is further configured to provide a sensing output based on the reference level and the comparison of the voltage of the input data with the reference voltage; and A latching circuit coupled to the first sensing node and the second sensing node and configured to latch and provide output data having a logic level with a voltage based on the sensing output.

2. The apparatus according to claim 1, wherein each of the input buffer circuits is configured to receive a corresponding clock, and each of the corresponding clocks has a different phase from each other.

3. The apparatus according to claim 2, wherein the corresponding clocks are related to each other as quadrature clocks.

4. The apparatus according to claim 1, wherein the first adjustable capacitor and the second reference capacitor are configured to provide corresponding capacitances to the first sensing node and the second sensing node respectively in response to a first logic level that activates the first switch and the fourth switch of the output data from the another input buffer circuit, and wherein the second adjustable capacitor and the first reference capacitor are configured to provide corresponding capacitances to the second sensing node and the first sensing node respectively in response to a second logic level that activates the second switch and the third switch of the output data from the another input buffer circuit.

5. The apparatus according to claim 4, wherein the output data is provided by the input buffer circuit providing a clock having an immediately preceding phase.

6. The apparatus according to claim 1, wherein: Each of the first adjustable capacitor and the second adjustable capacitor includes a plurality of capacitors, and each of the capacitors is configured to be enabled by a corresponding control signal; And Each of the first reference capacitor and the second reference capacitor includes a plurality of capacitors.

7. The apparatus according to claim 6, wherein each of the plurality of capacitors of the first adjustable capacitor is matched with a corresponding one of the plurality of capacitors of the second reference capacitor.

8. The apparatus according to claim 6, wherein each of the plurality of capacitors of the first adjustable capacitor and the second adjustable capacitor comprises a field effect transistor capacitor.

9. An input buffer circuit, comprising: a sensing circuit configured to compare a voltage of input data with a reference voltage and to provide a first voltage and a second voltage to a first sensing node and a second sensing node, respectively, based on the comparison; a latching circuit coupled to the sensing circuit and configured to latch and provide output data having a logic level based on a voltage of a sensing output provided by the sensing circuit; and a decision feedback equalizer coupled to the first sensing node and the second sensing node and configured to simultaneously provide a first capacitor to the first sensing node through the first switch when the first switch is activated and to provide a second capacitor to the second sensing node through the second switch when the second switch is activated, to set a reference level of the input buffer circuit based on output data from another input buffer circuit, wherein the sensing output provided by the sensing circuit is based on the first voltage, the second voltage, and the reference level.

10. The input buffer circuit according to claim 9, wherein the second capacitor is smaller than the first capacitor.

11. The input buffer circuit according to claim 9, wherein the decision feedback equalizer comprises: an adjustable capacitor coupled to the first sensing node via the first switch and configured to provide the first capacitor when the first switch is activated; and a reference capacitor coupled to the second sensing node via the second switch and configured to provide the second capacitor when the second switch is activated, wherein the first capacitor is set by a code provided to the adjustable capacitor.

12. The input buffer circuit according to claim 11, wherein the decision feedback equalizer further comprises: a second adjustable capacitor coupled to the second sensing node via a third switch and configured to provide a third capacitor when the third switch is activated; and a second reference capacitor coupled to the first sensing node via a fourth switch and configured to provide a fourth capacitor when the fourth switch is activated, wherein based on the output data from the another input buffer circuit, the third capacitor is provided to the second sensing node and the fourth capacitor is provided to the first sensing node, or the first capacitor is provided to the first sensing node and the second capacitor is provided to the second sensing node.

13. The input buffer circuit according to claim 9, wherein the latching circuit comprises: cross-coupled p-channel transistors coupled to a first output and a second output; and cross-coupled n-channel transistors coupled to the first output and the second output.

14. The input buffer circuit according to claim 9, wherein the sensing circuit comprises: An activation circuit, the activation circuit being configured to be coupled to a power supply and being configured to be powered by the power supply in response to a clock; An input circuit, the input circuit being coupled to the activation circuit and further coupling the first sensing node and the second sensing node, the input circuit being configured to receive the input data and the reference voltage; An output circuit, the output circuit being coupled to the first sensing node and the second sensing node and further being coupled to the latch circuit.

15. The input buffer circuit according to claim 14, wherein the input circuit includes a pair of p-channel transistors coupled to the activation circuit, and wherein the output circuit includes a pair of n-channel transistors configured to provide the sensed output to the latch circuit.

16. The input buffer circuit according to claim 15, wherein the pair of p-channel transistors includes low-threshold voltage devices.

17. The input buffer circuit according to claim 9, wherein the sensing circuit includes: A first precharge circuit, the first precharge circuit being coupled to the first sensing node and being configured to precharge the first sensing node and a first output of the latch circuit; and A second precharge circuit, the second precharge circuit being coupled to the second sensing node and being configured to precharge the second sensing node and a second output of the latch circuit, wherein the first sensing node and the second sensing node are precharged to the same voltage, and the first output and the second output of the latch circuit are precharged to a voltage different from that of the first sensing node and the second sensing node.

18. A method for operating an input buffer, comprising: Activating an input buffer circuit to receive input data; Comparing the voltage of the input data with a reference voltage and based thereon providing voltages to a first node and a second node; Setting a reference level of the input buffer circuit by providing a first capacitor to one of the first node or the second node through a first switch or a second switch while providing a second capacitor to the other node through a third switch or a fourth switch, wherein the activation of the first switch and the fourth switch or the activation of the second switch and the third switch is based on output data from another input buffer circuit; Providing a sensed output based on the reference level and the comparison of the voltage of the input data with the reference voltage; And Latching and providing output data based on the voltage of the sensed output.

19. The method according to claim 18, wherein the first capacitor is smaller than the second capacitor, and the first capacitor is an adjustable capacitor set by a code.

20. The method according to claim 18, wherein the first capacitor and the second capacitor are provided in response to the activation of the first switch and the fourth switch or the activation of the second switch and the third switch by the output data from the other input buffer circuit.

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